Wireless receiver device and aggregated symbol category determination method

Abstract

A wireless receiver device includes a decoder, a memory unit, and a processor. The decoder decodes an aggregated packet during a period of multiple symbols to obtain raw data, the aggregated packet having multiple sub-blocks. The memory unit temporarily stores the raw data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol among the symbols based on the number of symbols, the number of data bits per symbol corresponding to each of the sub-blocks, and the processor's performance characteristics. During the period of at least one non-idle symbol, the processor accesses the memory unit to perform data parsing processing on the raw data, but enters an idle state without accessing the memory unit during the period of at least one idle symbol.

Description

[Technical Field]

[0001] This disclosure relates to packet decoding and parsing, and in particular to a wireless receiver device, its data processing method, and a wireless communication system. [Previous Technology]

[0002] In wireless communication, the transmitting end typically encodes raw data into packets, and the receiving end then decodes the packets to reconstruct the raw data. When receiving packets, the decoder usually first decodes the packets to obtain the raw data and writes it into memory. Then, the processor accesses memory to retrieve the raw data and performs data parsing. Since the timing of memory write events is unpredictable, the processor must constantly access memory to obtain the decoded raw data, preventing it from performing other tasks, resulting in reduced efficiency and significant power consumption. Therefore, optimizing power consumption in packet processing for wireless communication devices is one of the main goals of the industry. [Summary of the Invention]

[0003] This disclosure proposes a wireless receiver device comprising a decoder, a memory unit, and a processor. The decoder is used to decode an aggregate packet during a period of multiple symbols to obtain raw data, the aggregate packet having multiple sub-blocks. The memory unit is used to temporarily store the raw data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol among these symbols based on the number of symbols, the number of data bits per symbol corresponding to these sub-blocks, and the performance characteristics of the processor, and to access the memory unit during the period of at least one non-idle symbol to perform data parsing processing on the raw data, but to enter an idle state without accessing the memory unit during the period of at least one idle symbol.

[0004] This disclosure also proposes a data processing method applicable to a wireless receiver device and comprising: decoding an aggregated packet during a period of multiple symbols to obtain original data, the aggregated packet having multiple sub-blocks; temporarily storing the original data in a memory unit; and determining at least one non-idle symbol and at least one idle symbol among the symbols based on the number of symbols, the number of data bits per symbol corresponding to the sub-blocks respectively, and the performance characteristics of the processor, and accessing the memory unit during the period of at least one non-idle symbol to perform data parsing processing on the original data, but entering an idle state without accessing the memory unit during the period of at least one idle symbol.

[0005] This disclosure further discloses a wireless receiver device, comprising a wireless transmitter device and a wireless receiver device, wherein the wireless transmitter device is configured to transmit aggregated packets, and the wireless receiver device is configured to receive aggregated packets via a wireless channel, wherein the aggregated packets have multiple sub-blocks. The wireless receiver device includes a decoder, a memory unit, and a processor. The decoder is used to decode the aggregated packets during the period of multiple symbols to obtain raw data. The memory unit is used to temporarily store the raw data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol among these symbols based on the number of symbols, the number of data bits per symbol corresponding to these sub-blocks, and the performance characteristics of the processor, and to access the memory unit during the period of at least one non-idle symbol to perform data parsing processing on the raw data, but to enter an idle state without accessing the memory unit during the period of at least one idle symbol.

Implementation Method

[0007] The embodiments of this disclosure are discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0008] According to current Wi-Fi system specifications, the transmission modes used by Wi-Fi systems can include, for example, orthogonal frequency division multiplexing (OFDM) transmission mode, high throughput (HT) mode, very high throughput (VHT) mode, high efficiency (HE) mode, and extremely high throughput (EHT) mode. Among them, high throughput mode, very high throughput mode, high efficiency mode, and extremely high throughput mode correspond to different communication generations of wireless local area network (WLAN) standards such as Wi-Fi 4, Wi-Fi 5, Wi-Fi 6, and Wi-Fi 7, respectively. The better the hardware specifications of the wireless transceiver and the more advanced the supported Wi-Fi system, the more transmission modes can be used. The embodiments disclosed herein may also support other wired and / or wireless communication technologies such as cellular network, Bluetooth, local area network (LAN) and / or Universal Serial Bus (USB).

[0009] Please refer to Figure 1, which is a schematic diagram of a wireless communication system 100 according to an embodiment of this disclosure. The communication technology used by the wireless communication system 100 may be, for example, wireless local area network communication technology conforming to the IEEE 802.11 standard (including IEEE 802.11ac, IEEE 802.11ax, IEEE 802.11be, etc.) and / or other applicable wireless communication technologies. The wireless communication system 100 includes wireless transceiver devices 110 and 120, which are connected via a wireless channel. The wireless transceiver devices 110 and 120 may simultaneously have packet transmission and reception functions. For example, in the scenario where the wireless transceiver device 110 transmits packets to the wireless transceiver device 120 via the wireless channel, the wireless transceiver devices 110 and 120 may also be referred to as a wireless transmitter device and a wireless receiver device, respectively.

[0010] The wireless channel in the wireless communication system 100 can support multiple-input multiple-output (MIMO), multiple-input single-output (MISO), single-input multiple-output (SIMO), and / or single-input single-output (SISO) transmissions between wireless transceivers 110 and 120. Each wireless transceiver 110 and 120 can represent various different implementations, including but not limited to mobile wireless transceivers such as stations (STAs), laptops, mobile phones, and tablets, and / or fixed wireless transceivers such as access points (APs), routers, switches, computer equipment, server equipment, and workstations.

[0011] Figure 2 is a block diagram of a wireless receiver device 200 according to an embodiment of the present disclosure. The wireless receiver device 200 may be the wireless transceiver device 110 and / or the wireless transceiver device 120 of Figure 1. The wireless receiver device 200 includes a decoder 210, a memory unit 220, and a processor 230. The decoder 210 is used to decode received packets to obtain raw data. Depending on the encoding technology used by the wireless communication system, the decoder 210 may be, for example, a convolutional decoder, a trellis decoder, a Viterbi decoder, and / or a turbo decoder, but is not limited thereto. For example, if the wireless receiver device 200 is used in a wireless local area network communication system, the decoder 210 may be a Viterbi decoder.

[0012] The memory unit 220 is coupled to the decoder 210 and can be used to temporarily store the original data obtained after the packets are decoded by the decoder 210. The memory unit 220 can be data memory (DMEM), static random access memory (SRAM) or other memory suitable for temporarily storing original data.

[0013] The processor 230 is coupled to the memory unit 220, and can access the memory unit 220 to obtain raw data temporarily stored in the memory unit 220, and perform data parsing processing on the obtained raw data. The processor 230 may be, for example, a conventional processor, a multi-core processor, a digital signal processor (DSP), a microprocessor, or an application-specific integrated circuit (ASIC), but is not limited thereto.

[0014] Decoder 210 decodes packets during multiple symbol cycles to obtain raw data. Specifically, during each symbol cycle, decoder 210 decodes the corresponding segment in the packet to obtain raw data with a data bit count per symbol. When the number of remaining bits of raw data after decoder 210 decodes the packet and is not written to memory unit 220 is greater than the threshold number of bits, decoder 210 can write a portion of the raw data to memory unit 220 for data parsing processing by processor 230. In particular, based on the clock-equivalent performance characteristics of processor 230, when the number of remaining bits of raw data first exceeds the threshold number of bits, decoder 210 writes 1 bit of raw data string to memory unit 220. Then, before the last symbol cycle, whenever the number of remaining bits of raw data does not increase to exceed the threshold number of bits for the first time, decoder 210 writes 2 bits of raw data string to memory unit 220. During the last symbol, decoder 210 writes all the raw data that has not yet been written to memory unit 220 to memory unit 220.

[0015] Figure 3 shows an example of decoding packets using the wireless receiver device 200 of Figure 2. In this example, the wireless receiver device 200 receives and decodes packets in High Efficiency Multi-User Entity Layer Protocol Data Unit (HE MU PPDU) format with a modulation and coding scheme (MCS) index value of 5 in an IEEE 802.11ax wireless local area network. The decoder 210 performs Viterbi decoding on the HE-SIG-B field in the received packet and writes it as a 64-bit string to the memory unit 220, and the HE-SIG-B field corresponds to 4 orthogonal frequency division multiplexing (OFDM) symbols (hereinafter referred to as OFDM symbols). During the first OFDM symbol, decoder 210 decodes the first segment of the HE-SIG-B field in the packet. Because the remaining number of bits in the original data is only 208 bits and does not exceed 256 bits, decoder 210 does not write any 64-bit original data string to memory unit 220; that is, there is no data write event in memory unit 220. During the second OFDM symbol, decoder 210 decodes the second segment of the HE-SIG-B field in the packet, increasing the remaining number of bits to 416 bits, which exceeds 256 bits. Therefore, decoder 210 writes one 64-bit original data string to memory unit 220 (i.e., one arrow in block B1). After writing one 64-bit string, the remaining number of bits is still 352 bits, which exceeds 256 bits. Therefore, decoder 210 then writes two more 64-bit original data strings to memory unit 220 (i.e., two arrows in block B2). During the third OFDM symbol, decoder 210 decodes the third segment of the HE-SIG-B field in the packet, causing the remaining number of bits to accumulate to 432 bits, exceeding 256 bits. Therefore, decoder 210 writes two 64-bit raw data strings to memory unit 220 (i.e., the two arrows in block B3). After writing the two 64-bit raw data strings, the remaining number of bits is still 304 bits, exceeding 256 bits. Therefore, decoder 210 then writes two more 64-bit raw data strings to memory unit 220 (i.e., the two arrows in block B4). During the fourth OFDM symbol, decoder 210 decodes the fourth segment of the HE-SIG-B field in the packet, and then divides the remaining 384 raw data bits into six 64-bit raw data strings and writes them to memory unit 220 (i.e., the six arrows in block B5).

[0016] Figure 4 is a flowchart illustrating the method 400 for counting the number of original data strings in symbols according to an embodiment of this disclosure. The method 400 for counting the number of original data strings in symbols can be used in the wireless receiver device 200 of Figure 2 or other suitable wireless receiver devices. For example, in an instance used in the wireless receiver device 200, the method 400 for counting the number of original data strings in symbols can be performed by the processor 230.

[0017] In the method 400 for counting the number of original data strings in a symbol, operation S402 is first performed to obtain the number of data bits per symbol and the number of symbols. The remaining number of original data bits is initialized to 0, the number of original data strings corresponding to the first to the second symbols are both 0, and the symbol index is 1. Next, operation S404 is performed to increase the remaining number of original data bits by the number of data bits per symbol. Then, operation S406 is performed to determine whether the first symbol (i.e., the current symbol) is the last symbol, i.e., to determine whether the symbol index is equal to the number of symbols. If so, operation S408 is performed to record the number of original data strings corresponding to the first symbol, and the method 400 for counting the number of original data strings in a symbol ends, where represents the ceiling function operation. Conversely, if the current symbol is not the last symbol, operation S410 is performed to determine whether the remaining number of original data bits is greater than the threshold number of bits. If the result of operation S410 indicates that the remaining number of bits in the original data is greater than the threshold number of bits, then operation S412 is performed to further determine whether the remaining number of bits in the original data is greater than the threshold number for the first time. Conversely, if the result of operation S410 indicates that the remaining number of bits in the original data is not greater than the threshold number of bits, then operation S414 is performed to proceed to the next symbol (i.e., the symbol number is incremented by 1), and operation S404 is returned to process the next symbol.

[0018] If the result of operation S412 is that the remaining number of bits in the original data is greater than the threshold number of bits for the first time, then operation S416 is performed, subtracting the number of bits of the original data string by 1 from the remaining number of bits in the original data (i.e., performing an operation), and increasing the number of original data strings corresponding to the i-th symbol by 1. Conversely, if the result of operation S412 is that the remaining number of bits in the original data is not greater than the threshold number of bits for the first time, then operation S418 is performed, subtracting the number of bits of the original data string by 2 from the remaining number of bits in the original data (i.e., performing an operation), and increasing the number of original data strings corresponding to the i-th symbol by 2. After operation S416 or operation S418 is completed, operation S420 is performed to determine whether the remaining number of bits in the original data is greater than the threshold number of bits. If it is determined that the remaining number of bits in the original data is greater than the threshold number of bits, then operation S418 is performed. Conversely, if it is determined that the remaining number of bits in the original data is not greater than the threshold number of bits, then operation S414 is performed.

[0019] The threshold bit count and the number of bits in the original data string counting method 400 in the symbol can be adjusted according to the hardware and software specifications and / or communication system specifications. In some embodiments, the threshold bit count should be greater than or equal to twice the number of bits in the original data string, i.e. In some embodiments, the threshold bit count and the number of bits in the original data string are 256 and 64, respectively. In addition, some operations in the original data string counting method 400 in the symbol also correspond to the operations of the decoder and memory unit. Operation S404 corresponds to the decoder decoding the first HE-SIG-B packet, operation S408 corresponds to the event that the decoder writes all remaining data to the memory unit at the end of the period of the last symbol, operation S416 corresponds to the event that the decoder writes 1 bit of original data string to the memory unit, and operation S418 corresponds to the event that the decoder writes 2 bits of original data string to the memory unit.

[0020] Figures 5A and 5B show examples of processor states with different numbers of data bits per symbol and the same number of symbols, where the threshold number of bits and the number of bits in the original data string are 256 and 64, respectively. In the example of Figure 5A, the number of data bits per symbol and the number of symbols are 208 and 8, respectively. As shown in Figure 5A, the decoder does not write any 64-bit original data string to the memory unit during the first symbol period, so the processor is woken up during each of the second to eighth symbols to enter the wake-up state (e.g., the working state) and perform operations. In contrast, in the example of Figure 5B, the number of data bits per symbol and the number of symbols are 28 and 8, respectively. As shown in Figure 5B, the decoder does not write any 64-bit original data string to the memory unit during the first to seventh symbols, and writes all the unwritten original data string to the memory unit during the eighth symbol period, so the processor is only woken up during the eighth symbol period to enter the wake-up state.

[0021] Figure 6 shows the raw data string count table TB for symbols with 20 symbols and data bits per symbol of 13, 26, 52, 78, 104, 156, and 208. The raw data string count table TB can be generated by performing the raw data string count method 400 in the symbols. Taking a data bit count of 104 per symbol as an example, the raw data string counts during the 3rd and 4th symbols are 1 and 2 respectively, indicating that the decoder writes 1 and 2 raw data strings to the memory unit during the 3rd and 4th symbols respectively.

[0022] In IEEE 802.11be wireless local area networks, aggregated downlink transmission can be performed using multiple EHT-SIG content channels and multiple sub-blocks. For example, a 320 MHz bandwidth channel has four sub-blocks, and each sub-block has a number of data bits per symbol, which is determined by the modulation and coding scheme (MCS) index value (hereinafter referred to as the MCS index value) and the dual-carrier modulation (DCM) setting value (hereinafter referred to as the DCM setting value). The MCS index value and DCM setting value corresponding to each sub-block can be obtained from the U-SIG field in the Very High Throughput Multi-User Protocol Data Unit (also known as EHT MU PPDU) format.

[0023] Table 1 shows the relationship between the MCS index value, DCM setting value, and the number of data bits per symbol for each EHT-SIG field in the VHT MU PPDU. According to Table 1, if the MCS index value is 0, the corresponding number of data bits per symbol for DCM settings of 0 (i.e., no dual-carrier modulation) and 1 (i.e., dual-carrier modulation) is 13 and 26, respectively. The number of data bits per symbol corresponding to other MCS index values ​​and DCM settings can be obtained from the content shown in Table 1. Table 1 MCS Index Value DCM settings 0 0 13 1 26 1 0 26 1 52 2 0 78 3 0 52 1 104 4 0 78 1 156 5 0 208

[0024] Further, the processor can determine the state of each aggregate symbol (a symbol after aggregating multiple sub-blocks) based on its performance characteristics and the MCS index value and DCM setting value (i.e., the number of data bits per symbol corresponding to each sub-block).

[0025] Figure 7 is a flowchart illustrating the aggregate symbol category determination method 700 according to an embodiment of this disclosure. The aggregate symbol category determination method 700 can be used in the wireless receiver device 200 of Figure 2 or other suitable wireless receiver devices. For example, in an instance used in the wireless receiver device 200, the aggregate symbol category determination method 700 can be performed by the processor 230.

[0026] In the aggregation symbol category discrimination method 700, operation S702 is first performed to aggregate the list of the number of original data strings output by each sub-block in each symbol to generate a list of the number of aggregated original data strings output by each aggregation symbol (the number of aggregated original data strings is the sum of the number of original data strings of each sub-block), and the remaining number of aggregated original data strings is initialized to 0 and the symbol number is 1. Taking the original data string count table TB shown in Figure 6 as an example, if four sub-blocks with 26, 52, 78 and 104 data bits per symbol are used for aggregated downlink transmission, then the original data string count list of these sub-blocks is the column in the original data string count table TB corresponding to 26, 52, 78 and 104 data bits per symbol, respectively, and the aggregated original data string count list is the sum of the above columns (for example, the original data string counts of these four sub-blocks are 0, 1, 2 and 2, respectively, and the aggregated original data string count in the aggregated original data string count list is 0+1+2+2=5).

[0027] Next, operation S704 is performed, increasing the remaining number of aggregated raw data strings by the number of aggregated raw data strings of the current symbol (i.e., the th symbol). Then, operation S706 is performed to determine whether the current symbol is the last symbol, i.e., whether the symbol sequence number is equal to the number of symbols. If so, operation S708 is performed, increasing the number of symbols by , where is the maximum number of raw data strings that the processor can process per symbol, and recording that the subsequent extended symbols (i.e., the th to the th symbols) are non-idle symbols. Then, the aggregated symbol category determination method 700 ends. Conversely, if the current symbol is not the last symbol, operation S710 is performed to determine whether the remaining number of aggregated raw data strings is greater than or equal to the maximum number of raw data strings that the processor can process per symbol. If the result of operation S710 is that the number of remaining aggregated raw data strings is greater than or equal to the maximum number of raw data strings that the processor can process per symbol, then operation S712 is performed to record the next symbol (i.e., the th symbol) as a non-idle symbol, and operation S714 is performed to subtract the maximum number of raw data strings that the processor can process per symbol from the number of remaining aggregated raw data strings. Conversely, if the result of operation S710 is that the number of remaining aggregated raw data strings is less than the maximum number of raw data strings that the processor can process per symbol, then operation S716 is performed to determine whether the sum of the number of remaining aggregated raw data strings and the number of aggregated raw data strings of the next symbol (i.e., the th symbol) is greater than the maximum number of raw data strings that the processor can process per symbol. If the sum of the remaining aggregated original data strings and the number of aggregated original data strings of the next symbol (i.e., the 1st symbol) is greater than the maximum number of original data strings that the processor can process per symbol, then operations S712 and S714 are performed; otherwise, if the sum of the remaining aggregated original data strings and the number of aggregated original data strings of the next symbol (i.e., the 1st symbol) is not greater than the maximum number of original data strings that the processor can process per symbol, then operation S718 is performed, and the next symbol (i.e., the 1st symbol) is recorded as an idle symbol. After operation S714 or operation S718 is completed, operation S720 is performed to move to the next symbol (i.e., the symbol number is incremented by 1), and then operation S704 is returned to process the next symbol.

[0028] According to this disclosure, the wireless receiver device 200 uses an aggregate symbol category discrimination method 700 to obtain the category of each aggregate symbol, thereby determining whether the processor 230 enters or maintains an idle state during idle symbol periods and enters or maintains a wake-up state during non-idle symbol periods. Therefore, it can be ensured that the processor 230, which can process a maximum number of raw data strings per symbol, retrieves the maximum number of aggregated raw data strings from the memory unit 220 during each non-idle symbol period when in the wake-up state, so as to process the raw data in the shortest possible time, thereby optimizing processing performance.

[0029] Figures 8A and 8B are aggregated symbol category lists CTB1 and CTB2 of an example processor disclosed herein, where the maximum number of raw data strings processed per symbol is 6 and 8, the number of data bits per symbol in the first to fourth sub-blocks are 26, 52, 104, and 52 respectively, the number of symbols is 20, and the number of threshold bits and the number of bits in the raw data string are 256 and 64 respectively. The number of raw data strings output in the first to fourth sub-blocks can be obtained by performing a method 400 to count the number of raw data strings in the symbols. The total number of output raw data strings is the number of aggregated raw data strings per symbol, and the symbol category can be obtained by performing an aggregated symbol category discrimination method 700. As shown in Figures 8A and 8B, under the condition of receiving the same aggregated packet, in the aggregated symbol category list CTB1, 10 out of 23 symbols are idle symbols, while in the aggregated symbol category list CTB2, 13 out of 23 symbols are idle symbols. That is, a processor with a maximum processing capacity of 6 raw data strings per symbol is idle during the 10 idle symbols, while a processor with a maximum processing capacity of 8 raw data strings per symbol is idle during the 13 idle symbols. Therefore, the better the processor performance (the larger the maximum processing capacity of raw data strings per symbol), the more idle states the processor can have (i.e., the longer the total idle time), thus exhibiting better power consumption performance.

[0030] Figure 9 is a schematic flowchart of a data processing method 900 according to an embodiment of the present disclosure. The data processing method 900 can be used in the wireless receiver device 200 of Figure 2 or other suitable wireless receiver devices. For example, in an instance used in the wireless receiver device 200, the data processing method 900 can be performed by the processor 230.

[0031] In the data processing method 900, operation S902 is first performed to generate an aggregated symbol category list based on processor performance, number of symbols, and number of data bits per symbol in all sub-blocks. The aggregated symbol category list may contain category information indicating whether each symbol is an idle symbol (i.e., an idle symbol or a non-idle symbol). The aggregated symbol category list may be the aggregated symbol category list CTB1 shown in Figure 8A or the aggregated symbol category list CTB2 shown in Figure 8B, and it may be obtained by performing the method 400 for counting the number of original data strings in the symbols and the method 700 for determining the aggregated symbol category.

[0032] Next, operation S904 is performed to determine whether the current symbol is an idle symbol based on the aggregate symbol category list. If so, operation S906 is performed to enter the idle state, and a wake-up timer is set according to the aggregate symbol category list (the wake-up time of the processor from the idle state is determined by the order in which the next non-idle symbol appears). When the wake-up timer expires, operation S908 is performed, the processor enters the wake-up state, and then operation S910 is performed to obtain the original data string from the memory unit for data parsing processing. Conversely, if the determination result of operation S904 is that the current symbol is a non-idle symbol, operation S910 is performed directly. After operation S910 is completed, operation S912 is performed to determine whether the current symbol is the last symbol based on the aggregate symbol category list. If the current symbol is determined to be the last symbol, operation S914 is performed, and the processor completes the data parsing processing. Conversely, if it is determined that the current symbol is not the last symbol, then operation S916 is performed to move to the next symbol and return to operation S904.

[0033] Figures 10A and 10B are the aggregate symbol category lists RTB1 and RTB2 of the processor in the first comparative example, with a maximum number of raw data strings processed per symbol being 6 and 8, respectively; the number of data bits per symbol in the 1st to 4th sub-blocks being 26, 52, 104, and 52, respectively; the number of symbols being 20; and the number of threshold bits and the number of bits in the raw data string being 256 and 64, respectively. During each symbol period, the processor polls the memory unit to retrieve the raw data temporarily stored in the memory unit. As shown in Figures 10A and 10B, in polling mode, each symbol is a non-idle symbol. Therefore, regardless of whether there is temporary raw data in the memory unit and regardless of the processor's performance, the processor remains in a wake-up state during each symbol period, which does not have any power reduction effect.

[0034] Figures 11A and 11B are the aggregate symbol category lists RTB3 and RTB4 of the processor in the second comparative example, respectively, when the maximum number of raw data strings processed per symbol is 6 and 8, the number of data bits per symbol in the 1st to 4th sub-blocks is 26, 52, 104, and 52, respectively, the number of symbols is 20, and the number of threshold bits and the number of bits of the raw data string are 256 and 64, respectively. In the second comparative example, if any raw data string is output in any sub-block from the 1st to the 4th sub-block during the current symbol period, the next symbol is a non-idle symbol. Conversely, if no raw data string is output in any sub-block from the 1st to the 4th sub-block during the current symbol period, the next symbol is an idle symbol. That is, the processor determines whether to enter the wake-up state or the idle state based on whether raw data is written to the memory unit during the period of each symbol. For example, as shown in Figure 11A, the number of raw data strings written to the memory cell during the 8th symbol period is 0, so the processor is idle during the 9th symbol period. During the 9th symbol period, the number of raw data strings written to the memory cell is 4, not 0, so the processor is awake during the 10th symbol period. Comparing Figures 8A, 8B, 11A, and 11B, it can be seen that the processor of this disclosed embodiment can have more idle time, thereby achieving better power consumption performance.

[0035] As can be seen from the above description, this disclosure improves power consumption performance by waking up the processor when the raw data after decoding accumulated in the memory unit reaches a considerable amount, so as to access the memory unit and obtain the raw data for data parsing and processing, while the processor is idle at other times.

[0036] Although this disclosure has been disclosed above with reference to embodiments, it is not intended to limit this disclosure. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0006] To better understand the embodiments and their advantages, the following description is made in conjunction with the accompanying drawings, in which: Figure 1 is a schematic diagram of a wireless communication system according to an embodiment of the present disclosure; Figure 2 is a circuit block diagram of a wireless receiver device according to an embodiment of the present disclosure; Figure 3 is an example of packet decoding processing using the wireless receiver device of Figure 2; Figure 4 is a flowchart illustrating a method for counting the number of original data strings in a symbol according to an embodiment of the present disclosure; Figures 5A and 5B are examples of processor states under different numbers of data bits per symbol and the same number of symbols; Figure 6 shows a table of the number of original data strings for a specific number of symbols and the number of data bits per symbol; Figure 7 is a flowchart illustrating a method for classifying aggregate symbols according to an embodiment of the present disclosure; Figures 8A and 8B are lists of aggregate symbol classes under different processor performances according to an example of the present disclosure; Figure 9 is a flowchart illustrating a data processing method according to an embodiment of the present disclosure. Figures 10A and 10B are lists of aggregate symbol categories under different processor performances in the first comparative example; and Figures 11A and 11B are lists of aggregate symbol categories under different processor performances in the second comparative example. [Biomaterial Storage]

[0038] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A wireless receiver device comprising: a decoder for decoding an aggregated packet during a plurality of symbols to obtain raw data, the aggregated packet having a plurality of sub-blocks; a memory unit for temporarily storing the raw data; and a processor configured to perform the following operations: aggregating each of the plurality of sub-blocks into a list of raw data strings output by the plurality of symbols to generate an aggregated raw data string count list; and incrementing the remaining aggregated raw data string count into the aggregated raw data string count list corresponding to the aggregated raw data string count of the current symbol of the plurality of symbols. If the number of remaining aggregated raw data strings is greater than or equal to the maximum number of raw data strings that one of the processors can process per symbol, then if so, the next symbol relative to the current symbol is recorded as a non-idle symbol accessing the memory unit. If not, then it is further determined whether the sum of the number of remaining aggregated raw data strings and the number of aggregated raw data strings of the next symbol is greater than the maximum number of raw data strings that can be processed per symbol. If the sum of the number of remaining aggregated raw data strings and the number of aggregated raw data strings of the next symbol is greater than the maximum number of raw data strings that can be processed per symbol, then the next symbol is recorded as a non-idle symbol. If not, then the next symbol is recorded as an idle symbol that does not access the memory unit.

2. The wireless receiver device as claimed in claim 1, wherein the processor is further configured to record that at least one subsequent extended symbol of the last symbol is a non-idle symbol when the current symbol is the last symbol of one of the plurality of symbols.

3. The wireless receiver device as described in claim 2, wherein the number of symbols of the at least one extended symbol is , where is the number of the remaining aggregated raw data strings, is the maximum number of raw data strings processed per symbol, and is a ceiling function operation.

4. The wireless receiver device as claimed in claim 1, wherein the processor is further configured to retrieve a maximum number of aggregated raw data strings from the memory unit during a period of each of the non-idle symbols, wherein is the maximum number of raw data strings processed per symbol.

5. The wireless receiver device as described in claim 1, wherein the maximum number of raw data strings processed per symbol is 6 or 8.

6. The wireless receiver device as described in claim 1, wherein the plurality of sub-blocks is 4 sub-blocks.

7. The wireless receiver device as claimed in claim 1, wherein the number of data bits per symbol in each of the plurality of sub-blocks is 13, 26, 52, 78, 104, 156 or 208.

8. A method for classifying aggregated symbols, applicable to a wireless receiver device, the method comprising: decoding an aggregated packet during a plurality of symbols to obtain original data, the aggregated packet having a plurality of sub-blocks; temporarily storing the original data in a memory unit of the wireless receiver device; and aggregating each of the plurality of sub-blocks into a list of the number of original data strings output by the plurality of symbols to generate an aggregated original data string count list; and adding the remaining aggregated original data string count to the aggregated original data string count list corresponding to the aggregated original data string count of the current symbol of the plurality of symbols; If the number of remaining aggregated raw data strings is greater than or equal to the maximum number of raw data strings that one of the processors in the wireless receiver device can process per symbol, then if so, the next symbol relative to the current symbol is recorded as a non-idle symbol that accesses the memory unit. If not, then it is further determined whether the sum of the number of remaining aggregated raw data strings and the number of aggregated raw data strings of the next symbol is greater than the maximum number of raw data strings that can be processed per symbol. If the sum of the number of remaining aggregated raw data strings and the number of aggregated raw data strings of the next symbol is greater than the maximum number of raw data strings that can be processed per symbol, then the next symbol is recorded as a non-idle symbol. If not, then the next symbol is recorded as an idle symbol that does not access the memory unit.

9. The aggregate symbol category determination method as described in claim 8, wherein the processor is further configured to record that at least one subsequent extended symbol of the last symbol is a non-idle symbol when the current symbol is the last symbol of one of the plurality of symbols.

10. The aggregation symbol category discrimination method as described in claim 9, wherein the number of symbols of the at least one extended symbol is , where is the number of the remaining aggregated original data strings, is the maximum number of original data strings processed per symbol, and is an upper rounding function operation.

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