Semiconductor device

Abstract

A semiconductor device includes a substrate, a semiconductor stack structure, a gate structure, a source, a drain, and a charge trapping suppression structure. The semiconductor stack structure is disposed on the substrate. The gate structure is disposed on the semiconductor stack structure. The source and drain are disposed on opposite sides of the gate structure. The charge trapping suppression structure is disposed between the gate structure and the drain. The charge trapping suppression structure includes a p-type semiconductor layer and a conductive metal layer. The p-type semiconductor layer is disposed on the semiconductor stack structure. The conductive metal layer is disposed on the semiconductor stack structure and laterally connected to the p-type semiconductor layer. The contact interface between the conductive metal layer and the p-type semiconductor layer is configured as an ohmic contact, and the contact interface between the conductive metal layer and the semiconductor stack structure is configured as an ohmic contact.

Claims

1. A semiconductor device, comprising: Base; A semiconductor stack structure is disposed on the substrate; A gate structure is disposed on the semiconductor stack structure, wherein the gate structure includes: a metal gate disposed on the semiconductor stack structure; and a p-type semiconductor gate disposed between the metal gate and the semiconductor stack structure; a source and a drain disposed on opposite sides of the gate structure; and a charge trapping suppression structure disposed between the gate structure and the drain, wherein the charge trapping suppression structure includes: a p-type semiconductor layer disposed on the semiconductor stack structure; and a conductive metal layer disposed on the semiconductor stack structure and laterally connected to the p-type semiconductor layer, wherein the contact interface between the conductive metal layer and the p-type semiconductor layer is configured as an ohmic contact, and the contact interface between the conductive metal layer and the semiconductor stack structure is configured as an ohmic contact, wherein the p-type semiconductor gate is shared with the p-type semiconductor layer of the charge trapping suppression structure, such that the conductive metal layer of the charge trapping suppression structure is in direct contact with the p-type semiconductor gate.

2. The semiconductor device of claim 1, wherein the material of the p-type semiconductor layer comprises p-type gallium nitride.

3. The semiconductor device of claim 1, wherein the conductive metal layer is located between the p-type semiconductor layer and the drain.

4. The semiconductor device of claim 1, wherein the charge trapping suppression structure is electrically floating.

5. The semiconductor device of claim 1, wherein the charge trapping suppression structure has a strip structure or an island structure.

6. The semiconductor device of claim 1, wherein the conductive metal layer further extends to the top surface of the p-type semiconductor layer.

7. The semiconductor device of claim 1, wherein the p-type semiconductor layer further extends to the top surface of the conductive metal layer.

8. The semiconductor device of claim 1, wherein the semiconductor stack structure comprises: A first semiconductor layer is disposed on the substrate, wherein the first semiconductor layer comprises gallium nitride; A second semiconductor layer is disposed on the first semiconductor layer, wherein the second semiconductor layer comprises aluminum gallium nitride, and wherein an ohmic contact is formed between the conductive metal layer and the second semiconductor layer.

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