Content addressable memory with split search

Abstract

This invention relates to a content-addressable memory with a phased search function. The content-addressable memory includes an array of memory cells. In the memory cell array, a plurality of memory cells in a first column store stored data, and the plurality of memory cells in the first column are connected to a matching line. Furthermore, the plurality of memory cells in the first column are divided into multiple groups. During a first search phase, the memory cells in the first group are searched. During a second search phase, the memory cells in the second group are searched. When the stored data matches the search data, the matching line is at a first logic level in both the first and second search phases. When the stored data does not match the search data, the matching line is at a second logic level in either the first or second search phase.

Claims

1. A content-addressable memory, comprising: A memory cell array, a first column of the memory cell array including: a first content-addressable memory cell and a second content-addressable memory cell, the first content-addressable memory cell storing a first data bit, the second content-addressable memory cell storing a second data bit, and the first stored data including the first data bit and the second data bit; wherein the first content-addressable memory cell is connected to a first match line, a first word line, a first bit line, a first inverted bit line, a first search line, a first inverted search line, and a first select line; and the second content-addressable memory cell is connected to the first match line, the first word line, a second bit line, a second inverted bit line, a second search line, a second inverted search line, and a second select line; A search data receiver receives search data, the search data including a first search bit and a second search bit; and a switching controller is connected to the search data receiver, the first selection line, and the second selection line; wherein, in a first search phase, the first selection line operates, the first content-addressable memory cell is selected, the switching controller transmits the first search bit to the first search line, and the switching controller transmits the inverted first search bit to the first inverted search line; and, in a second search phase, the second selection line operates, the second content-addressable memory cell is selected, the switching controller transmits the second search bit to the second search line, and the switching controller transmits the inverted second search bit to the second inverted search line; wherein, when the first stored data matches the search data, the first matching line is a first logic level in both the first search phase and the second search phase; Wherein, when the first stored data does not match the search data, the first matching line is a second logic level in the first search phase; or, the first matching line is the second logic level in the second search phase.

2. The content-addressable memory as described in claim 1, wherein a second column of the memory cell array includes: A third content-addressable memory cell and a fourth content-addressable memory cell, the third content-addressable memory cell storing a third data bit, the fourth content-addressable memory cell storing a fourth data bit, and a second stored data including the third data bit and the fourth data bit; wherein, the third content-addressable memory cell is connected to a second match line, a second word line, the first bit line, the first inverted bit line, the first search line, and the first inverted search line; the fourth content-addressable memory cell is connected to the second match line, the second word line, the second bit line, the second inverted bit line, the second search line, and the second inverted search line; and, the third content-addressable memory cell is coupled to the first select line and the fourth content-addressable memory cell is coupled to the second select line.

3. The content-addressable memory as described in claim 2, wherein when the second stored data matches the search data, the second matching line is at the first logical level in both the first search phase and the second search phase; and when the second stored data does not match the search data, the second matching line is at the second logical level in the first search phase, or the second matching line is at the second logical level in the second search phase.

4. The content-addressable memory as described in claim 2, wherein the first content-addressable memory cell, the second content-addressable memory cell, the third content-addressable memory cell, and the fourth content-addressable memory cell are binary content-addressable memory cells.

5. The content-addressable memory as described in claim 2, wherein the first content-addressable memory cell comprises: A first storage circuit is connected to the first word line, the first bit line, the first inverted bit line, a first data line, and a first inverted data line, wherein the first data bit in the first stored data is stored in the first storage circuit; a first comparison circuit is connected to the first data line, the first inverted data line, the first matching line, the first search line, the first inverted search line, and a first node; and a first pull circuit is connected to the first node and the first select line.

6. The content addressable memory as described in claim 5, wherein the first comparison circuitry includes: A first transistor, a second transistor, a third transistor, and a fourth transistor; a first drain / source terminal of the first transistor is connected to the first matching line, and a gate terminal of the first transistor is connected to the first data line; a first drain / source terminal of the second transistor is connected to the first matching line, and a gate terminal of the second transistor is connected to the first inverting data line; a first drain / source terminal of the third transistor is connected to a second drain / source terminal of the first transistor, a second drain / source terminal of the third transistor is connected to the first node, and a gate terminal of the third transistor is connected to the first search line; and a first drain / source terminal of the fourth transistor is connected to a second drain / source terminal of the second transistor, a second drain / source terminal of the fourth transistor is connected to the first node, and a gate terminal of the fourth transistor is connected to the first inverting search line.

7. The content-addressable memory as described in claim 6, wherein the first pull circuit includes: A fifth transistor; A first drain / source terminal of the fifth transistor is connected to the first node, a second drain / source terminal of the fifth transistor is connected to a supply voltage, and a gate terminal of the fifth transistor is connected to the first select line.

8. The content-addressable memory as described in claim 5, wherein the second content-addressable memory cell comprises: A second storage circuit is connected to the first word line, the second bit line, the second inverted bit line, a second data line, and a second inverted data line, wherein the second data bit in the first stored data is stored in the second storage circuit; a second comparison circuit is connected to the second data line, the second inverted data line, the first matching line, the second search line, the second inverted search line, and a second node; and a second pull circuit is connected to the second node and the second select line.

9. The content-addressable memory as described in claim 8, wherein the third content-addressable memory cell includes: A third storage circuit is connected to the second word line, the first bit line, the first inverted bit line, a third data line, and a third inverted data line, wherein the third data bit in the second stored data is stored in the third storage circuit; and a third comparison circuit is connected to the third data line, the third inverted data line, the second matching line, the first search line, the first inverted search line, and the first node; wherein the third comparison circuit is coupled to the first select line via the first pull circuit.

10. The content-addressable memory as described in claim 9, wherein the fourth content-addressable memory cell includes: A fourth storage circuit is connected to the second word line, the second bit line, the second inverted bit line, a fourth data line, and a fourth inverted data line, wherein the fourth data bit in the second stored data is stored in the fourth storage circuit; and a fourth comparison circuit is connected to the fourth data line, the fourth inverted data line, the second matching line, the second search line, the second inverted search line, and the second node; wherein the fourth comparison circuit is coupled to the second select line via the second pull circuit.

11. A content-addressable memory, comprising: A memory cell array, a first column of the memory cell array including: a first content-addressable memory cell and a second content-addressable memory cell; wherein the first content-addressable memory cell and the second content-addressable memory cell store a first stored data; wherein the first content-addressable memory cell is connected to a first match line, a first word line, a second word line, a first bit line, a first inverted bit line, a first search line, a first inverted search line, and a first select line; and the second content-addressable memory cell is connected to the first match line, the first word line, the second word line, a second bit line, a second inverted bit line, a second search line, a second inverted search line, and a second select line; A search data receiver receives search data, the search data including a first search bit and a second search bit; and a switching controller is connected to the search data receiver, the first selection line, and the second selection line; wherein, in a first search phase, the first selection line operates, the first content-addressable memory cell is selected, the switching controller transmits the first search bit to the first search line, and the switching controller transmits the inverted first search bit to the first inverted search line; and, in a second search phase, the second selection line operates, the second content-addressable memory cell is selected, the switching controller transmits the second search bit to the second search line, and the switching controller transmits the inverted second search bit to the second inverted search line; wherein, when the first stored data matches the search data, the first matching line is a first logic level in both the first search phase and the second search phase; Wherein, when the first stored data does not match the search data, the first matching line is a second logic level in the first search phase; or, the first matching line is the second logic level in the second search phase.

12. The content-addressable memory as described in claim 11, wherein a second column of the memory cell array includes: A third content-addressable memory cell and a fourth content-addressable memory cell; wherein the third content-addressable memory cell and the fourth content-addressable memory cell store a second stored data; wherein the third content-addressable memory cell is connected to a second match line, a third word line, a fourth word line, the first bit line, the first anti-phase bit line, the first search line and the first anti-phase search line; the fourth content-addressable memory cell is connected to the second match line, the third word line, the fourth word line, the second word line, the second bit line, the second anti-phase bit line, the second search line and the second anti-phase search line; and the third content-addressable memory cell is coupled to the first select line and the fourth content-addressable memory cell is coupled to the second select line.

13. The content-addressable memory as described in claim 12, wherein when the second stored data matches the search data, the second matching line is at the first logical level in both the first search phase and the second search phase; and when the second stored data does not match the search data, the second matching line is at the second logical level in the first search phase, or the second matching line is at the second logical level in the second search phase.

14. The content-addressable memory as described in claim 12, wherein the first content-addressable memory cell, the second content-addressable memory cell, the third content-addressable memory cell, and the fourth content-addressable memory cell are ternary content-addressable memory cells.

15. The content-addressable memory as described in claim 12, wherein the first content-addressable memory cell comprises: A first storage circuit connected to the first word line, the first bit line, and the first inverting bit line, wherein a first data bit of the first stored data is stored in the first storage circuit; a second storage circuit connected to the second word line, the first bit line, and the first inverting bit line, wherein a first acknowledge bit of the first stored data is stored in the second storage circuit; a first comparison circuit receiving the first data bit and the first acknowledge bit, and the first comparison circuit being connected to the first matching line, the first search line, the first inverting search line, and a first node; and a first pull circuit connected to the first node and the first select line.

16. The content-addressable memory as described in claim 15, wherein the first comparison circuitry includes: A first transistor, a second transistor, a third transistor, and a fourth transistor; a first drain / source terminal of the first transistor is connected to the first matching line, and a gate terminal of the first transistor receives the first data bit; a first drain / source terminal of the second transistor is connected to the first matching line, and a gate terminal of the second transistor receives the first acknowledged bit; a first drain / source terminal of the third transistor is connected to a second drain / source terminal of the first transistor, a second drain / source terminal of the third transistor is connected to the first node, and a gate terminal of the third transistor is connected to the first search line; and a first drain / source terminal of the fourth transistor is connected to a second drain / source terminal of the second transistor, a second drain / source terminal of the fourth transistor is connected to the first node, and a gate terminal of the fourth transistor is connected to the first inverting search line.

17. The content-addressable memory as described in claim 16, wherein the first pull circuit includes: A fifth transistor; A first drain / source terminal of the fifth transistor is connected to the first node, a second drain / source terminal of the fifth transistor is connected to a supply voltage, and a gate terminal of the fifth transistor is connected to the first select line.

18. The content-addressable memory as described in claim 15, wherein the second content-addressable memory cell comprises: A third storage circuit connected to the first word line, the second bit line, and the second inverted phase bit line, wherein a second data bit in the first stored data is stored in the third storage circuit; a fourth storage circuit connected to the second word line, the second bit line, and the second inverted phase bit line, wherein a second acknowledge bit in the first stored data is stored in the fourth storage circuit; a second comparison circuit receiving the second data bit and the second acknowledge bit, and the second comparison circuit being connected to the first matching line, the second search line, the second inverted search line, and a second node; and a second pull circuit connected to the second node and the second select line.

19. The content-addressable memory as described in claim 18, wherein the third content-addressable memory cell comprises: A fifth storage circuit, connected to the third word line, the first bit line, and the first inverted phase line, wherein a third data bit in the second stored data is stored in the fifth storage circuit; a sixth storage circuit, connected to the fourth word line, the first bit line, and the first inverted phase line, wherein a third attention bit in the second stored data is stored in the sixth storage circuit; and a third comparison circuit, receiving the third data bit and the third attention bit, and connected to the second matching line, the first search line, the first inverted search line, and the first node; wherein the third comparison circuit is coupled to the first select line via the first pull circuit.

20. The content-addressable memory as described in claim 19, wherein the fourth content-addressable memory cell includes: A seventh storage circuit, connected to the third word line, the second bit line, and the second inverted phase line, wherein a fourth data bit in the second stored data is stored in the seventh storage circuit; an eighth storage circuit, connected to the fourth word line, the second bit line, and the second inverted phase line, wherein a fourth acknowledge bit in the second stored data is stored in the eighth storage circuit; and a fourth comparison circuit, receiving the fourth data bit and the fourth acknowledge bit, and connected to the second matching line, the second search line, the second inverted search line, and the second node; wherein the fourth comparison circuit is coupled to the second select line via the second pull circuit.

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