Semiconductor device and method for fabricating the same

TWI942444BActive Publication Date: 2026-10-11UNITED MICROELECTRONICS CORP
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Patent Information

Application Number
TW114131227
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-08-15
Publication Date
2026-10-11
Estimated Expiration
2045-08-14

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    Figure TWG2TB001915621_003
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Abstract

This invention discloses a method for manufacturing a semiconductor device, which mainly involves first forming an intermetallic dielectric layer on a substrate, then forming a first metal interconnect and a second metal interconnect within the intermetallic dielectric layer, forming a first pixel unit on the first metal interconnect and a second pixel unit on the second metal interconnect, and then forming a vent between the first pixel unit and the second pixel unit, wherein the bottom surface of the vent is lower than the top surface of the first metal interconnect.
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Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: forming an intermetallic dielectric layer on a substrate; forming a first metal interconnect and a second metal interconnect within the intermetallic dielectric layer; forming a first pixel unit on the first metal interconnect and a second pixel unit on the second metal interconnect; and forming a vent between the first pixel unit and the second pixel unit, wherein the bottom surface of the vent is lower than the top surface of the first metal interconnect.

2. The method as described in claim 1, further comprising: forming a first masking layer on the intermetallic dielectric layer; forming a first metal interconnect and a second metal interconnect within the intermetallic dielectric layer and the first masking layer; forming a first heating structure on the first metal interconnect and a second heating structure on the second metal interconnect; forming a first dielectric layer surrounding the first heating structure and the second heating structure; forming a mirror layer on the first heating structure and the second heating structure; forming a first phase transition structure and a second phase transition structure on the mirror layer; forming a sidewall beside the first phase transition structure and the second phase transition structure; removing a portion of the sidewall, a portion of the first dielectric layer, and a portion of the first masking layer; and forming a second dielectric layer on the first phase transition structure, the second phase transition structure, and the pore between the first phase transition structure and the second phase transition structure.

3. The method as described in claim 2, wherein the first heating structure comprises: a heating layer; and a second covering layer disposed on the heating layer.

4. The method as described in claim 3, wherein the heating layer comprises metal.

5. The method as described in claim 2, wherein the first phase conversion structure comprises: a third masking layer; a phase conversion layer disposed on the third masking layer; and a fourth masking layer disposed on the phase conversion layer.

6. The method as described in claim 5, wherein the phase conversion layer comprises germanium antimony telluride (GST).

7. The method as described in claim 1, wherein the pore comprises a teardrop shape.

8. The method as described in claim 1, wherein the pore comprises an inverted funnel shape.

9. A semiconductor device, characterized in that it comprises: an intermetallic dielectric layer disposed on a substrate; a first metal interconnect and a second metal interconnect disposed within the intermetallic dielectric layer; a first pixel unit disposed on the first metal interconnect; a second pixel unit disposed on the second metal interconnect; and a vent disposed between the first pixel unit and the second pixel unit, wherein the bottom surface of the vent is lower than the top surface of the first metal interconnect.

10. The semiconductor device as described in claim 9 further comprises: a first shielding layer disposed on the inter-metal dielectric layer; the first metal interconnect and the second metal interconnect disposed within the inter-metal dielectric layer and the first shielding layer; a first heating structure disposed on the first metal interconnect; a second heating structure disposed on the second metal interconnect; a first dielectric layer surrounding the first heating structure and the second heating structure; a mirror layer disposed on the first heating structure and the second heating structure; a first phase transition structure disposed on the first heating structure; and a second phase transition structure disposed on the second heating structure.

11. The semiconductor device as described in claim 10 further includes a second dielectric layer disposed on the first phase transition structure and the second phase transition structure and surrounding the vent.

12. The semiconductor device as described in claim 10, wherein the first heating structure comprises: a heating layer; and a second shielding layer disposed on the heating layer.

13. The semiconductor device as described in claim 12, wherein the heating layer comprises metal.

14. The semiconductor device as described in claim 10, wherein the first phase conversion structure comprises: a third masking layer; a phase conversion layer disposed on the third masking layer; and a fourth masking layer disposed on the phase conversion layer.

15. The semiconductor device as described in claim 14, wherein the phase conversion layer comprises germanium antimony telluride (GST).

16. The semiconductor element as described in claim 9, wherein the pore comprises a teardrop shape.

17. The semiconductor element as described in claim 9, wherein the pore comprises an inverted funnel shape.

Citation Information

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