Method for making semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device using double-sided molding technology. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, the second surface of the substrate being non-planar; forming a coating on the second surface of the substrate such that a first surface of the coating is planar and faces away from the second surface of the substrate; mounting a first electronic component on the first surface of the substrate; and forming a first sealant on the first surface of the substrate to cover the first electronic component.

Description

[Technical Field]

[0001] This invention relates generally to semiconductor technology, and more specifically to a method for manufacturing a semiconductor device using double-sided molding technology. [Previous Technology]

[0002] As consumers demand smaller, faster, and higher-performing electronics, and increasingly more functionality packaged into a single device, the semiconductor industry has faced the challenge of complex integration. One solution is System-in-Package (SiP). A SiP is a functional electronic system or subsystem that contains two or more heterogeneous semiconductor dies, such as logic chips, memory, integrated passive devices, RF filters, sensors, heat sinks, or antennas, within a single package. Recently, SiP has utilized Double Side Molding (DSM) technology to further reduce the overall package size.

[0003] Typically, DSM technology uses substrates with cavities or copper pillars. However, substrates with cavities or copper pillars are susceptible to damage during surface mount processes, so protective films are usually attached to the substrate to reduce potential damage (e.g., cracks). However, significant yield losses still occur in manufacturing processes using such protective films.

[0004] Therefore, it is necessary to further improve the double-sided molding process. [Summary of the Invention]

[0005] The purpose of this invention is to provide a method for manufacturing a semiconductor device with high reliability.

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device using double-sided molding technology is provided. The method may include: providing a substrate having a first surface and a second surface opposite to the first surface, the second surface of the substrate being non-planar; forming a coating on the second surface of the substrate such that a first surface of the coating is planar and facing away from the second surface of the substrate; mounting a first electronic component on the first surface of the substrate; and forming a first sealant on the first surface of the substrate to cover the first electronic component.

[0007] According to another aspect of the present invention, a semiconductor device is provided. This semiconductor device can be manufactured using the method described above.

[0008] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, and not intended to limit the invention. Furthermore, the drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the specification, serve to explain the principles of the invention.

Implementation Method

[0014] The following detailed description of exemplary embodiments of the present invention is taken with reference to the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which the invention may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the invention. Those skilled in the art can further utilize other embodiments of the invention and make logical, mechanical, and other changes without departing from the spirit or scope of the invention. Therefore, the reader of the following detailed description should not interpret it in a restrictive manner, and the scope of the embodiments of the invention is limited only to the claims.

[0015] In this invention, unless otherwise expressly stated, the singular is used to include the plural. In this invention, unless otherwise stated, the use of "or" means "and / or". Furthermore, the use of the term "comprising" and other forms such as "including" and "containing" is not limiting. Furthermore, unless otherwise expressly stated, terms such as "element" or "component" cover elements and components comprising one unit, as well as elements and components comprising more than one subunit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the described subject matter.

[0016] As used herein, spatially relative terms, such as “below,” “under,” “above,” “over,” “upper,” “upper side,” “lower side,” “left side,” “right side,” “horizontal,” “vertical,” “side,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the directions depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0017] Figure 1 shows a cross-sectional view of a semiconductor device 100 formed using double-sided molding (DSM) technology.

[0018] As shown in FIG. 1, the semiconductor device 100 includes a substrate 110 having a top surface 110a and a bottom surface 110b. The substrate 110 also includes a redistribution structure (RDS) 115 having one or more dielectric layers and one or more conductive layers located between and through the dielectric layers. A plurality of conductive pillars (e.g., copper pillars) 136 are formed on the bottom surface 110b of the substrate 110 and electrically connected to corresponding conductive patterns in the RDS 115. A top electronic component 125 is mounted on the top surface 110a of the substrate 110, and a bottom electronic component 135 is mounted on the bottom surface 110b. A top sealant 120 and a bottom sealant 130 are formed on the top surface 110a and the bottom surface 110b of the substrate 110, respectively, to protect the top electronic component 125 and the bottom electronic component 135 from external factors and contaminants. For each conductive post 136, a bump 138 (e.g., a solder ball) is further formed on the exposed surface of the conductive post 136 to enable connection of the internal circuitry of the semiconductor device 100 to an external device or system.

[0019] The components on the top surface 110a and bottom surface 110b are typically formed in two steps. In one example, the top electronic component 125 is first mounted on the top surface 110a of the substrate 110, and then the substrate 110 is loaded into a molding apparatus to form the top sealant 120. Since the substrate 110 may be attached to the mold of the molding apparatus, and the conductive post 136 is in contact with the mold, the conductive post 136 is likely to be damaged during the molding process. In addition, the substrate 110 may warp due to the high pressure and high temperature during the molding process.

[0020] In another example, the bottom electronic component 135 and the bottom sealant 130 are first formed on the bottom surface 110b of the substrate 110, and then the top electronic component 125 is mounted on the top surface 110a of the substrate 110. Sometimes, a protective film such as UV tape may be applied to the bottom surface 110b before the top sealant 120 molding process to prevent the conductive post 136 from directly contacting the mold of the molding device. However, due to the high strip warpage of the substrate 110 and / or the protective film caused by the molding process, the yield of the device manufactured in this way may still be reduced by about 3% or more.

[0021] Similar problems also occur when using a substrate with a cavity in DSM technology and covering it with a similar protective film.

[0022] To solve at least one of the above-mentioned problems, one aspect of the present invention provides a method for manufacturing a semiconductor device. In this method, a coating is formed on the bottom surface of a substrate to cover conductive pillars (or fill cavities), and then top electronic components and a top sealant can be formed on the top surface of the substrate. This coating not only protects the conductive pillars but also prevents warping of the substrate during the molding process of the top surface of the substrate.

[0023] Referring to Figures 2A to 2L, cross-sectional views are shown of various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention. This method can be used to manufacture the semiconductor device shown in Figure 1, or any other similar device using DSM technology. The method will now be described in more detail with reference to Figures 2A to 2L.

[0024] As shown in FIG. 2A, a substrate 210 is provided. The substrate 210 has a first surface 210a and a second surface 210b opposite to the first surface 210a. In some embodiments, the substrate 210 may be a laminated interlayer, a PCB, a wafer-form, a strip interlayer, a lead frame, or any other suitable substrate. The substrate 210 may include one or more insulating or passivation layers, one or more conductive vias formed through the insulating layer, and one or more conductive layers formed above or between the insulating layers. The substrate 210 may include one or more laminated pre-impregnated polytetrafluoroethylene, FR-4, FR-1, CEM-1, or CEM-3 having a combination of phenolic cotton paper, epoxy resin, resin, woven glass, frosted glass, polyester, and other reinforcing fibers or fabrics. The insulating layer may comprise one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other materials with similar insulating and structural properties. The substrate 210 may also be a multilayer flexible laminate, ceramic, copper-clad laminate, glass, or a semiconductor wafer, which may include an active surface containing one or more transistors, diodes, and other circuit components to realize analog or digital circuitry.

[0025] In the example shown in FIG. 2A, the substrate 210 may include a redistribution structure (RDS) 215 having one or more dielectric layers and one or more conductive layers located between and through the dielectric layers. The conductive layers may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically on the RDS. The RDS 215 may include one or more of Al, Cu, Sn, Ni, Au, Ag, or any other suitable conductive material. It is understood that the RDS 215 may be implemented in a variety of structures and types, but aspects of the invention are not limited to the examples described above.

[0026] Still referring to FIG. 2A, a plurality of conductive pillars 236 are formed on the second surface 210b of the substrate 210. The conductive pillars 236 may include one or more of Cu, Al, Sn, Ni, Au, Ag, or other suitable conductive materials. In the example, each conductive pillar 236 is a copper pillar, but aspects of this disclosure are not limited thereto. The conductive pillars 236 may be formed on the second surface 210b of the substrate 210 for electrically connecting redistribution structures in the substrate 210 to external devices. In the example, the conductive pillars 236 are formed by depositing (e.g., sputtering or electroplating) one or more layers of conductive material into openings in a mask layer. In other embodiments, another suitable metal deposition technique or surface mount technique may be used to form the conductive pillars 236.

[0027] It is understood that the substrate 210 and conductive pillar 236 shown in FIG. 2A are for illustrative purposes only and not for limitation. In some other embodiments, one or more electronic components (e.g., active devices such as semiconductor dies, semiconductor packages, discrete transistors, discrete diodes, etc., or passive devices such as capacitors, inductors, or resistors) may be attached to the second surface 210b of the substrate 210. The one or more electronic components may have a smaller height than the conductive pillar 236. The one or more electronic components may be attached to the second surface 210b of the substrate 210 before or after the conductive pillar 236 is formed, or may be attached to the second surface 210b of the substrate 210 together with the conductive pillar 236, which is not a limitation of the present invention.

[0028] Referring to Figures 2B and 2C, a coating 240 is formed on the second surface 210b of the substrate 210. The coating 240 can planarize the substrate 210 so that the substrate 210 will not experience stress concentration in subsequent processes.

[0029] In some embodiments, as shown in FIG2B, a coating apparatus 280 is provided. The coating apparatus 280 can be used to form a coating on a package. The coating apparatus 280 may include an upper mold 281a and a lower mold 281b. The lower mold 281b can be used to hold the coating material and the package to be coated. The upper mold 281a and the lower mold 281b can define the geometry of the coating material around the package. Pressure and heat can be applied to the coating material, and the upper mold 281a and the lower mold 281b can compress the coating material into a desired shape and / or geometry around the package. In some cases, the coating apparatus 280 may also include a movement control unit (not shown in FIG2B) to move the upper mold 281a downward, the lower mold 281b upward, or both simultaneously, depending on the requirements of the coating process. It is understood that the coating apparatus 280 shown in FIG2B is for illustrative purposes only and not for limitation.

[0030] Still referring to FIG. 2B, a substrate 210 is loaded into a coating apparatus 280, and a first surface 210a of the substrate 210 is attached to a lower mold 281b of the coating apparatus 280. A liquid solution 242 is provided on a second surface 210b of the substrate 210. In one example, the liquid solution 242 may include a silicone elastomer material and optional additives such as a curing agent or catalyst, and may be used to form a smooth silicone elastomer layer by a compression molding process. For example, the silicone elastomer may include polydimethylsiloxane (PDMS) or any other suitable silicone elastomer material. Subsequently, the upper mold 281a and the lower mold 281b may move close to each other to compress the liquid solution 242, and a compression process may be applied to the liquid solution 242. The upper mold 281a and lower mold 281b can compress silicone rubber around the conductive pillars 236 formed on the second surface 210b of the substrate 210 into the desired shape and / or geometry, and during compression, the silicone rubber can be cured in a temperature range of 100-170°C. After the silicone rubber has cured, the upper mold 281a and lower mold 281b are separated from each other, and the substrate 210 is removed from the coating equipment 280.

[0031] In another example, the liquid solution 242 may be a solution containing a resin material dissolved in an organic solvent and may be used to form a smooth resin layer by heat treatment. For example, the liquid solution 242 may include an epoxy coating compound (EMC), epoxy resin, polyurethane, and / or any other suitable resin material having sufficient mechanical strength, good adhesion to the encapsulated component, electrical resistance, low coefficient of thermal expansion, and / or high thermal stability. The upper mold 281a and lower mold 281b may then be moved close to each other to compress the liquid solution 242 and apply pressure and a heating process to the liquid solution 242. The heat and pressure within the coating apparatus 280 may be sufficient to harden the liquid solution 242. The upper mold 281a and lower mold 281b may compress the heated resin material (e.g., liquid and / or uncured resin material) around the conductive pillars 236 formed on the second surface 210b of the substrate 210 into the desired shape and / or geometry until the resin material hardens. After the liquid solution 242 has hardened and cured, the upper mold 281a and the lower mold 281b are separated from each other, and the substrate 210 is removed from the coating equipment 280.

[0032] As shown in FIG2C, after the substrate 210 is removed from the coating equipment, a coating 240 is formed on the second surface 210b of the substrate 210. Since the solution used in the coating process is liquid or flowable, the coating 240 can fill the tiny gaps between the multiple conductive pillars 236, and the top surface of the coating 240 is flat.

[0033] It is understood that the coating process described with reference to Figures 2B and 2C is for illustrative purposes only and not for limitation. In other embodiments, the coating may be formed by spin coating or other suitable processes.

[0034] Referring to FIG2D, the substrate 210 is flipped so that the first surface 210a faces upward, and one or more first electronic components 225 can then be mounted on the first surface 210a of the substrate 210, wherein the substrate 210 is supported on a platform or bracket via a coating 240.

[0035] In some embodiments, solder paste may be deposited or printed onto a top conductive pattern at locations on the redistribution structure 215 where a first electronic component 225 may be surface-mounted. The solder paste may be dispensed using jet printing, laser printing, pneumatics, needle transfer, photoresist masking, template printing, or other suitable processes. The first electronic component 225 may then be mounted on a first surface 210a, with the terminals of the first electronic component 225 contacting and resting on the solder paste. The solder paste may be reflowed to mechanically and electrically couple the first electronic component 225 to the top conductive pattern. The first electronic component 225 may include one or more semiconductor dies 221 and discrete devices 222. The first electronic component 225 may be a passive or active device as needed to implement any given electrical function within the semiconductor package to be formed. The first electronic component 225 may be an active device, such as a semiconductor die, semiconductor package, discrete transistor, discrete diode, etc. The first electronic component 225 may also be a passive device, such as a capacitor, inductor, or resistor.

[0036] Referring to FIG2E, a first sealant 220 is formed on a first surface 210a of a substrate 210 to cover a first electronic component 225.

[0037] For example, a molding process can be used to form the first sealant 220 on the first surface 210a of the substrate 210. In some other embodiments, the first sealant 220 can be formed using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable processes. The first sealant 220 can be made of a polymer composite material, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers, etc., but the scope of the invention is not limited thereto. The first sealant 220 can protect the first electronic component 225 from external components and contaminants. In some examples, the first sealant 220 can be planarized if desired.

[0038] Referring again to Figures 2F and 2G, the substrate 210 can be flipped over again, and then the coating 240 on the second surface 210b of the substrate 210 can be removed to expose the plurality of conductive pillars 236. The properties of the coating 240 ensure that it can be removed from the substrate 210, and the conductive pillars 236 may not fall off with the removal of the coating 240.

[0039] In the example shown in FIG. 2F, the substrate 210 is flipped so that the coating 240 faces upward. A de-taping tape 245 is attached to the coating 240 and used to peel the coating 240 from the second surface 210b of the substrate 210. The peeling process can be performed manually or by a peeling system. However, the invention is not limited thereto. In some other embodiments, the coating 240 can be removed from the second surface 210b of the substrate 210 using a laser ablation process or an etching process.

[0040] Subsequently, as shown in FIG2H, a second electronic component 235 is mounted on the second surface 210b of the substrate 210. For example, after removing the coating 240 from the second surface 210b of the substrate 210, some conductive patterns of the RDS 215 may be exposed. Solder paste may then be patterned on the exposed conductive patterns of the RDS 215, and the second electronic component 235 may be mounted on the second surface 210b of the substrate 210 via the solder paste surface. In the example shown in FIG2H, the second electronic component 235 is shown as a semiconductor die. In some other embodiments, multiple semiconductor dies or one or more discrete devices may be mounted on the second surface 210b of the substrate 210 via the solder paste surface. It can be seen that it is preferable to mount the second electronic component 235 after the formation and removal of the coating 240, because if the second electronic component 235 is mounted at an earlier stage, the coating 240 may fill the space between the second electronic component 235 and the substrate 210.

[0041] Referring to FIG. 2I, a second sealant 230 is formed on the second surface 210b of the substrate 210 to cover the plurality of conductive pillars 236 and the second electronic component 235. For example, the second sealant 230 may be non-conductive and environmentally protect the second electronic component 235 and the conductive pillars 236 from external components and contaminants. In some cases, the second sealant 230 may be formed using a process similar to the compression molding process used to form the first sealant 220. In some cases, the second sealant 230 may be formed using paste printing, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The second sealant 230 and the first sealant 220 may be made of the same material, such as epoxy resin. In some examples, the second sealant 230 may be planarized if desired.

[0042] Referring to FIG. 2J, the second sealant 230 can be polished to expose the top surface of each of the plurality of conductive pillars 236. In some embodiments, the thickness of the second sealant 230 and the conductive pillars 236 can be reduced and the polishing process can be used, such as a polishing operation of a polishing machine or other suitable chemical or mechanical polishing or etching process. The polishing process can remove a portion of the second sealant 230 so that the top surface of the second sealant 230 is coplanar with the top surface of the conductive pillar 236. In the example shown in FIG. 2J, the top surface of the conductive pillar 236 is substantially coplanar with the top surface of the second electronic component 235, so the top surface of the second electronic component 235 is also exposed outside the second sealant 230 after the polishing process. In some other examples, the top surface of the second electronic component 235 may be lower than the top surface of the conductive pillar 236, and the top surface of the second electronic component 235 may still be covered by the second sealant 230 after the polishing process.

[0043] Referring to FIG. 2K, bumps 238 are formed on the exposed surface of each conductive post 236. In some embodiments, conductive bump material may be deposited on the exposed surface of each conductive post 236 using one or any combination of processes such as evaporation, electroplating, electroless plating, droplet formation, or screen printing. The conductive bump material may include Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and optionally a flux solution. For example, the conductive bump material may be solder paste, and the solder paste may be printed onto the exposed surface of each conductive post 236. The conductive bump material may then be reflowed by heating it above its melting point to form conductive balls or bumps 238. Each bump 238 may cover the exposed surface of the corresponding conductive post 236. The bumps 238 may extend beyond the top surface of the second sealant 230 and enable the internal circuitry of the semiconductor device to be electrically connected to an external device or system. When the conductive bump material includes a flux solution, a flux removal operation can also be performed to remove the flux solution. In some other embodiments, the bump 238 can also be press-fitted or heat-press-fitted to the corresponding conductive post 236. The hemispherical bump 238 shown in FIG2K can represent one form of interconnect structure that can be formed on the conductive post 236. In other examples, the individual bumps 238 can be cylindrical bumps, microbumps, or other electrical interconnect structures.

[0044] Finally, referring to FIG. 2L, an electromagnetic interference (EMI) shielding layer 250 is formed, and the EMI shielding layer 250 may at least cover the top and side surfaces of the first sealant 220. In some embodiments, the EMI shielding layer 250 may be formed of copper, aluminum, iron, or any other material suitable for EMI shielding. In some embodiments, the EMI shielding layer 250 may be formed by spraying, electroplating, sputtering, or any other suitable metal deposition process. The EMI shielding layer 250 may be a conformal shield that follows the shape and / or contour of the first sealant 220, the substrate 210, and the second sealant 230. Specifically, as shown in FIG. 2L, the EMI shielding layer 250 covers the top and side surfaces of the first sealant 220, the side surface of the substrate 210, and the side surface of the second sealant 230. However, the bump 238, the bottom surface of the second sealant 230, and the bottom surface of the second electronic component 235 are exposed from the EMI shielding layer 250. The EMI shielding layer 250 can shield electronic components within a semiconductor device from EMI or other interference.

[0045] In some embodiments, in order to form multiple semiconductor devices simultaneously, the above steps can be performed on a strip-based substrate. After forming bumps on the conductive pillars, the strip-based substrate can be divided into individual semiconductor devices, and then an EMI shielding layer can be formed on each individual semiconductor device.

[0046] Referring to Figures 3A-3K, cross-sectional views are shown of various steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. Unlike the embodiment described with reference to Figures 2A-2L, the substrate used in this embodiment may have one or more cavities that, similar to the conductive pillars shown in Figures 2A-2L, cause the surface of the substrate to undulate.

[0047] Referring to FIG. 3A, a substrate 310 is provided. The substrate 310 has a first surface 310a and a second surface 310b relative to the first surface 310a. One or more redistribution structures 315 may be formed in the substrate 310. The substrate 310 and the redistribution structure 315 are similar to the substrate 210 and redistribution structure 215 shown in FIG. 2A, respectively, and will not be described in detail here.

[0048] Unlike the substrate 210 shown in FIG. 2A, the first surface 310a of the substrate 310 shown in FIG. 3A has at least one first cavity 311 formed therein, and the second surface 310b of the substrate 310 has at least one second cavity 312 formed therein. The first cavity 311 and the second cavity 312 can accommodate electronic components to be mounted on the substrate 310 to reduce the overall thickness of the semiconductor device to be formed. Specifically, the area of ​​each of the first cavity 311 and the second cavity 312 formed in the substrate 310 can be substantially equal to or greater than the size of the electronic component later mounted in the cavity. The first cavity 311 and / or the second cavity 312 can be formed by laser, drilling, grooving, scraping or scribing.

[0049] Referring to Figures 3B and 3C, a coating 340 is formed on the second surface 310b of a substrate 310. For example, as shown in Figure 3B, the substrate 310 is loaded into a coating apparatus 380. The first surface 310a of the substrate 310 is attached to the lower mold 381b of the coating apparatus 380, and a liquid solution 342 is provided onto the second surface 310b of the substrate 310 and fills the second cavity 312 in the second surface 310b of the substrate 310. Subsequently, the upper mold 381a and the lower mold 381b can be moved closer to each other to compress the liquid solution 342 and apply a pressing process to the liquid solution 342. After the liquid solution 342 has solidified, the upper mold 381a and the lower mold 381b are separated from each other, and the substrate 310 is removed from the coating apparatus 380. Thus, as shown in Figure 3C, a coating 340 with a flat top surface is formed on the second surface 310b of the substrate 310. However, the present invention is not limited to the example shown in Figures 3B and 3C. In other embodiments, the coating may be formed by spin coating or other suitable processes.

[0050] Referring to FIG. 3D, one or more first electronic components 325 are mounted on the first surface 310a of the substrate 310. Specifically, the substrate 310 is flipped so that the first surface 310a faces upward, and the first electronic components 325 can be mounted on the first surface 310a of the substrate 310 via solder paste. In the example shown in FIG. 3D, the first electronic component 325 may include two semiconductor dies 321a and 321b and a discrete device 322. Since the thickness of the semiconductor dies 321a and the discrete device 322 is greater than the thickness of the semiconductor die 321b, the semiconductor dies 321a and the discrete device 322 can be mounted in two first cavities 311 formed in the substrate 310, and the semiconductor die 321b is mounted in a region outside the two first cavities 311, thereby reducing the total thickness of the semiconductor device to be formed.

[0051] Referring to FIG. 3E, a first sealant 320 is formed on a first surface 310a of a substrate 310. The first sealant 320 may fill the voids left in the first cavity formed in the first surface 310a of the substrate 310 and cover the first electronic component 325. The first sealant 320 may be formed using compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, paste printing, or other suitable applicators. The first sealant 320 may be made of a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with suitable filler, but the scope of the invention is not limited thereto.

[0052] Referring to Figures 3F and 3G, the coating 340 on the second surface 310b of the substrate 310 is removed to expose at least one second cavity 312. As shown in the example in Figure 3F, a release tape 345 is attached to the coating 340 to peel the coating 340 off from the second surface 310b of the substrate 310. However, the invention is not limited thereto.

[0053] Subsequently, as shown in FIG3H, a second electronic component 335 is mounted within the second cavity 312, and a plurality of bumps 338 are formed on the second surface 310b of the substrate 310. Specifically, the second electronic component 335 can be mounted within the second cavity 312 via solder paste, and the plurality of bumps 338 are electrically connected to corresponding conductive patterns in the RDS 315. When the second electronic component 335 is mounted in the second cavity 312, the plurality of bumps 338 can extend from the second surface 310b of the substrate 310 and are higher than the top surface of the second electronic component 335. In this way, the second electronic component 335 does not interfere with the mounting of the semiconductor device onto another device, such as a printed circuit board, via the bumps 338.

[0054] Referring to FIG. 3I, a second sealant 330 is formed on the second surface 310b of the substrate 310. The second sealant 330 can fill the voids in the second cavity formed on the second surface 310b of the substrate 310 and cover the second electronic component 335 and the plurality of bumps 338. The second sealant 330 can be formed using compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, paste printing or other suitable applicators. The second sealant 330 can be made of the same material as the first sealant 320, such as epoxy resin.

[0055] Referring to FIG. 3J, a portion of the thickness of the second sealant 330 is removed to at least expose the top surface of each bump 338. In some embodiments, removing a portion of the thickness of the second sealant 330 may be performed using a laser ablation process, an etching process, or any other process known in the art, as long as it reduces the amount of sealant material. In the example shown in FIG. 3J, the top surface of the second electronic component 335 is also exposed outside the second sealant 330. However, the invention is not limited thereto. In some other embodiments, some sealant material may remain on top of the second electronic component 335.

[0056] Subsequently, referring to FIG3K, an EMI shielding layer 350 is formed, and the EMI shielding layer 350 may at least cover the top surface and side surface of the first sealant 320. The EMI shielding layer 350 may be a conformal shield, which follows the shape and / or contour of the first sealant 320, the substrate 310, and the second sealant 330. Specifically, as shown in FIG3K, the EMI shielding layer 350 covers the top surface and side surface of the first sealant 320, the side surface of the substrate 310, and the side surface of the second sealant 330. The EMI shielding layer 350 may shield electronic components within the semiconductor device from EMI or other interference received (or generated).

[0057] Although the process for manufacturing a semiconductor device having an uneven surface (at least during certain stages of the process) has been shown in conjunction with Figures 2A-2L and 3A-3K, those skilled in the art will understand that modifications and adjustments can be made to the process without departing from the scope of the invention.

[0058] The discussion herein includes numerous illustrative diagrams illustrating various parts of a semiconductor device and methods of manufacturing such a semiconductor device. For clarity, these diagrams do not show all aspects of each example element. Any example element and / or method provided herein may share any or all features with any or all other elements and / or methods provided herein.

[0059] Various embodiments have been described herein with reference to illustrations. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be implemented without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the practice of one or more embodiments of the invention disclosed herein. Therefore, the invention and the embodiments herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the list of exemplary patent claims appended. [Simplified Explanation of the Diagram]

[0009] The drawings referenced herein form part of the specification. The features shown in the drawings illustrate only some embodiments of the invention, and not all embodiments of the invention, unless otherwise expressly stated in the detailed description, and the reader of the specification should not imply the contrary.

[0010] Figure 1 shows a cross-sectional view of a semiconductor device formed using double-sided molding (DSM) technology.

[0011] Figures 2A to 2L are cross-sectional views of various steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0012] Figures 3A to 3K are cross-sectional views of various steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0013] The same diagrammatic symbols will be used throughout the diagram to represent the same or similar parts.

Claims

1. A method for manufacturing a semiconductor device, characterized in that the method comprises: A substrate is provided having a first surface and a second surface opposite to the first surface, wherein the second surface of the substrate is not flat; A coating is formed on the second surface of the substrate to planarize the second surface of the substrate, such that the first surface of the coating is flat and the first surface of the coating faces away from the second surface of the substrate; the coating comprises a resin material or a silicone rubber material. A first electronic component is mounted on a first surface of the substrate; A first sealant is formed on a first surface of the substrate to cover the first electronic component; a release tape is attached to the coating; and the coating is peeled off from a second surface of the substrate using the release tape.

2. The method of claim 1, wherein removing the coating from the second surface of the substrate comprises: The first surface of the substrate is attached to the lower mold of the coating equipment; A liquid solution is formed on the second surface of the substrate; The upper and lower molds of the coating apparatus are brought close together to compress the liquid solution located between the flat inner surface of the upper mold and the uneven second surface of the substrate; The liquid solution is then cured to form the coating.

3. The method as described in claim 2, wherein the method further comprises: Separate the upper mold and the lower mold from each other; And remove the substrate from the coating device.

4. The method of claim 1, wherein a plurality of conductive pillars are formed on the uneven second surface of the substrate.

5. The method of claim 4, wherein the coating is removed from a second surface of the substrate to expose the plurality of conductive pillars.

6. The method as described in claim 5, wherein the method further comprises: A second electronic component is mounted on the second surface of the substrate; A second sealant is formed on the second surface of the substrate to cover the plurality of conductive pillars and the second electronic component; The second sealant is then ground to expose the top surface of each of the plurality of conductive pillars.

7. The method as described in claim 6, wherein the method further comprises: A bump is formed on the top surface of each of the plurality of conductive pillars.

8. The method of claim 1, wherein at least one first cavity is formed in the first surface of the substrate, and the first electronic component is mounted in the at least one first cavity.

9. The method of claim 1, wherein the uneven second surface of the substrate has at least one second cavity formed therein.

10. The method of claim 9, wherein the at least one second cavity is exposed after the coating is removed from the second surface of the substrate.

11. The method as described in claim 10, wherein the method further comprises: A second electronic component is installed within the at least one second cavity; Multiple bumps are formed on the second surface of the substrate; A second sealant is formed on the second surface of the substrate to cover the second electronic component and the plurality of bumps.

12. The method as described in claim 11, wherein the method further comprises: Remove a portion of the thickness of the second sealant to expose at least the top surface of each of the plurality of bumps.

13. The method as described in claim 1, wherein the method further comprises: An electromagnetic interference shielding layer is formed to at least cover the first sealant.

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