Semiconductor structure and manufacturing method thereof

TWI942467BActive Publication Date: 2026-10-11POWERCHIP SEMICON MFG CORP
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
TW114133726
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-09-03
Publication Date
2026-10-11
Estimated Expiration
2045-09-02

Smart Images

  • Figure TWG2TB001915644_001
    Figure TWG2TB001915644_001
  • Figure TWG2TB001915644_002
    Figure TWG2TB001915644_002
  • Figure TWG2TB001915644_003
    Figure TWG2TB001915644_003
Patent Text Reader

Abstract

A semiconductor structure includes a substrate, multiple stacked structures, multiple first suspended dielectric layers, a dielectric layer, and multiple second suspended dielectric layers. The multiple stacked structures are located on the substrate. A gap exists between adjacent stacked structures. Each first suspended dielectric layer covers the top of its corresponding stacked structure. The dielectric layer is located on the multiple first suspended dielectric layers, the sidewalls of the multiple stacked structures, and the substrate. The multiple second suspended dielectric layers are located on the dielectric layer. Adjacent second suspended dielectric layers are connected to each other, sealing the top of the gap and forming an air gap between adjacent stacked structures.
Need to check novelty before this filing date? Find Prior Art

Claims

1. A semiconductor structure, comprising: Base; Multiple stacked structures are located on the substrate, wherein there is a gap between two adjacent stacked structures; A plurality of first suspended dielectric layers, wherein each first suspended dielectric layer covers the top of the corresponding stacked structure; a dielectric layer is located on the plurality of first suspended dielectric layers, the sidewalls of the plurality of stacked structures, and the substrate, wherein the dielectric layer is in direct contact with the substrate; And a plurality of second suspended dielectric layers, located on the dielectric layer, wherein two adjacent second suspended dielectric layers are connected to each other and seal the top of the gap, and form an air gap between two adjacent stacked structures.

2. The semiconductor structure as claimed in claim 1, wherein the plurality of said stacked structures include a plurality of gate stacked structures.

3. The semiconductor structure as claimed in claim 1, wherein the first dangling dielectric layer exposes a portion of the sidewalls of the stacked structure.

4. The semiconductor structure as claimed in claim 1, wherein the second dangling dielectric layer exposes a portion of the dielectric layer located in the gap.

5. The semiconductor structure of claim 1, wherein the material of the first dangling dielectric layer, the material of the dielectric layer, and the material of the second dangling dielectric layer comprise silicon oxide.

6. A method for manufacturing a semiconductor structure, comprising: Provide a base; A plurality of stacked structures are formed on the substrate, wherein a gap exists between two adjacent stacked structures; a plurality of first suspended dielectric layers are formed, wherein each first suspended dielectric layer covers the top of the corresponding stacked structure; dielectric layers are formed on the plurality of first suspended dielectric layers, the sidewalls of the plurality of stacked structures, and the substrate, wherein the dielectric layers directly contact the substrate; and a plurality of second suspended dielectric layers are formed on the dielectric layers, wherein two adjacent second suspended dielectric layers are connected to each other, sealing the top of the gap, and forming an air gap between two adjacent stacked structures.

7. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the method for forming a plurality of said stacked structures includes performing a self-aligned dual patterning process.

8. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the method for forming a plurality of the first dangling dielectric layers includes plasma-enhanced chemical vapor deposition.

9. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the method for forming the dielectric layer includes atomic layer deposition.

10. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the method for forming a plurality of second dangling dielectric layers includes plasma-enhanced chemical vapor deposition.

Citation Information

Patent Citations

  • Method for manufacturing semiconductor component

    CN103515216A

  • Semiconductor device and method for manufacturing the same

    US20140110850A1