Integrated circuit device and method of forming the same

Abstract

An integrated circuit device includes: a semiconductor layer portion having a front surface and a back surface, and a first diode. The back surface and the front surface are spaced apart in a first direction, and the back surface of the front surface and the back surface each extend at least in a second direction, which is transverse to the first direction. The first diode includes a first doped region disposed in the semiconductor layer portion; a second doped region disposed in the semiconductor layer portion and spaced apart from the first doped region; a first conductive contact structure connected to the first doped region; and a second conductive contact structure connected to the second doped region. The first doped region is closer to the front surface than the second doped region, and the first doped region and the second doped region are offset from each other in the second direction.

Claims

1. An integrated circuit device, comprising: A semiconductor layer portion has a front surface and a back surface, the back surface being spaced apart from the front surface in a first direction, the back surface of the front surface and the back surface each extending in at least a second direction, the second direction being transverse to the first direction; The first diode includes: a first doped region disposed in the semiconductor layer portion; a second doped region disposed in the semiconductor layer portion and spaced apart from the first doped region; a first conductive contact structure connected to the first doped region; and a second conductive contact structure connected to the second doped region, wherein the first doped region is closer to the front surface than the second doped region, and the first doped region and the second doped region are offset from each other in a second direction.

2. The integrated circuit device as described in claim 1, wherein: The semiconductor layer includes a multilayer stack with alternating compositions of the film layers in the multilayer stack; the first doped region is an n-type doped region or a p-type doped region and is disposed on the front surface of the multilayer stack; and the second doped region is a doped region of the opposite doping type to the first doped region and is disposed on the back surface of the multilayer stack.

3. The integrated circuit device as claimed in claim 2 further includes a field-effect transistor formed in the semiconductor layer portion, the field-effect transistor sharing at least one subset of the film layers of the multilayer stack with the first diode.

4. The integrated circuit arrangement as described in claim 3, wherein: The alternating layers in the multilayer stack are multiple layers of a first-class semiconductor; and the field-effect transistor includes a plurality of channels formed by the layers of the first-class semiconductor.

5. The integrated circuit device as claimed in claim 1, further comprising a complementary field-effect transistor formed in a first portion of the semiconductor layer portion, and including a pair of field-effect transistors stacked along the first direction, wherein: The semiconductor layer portion includes a multilayer stack comprising a plurality of first semiconductor layers of a first type; and the complementary field-effect transistor includes a plurality of channels, each of which includes a portion corresponding to one of the first semiconductor layers.

6. The integrated circuit arrangement as described in claim 5, wherein: The multilayer stack includes a second portion, the second portion further including a plurality of second semiconductor layers arranged in an alternating stacking order with the first semiconductor layers; and the first diode formed in the second portion.

7. The integrated circuit arrangement as claimed in claim 1, wherein the semiconductor layer portion comprises: Multiple first layers; Multiple second layers; And a third layer; The first layer, the second layer, and the third layer are formed in a stacked order, with the third layer separating the first layer from the second layer; the first layer includes alternating layers of a first semiconductor and a second semiconductor; the second layer includes alternating layers of the first semiconductor and the second semiconductor; and the third layer is a third semiconductor.

8. The integrated circuit arrangement as described in claim 7, wherein: The first semiconductor is silicon; the second semiconductor is a silicon-germanium alloy; and the third semiconductor is germanium or silicon-germanium with a higher germanium content than the second semiconductor.

9. An integrated circuit device as claimed in any one of claims 1 to 8, wherein the first doped region and the second doped region have different dimensions.

10. The integrated circuit device as claimed in claim 1, further comprising a second diode, the second diode including: A third doped region is disposed in this semiconductor layer portion; A fourth doped region is disposed in the semiconductor layer portion and spaced apart from the third doped region; a third conductive contact structure is connected to the third doped region; and a fourth conductive contact structure is connected to the fourth doped region; the third doped region is closer to the front surface than the fourth doped region, and the third doped region and the fourth doped region are offset from each other in a second direction, wherein: the offset of the third doped region and the fourth doped region in the second direction is different from the offset of the first doped region and the second doped region in the second direction, or the first doped region and the third doped region have different sizes.

11. An integrated circuit device, comprising: A semiconductor layer having a top surface and a bottom surface, the top surface and the bottom surface being substantially oriented along a first direction and extending at least along a second direction transverse to the first direction; a complementary field-effect transistor formed in the semiconductor layer, including a top field-effect transistor and a bottom field-effect transistor disposed below the top field-effect transistor along the first direction. And a semiconductor device formed in the semiconductor layer, and including: a first doped region disposed in the semiconductor layer; A second doped region is disposed in the semiconductor layer and spaced apart from the first doped region; a first conductive contact structure is connected to the first doped region; and a second conductive contact structure is connected to the second doped region, wherein the first doped region is disposed on the top surface, and the first doped region and the second doped region are offset from each other in a second direction.

12. The integrated circuit device as claimed in claim 11, wherein the first doped region is an n-doped region or a p-doped region, and the second doped region is a doped region of the same doping type as the first doped region.

13. The integrated circuit device as claimed in claim 12, wherein the semiconductor device further includes a third doped region, which is of the opposite doping type to the first doped region and the second doped region.

14. A method for forming an integrated circuit device, comprising: A semiconductor layer having a top surface and a bottom surface is formed, the semiconductor layer comprising a stacked semiconductor layer sequence along a first direction, the semiconductor layer extending at least along a second direction transverse to the first direction; A first semiconductor device is formed in the semiconductor layer by the following steps: doping a first portion of the semiconductor layer on the top surface of the stacked semiconductor layer sequence; doping a second portion of the semiconductor layer on the bottom surface of the stacked semiconductor layer sequence, the second portion being offset from the first portion in a direction substantially parallel to the semiconductor layer; and forming a second semiconductor device including a complementary field-effect transistor by forming a plurality of channels, the channels being corresponding channels in a subset of the stacked semiconductor layer sequence.

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