Display panel and method of manufacturing the same

Abstract

A display panel includes a substrate having a plurality of pixels, each pixel having a first patterned area and a second patterned area adjacent to the first patterned area. An insulating layer is disposed on the substrate and includes a first intaglio pattern in the first patterned area. A pair of light-emitting elements are disposed on the first intaglio pattern of the insulating layer. The first intaglio pattern has a length in a first direction and a length in a second direction different from the first direction. The light-emitting areas of the pair of light-emitting elements are offset in multiple different directions along an extension line extending from the center of the first intaglio pattern along the first direction or the second direction, thereby achieving improved display quality even when one light-emitting element is defective.

Description

Technical Field

[0001] This application relates to a display panel and a method for manufacturing the same, and more specifically, to a display panel and a method for manufacturing the same that can improve the productivity of a pair of light-emitting elements, such as micro light-emitting diodes (micro LEDs), arranged in different directions and prevent the visibility of stains caused by defective light-emitting elements. Prior Technology

[0002] With the advent of the information age, the field of display devices for visualizing electrical information signals is developing rapidly. Therefore, research is underway to improve certain aspects of various display devices, including thinner profiles, lighter weight, and lower power consumption.

[0003] Specific examples of display devices may include liquid crystal display (LCD) devices, light-emitting display (LED) devices, quantum dot display devices, etc.

[0004] Among these display devices, the light-emitting display device may include an organic light-emitting diode (OLED) display device (which contains organic materials as the light-emitting layer) or a micro light-emitting diode (micro LED) display device (which contains inorganic materials as the light-emitting layer).

[0005] Here, the micro-LED display device uses inorganic materials that are resistant to moisture and oxygen as its light-emitting layer, making it less susceptible to external environmental factors, thus ensuring high reliability and providing a longer lifespan than OLED display devices. Furthermore, the micro-LED display device has the advantage of achieving a flexible display device in a thinner structure than OLED display devices.

[0006] Micro-LED transfer technology is a process that transfers micro-LED chips (light-emitting element chips) grown on a growth substrate to a panel substrate. As micro-LED chips become smaller and smaller, research is underway on technologies to transfer micro-LED chips onto panel substrates with high precision. Summary of the Invention

[0007] A display panel incorporating micro LEDs may include one or more sub-pixel units in each pixel. The one or more sub-pixel units may include a first light-emitting element (first sub-pixel) and a second light-emitting element (second sub-pixel) to prepare for defective chips during the process of properly transferring the light-emitting elements to the substrate of the panel.

[0008] Here, when a defective light-emitting element appears in each sub-pixel unit, the stain may become visible due to the difference in distance between the first and second light-emitting elements.

[0009] In addition, depending on the uniformity of the adhesive layer, problems such as non-transfer defects (the light-emitting element fails to be transferred to the panel) or over-transfer defects (the light-emitting element is over-transferred to the panel) may occur.

[0010] Therefore, the embodiments of this application aim to improve the productivity of light-emitting elements (e.g., micro LEDs) arranged in one of different directions, while preventing the visibility of stains caused by defective light-emitting elements.

[0011] The problem to be solved in this application is not limited to the above-mentioned technical problems. Those skilled in the art will clearly understand from the following description other unmentioned technical problems to which the technical concept of this application pertains.

[0012] The disclosed display panel architecture uses subpixels, each containing a pair of light-emitting elements (a primary element and a backup element), arranged within a precisely formed intaglio pattern on the substrate. This configuration ensures that even if one element is defective, the other maintains display quality, preventing visible defects (such as blemishes or dead pixels). By positioning the light-emitting areas relative to each other and controlling their spacing to be less than the binocular resolution of the human eye, this design minimizes color shift and ensures that the defect is imperceptible to the viewer.

[0013] The manufacturing method employs a two-stage stamping transfer process using two gravure patterns. The first gravure pattern provides the final placement positions for multiple components, while the second gravure pattern acts as a temporary placement area during transfer. This multi-stage process improves placement accuracy, reduces clustering defects, and allows for a closer spacing between multiple light-emitting elements compared to traditional single-step transfer methods. The method also includes an optimized adhesive layer etching process to improve electrode contact and overall panel uniformity.

[0014] This design further integrates shared pixel drive circuitry for multiple sub-pixels, simplifying the overall panel structure and reducing power consumption, while supporting high-resolution micro-LED displays. These features, individually or in combination, improve manufacturing yield, productivity, and display performance, making the technology suitable for advanced high-resolution and defect-resistant displays.

[0015] According to one aspect of this disclosure, a display panel is provided, comprising: a substrate including a plurality of pixels, each pixel having a first pattern area and a second pattern area surrounding the first pattern area; an insulating layer disposed on the substrate and including a first intaglio pattern disposed in the first pattern area; and a pair of light-emitting elements disposed on the first intaglio pattern of the insulating layer, wherein the first intaglio pattern has a length in a first direction and a length in a second direction, and the respective light-emitting areas of the pair of light-emitting elements are offset from the center of the first intaglio pattern along an extension line in the first direction or the second direction in different directions. Simple Explanation of the Diagram

[0016] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein: Figure 1 is a plan view of a display panel according to an embodiment of the present application; Figure 2 is a plan view of pixels according to an embodiment of the present application; Figure 3 is a plan view of a portion of a display panel according to a first embodiment of the present application; Figure 4 is a cross-sectional view taken along line I-I' of Figure 3; Figure 5 is a cross-sectional view taken along line II-II' of Figure 3; Figure 6 is a first modification example of a display panel according to the first embodiment of the present application; Figure 7 is a second modification example of a display panel according to the first embodiment of the present application; Figure 8 is a plan view of a display panel according to a second embodiment of the present application; Figure 9 is a cross-sectional view taken along line III-III' of Figure 8; Figure 10 is a first modification example of a display panel according to the second embodiment of the present application; Figure 11A is a plan view of a display panel according to a third embodiment of the present application. Schematic diagrams; Figure 11B is a plan view showing a comparison between the first and second intaglio patterns of Figure 11A; Figure 12 is a cross-sectional view taken along line IV-IV' of Figure 11A; Figure 13 is a plan view of a portion of a display panel according to the fourth embodiment of this application; Figure 14 is a first modified example of a display panel according to the fourth embodiment of this application; Figure 15 is a plan view of a portion of a display panel according to the fifth embodiment of this application; Figure 16 is a first modified example of a display panel according to the fifth embodiment of this application; Figure 17 is a plan view of a portion of a display panel according to the sixth embodiment of this application; Figures 18A to 18E are process plan views of the first embodiment of this application; and Figures 19A to 19F are process cross-sectional views of the first embodiment of this application, respectively. Implementation

[0017] The advantages and features of this application, as well as the methods for implementing these methods, will become clear through the following detailed description of embodiments in conjunction with the accompanying drawings. However, this application is not limited to the embodiments described below, and various modifications can be made. These embodiments are provided only to enable those skilled in the art to fully understand the scope of this application, and this application is limited only to the scope of the claims.

[0018] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the drawings for the purpose of describing embodiments of this application are illustrative only and are not limited to the matters shown in this application. Furthermore, in describing this application, detailed descriptions of prior art will be omitted where it is determined that this may unnecessarily obscure the essence of the application.

[0019] Terms such as “comprising,” “having,” and “consisting of” as used herein are intended to allow for the addition of other elements, unless these terms are used in conjunction with the term “only.” Unless explicitly stated otherwise, any reference to the singular may include the plural.

[0020] Even if such margins are not explicitly stated, components are interpreted as including a normal tolerance range.

[0021] When using terms such as "above," "over," "below," and "adjacent" to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used with the terms "immediately" or "directly."

[0022] When a device or layer is referred to as being "on" another device or layer, it includes situations where a device or layer is directly located on the other device or layer, or situations where there are other devices or layers interposed between the two devices or layers.

[0023] Furthermore, although the terms "first," "second," etc., may be used herein to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component described below may be the second component within the technical scope of this application.

[0024] Throughout the application, the same reference number refers to the same component.

[0025] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), proportions, angles, number of elements, etc., described in the accompanying drawings for the purpose of illustrating the embodiments of this disclosure are merely examples, and this disclosure is not limited thereto.

[0026] The dimensions (including dimensions and thickness) of each component illustrated in the drawings are for ease of description, and this disclosure is not limited to the dimensions and thickness of the illustrated components. However, it should be noted that the relative dimensions (including relative dimensions, positions, and thicknesses) of the components illustrated in the various drawings submitted herein are part of this disclosure.

[0027] As used herein, the term "connection" is intended to have the broadest possible meaning. Specifically, the phrase "A connected to B" encompasses both direct connections (where no intervening component or element is present) and indirect connections (where one or more intermediate components or elements exist between A and B). In other words, "A connected to B" includes both direct physical or electrical coupling and indirect coupling through one or more intervening components. Unless explicitly stated otherwise, these terms do not require direct physical or electrical contact. The terms "coupling" and "contact" should be interpreted in the same manner.

[0028] The features of the various embodiments of this application may be combined in part or in whole with each other. These embodiments may be technically linked and operate in various ways, and may be implemented independently or in connection with each other.

[0029] As used herein, the term "device" may include display devices, such as liquid crystal modules (LCMs) comprising a display panel and driving portions for driving the display panel, and organic light-emitting display (OLED) modules. Furthermore, display devices may include notebook computers, televisions, computer monitors, vehicle devices, automotive devices, equipment comprising one or more components or parts for a vehicle, and assemblies of electronic devices (or assemblies or assemblies of equipment) comprising mobile electronic devices (such as smartphones, electronic mats, etc.), which are complete products or end products including LCMs, OLED modules, etc.

[0030] Therefore, the display device used in this article may include the display device itself, such as LCM, OLED module, etc., as well as application products including LCM, OLED module, etc., or complete sets of equipment as end consumer devices.

[0031] Furthermore, in some embodiments, an LCM or OLED module including a display panel, driving components, etc., may be referred to as a "display device," and an electronic device including an LCM or OLED module as a complete product may be referred to as a "package." For example, a display device may include a liquid crystal display (LCD) or OLED display panel, and a source printed circuit board (PCB) serving as a controller for driving the display panel. A package may further include a package of PCBs, which serve as a package controller for controlling the entire package and are electrically connected to the source PCB.

[0032] The display panel used in the embodiments of this application may include all types of display panels, such as LCD panels, organic light-emitting diode (OLED) display panels, and electroluminescent display panels. However, the embodiments of this application are not limited to these.

[0033] The features of the various embodiments of this application may be coupled or combined with each other in part or in whole, and may interoperate and be technically driven with each other in various ways as will be fully understood by one of ordinary skill in the art. The embodiments of this application may be implemented independently of each other, or may be implemented together in an associated relationship.

[0034] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. For ease of description, the scale of the components shown in the drawings may differ from the actual scale, and therefore the scope is not limited to the scale shown in the drawings.

[0035] Figure 1 is a plan view of a display panel according to an embodiment of the present application, and Figure 2 is a plan view of pixels according to an embodiment of the present application.

[0036] Referring to Figures 1 and 2, the horizontal direction X and vertical direction Y of the display panel 1 can be the longitudinal direction and width direction of the display panel 1, respectively. Furthermore, the horizontal direction X and vertical direction Y of the display panel 1 can also be represented as the column direction and row direction, respectively. The thickness direction Z can refer to the direction perpendicular to the plane having the horizontal direction X and vertical direction Y of the display panel 1. Additionally, the display panel 1 may have a cross-section in the thickness direction Z.

[0037] Referring to Figures 1 and 2, a display panel 1 according to an embodiment of this application may include: a substrate 10 (see Figure 4) comprising a plurality of pixels P (specifically, a plurality of pixels P are arranged on the substrate), each of the pixels P comprising: a first pattern region IA1 and a second pattern region IA2 surrounding the first pattern region IA1; an insulating layer 40 (see Figure 4) disposed on the substrate 10 and comprising a first intaglio pattern IP1 (see Figure 3) disposed in the first pattern region IA1; and a pair of light-emitting elements LD (e.g., a pair of light-emitting elements LD, but not limited thereto) disposed on the first intaglio pattern IP1 of the insulating layer 40. The first intaglio pattern IP1 has a length in a first direction (e.g., the longitudinal direction of the display panel) and a length in a second direction (e.g., the width direction of the display panel), the second direction being different from the first direction, and the light-emitting region E of the light-emitting element LD (see Figure 4) may be offset from the center of the first intaglio pattern IP1 along an extension line in the first or second direction in different directions (e.g., opposite directions).

[0038] Display panel 1 can provide information, video and / or images to users. For example, display panel 1 may include a display area AA and a non-display area NA. For example, substrate 10 (see FIG. 4) may include a display area AA and a non-display area NA.

[0039] The substrate 10 may be formed of an insulating material. For example, the substrate 10 may be formed of glass, resin, or the like. Furthermore, the substrate 10 may be formed of a flexible material. For example, the substrate 10 may be formed of a flexible plastic material such as polyimide (PI). However, the embodiments of this application are not limited to these.

[0040] The display area AA can be an area for displaying images. The display area AA of the substrate 10 or the display panel 1 can be configured into various shapes according to the design of the display device. For example, the display area AA can be configured into a rectangular shape with four rounded corners, but the embodiments of this application are not limited to this. As another example, the display area AA can be configured into a rectangular shape with four right angles, a circular shape, etc., but the embodiments of this application are not limited to this.

[0041] The display area AA may contain multiple pixels P. Each of these pixels P may be composed of multiple sub-pixel units SP (first sub-pixel unit SP1, second sub-pixel unit SP2, and third sub-pixel unit SP3). Multiple light-emitting elements LD (light-emitting elements LD1-1 and LD1-2, LD2-1 and LD2-2, or LD3-1 and LD3-2) may be disposed in each of these sub-pixel units SP. These light-emitting elements LD may be configured differently depending on the type of display device. For example, when the display device is an inorganic light-emitting display device, the light-emitting elements may be light-emitting diodes (LEDs), micro LEDs, or mini LEDs, but the embodiments of this application are not limited to these.

[0042] The non-display area NA can be an area where no image is displayed. Various lines and circuits used to drive some pixels P in the display area AA can be set in the non-display area NA. For example, various lines and driving circuits can be installed in the non-display area NA, and pads for connecting integrated circuits, printed circuits, etc. can be provided, but the embodiments of this application are not limited to this.

[0043] For example, these driving circuits may be data driving circuits and / or gate driving circuits, but embodiments of this application are not limited to this. Lines for supplying control signals to these driving circuits may be disposed on the display panel. For example, these control signals may include various timing signals such as clock signals, input data enable signals, and synchronization signals, but embodiments of this application are not limited to this. Control signals may be received through pad portions. For example, connection lines for transmitting signals may be disposed in the non-display area NA. For example, driving components such as flexible circuit boards and printed circuit boards may be connected to the pad portions.

[0044] Each of these pixels P may contain one or more sub-pixel units and may be included in the display area AA. These pixels P may be arranged in a matrix to form multiple columns and multiple rows, but the display panel of this application is not limited to this.

[0045] Each of these pixels P may include a first sub-pixel unit SP1, a second sub-pixel unit SP2, and a third sub-pixel unit SP3. These sub-pixel units SP (first sub-pixel unit SP1, second sub-pixel unit SP2, and third sub-pixel unit SP3) may be arranged in various ways. For example, the first sub-pixel unit SP1, second sub-pixel unit SP2, and third sub-pixel unit SP3 may be arranged side-by-side along the X-axis. The arrangement of these sub-pixel units SP will be specifically described in the following embodiments. However, the number of sub-pixel units SP constituting a pixel P is exemplary, and the embodiments of this application are not limited thereto.

[0046] The first sub-pixel unit SP1, the second sub-pixel unit SP2, and the third sub-pixel unit SP3 can emit light of different colors. For example, one of the first sub-pixel unit SP1, the second sub-pixel unit SP2, and the third sub-pixel unit SP3 can be a red sub-pixel unit, another can be a green sub-pixel unit, and the last one can be a blue sub-pixel unit. The types of these sub-pixel units are exemplary, and the embodiments of this application are not limited thereto.

[0047] One of the first sub-pixel unit SP1, the second sub-pixel unit SP2, and the third sub-pixel unit SP3 may include one or more light-emitting elements (LDs). The light-emitting elements may constitute a sub-pixel of each sub-pixel unit. For example, the first sub-pixel unit SP1 may include a pair of light-emitting elements (LD1-1 and LD1-2), the second sub-pixel unit SP2 may include a pair of light-emitting elements (LD2-1 and LD2-2), and the third sub-pixel unit SP3 may include a pair of light-emitting elements (LD3-1 and LD3-2). However, the number of light-emitting elements included in a sub-pixel unit is exemplary, and the embodiments of this application are not limited thereto.

[0048] Multiple signal lines can be positioned in the area between the sub-pixel units SP. These signal lines can extend along the row direction between the sub-pixel units SP. These signal lines can be lines that transmit the pixel voltage output from the pixel driving circuit PD (see Figure 4) to the sub-pixel units SP.

[0049] For example, these signal lines can be electrically connected to multiple pixel driving circuits (PDs) and pixel electrodes such as first pixel electrode 55a and second pixel electrode 55b (see FIG. 4). Pixel voltages output from these pixel driving circuits (PDs) can be transmitted through these signal lines to the first pixel electrode 55a and second pixel electrode 55b of these sub-pixel units (SPs). For example, the first pixel electrode 55a and second pixel electrode 55b can be electrodes electrically connected to the first electrodes 93a and 93b (see FIG. 4) of these light-emitting elements (LDs). Therefore, the pixel voltage transmitted through the signal lines can be transmitted through the first pixel electrode 55a and second pixel electrode 55b to the first electrodes 93a and 93b (see FIG. 4) of the light-emitting element (LD).

[0050] Therefore, by using a pixel driving circuit that integrates multiple pixel circuits, instead of forming multiple transistors and storage capacitors in each of the sub-pixel units SP, the structure of the display panel 1 can be simplified. Furthermore, since the circuitry in each of the sub-pixel units SP is integrated into a single pixel driving circuit PD, high-efficiency and low-power operation can be achieved.

[0051] According to one embodiment, each of the pixels P may include one or more first pattern regions IA1 (pattern region IA1-1, pattern region IA1-2, and pattern region IA1-3) and a second pattern region IA2 surrounding the first pattern regions IA1. The first pattern regions IA1 and the second pattern regions IA2 may include groove-like patterns (in other words, gravure patterns) formed in the insulating layer 40 (see FIG. 4). Here, the groove-like patterns may be formed by removing a certain thickness from the upper surface of the insulating layer 40, 140, or 240.

[0052] Each of the first pattern regions IA1 according to one embodiment may correspond to each of the sub-pixel units SP. In other words, each of the first pattern regions IA1 according to one embodiment may include each of the sub-pixel units SP. When multiple sub-pixel units SP are provided, one or more first pattern regions IA1 may also be provided as multiple. For example, one or more first pattern regions IA1 may include pattern region IA1-1 (1-1), pattern region IA1-2 (1-2), and pattern region IA1-3 (1-3).

[0053] A sub-pixel unit SP may be disposed in each of the first pattern regions IA1. A first pattern region IA1 may contain a pair of light-emitting elements (e.g., a pair of light-emitting elements, but not limited thereto). For example, pattern region IA1-1 may contain light-emitting elements LD1-1 and LD1-2 of the first sub-pixel unit SP1. For example, pattern region IA1-2 may contain light-emitting elements LD2-1 and LD2-2 of the second sub-pixel unit SP2. For example, pattern region IA1-3 may contain light-emitting elements LD3-1 and LD3-2 of the third sub-pixel unit SP3.

[0054] The second pattern area IA2 may include one or more second intaglio patterns IP2 (see Figure 3). The one or more second intaglio patterns IP2 may be configured to correspond to each of at least one of the sub-pixel units SP. For example, when three sub-pixel units are included (e.g., first sub-pixel unit SP1, second sub-pixel unit SP2, and third sub-pixel unit SP3), at least three second intaglio patterns IP2 may be configured to correspond to each of the three sub-pixel units (e.g., first sub-pixel unit SP1, second sub-pixel unit SP2, and third sub-pixel unit SP3).

[0055] The second gravure pattern IP2 can serve as a space where the light-emitting elements LD are temporarily transferred during the stamping process of the light-emitting elements LD. Therefore, the second gravure pattern IP2 can be configured to be adjacent to the first pattern area IA1 in which the light-emitting elements LD are disposed, while maintaining a predetermined distance from the first pattern area IA1.

[0056] The second pattern area IA2 may further include one or more first dummy patterns DP1 and one or more second dummy patterns DP2. The first dummy patterns DP1 and the second dummy patterns DP2 may be dummy areas where the light-emitting element LD is not temporarily placed during the stamping process. Therefore, the first dummy patterns DP1 and the second dummy patterns DP2 can increase the design freedom of the light-emitting element LD and improve the uniformity of the adhesive layer in contact with the light-emitting element LD.

[0057] In the following embodiments, the first pattern area IA1 and the second pattern area IA2 will be described in detail.

[0058] Figure 3 is a plan view of a portion of the display panel according to the first embodiment of this application. Figure 4 is a cross-sectional view taken along line I-I' of Figure 3, and Figure 5 is a cross-sectional view taken along line II-II' of Figure 3.

[0059] Referring to Figures 3 to 5, the display panel according to the first embodiment of this application may include a plurality of pixels P on a substrate 10. The display panel according to the first embodiment of this application may include a first intaglio pattern IP1 (1-1 intaglio pattern IP1-1, 1-2 intaglio pattern IP1-2, or 1-3 intaglio pattern IP1-3) in a first pattern area IA1 of each of the pixels P, and a plurality of second intaglio patterns IP2 in a second pattern area IA2 surrounding the first pattern area IA1. Pairs of light-emitting elements LD (1-1 light-emitting element LD1-1 and 1-2 light-emitting element LD1-2, 2-1 light-emitting element LD2-1 and 2-2 light-emitting element LD2-2, or 3-1 light-emitting element LD3-1 and 3-2 light-emitting element LD3-2) may be disposed on each first intaglio pattern IP1.

[0060] These pixels P can be arranged in a matrix with multiple rows and columns. However, this application is not limited to this.

[0061] The distance between adjacent pixels P can form a first gap PP. The first gap PP can be measured as the distance between the centers of the light-emitting elements LD at corresponding positions of two adjacent pixels P in the vertical or width direction. However, the measurement standard of the first gap PP in this application is not limited to this. For example, the first gap PP can also be measured as the distance between the centers of two adjacent pixels P in the vertical or width direction (in other words, the shortest distance).

[0062] Each pixel P may contain multiple sub-pixel units SP (first sub-pixel unit SP1, second sub-pixel unit SP2, and third sub-pixel unit SP3). These sub-pixel units SP may contain first sub-pixel unit SP1, second sub-pixel unit SP2, and third sub-pixel unit SP3.

[0063] These sub-pixel units SP can be arranged in various ways. According to the first embodiment, these sub-pixel units SP can be spaced apart from each other by a predetermined distance along the column direction. The second intaglio pattern IP2 can be disposed between these spaced-apart sub-pixel units SP.

[0064] The distance between adjacent sub-pixel units SP can form a second spacing SPP. The second spacing SPP can be measured as the distance between the centers of adjacent sub-pixel units SP. The second spacing SPP can also be measured as the shortest distance between the centers of the first intaglio patterns IP1 that are adjacent to each other. However, in this application, the measurement standard of the second spacing SPP is not limited to these. For example, the second spacing SPP can also be measured as the distance between the leftmost end of the first sub-pixel unit SP1 and the leftmost end of the second sub-pixel unit SP2.

[0065] The first sub-pixel unit SP1, the second sub-pixel unit SP2, and the third sub-pixel unit SP3 may each contain pairs of light-emitting elements (LDs) (1-1 LD1-1 and 1-2 LD1-2, 2-1 LD2-1 and 2-2 LD2-2, or 3-1 LD3-1 and 3-2 LD3-2). Each pair of LDs constitutes a sub-pixel. For example, the first sub-pixel unit SP1 may contain 1-1 LD1-1 and 1-2 LD1-2, the second sub-pixel unit SP2 may contain 2-1 LD2-1 and 2-2 LD2-2, and the third sub-pixel unit SP3 may contain 3-1 LD3-1 and 3-2 LD3-2.

[0066] When micro-LEDs are used as light-emitting elements (LDs), multiple micro-LEDs can be formed on a wafer and transferred to the substrate 10 of the display panel 1 to manufacture the display panel 1. During the process of transferring these micro-sized light-emitting elements (LDs) from the wafer to the substrate 10, various defects may occur.

[0067] For example, in some sub-pixels, the transfer of untransferred light-emitting elements (LDs) may fail, or the LDs may be misaligned and transferred to positions outside their intended locations. Furthermore, even if the transfer process proceeds normally, the transferred LDs themselves may be defective. Therefore, considering the potential defects that may occur during the transfer process of these LDs, multiple LDs of the same type can be transferred to a single sub-pixel. A lighting test can be performed on these LDs, and ultimately, only the LD determined to be functioning correctly can be used.

[0068] One of the light-emitting elements (LDs) can be the primary (or secondary) LD, while the other can be a backup LD. The backup LD can be a pre-transferred LD intended for use in a defective LD. When the primary LD is defective, the backup LD can serve as a replacement. Accordingly, by transferring both the primary and backup LDs to a single subpixel unit (SP), the degradation in display quality due to the failure of either the primary or backup LD can be minimized. Since color reproduction is still possible within the subpixel unit even when only one of the primary or backup subpixels is driven, yield can be improved.

[0069] For example, 1-1 light-emitting element LD1-1, 2-1 light-emitting element LD2-1 and 3-1 light-emitting element LD3-1 can be used as the main light-emitting element (or main sub-pixel), and 1-2 light-emitting element LD1-2, 2-2 light-emitting element LD2-2 and 3-2 light-emitting element LD3-2 can be used as the spare light-emitting element (or spare sub-pixel).

[0070] The paired light-emitting elements (LDs) can be arranged in various ways. According to the first embodiment, the paired light-emitting elements (LDs) can be arranged side by side along the Y-axis.

[0071] The light-emitting areas of the pair of light-emitting elements (LDs) can be arranged (or oriented) in different directions. For example, when the first gravure pattern IP1 (1-1 gravure pattern IP1-1, 1-2 gravure pattern IP1-2, or 1-3 gravure pattern IP1-3) has a length along a first direction and a length along a second direction different from the first direction, the light-emitting areas of the pair of light-emitting elements (LDs) can be offset relative to the extension line from the center of the first gravure pattern IP1 along the first or second direction in different directions (e.g., opposite directions, but not limited thereto). According to the first embodiment, the pair of light-emitting elements (LDs) can be configured such that the light-emitting areas E of these light-emitting elements are opposite to each other.

[0072] The light-emitting regions E may be biased towards one side of the light-emitting element LD. These light-emitting regions E of the light-emitting element LD may be biased towards the side where the active layers 96a and 96b are located. The active layers 96a and 96b of the light-emitting element LD may overlap with the first electrodes 93a and 93b of the light-emitting element LD, respectively. Accordingly, the light-emitting regions E according to this application may overlap with the first electrodes 93a and 93b of the light-emitting element LD.

[0073] In the display panel according to the first embodiment of this application, the light-emitting areas E of the pair of light-emitting elements LDs can be provided opposite to each other. Since the pair of light-emitting elements LDs are arranged side by side along the Y-axis, the light-emitting areas E of the pair of light-emitting elements LDs can also be arranged adjacent to each other along the Y-axis. For example, the pair of light-emitting elements LDs according to the first embodiment can be configured such that the light-emitting areas E of the pair of light-emitting elements are opposite to each other and can be vertically symmetrical about any X-axis direction.

[0074] The color wavelengths of the display panel according to the first embodiment of this application can be uniformly dispersed. When the light-emitting areas E of the pair of light-emitting elements LD are arranged adjacent to each other, the color shift in the pair of light-emitting elements LD can be significantly reduced. Accordingly, the display panel of this application can prevent the visibility of stains in the stamp-area unit. Here, stains in the stamp-area unit can refer to color differences caused by various factors such as non-uniform dispersion of color wavelengths.

[0075] The pair of light-emitting elements (LDs) can be separated by a first distance D1. The first distance D1 can be measured as the distance between the centers of the pair of light-emitting elements (in other words, the shortest distance). However, the measurement standard of the first distance D1 in this application is not limited to this. For example, the first distance D1 can also be measured as the distance between the upper end of one of the light-emitting elements LD1-1 (1-1) and the upper end of one of the light-emitting elements LD1-2 (1-2).

[0076] According to this application, the first distance D1 of the display panel can be configured to be less than the pixel distance based on the viewing distance for binocular resolution. The first distance D1 can be derived by calculating the minimum perceptible pixel spacing at the viewing distance. Binocular resolution can also be referred to as binocular acuity, binocular resolution, etc. Binocular resolution refers to the visual ability to accurately distinguish details when both eyes work together to recognize objects. Assuming that these pixels are located along a vertical line between the viewer and the screen, the binocular resolution of the pixel distance can be measured as the angle between the closest perceptible pixels along the vertical line.

[0077] For example, based on a viewer with 1.0 vision, the binocular resolution at pixel distance can be 1 / 60°. Similarly, based on a viewer with 2.0 vision, the binocular resolution at pixel distance can be 1 / 120°.

[0078] The minimum perceptible pixel spacing α at a given viewing distance can be calculated using binocular resolution BR, viewing distance VD, etc. Viewing distance VD refers to the vertical distance between the viewer and the screen. The minimum perceptible pixel spacing α at viewing distance VD can be calculated using the following equation 1. Equation 1

[0079] For example, when the viewing distance is 3 meters and the binocular resolution is 1 / 60° based on 1.0 visual acuity, by substituting VD = 3 and BR = 1 / 60 into "Equation 1", the minimum perceptible pixel spacing α at the viewing distance is approximately 872.6646.

[0080] The minimum perceptible pixel spacing α at the viewing distance can determine the first spacing PP, and the first distance D1, which is the distance between the pair of light-emitting elements, can be determined based on the determined first spacing PP.

[0081] To ensure that the viewer cannot perceive the distance difference between pixels P, the first spacing PP can be configured to be less than the minimum perceptible pixel spacing α at the viewing distance. For example, the first spacing PP can be configured to be less than 1 / 2 of the minimum perceptible pixel spacing α at the viewing distance.

[0082] The first distance D1 between the pair of light-emitting elements can be set to a value less than the first pitch PP. For example, the first distance D1 can be at most 1 / 2 of the first pitch PP. Alternatively, the first distance D1 can be less than or equal to 1 / 10 of the first pitch PP. However, the first distance D1 in the display panel of this application is not limited to this and can be set to a distance less than 1 / 10 of the first pitch PP, such as 1 / 11, 1 / 12, 1 / 13, ..., or 1 / n of the first pitch PP (where n is a number greater than 10). The first distance D1 between the pair of light-emitting elements can be set so that the first light-emitting element and the second light-emitting element are placed as close as possible.

[0083] In the display panel of this application, the pair of light-emitting elements (LDs) can be transferred using a two-stage stamping method (in other words, a stamping method including a first stamping process and a second stamping process), thereby making the first distance D1 less than the binocular resolution. The achieved first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP. Alternatively, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP and greater than or equal to 1 / 10 of the first pitch PP. Accordingly, in the display panel of this application, even if defects occur consecutively in the sub-pixels of each sub-pixel unit, the viewer may not be able to perceive the stains caused by these defects.

[0084] By employing a two-stage stamping method, the productivity (production volume) of transferring the pair of light-emitting elements (LDs) arranged (or oriented) in different directions can be improved. In the second stamping process, the distance (second distance D2) between each first gravure pattern IP1 (1-1 gravure pattern IP1-1, 1-2 gravure pattern IP1-2, or 1-3 gravure pattern IP1-3) and the second gravure pattern IP2 can be set to a predetermined distance to prevent cluster defects from occurring during the first stamping process.

[0085] Referring to FIG2 and FIG3, the display panel according to the first embodiment of the present application may include 1-1 gravure pattern IP1-1, 1-2 gravure pattern IP1-2 and 1-3 gravure pattern IP1-3 located in a plurality of first pattern areas IA1-1, IA1-2 and IA1-3 (see FIG2), and may include a plurality of second gravure patterns IP2 in the second pattern area IA2 (see FIG2).

[0086] The first gravure pattern IP1 may include gravure pattern IP1-1 (1-1), gravure pattern IP1-2 (1-2), and gravure pattern IP1-3 (1-3). Gravure pattern IP1-1, gravure pattern IP1-2, and gravure pattern IP1-3 may be spaced apart from each other, with a second gravure pattern IP2 intervening between these gravure patterns. The second gravure pattern IP2 may be disposed on one side of each of gravure pattern IP1-1, gravure pattern IP1-2, and gravure pattern IP1-3. The gravure pattern IP1-1 (1-1) and the second gravure pattern IP2 (2-3) will now be described in detail as an example with reference to the cross-sectional schematic diagrams in Figures 4 and 5.

[0087] Referring to Figures 4 and 5, a display panel according to an embodiment of this application may include a plurality of insulating layers (e.g., a first insulating layer 20, a second insulating layer 30, a third insulating layer 40, a fourth insulating layer 50, a fifth insulating layer 60, and a sixth insulating layer 70) located on a substrate 10. Between these insulating layers (e.g., the first insulating layer 20, the second insulating layer 30, the third insulating layer 40, the fourth insulating layer 50, the fifth insulating layer 60, and the sixth insulating layer 70), there is a driving circuit containing at least one transistor T, an adhesive layer (e.g., a first adhesive layer 45 and a second adhesive layer 47), and the pair of light-emitting elements LD (1-1 light-emitting element LD1-1 and 1-2 light-emitting element LD1-2). These multiple insulating layers (e.g., first insulating layer 20, second insulating layer 30, third insulating layer 40, fourth insulating layer 50, fifth insulating layer 60 and sixth insulating layer 70) may be sequentially included on the substrate 10 as the first insulating layer 20, second insulating layer 30, third insulating layer 40, fourth insulating layer 50, fifth insulating layer 60 and sixth insulating layer 70.

[0088] At least one transistor T may include a gate electrode 11, a semiconductor layer 21, an ohmic contact layer 23, a source electrode 31, and a drain electrode 33.

[0089] The gate electrode 11 may be disposed on the substrate 10. The gate electrode 11 may be formed on the same layer as the reflective layer 13 and the common power line 15 on the substrate 10. For example, the gate electrode 11 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0090] The semiconductor layer 21 may be disposed on the first insulating layer 20 to overlap with the gate electrode 11. For example, the semiconductor layer 21 may be formed of a semiconductor material including any one of amorphous silicon, polycrystalline silicon, oxide and organic materials, but this application is not limited thereto.

[0091] The ohmic contact layer 23 may be disposed on the semiconductor layer 21. The ohmic contact layer 23 is configured to form an ohmic contact between the semiconductor layer 21 and the source electrode 31 and the drain electrode 33, and this ohmic contact layer may be omitted.

[0092] The source electrode 31 may be disposed on the ohmic contact layer 23, overlapping one side of the semiconductor layer 21. The drain electrode 33 may be disposed on the other side of the ohmic contact layer 23, spaced apart from the source electrode 31. The source electrode 31 and the drain electrode 33 may be formed together. For example, the source electrode 31 and the drain electrode 33 may be formed as a single layer of a metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, or a multilayer structure using such materials.

[0093] The reflective layer 13 on the substrate 10 may be provided at least below the light-emitting area of ​​each of the light-emitting elements LD1-1 and LD1-2. For example, the reflective layer 13 may overlap with both the light-emitting elements LD1-1 and LD1-2 and may be formed as a single pattern. However, this application is not limited thereto.

[0094] A common power line 15 on the substrate 10 extends from the non-display area NA to the display area AA. The common power line 15 supplies pixel driving power from a pad portion of the non-display area NA to the pair of light-emitting elements LD.

[0095] The first insulating layer 20 may cover the gate electrode 11, reflective layer 13, common power line 15, etc., formed on the substrate 10. The first insulating layer 20 may be formed on at least the entire display area AA. The first insulating layer 20 may refer to a commonly used gate insulating layer. For example, the first insulating layer 20 may be formed as a single layer or multiple layers of inorganic materials, and may include silicon oxide (SiOx), silicon nitride (SiNx), etc. However, this application is not limited to this.

[0096] The second insulating layer 30 may cover the driving circuit containing at least one transistor T on the first insulating layer 20. The second insulating layer 30 may be formed at least over the entire display area AA and may be in contact with the first insulating layer 20 in some areas. The second insulating layer 30 may refer to a commonly used interlayer insulating layer. For example, the second insulating layer 30 may be formed of an inorganic material (e.g., silicon oxide (SiOx) or silicon nitride (SiNx)) or an organic material (e.g., benzocyclobutene or photoacrylate). The second insulating layer 30 may be omitted. However, this application is not limited thereto.

[0097] The third insulating layer 40 may be disposed on the second insulating layer 30. The third insulating layer 40 may be formed at least over the entire display area AA. For example, the third insulating layer 40 may be formed of an organic material (e.g., benzocyclobutene or photoacrylate). However, this application is not limited thereto.

[0098] The third insulating layer 40 may include at least one first gravure pattern IP1 (1-1 gravure pattern IP1-1, 1-2 gravure pattern IP1-2, or 1-3 gravure pattern IP1-3) and at least one second gravure pattern IP2. The first gravure pattern IP1 and the second gravure pattern IP2 may be formed by partially removing the thickness of the third insulating layer 40 from its upper surface. The first gravure pattern IP1 and the second gravure pattern IP2 may be spaces for mounting the light-emitting element LD during the stamping process (i.e., mounting space). The term "mounting space" does not necessarily refer to a space for fixing the light-emitting element LD. For example, a mounting space may include a space for temporarily mounting and then peeling off the light-emitting element LD during the stamping process, and a space for transferring and fixing the light-emitting element LD.

[0099] The first gravure pattern IP1 and the second gravure pattern IP2 can guide the position of the plurality of light-emitting elements LDs during the transfer process of transferring the plurality of light-emitting elements LDs to the display panel 1. During the transfer process of transferring the plurality of light-emitting elements LDs, the plurality of light-emitting elements LDs can be transferred onto the first gravure pattern IP1 and the second gravure pattern IP2.

[0100] For example, the pair of light-emitting elements LD1-1 and LD1-2 can be disposed on the 1-1 gravure pattern IP1-1, wherein a first adhesive layer 45 intervenes between the 1-1 gravure pattern IP1-1 and the pair of light-emitting elements LD1-1 and LD1-2. The 1-1 gravure pattern IP1-1 can have a predetermined area sufficient to accommodate the pair of light-emitting elements LD1-1 and LD1-2 spaced apart by a first distance D1. For example, when each light-emitting element LD is formed such that its length along the Y-axis is greater than its length along the X-axis, and the pair of light-emitting elements LD1-1 and LD1-2 are arranged side by side along the Y-axis, the 1-1 gravure pattern IP1-1 can be formed such that its length along the Y-axis is greater than its length along the X-axis.

[0101] A second adhesive layer 47 may be formed on each second gravure pattern IP2. In the display panel according to the first embodiment of this application, a second gravure pattern IP2 may be formed corresponding to each 1-1 gravure pattern IP1-1. The second gravure pattern IP2 may be an area on the 1-1 gravure pattern IP1-1 during the stamping process where one of the pair of light-emitting elements LD1-1 and LD2-1 is temporarily placed. Therefore, the second gravure pattern IP2 according to this embodiment may have an area smaller than that of the 1-1 gravure pattern IP1-1 in the plane of the display panel.

[0102] Gravure pattern IP1-1 and second gravure pattern IP2 can be spaced apart by a second distance D2. In the secondary stamping method, during the first stamping process, multiple LED chips can be transferred onto gravure pattern IP1-1 and second gravure pattern IP2. The second distance D2 can be a predetermined distance to prevent clustering defects of these light-emitting elements during the first stamping process. For example, the second distance D2 can be less than or equal to the shortest distance between a sub-pixel unit SP, i.e., 1 / 2 of the second spacing SPP.

[0103] The first adhesive layer 45 and the second adhesive layer 47 can be respectively disposed on the first gravure pattern IP1 and the second gravure pattern IP2 of the third insulating layer 40. The first adhesive layer 45 and the second adhesive layer 47 can include the first adhesive layer 45 disposed on the first gravure pattern IP1 and the second adhesive layer 47 disposed on the second gravure pattern IP2. For example, the first adhesive layer 45 and the second adhesive layer 47 can include optically clear adhesive (OCA), optically clear resin (OCR), pressure sensitive adhesive (PSA), etc. However, this application is not limited to this.

[0104] A first adhesive layer 45 may be disposed on a first gravure pattern IP1. The first adhesive layer 45 may be formed along the side surface and bottom surface of the gravure pattern IP1-1. The first adhesive layer 45 may include a lower surface Ca1 in contact with the bottom surface of the gravure pattern IP1-1, an upper surface Ca2 in contact with the first light-emitting element LD1-1 and the second light-emitting element LD1-2, and a groove H. The groove H of the first adhesive layer 45 may include a bottom surface Ca3 that is closer to the substrate 10 than the upper surface Ca2, and a side surface Ca4 located between the upper surface Ca2 and the bottom surface Ca3.

[0105] To improve the contact capability of the first electrode 93a and second electrode 91a of the first light-emitting element LD1-1 and the first electrode 93b and second electrode 91b of the second light-emitting element LD1-2, an etching process can be performed after the first light-emitting element LD1-1 and the second light-emitting element LD1-2 are transferred onto the adhesive layer. In this process, since the adhesive layer of the first light-emitting element LD1-1 and the second light-emitting element LD1-2 overlaps and is etched, a groove H in the first adhesive layer 45 can be formed.

[0106] Accordingly, a thickness difference will be generated in the first adhesive layer 45. In the first adhesive layer 45, a first thickness t1 can be formed between the lower surface Ca1 and the bottom surface Ca3 of the groove H, and a second thickness t2 can be formed between the upper surface Ca2 and the lower surface Ca1. As a result of the etching process, the first thickness t1 can be formed to be smaller than the second thickness t2.

[0107] A second adhesive layer 47 may be disposed on the second gravure pattern IP2. The second adhesive layer 47 may be formed along the side surface and bottom surface of the second gravure pattern IP2. The second gravure pattern IP2 may include a lower surface Cb1 contacting the third insulating layer 40 and an upper surface Cb2 opposite to the lower surface Cb1. A third thickness t3 may be formed between the upper surface Cb2 and the lower surface Cb1 of the second gravure pattern IP2. When the first adhesive layer 45 and the second adhesive layer 47 are formed in the same process, as a result of the etching process, the third thickness t3 may be similar to (e.g., equal to) the first thickness t1 and less than the second thickness t2.

[0108] Prior to the etching process, the first adhesive layer 45 and the second adhesive layer 47 may be disposed on the entire third insulating layer 40, including the 1-1 gravure pattern IP1-1 and the second gravure pattern IP2. Except for the 1-1 gravure pattern IP1-1 and the second gravure pattern IP2, the adhesive layers disposed on the upper surface of the third insulating layer 40 may be removed by the etching process. However, the display panel of this application is not limited to this, and the adhesive layer material may be partially present on the upper surface of the third insulating layer 40.

[0109] The pair of 1-1 light-emitting elements LD1-1 and 1-2 light-emitting elements LD1-2 can be disposed on the first adhesive layer 45. According to one embodiment, the 1-1 light-emitting elements LD1-1 and 1-2 light-emitting elements LD1-2 can respectively include a light-emitting layer, the first electrodes (or anode terminals) 93a and 93b and the second electrodes (or cathode terminals) 91a and 91b.

[0110] The light-emitting layer emits light through recombination of electrons and holes caused by the current flowing between the first electrodes 93a and 93b and the second electrodes 91a and 91b. According to one embodiment, the light-emitting layer may include first semiconductor layers 94a and 94b, active layers 96a and 96b, and second semiconductor layers 98a and 98b.

[0111] The first semiconductor layers 94a and 94b can provide electrons to the active layers 96a and 96b. For example, the first semiconductor layers 94a and 94b can be formed of an n-type GaN-based semiconductor material, and the n-type GaN-based semiconductor material can include GaN, AlGaN, InGaN, AlInGaN, etc. Here, the dopants used to dope the first semiconductor layers 94a and 94b can include Si, Ge, Se, Te, C, etc.

[0112] Active layer 96a may be provided on one side of the first semiconductor layer 94a, and active layer 96b may be provided on one side of the first semiconductor layer 94b. These active layers 96a and 96b may have a multi-quantum well (MQW) structure, comprising well layers and barrier layers having a higher bandgap than the well layers. For example, active layers 96a and 96b may have a multi-quantum well structure, such as InGaN / GaN.

[0113] Second semiconductor layers 98a and 98b can be provided on the active layers 96a and 96b, respectively, and holes can be supplied to the active layers 96a and 96b, respectively. For example, the second semiconductor layers 98a and 98b can be formed of a p-type GaN-based semiconductor material, and the p-type GaN-based semiconductor material can include GaN, AlGaN, InGaN, AlInGaN, etc. Here, the dopants used to incorporate the second semiconductor layers 98a and 98b can include Mg, Zn, Be, etc.

[0114] First electrodes 93a and 93b may be provided on the second semiconductor layers 98a and 98b, respectively. The first electrodes 93a and 93b may be connected to the source electrode 31 of at least one transistor T.

[0115] The second electrode 91a can be provided on the other side of the first semiconductor layer 94a to be electrically isolated from the active layer 96a and the second semiconductor layer 98a, and the second electrode 91b can be provided on the other side of the first semiconductor layer 94b to be electrically isolated from the active layer 96b and the second semiconductor layer 98b. The second electrodes 91a and 91b can be connected to the common power line 15.

[0116] For example, each of the first electrodes 93a and 93b and each of the second electrodes 91a and 91b may be formed of a material comprising one or more metallic materials (e.g., Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr) or alloys thereof. As another example, each of the first electrodes 93a and 93b and each of the second electrodes 91a and 91b may be formed of a transparent conductive material, and the transparent conductive material may comprise indium tin oxide (ITO) or indium zinc oxide (IZO), but this application is not limited thereto.

[0117] Light-emitting elements LD1-1 and LD1-2 emit light through recombination of electrons and holes caused by the current flowing between corresponding portions of the first electrodes 93a and 93b and corresponding portions of the second electrodes 91a and 91b. For example, light emitted from LD1-1 and LD1-2 can pass through corresponding portions of the first electrodes 93a and 93b and corresponding portions of the second electrodes 91a and 91b and can be emitted outward. Light emitted from LD1-1 and LD1-2 can pass through corresponding portions of the first electrodes 93a and 93b and corresponding portions of the second electrodes 91a and 91b in a second direction opposite to the first direction and toward the bottom surface of the intaglio pattern IP1-1 to display an image.

[0118] The fourth insulating layer 50 may be disposed on the first adhesive layer 45 and the second adhesive layer 47 and on the third insulating layer 40 on which the light-emitting element LD is formed. The fourth insulating layer 50 may be formed on the entire display area AA except for the upper surface of the light-emitting element LD. The fourth insulating layer 50 may be exposed on the upper surface of the light-emitting element LD to contact the first electrodes 93a, 93b and the second electrodes 91a, 91b on the upper surface of the light-emitting element LD.

[0119] The fourth insulating layer 50 may be formed of a black organic pigment as a photoresist material. The fourth insulating layer 50 may have a structure surrounding the light-emitting region of the light-emitting elements (LDs) and may be formed of a material containing the black pigment. For example, the fourth insulating layer 50 may be formed of inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx) containing the black pigment, or of organic materials such as benzocyclobutene or photoacrylates. However, this application is not limited to these.

[0120] A fifth insulating layer 60 may be disposed on a portion of the fourth insulating layer 50, and may be disposed at least between the first electrode 93a and the second electrode 91a of the 1-1 light-emitting element LD1-1, and at least between the first electrode 93b and the second electrode 91b of the 1-2 light-emitting element LD1-2. The fifth insulating layer 60 can prevent short circuits between the first electrode 93a and the second electrode 91a, and between the first electrode 93b and the second electrode 91b. Along the Z-axis direction relative to the substrate 10, the upper surface of the fifth insulating layer 60 disposed on a portion of the fourth insulating layer 50 may be positioned higher than the upper surface of the light-emitting element LD. For example, the fifth insulating layer 60 may protrude along the Z-axis direction relative to the substrate 10 and extend beyond the light-emitting element LD.

[0121] For example, the fifth insulating layer 60 may be formed of an organic material (e.g., benzocyclobutene or photoacrylate). However, this application is not limited thereto.

[0122] The first pixel electrode 55a, the second pixel electrode 55b, the first common electrode 51a, and the second common electrode 51b can be disposed on the substrate 10 on which the fifth insulating layer 60 is formed.

[0123] The first pixel electrode 55a of the light-emitting element LD1-1 (contact 1-1) and the second pixel electrode 55b of the light-emitting element LD1-2 (contact 1-2) can be integrally formed and connected in series. However, this application is not limited to this. For example, the first pixel electrode 55a and the second pixel electrode 55b can be formed separately and connected in parallel.

[0124] The first pixel electrode 55a and the second pixel electrode 55b can be connected in series, and therefore, the two first electrodes 93a and 93b can be connected to the source electrode 31 of at least one transistor T. The first pixel electrode 55a and the second pixel electrode 55b can be defined as anodes. For example, the first pixel electrode 55a and the second pixel electrode 55b can be provided on the upper surface and side surface of the fifth insulating layer 60 of the first electrodes 93a and 93b that overlap with the 1-1 light-emitting element LD1-1 and the 1-2 light-emitting element LD1-2, and on the side surface and bottom surface of the fourth insulating layer 50 disposed between the 1-1 light-emitting element LD1-1 and the 1-2 light-emitting element LD1-2.

[0125] A portion of the first pixel electrode 55a and the second pixel electrode 55b can be electrically connected to the source electrode 31 of at least one transistor T through contact holes provided through the second insulating layer 30 and the third insulating layer 40. The first pixel electrode 55a can be connected to the first electrode 93a of the 1-1 light-emitting element LD1-1 exposed between the fourth insulating layer 50 and the fifth insulating layer 60. The second pixel electrode 55b can be electrically connected to the first electrode 93b of the 1-2 light-emitting element LD1-2 exposed between the fourth insulating layer 50 and the fifth insulating layer 60.

[0126] Accordingly, the first electrodes 93a and 93b can be electrically connected to the source electrode 31 of at least one transistor T through the first pixel electrode 55a and the second pixel electrode 55b. For example, when the display device adopts a top-emitting scheme, the first pixel electrode 55a and the second pixel electrode 55b can be formed of a transparent conductive material. For example, when the display device adopts a bottom-emitting scheme, the first pixel electrode 55a and the second pixel electrode 55b can be formed of a reflective conductive material.

[0127] Transparent conductive materials may include indium tin oxide (ITO), indium zinc oxide (IZO), etc., but this application is not limited to these. Reflective conductive materials may include Al, Ag, Au, Pt, Cu, etc., but this application is not limited to these. When the first pixel electrode 55a and the second pixel electrode 55b are formed of reflective conductive materials, the first pixel electrode 55a and the second pixel electrode 55b may be formed as a single layer or a multilayer of single layers stacked together containing reflective conductive materials.

[0128] The first common electrode 51a and the second common electrode 51b can be electrically connected to each other. For example, the first common electrode 51a and the second common electrode 51b can be integrally formed on the outer side of the 1-1 light-emitting element LD1-1 and the 1-2 light-emitting element LD1-2. However, this application is not limited to this. In addition, the first common electrode 51a and the second common electrode 51b can be formed of the same material as the first pixel electrode 55a and the second pixel electrode 55b.

[0129] The first common electrode 51a and the second common electrode 51b can electrically connect the second electrode 91a of the 1-1 light-emitting element LD1-1 and the second electrode 91b of the 1-2 light-emitting element LD1-2 to the common power line 15, respectively. Depending on the situation, the first common electrode 51a and the second common electrode 51b can be defined as cathodes. The first common electrode 51a and the second common electrode 51b can be disposed along the upper surface, side surface and bottom surface of the fourth insulating layer 50, and along the side surface and upper surface of the fifth insulating layer 60.

[0130] For example, the first common electrode 51a may overlap with the second electrode 91a exposed between the fourth insulating layer 50 and the fifth insulating layer 60. For example, the second common electrode 51b may overlap with the second electrode 91b exposed between the fourth insulating layer 50 and the fifth insulating layer 60.

[0131] According to one embodiment, one side of the second common electrode 51b can be electrically connected to the common power line 15 through a contact hole provided to penetrate the first insulating layer 20, the second insulating layer 30, the third insulating layer 40, and the fourth insulating layer 50. According to one embodiment, one side of the first common electrode 51a can be electrically connected to the second electrode 91a of the 1-1 light-emitting element LD1-1, and the other side of the second common electrode 51b can be electrically connected to the second electrode 91b of the 1-2 light-emitting element LD1-2. Accordingly, the second electrode 91a of the 1-1 light-emitting element LD1-1 and the second electrode 91b of the 1-2 light-emitting element LD1-2 can be electrically connected to the common power line 15 through the first common electrode 51a and the second common electrode 51b, respectively.

[0132] According to one embodiment, the first pixel electrode 55a, the second pixel electrode 55b, the first common electrode 51a, and the second common electrode 51b can be formed simultaneously through a deposition process for depositing an electrode material and an electrode patterning process using lithography and etching processes. Accordingly, in the display panel according to this embodiment, the first pixel electrode 55a, the second pixel electrode 55b, the first common electrode 51a, and the second common electrode 51b for connecting the light-emitting element LD to a pixel driving circuit PD can be formed simultaneously. Furthermore, the display panel according to this embodiment simplifies the electrode connection process. Additionally, the display panel according to this embodiment significantly reduces the process time for connecting the light-emitting element LD to the pixel driving circuit PD, thereby improving the productivity of the display panel.

[0133] A sixth insulating layer 70 may be disposed on the substrate 10 on which the first pixel electrode 55a, the second pixel electrode 55b, the first common electrode 51a, and the second common electrode 51b are formed. The sixth insulating layer 70 may be configured to surround the pair of light-emitting elements LD1-1 and LD1-2. For example, as shown in FIG4, the sixth insulating layer 70 may contact the upper surfaces of the first pixel electrode 55a, the second pixel electrode 55b, the first common electrode 51a, and the second common electrode 51b in some areas. For example, as shown in FIG5, the sixth insulating layer 70 may contact the ends of the first pixel electrode 55a, the second pixel electrode 55b, the first common electrode 51a, and the second common electrode 51b in some areas. However, the display panel of this application is not limited to this.

[0134] The sixth insulating layer 70 may partially overlap with the fifth insulating layer 60 disposed on the fourth insulating layer 50. Therefore, the sixth insulating layer 70 disposed on the protruding fifth insulating layer 60 can prevent color mixing between adjacent sub-pixel units SP.

[0135] For example, the sixth insulating layer 70 may be formed of a material containing a black pigment. For example, the sixth insulating layer 70 may be formed of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), or of an organic material such as benzocyclobutene or photoacrylate. The sixth insulating layer 70 may be omitted. However, this application is not limited thereto.

[0136] A transparent buffer layer 80 may be disposed on the sixth insulating layer 70. The transparent buffer layer 80 may be disposed on the substrate 10 on which the sixth insulating layer 70 is formed to provide a flat surface. The transparent buffer layer 80 may at least cover the entire display area AA of the substrate 10. The transparent buffer layer 80 may protect the light-emitting element LD and circuitry formed on the substrate 10 from external impacts. For example, the transparent buffer layer 80 may contain an optically clear adhesive (OCA) or an optically clear resin (OCR), but this application is not limited to these.

[0137] In the following embodiments, the same description as that of the display panel according to the first embodiment will be omitted.

[0138] Figure 6 is a first modified example of a display panel according to the first embodiment of this application. Figure 6 is a planar schematic diagram of one pixel P among a plurality of pixels P.

[0139] Referring to Figures 2 and 6, the display panel of the first modified example of the first embodiment of this application may include a plurality of first intaglio patterns IP1 located in a plurality of first pattern areas IA1 (see Figure 2), and a plurality of second intaglio patterns IP2 located in a second pattern area IA2. Here, a sub-pixel unit SP comprising a pair of first light-emitting elements LD1 and a second light-emitting element LD2 may be included in each of the first intaglio patterns IP1.

[0140] According to this embodiment, the first gravure patterns IP1 can be configured to be spaced apart from each other along the X-axis. The distance between the first gravure patterns IP1 can be set to a predetermined distance to prevent clustering defects from occurring during the first stamping process. For example, the distance between the first gravure patterns IP1 can be set to a two-chip pitch or greater.

[0141] Each first intaglio pattern IP1 can be formed such that its length along the Y-axis is longer than its length along the X-axis, so that the first light-emitting element LD1 and the second light-emitting element LD2 are arranged along the Y-axis inside the first intaglio pattern IP1. In addition, each first intaglio pattern IP1 can be provided with a size such that the first light-emitting element LD1 and the second light-emitting element LD2 are spaced apart by a predetermined first distance D1.

[0142] According to this embodiment, each of the second intaglio patterns IP2 can be configured to correspond to a first intaglio pattern IP1. A second intaglio pattern IP2 can be configured on one side of each of the first intaglio patterns IP1 along the Y-axis direction. Furthermore, in the secondary stamping method, each second intaglio pattern IP2 can be spaced apart from its corresponding first intaglio pattern IP1 along the Y-axis direction by at least a predetermined second distance D2 to prevent clustering defects during the first stamping process. For example, the second distance D2 can be less than or equal to 1 / 2 of the second spacing SPP.

[0143] The second gravure pattern IP2 may be an area for temporary transfer of one of the light-emitting elements, the first light-emitting element LD1 and the second light-emitting element LD2, during the first stamping process. Accordingly, the second gravure pattern IP2 may have an area corresponding to at least one light-emitting element.

[0144] According to this embodiment, each sub-pixel unit SP may be included in each of the first gravure patterns IP1. Each sub-pixel unit SP may include a pair of first light-emitting elements LD1 and second light-emitting elements LD2. The pair of light-emitting elements LD1 and LD2 may be arranged side by side along the Y-axis direction.

[0145] The first light-emitting element LD1 and the second light-emitting element LD2 can be configured such that their light-emitting areas are opposite to each other. Here, the light-emitting area may include the area where the first electrode E1 of each of the first light-emitting element LD1 and the second light-emitting element LD2 is located. Accordingly, in the display panel of this application, by arranging the light-emitting areas of the first light-emitting element LD1 and the second light-emitting element LD2 adjacent to each other, the dispersion of color wavelengths can be stabilized.

[0146] Each of the first light-emitting element LD1 and the second light-emitting element LD2 may include a first electrode E1 and a second electrode E2. Here, the first electrode E1 is a region that overlaps with one of the active layers of the light-emitting element and may overlap with most of the light-emitting region. Accordingly, in the display panel of this application, by arranging these first electrodes E1 opposite to each other, the dispersion of color wavelengths can be stabilized.

[0147] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. The first distance D1 of the display panel according to this application can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of a first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP.

[0148] In the display panel of this application, the pair of light-emitting elements, LD1 and LD2, can be transferred using a secondary stamping method, thereby configuring a first distance D1 that is less than the minimum perceptible pixel spacing at the viewing distance. Accordingly, even if defects are continuously generated in the subpixels of each subpixel unit, the display panel of this application can prevent the viewer from perceiving stains caused by defects. When this secondary stamping method is used, the productivity of transferring the pair of light-emitting elements, LD1 and LD2, arranged in different directions, can be improved.

[0149] Figure 7 is a second modified example of the display panel according to the first embodiment of this application. Figure 7 is a plan view of one of the plurality of pixels P.

[0150] Referring to FIG2 and FIG7, the display panel of the second modified example of the first embodiment of this application may include a plurality of first intaglio patterns IP1 located in a plurality of first pattern areas IA1 (see FIG2), and may include a plurality of second intaglio patterns IP2 located in a second pattern area IA2 (see FIG2). A sub-pixel unit SP including a pair of first light-emitting elements LD1 and second light-emitting elements LD2 may be included in each of the first intaglio patterns IP1.

[0151] According to this embodiment, the first gravure patterns IP1 can be spaced apart from each other along the X-axis. Second gravure patterns IP2 can be disposed between these spaced-apart first gravure patterns IP1.

[0152] Each first intaglio pattern IP1 can be formed such that its length along the X-axis is greater than its length along the Y-axis, such that the first light-emitting element LD1 and the second light-emitting element LD2 are arranged along the X-axis inside the first intaglio pattern IP1. Each first intaglio pattern IP1 can be provided with a size that allows the first light-emitting element LD1 and the second light-emitting element LD2 to be spaced apart by a predetermined first distance D1.

[0153] According to this embodiment, each of the second intaglio patterns IP2 can be configured to correspond to each first intaglio pattern IP1. Each second intaglio pattern IP2 can be disposed on one side of each of the first intaglio patterns IP1 along the X-axis direction. In the secondary stamping method, each second intaglio pattern IP2 can be spaced apart from its corresponding first intaglio pattern IP1 along the X-axis direction by a predetermined second distance D2 to prevent clustering defects during a first stamping process. For example, the second distance D2 can be less than or equal to 1 / 2 of the second spacing SPP.

[0154] The second gravure pattern IP2 may be an area where one of the light-emitting elements, the first light-emitting element LD1 and the second light-emitting element LD2, is temporarily transferred during the first stamping process. Accordingly, the second gravure pattern IP2 may have an area corresponding to at least one light-emitting element.

[0155] According to this embodiment, the sub-pixel unit SP may include a first light-emitting element LD1 and a second light-emitting element LD2, a pair of light-emitting elements. The first light-emitting element LD1 and the second light-emitting element LD2 may be arranged side by side along the X-axis. The first light-emitting element LD1 and the second light-emitting element LD2 may be configured such that the light-emitting areas of these light-emitting elements face opposite directions about the Y-axis. Accordingly, in the display panel of this application, by arranging the light-emitting areas of the first light-emitting element LD1 and the second light-emitting element LD2 adjacently about the X=Y axis direction (diagonal direction), the dispersion of color wavelengths can be stabilized.

[0156] Each of the first light-emitting element LD1 and the second light-emitting element LD2 may include a first electrode E1 and a second electrode E2. The first electrode E1 is the region that overlaps with the active layer of the light-emitting element and may overlap with most of the light-emitting area.

[0157] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. According to the present application, the first distance D1 of the display panel can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of a first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP.

[0158] In the display panel of this application, the first light-emitting element LD1 and the second light-emitting element LD2 can be transferred using a secondary stamping method, thereby configuring the first distance D1 to be less than the minimum perceptible pixel spacing at the viewing distance. Accordingly, even if multiple defects occur consecutively in the subpixels of each subpixel unit, the display panel of this application can prevent the viewer from perceiving stains caused by these defects. When the secondary stamping method is used, the productivity of transferring the first light-emitting element LD1 and the second light-emitting element LD2, which are arranged in different directions, can be improved.

[0159] Figure 8 is a plan view of the display panel according to the second embodiment of this application, and Figure 9 is a cross-sectional view taken along line III-III' of Figure 8. Figure 8 is a plan view of one of the plurality of pixels P.

[0160] Referring to Figures 8 and 9, the display panel according to this embodiment of the present application may include 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12 located on the third insulating layer 140, a first adhesive layer 145a, 145b and a second adhesive layer (not shown) located on the third insulating layer 140, a fourth insulating layer 150 covering the first adhesive layer 145a, 145b and the second adhesive layer (not shown) and exposing the first light-emitting element LD1 and the second light-emitting element LD2, and a portion disposed on the fourth insulating layer 150. The substrate 10 comprises a fifth insulating layer 160, a first pixel electrode 155a and a second pixel electrode 155b in contact with the first electrode 93a of the first light-emitting element LD1 and the first electrode 93b of the second light-emitting element LD2, a first common electrode 151a and a second common electrode 151b in contact with the second electrodes 91a and 91b, a sixth insulating layer 170 disposed around the light-emitting elements LD1 and LD2, and a transparent buffer layer 180 disposed for planarizing the uneven surface on the substrate 10.

[0161] Referring to Figures 8 and 9 in conjunction with Figure 2, the display panel according to the second embodiment of this application may include a 1-1 intaglio pattern IP11, a 1-2 intaglio pattern IP12 and a protruding pattern EP located in each of a plurality of first pattern areas IA1-1, IA1-2 and IA1-3 (see Figure 2), and may include a plurality of second intaglio patterns IP2 in the second pattern area IA2 (see Figure 2).

[0162] Each of the multiple first pattern regions, including 1-1 gravure pattern IP11, 1-2 gravure pattern IP12, and embossed pattern EP, can be configured to be spaced apart from each other along the X-axis. Additionally, a second gravure pattern IP2 can be disposed in a second pattern region between these first pattern regions.

[0163] Gravure patterns IP11 (1-1) and IP12 (1-2) can be spaced apart from each other in the Y-axis direction. A first light-emitting element LD1 can be disposed within gravure pattern IP11 (1-1), and a second light-emitting element LD2 can be disposed within gravure pattern IP12 (1-2). Each of gravure patterns IP11 (1-1) and IP12 (1-2) can be provided with dimensions corresponding to the area of ​​at least one light-emitting element. For example, when the length of the light-emitting element in the Y-axis direction is greater than its length in the X-axis direction, each of gravure patterns IP11 (1-1) and IP12 (1-2) can be formed such that its length in the Y-axis direction is greater than its length in the X-axis direction.

[0164] A raised pattern EP can be disposed between 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12. The raised pattern EP can be formed along the length of each of the 1-1 gravure patterns IP11 and 1-2 gravure patterns IP12 in the X-axis direction. The raised pattern EP can be integrally formed with the third insulating layer 140. When the 1-1 gravure patterns IP11 and 1-2 gravure patterns IP12 of the third insulating layer 140 are formed, the raised pattern EP can be formed together with the 1-1 gravure patterns IP11 and 1-2 gravure patterns IP12.

[0165] Referring to FIG9, the protruding pattern EP may have a shape that protrudes from the bottom surfaces of the 1-1 gravure patterns IP11 and 1-2 gravure patterns IP12 in the Z-axis direction (away from the substrate 10). The protruding pattern EP may include a side surface adjacent to each of the 1-1 gravure patterns IP11 and 1-2 gravure patterns IP12. The protruding pattern EP may partially overlap with the 1-1 gravure patterns IP11 and 1-2 gravure patterns IP12.

[0166] The raised pattern EP can prevent interference between two light-emitting elements during the process of transferring these light-emitting elements onto the 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12. The 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12 can guide the position of these light-emitting elements LD during the transfer process of transferring these light-emitting elements LD to the display panel 1.

[0167] Because a protruding pattern EP is formed, this embodiment may further include protrusions 100a located on the protruding pattern EP. Protrusions 100a may include a first protrusion 150a of the fourth insulating layer 150, a second protrusion 160a of the fifth insulating layer 160, and a third protrusion 170a of the sixth insulating layer 170. The first protrusion 150a, the second protrusion 160a, and the third protrusion 170a may be naturally formed during the formation of the corresponding insulating layers due to the protruding shape of the protruding pattern EP. In some cases, the first protrusion 150a, the second protrusion 160a, and the third protrusion 170a may not be formed or may be selectively formed.

[0168] Since a protruding pattern EP is formed, a first adhesive layer can be disposed in each of the 1-1 gravure pattern IP11 and the 1-2 gravure pattern IP12. Accordingly, the first adhesive layer of this embodiment may include a first adhesive layer 145a disposed in the 1-1 gravure pattern IP11 and a first adhesive layer 145b disposed in the 1-2 gravure pattern IP12. According to this embodiment, a second gravure pattern IP2 may be disposed corresponding to one of the 1-1 gravure pattern IP11 and the 1-2 gravure pattern IP12. Each second gravure pattern IP2 may be disposed on one side of the 1-1 gravure pattern IP11 or the 1-2 gravure pattern IP12 along the X-axis direction. In addition, in the first and second stamping method, each second gravure pattern IP2 may be spaced apart from the corresponding 1-1 gravure pattern IP11 or the 1-2 gravure pattern IP12 by a predetermined second distance D2 along the X-axis direction to prevent clustering defects during a first stamping process. For example, the second distance D2 can be formed to be less than or equal to 1 / 2 of a second distance SPP.

[0169] The second gravure pattern IP2 may be an area where one of the first light-emitting element LD1 and the second light-emitting element LD2 is temporarily transferred during the first stamping process. Accordingly, the second gravure pattern IP2 may have an area corresponding to at least one light-emitting element.

[0170] The first light-emitting element LD1 can be disposed on the 1-1 gravure pattern IP11, and the second light-emitting element LD2 can be disposed on the 1-2 gravure pattern IP12. The first light-emitting element LD1 and the second light-emitting element LD2 can constitute a pixel unit SP. The first light-emitting element LD1 and the second light-emitting element LD2 can be configured such that their first electrodes E1 are opposite to each other. The first electrode E1 of the light-emitting element is the area overlapping with the active layer of the light-emitting element, and can overlap with most of the light-emitting area. Accordingly, the display panel of this application can have uniform color wavelength dispersion.

[0171] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. The first distance D1 of the display panel according to this application can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP. Accordingly, even if multiple defects occur consecutively in the subpixels of each subpixel unit, the display panel of this application can prevent the viewer from perceiving stains caused by defects. Furthermore, by employing a secondary stamping method, the productivity of transferring the first light-emitting element LD1 and the second light-emitting element LD2, which are arranged in different directions, can be improved.

[0172] Figure 10 is a first modified example of a display panel according to the second embodiment of this application. Figure 10 is a plan view of one of the plurality of pixels P.

[0173] Referring to FIG2 and FIG10, the display panel of the first modified example of the second embodiment of the present application may include 1-1 gravure pattern IP11, 1-2 gravure pattern IP12 and protruding pattern EP (see FIG2) in each of a plurality of first pattern areas IA1-1, IA1-2 and IA1-3, and may include a plurality of second gravure patterns IP2 (see FIG2) in the second pattern area IA2.

[0174] Each of the multiple first pattern regions, including 1-1 gravure pattern IP11, 1-2 gravure pattern IP12, and protruding pattern EP, can be configured to be spaced apart from each other in the X-axis direction. A second gravure pattern IP2 can be disposed in the second pattern region between these first pattern regions.

[0175] Gravure pattern IP11 (1-1) and gravure pattern IP12 (1-2) can be arranged to be spaced apart from each other in the X-axis direction. First light-emitting element LD1 can be disposed within gravure pattern IP11 (1-1). Second light-emitting element LD2 can be disposed within gravure pattern IP12 (1-2).

[0176] 1-1 Gravure pattern IP11 and 1-2 Gravure pattern IP12 may each be provided with dimensions corresponding to the area of ​​at least the light-emitting element. For example, when the length of the light-emitting element along the Y-axis is greater than the length along the X-axis, each of 1-1 Gravure pattern IP11 and 1-2 Gravure pattern IP12 may be formed such that the length along the Y-axis is greater than the length along the X-axis.

[0177] A raised pattern EP may be disposed between gravure pattern IP11 (1-1) and gravure pattern IP12 (1-2). The raised pattern EP may be formed along the length of the Y-axis of each of gravure pattern IP11 (1-1) and gravure pattern IP12 (1-2). The raised pattern EP may be integrally formed with the third insulating layer 140 (see FIG. 9). The raised pattern EP is not limited to that shown in FIG. 10, and may partially overlap with the adjacent side surfaces of the gravure patterns IP11 (1-1) and IP12 (1-2).

[0178] According to this embodiment, the second gravure patterns IP2 can be configured to correspond to gravure patterns IP11 (1-1) and IP12 (1-2). Each second gravure pattern IP2 can be disposed on one side of gravure pattern IP11 or gravure pattern IP12 along the X-axis direction. In the secondary stamping method, each second gravure pattern IP2 can be spaced apart from its corresponding gravure pattern IP11 or gravure pattern IP12 along the X-axis direction by a predetermined second distance D2 to prevent clustering defects during the first stamping process. For example, the second distance D2 can be less than or equal to 1 / 2 of the second spacing SPP.

[0179] The second gravure pattern IP2 may be an area where one of the first light-emitting elements LD1 and the second light-emitting element LD2 is temporarily transferred during the first stamping process. Accordingly, the second gravure pattern IP2 may have an area corresponding to at least one light-emitting element.

[0180] The first light-emitting element LD1 can be disposed on the 1-1 gravure pattern IP11, and the second light-emitting element LD2 can be disposed on the 1-2 gravure pattern IP12. The first light-emitting element LD1 and the second light-emitting element LD2 can constitute a pixel unit SP. In this case, the first light-emitting element LD1 and the second light-emitting element LD2 can be configured such that the light-emitting areas of these light-emitting elements are oriented in opposite directions about the Y-axis. Accordingly, in the display panel of this application, by arranging the light-emitting areas of the first light-emitting element LD1 and the second light-emitting element LD2 adjacent to each other about the X=Y axis, the dispersion of color wavelengths can be stabilized.

[0181] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. According to the present application, the first distance D1 of the display panel can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP. Accordingly, even if defects are continuously generated in the subpixels of each subpixel unit, the display panel of the present application can still prevent a viewer from perceiving stains caused by defects. Furthermore, by employing this secondary stamping method, the productivity of transferring the first light-emitting element LD1 and the second light-emitting element LD2, which are arranged in different directions, can be improved.

[0182] Figure 11A is a plan view of a display panel according to a third embodiment of this application, and Figure 11B is a plan view showing a comparison between the first and second intaglio patterns of Figure 11A. Figure 12 is a cross-sectional view taken along line IV-IV' of Figure 11A. Here, Figure 11A is a plan view of pixel P among a plurality of pixels P.

[0183] Referring to Figures 11A to 12, the display panel according to this embodiment of the present application may include 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12 located on the third insulating layer 240, a first adhesive layer 245 and a second adhesive layer 247 located on the third insulating layer 240, a fourth insulating layer 250 covering the first adhesive layer 245 and the second adhesive layer 247 and exposing the first light-emitting element LD1 and the second light-emitting element LD2, a fifth insulating layer 260 disposed on a portion of the fourth insulating layer 250, a common electrode 251b in contact with the second electrode 91b of the second light-emitting element LD2, a sixth insulating layer 270 disposed around the first light-emitting elements LD1 and the second light-emitting elements LD2, and a transparent buffer layer 280 for planarizing the uneven surface on the substrate 10.

[0184] Referring to FIG2 and FIG11A, the display panel according to the third embodiment of the present application may include 1-1 gravure pattern IP11, 1-2 gravure pattern IP12 and protruding pattern EP in each of a plurality of first pattern areas IA1-1, IA1-2 and IA1-3 (see FIG2), and may include a plurality of second gravure patterns IP2 in the second pattern area IA2 (see FIG2).

[0185] Referring to Figures 11A and 11B, in the display panel according to this embodiment, the first region A1 of each of the 1-1 gravure pattern IP11 and the 1-2 gravure pattern IP12 may be larger than the second region A2 of the second gravure pattern IP2. Referring to Figure 12, the first length A1-a of each of the 1-1 gravure pattern IP11 and the 1-2 gravure pattern IP12 along the X-axis direction may be larger than the second length A2-a of the second gravure pattern IP2 along the X-axis direction.

[0186] 1-1 Gravure pattern IP11 and 1-2 Gravure pattern IP12 may be areas that are transferred and adhered to the first light-emitting element LD1 and the second light-emitting element LD2 during the stamping process. Conversely, the second gravure pattern IP2 may be a non-transfer area in which one of the light-emitting elements, the first light-emitting element LD1 and the second light-emitting element LD2, is temporarily placed after being transferred during the stamping process but is ultimately not transferred.

[0187] Since each of the 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12 is formed in an area sufficiently larger than each of the first light-emitting elements LD1 and the second light-emitting elements LD2, a relatively strong pressure can be applied. The area formed being larger than each of the first light-emitting elements LD1 and the second light-emitting elements LD2 can refer to each of the 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12 being larger than the second gravure pattern IP2. Applying a relatively strong pressure can mean that the pressure applied to the 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12 is greater than the pressure applied to the second gravure pattern IP2. Accordingly, even if the adhesive layer is substantially unevenly formed on the 1-1 gravure pattern IP11 and 1-2 gravure pattern IP12 or a pressure difference occurs in the donor substrate, the light-emitting elements can be transferred with a relatively strong force, thereby reducing the defect rate of untransferred light-emitting elements.

[0188] Figure 13 is a plan view of a portion of a display panel according to the fourth embodiment of this application. Figure 13 is a plan view of one pixel P among a plurality of pixels P.

[0189] Referring to Figure 13 in conjunction with Figure 2, the display panel according to the fourth embodiment of this application may include a first intaglio pattern IP1 (see Figure 2) in each of a plurality of first pattern areas IA1-1, IA1-2, and IA1-3, and may include a plurality of second intaglio patterns IP2 and a plurality of first dummy intaglio patterns DP1 in a second pattern area IA2 (see Figure 2). For example, the first dummy intaglio patterns DP1 and the second intaglio patterns IP2 may be formed in the same manner.

[0190] The second intaglio pattern IP2 and the first dummy intaglio pattern DP1 can be disposed on one side of each of the first intaglio patterns IP1. The second intaglio pattern IP2 and the first dummy intaglio pattern DP1 can be configured to correspond to each pair of first light-emitting elements LD1 and second light-emitting elements LD2 disposed in the first intaglio patterns IP1. As shown in Figure 13, when the pair of light-emitting elements LD1 and LD2 are disposed side by side in the Y-axis direction, the second intaglio pattern IP2 and the first dummy intaglio pattern DP1 can also be disposed side by side in the Y-axis direction.

[0191] For example, the first dummy intaglio pattern DP1 can be configured to correspond to one side of the first light-emitting element LD1, and the second intaglio pattern IP2 can be configured to correspond to one side of the second light-emitting element LD2. Compared with the previous embodiment, the display panel according to this embodiment can further include the first dummy intaglio pattern DP1 configured to correspond to the light-emitting element. Accordingly, the display panel according to this embodiment can have improved degrees of freedom in the transfer direction. In addition, the first dummy intaglio pattern DP1 can further accommodate an adhesive layer, thereby allowing the adhesive layer within the intaglio patterns to be formed with a more uniform thickness.

[0192] Figure 14 is a first modified example of a display panel according to the fourth embodiment of this application. Figure 14 is a plan view of one of the plurality of pixels P.

[0193] Referring to FIG2 and FIG14, the display panel of the first modified example of the fourth embodiment of this application may include a first intaglio pattern IP1 in each of a plurality of first pattern areas IA1-1, IA1-2 and IA1-3 (see FIG2), and may include a plurality of second intaglio patterns IP2 and a plurality of first pseudo intaglio patterns DP1 in the second pattern area IA2 (see FIG2).

[0194] The second intaglio pattern IP2 and the first dummy intaglio pattern DP1 can be disposed on one side of each of the first intaglio patterns IP1. The first dummy patterns DP1 can also be disposed in the area on the other side of the first intaglio pattern IP1 at the edge of pixel P where the second intaglio pattern IP2 is not disposed.

[0195] For example, on one side of each of the first intaglio patterns IP1 located in the first, second, and third rows, the first dummy intaglio pattern DP1 and the second intaglio pattern IP2 can be arranged side by side in the Y-axis direction. Additionally, on the other side of the first intaglio pattern IP1 located in the first column, two first dummy intaglio patterns DP1 can be arranged side by side along the Y-axis direction.

[0196] The display panel according to this embodiment may further include a first pseudo-gravure pattern DP1, thereby further improving the degree of freedom of the transfer direction. In addition, the first pseudo-gravure pattern DP1 may also accommodate an adhesive layer, thereby forming an adhesive layer within the gravure pattern with a more uniform thickness.

[0197] Figure 15 is a plan view of a portion of a display panel according to the fifth embodiment of this application. Figure 15 is a plan view of one pixel P among a plurality of pixels P.

[0198] Referring to FIG2 and FIG15, the display panel according to the fifth embodiment of the present application may include a first intaglio pattern IP1 (see FIG2) in each of a plurality of first pattern areas IA1-1, IA1-2 and IA1-3, and may include a plurality of second intaglio patterns IP2, a plurality of first pseudo intaglio patterns DP1 and a plurality of second pseudo intaglio patterns DP2 (see FIG2) in a second pattern area IA2.

[0199] The second intaglio pattern IP2 and the first dummy intaglio pattern DP1 can be disposed on one side of each of the first intaglio patterns IP1. On the other side of the first intaglio pattern IP1 at the edge of pixel P, the first dummy patterns DP1 can be disposed in the area where the second intaglio pattern IP2 is not disposed.

[0200] The second dummy intaglio patterns DP2 can be respectively disposed in the Y-axis direction corresponding to the first intaglio patterns IP1, the plurality of second intaglio patterns IP2 and the plurality of first dummy intaglio patterns DP1. The first dummy intaglio patterns DP1 and the second dummy intaglio patterns DP2 can have an arrangement structure surrounding the first intaglio patterns IP1.

[0201] For example, seven second pseudo-intaglio patterns DP2 can be arranged side by side in the first column. For example, the first pseudo-intaglio patterns DP1, IP1, DP1, IP1, IP1, DP1, IP1, IP1, and IP1, corresponding to the seven second pseudo-intaglio patterns DP2, can be arranged sequentially from left to right in the second column.

[0202] For example, the first fake intaglio pattern DP1, the first intaglio pattern IP1, the second intaglio pattern IP2, the first intaglio pattern IP1, the second intaglio pattern IP2, the first intaglio pattern IP1, the second intaglio pattern IP2, and the second intaglio pattern IP2, respectively, can be arranged sequentially from left to right in the third column. For example, the seven second fake intaglio patterns DP2 can be arranged in the fourth column.

[0203] Compared with the previous embodiment, the display panel of this embodiment, by including the second pseudo-gravure pattern DP2, can achieve the effects of improving the freedom of transfer direction and improving the thickness uniformity of the adhesive layer.

[0204] Figure 16 is a first modified example of a display panel according to the fifth embodiment of this application. Figure 16 is a plan view of one of the plurality of pixels P.

[0205] Referring to FIG2 and FIG16, the display panel of the first modified example of the fifth embodiment of this application may include a first intaglio pattern IP1 in each of a plurality of first pattern areas IA1-1, IA1-2 and IA1-3 (see FIG2), and may include a plurality of second intaglio patterns IP2, a plurality of first pseudo intaglio patterns DP1 and a plurality of second pseudo intaglio patterns DP2 located in the second pattern area IA2 (see FIG2).

[0206] The second intaglio pattern IP2 and the first dummy intaglio pattern DP1 can be disposed on one side of each of the first intaglio patterns IP1. In addition, the first dummy patterns DP1 can also be disposed on the opposite side of the first intaglio pattern IP1 at the edge of pixel P, in the area where the second intaglio pattern IP2 is not disposed.

[0207] The second dummy intaglio patterns DP2 can be arranged in two directions, the X-axis and the Y-axis, respectively, corresponding to the first intaglio patterns IP1, the second intaglio patterns IP2 and the first dummy intaglio patterns DP1. In other words, the second dummy intaglio patterns DP2 can have an arrangement structure surrounding the first intaglio patterns IP1, the second intaglio patterns IP2 and the first dummy intaglio patterns DP1.

[0208] For example, nine second fake intaglio patterns DP2 can be arranged side-by-side in a first column. For example, the second fake intaglio patterns DP2, first fake intaglio pattern DP1, first intaglio pattern IP1, first fake intaglio pattern DP1, first fake intaglio pattern IP1, first fake intaglio pattern DP1, first fake intaglio pattern IP1, first fake intaglio pattern IP1, first fake intaglio pattern IP1, first fake intaglio pattern DP1, and second fake intaglio pattern DP2, respectively, can be arranged sequentially from left to right in a second column. For example, the nine second fake intaglio patterns DP2, respectively, can be arranged sequentially from left to right in a third column. For example, the nine second fake intaglio patterns DP2, respectively, can be arranged in a fourth column.

[0209] The second dummy intaglio patterns DP2, located at both ends of the first intaglio pattern IP1 along the X-axis, can make the thickness of the adhesive layer within the second intaglio pattern IP2 uniform, and represent an area where the light-emitting elements are temporarily transferred during the first stamping process. Accordingly, the display panel of this application can prevent excessive transfer of the light-emitting elements to the second intaglio pattern IP2 during the first stamping process. Here, the second dummy intaglio patterns DP2 located at both ends of the second and third rows of the first intaglio pattern IP1 along the X-axis can be referred to as the four second dummy intaglio patterns DP2 located at both ends of the second and third rows, as shown in FIG16.

[0210] Figure 17 is a plan view of a portion of a display panel according to the sixth embodiment of this application. Figure 17 is a plan view of one of a plurality of pixels P.

[0211] Referring to FIG2 and FIG17, the display panel according to the sixth embodiment of the present application may include a 1-1 intaglio pattern IP11, a 1-2 intaglio pattern IP12 and a protruding pattern EP3 located in each of a plurality of first pattern areas IA1-1, IA1-2 and IA1- (see FIG2), and may include a plurality of second intaglio patterns IP2, a plurality of first pseudo intaglio patterns DP1 and a plurality of second pseudo intaglio patterns DP2 located in the second pattern area IA2 (see FIG2).

[0212] This embodiment relates to the arrangement structure of the first dummy intaglio patterns DP1 and the second dummy intaglio patterns DP2 spaced apart from each other along the X-axis when each of the plurality of first pattern regions includes 1-1 gravure pattern IP11, 1-2 gravure pattern IP12 and protruding pattern EP.

[0213] The second intaglio pattern IP2 may be disposed along the X-axis on one side of each of the 1-1 intaglio patterns IP11 and 1-2 intaglio patterns IP12. The first dummy intaglio pattern DP1 may be disposed along the X-axis on the other side of the 1-1 intaglio patterns IP11 and 1-2 intaglio patterns IP12 where the second intaglio pattern IP2 is not disposed.

[0214] The second dummy intaglio patterns DP2 can be arranged around the 1-1 intaglio patterns IP11, 1-2 intaglio patterns IP12, the second intaglio patterns IP2 and the first dummy intaglio pattern DP1.

[0215] For example, twelve second fake intaglio patterns DP2 can be arranged side-by-side in the first column. For example, in the second column, the second fake intaglio pattern DP2, the first fake intaglio pattern DP1, the 1-1 intaglio pattern IP11, the 1-2 intaglio pattern IP12, the second intaglio pattern IP2, the 1-1 intaglio pattern IP11, the 1-2 intaglio pattern IP12, the second intaglio pattern IP2, the 1-1 intaglio pattern IP11, the 1-2 intaglio pattern IP12, the second intaglio pattern IP2, and the second fake intaglio pattern DP2 can be arranged sequentially from left to right, each corresponding to one of the twelve second fake intaglio patterns DP2. For example, in the third column, the twelve second fake intaglio patterns DP2 can be arranged to correspond to each of the twelve second fake intaglio patterns DP2.

[0216] Accordingly, the display panel of this embodiment can improve the degree of freedom of transfer direction and improve the uniformity of adhesive layer thickness.

[0217] Figures 18A to 18E and Figures 19A to 19F are schematic diagrams of the process plan and process cross-section according to the first embodiment of this application, respectively.

[0218] Figure 18A corresponds to the same process operation (or step) as Figure 19A, Figure 18B corresponds to the same process operation as Figure 19B, Figure 18C corresponds to the same process operation (or step) as Figure 19C, and Figure 18E corresponds to the same process operation (or step) as Figure 19D.

[0219] In Figures 18A to 18E and Figures 19A to 19F, for ease of description, the intaglio patterns IP1-1 (1-1), IP1-2 (1-2), and IP1-3 (1-3) shown in Figures 3 to 5 are shown and depicted as the first intaglio patterns IP1; the light-emitting elements LD1-1 (1-1), LD2-1 (2-1), and LD3-1 (3-1) are shown and depicted as the first light-emitting elements LD1; and the light-emitting elements LD1-2 (1-2), LD2-2 (2-2), and LD3-2 (3-2) are shown and depicted as the second light-emitting elements LD2. The first electrodes 93a and 93b in Figure 19F are the same as the first electrode E1 in Figures 18A to 18E, and the second electrodes 91a and 91b in Figure 19F are the same as the second electrode E2 in Figures 18A to 18E.

[0220] In Figures 19A to 19F, one of the cross-sectional views along line I-I' (left side) is a cross-sectional view for pixel P along the Y-axis, and the cross-sectional view along line II-II' (right side) is a cross-sectional view for pixel P along the X-axis. Furthermore, referring to Figures 18A to 19F, the XY coordinate system on the panel and the x'y' coordinate system on the donor substrate are considered to be independent of each other.

[0221] Referring to Figures 18A and 19A, the first intaglio pattern IP1 and the second intaglio pattern IP2 can be alternately disposed on the substrate 10 of the panel in the X-axis direction.

[0222] The first adhesive layer 1145 can be completely disposed on the primary third insulating layer 40'. Because the first adhesive layer 1145 is fluid, it can flow into the first gravure pattern IP1 and the second gravure pattern IP2, which are located at a relatively lower position. Therefore, apart from these first gravure patterns IP1 and the second gravure pattern IP2, the first adhesive layer 1145 can be formed on the upper part of the primary third insulating layer 40' with a relatively small thickness.

[0223] The first gravure pattern IP1 can be the area where light-emitting elements LD1 and LD2 are transferred and adhered. The second gravure pattern IP2 can be the area where light-emitting elements LD1 and LD2 are temporarily placed and detached after the first stamping process. The primary second adhesive layer 1145b formed on the second gravure pattern IP2 can have a lower surface adhesion than the primary first adhesive layer 1145a formed on the first gravure pattern IP1. Therefore, the primary second adhesive layer 1145b can be in a surface-hardened state.

[0224] On the donor substrate, a plurality of first light-emitting elements LD1 and a plurality of second light-emitting elements LD2 may be alternately arranged in the x' axis direction. Each of the second light-emitting elements LD2 on the donor substrate may be configured to correspond to a first gravure pattern IP1, and each of the first light-emitting elements LD1 on the donor substrate may be configured to correspond to a second gravure pattern IP2. Alternatively, each of the first light-emitting elements LD1 on the donor substrate may be configured to correspond to a first gravure pattern IP1, and each of the second light-emitting elements LD2 on the donor substrate may be configured to correspond to a second gravure pattern IP2.

[0225] The first electrode E1 of each of the first light-emitting element LD1 and the second light-emitting element LD2 can be aligned in the same direction. That is, the light-emitting area of ​​each of the first light-emitting element LD1 and the second light-emitting element LD2 can be aligned in the same direction along an extension line in the longitudinal or width direction of the donor substrate. For example, the light-emitting areas of each of the first light-emitting element LD1 and the second light-emitting element LD2 can be aligned in the y' axis direction of the donor substrate.

[0226] The primary first insulating layer 20', primary second insulating layer 30' and primary third insulating layer 40' can be in a state where no contact holes are formed for exposing the pixel driving circuit PD and the common power line 15.

[0227] Referring to Figures 18B and 19B, the panel and the donor substrate can be aligned, and a first stamping process can be performed. The plurality of first light-emitting elements LD1 and second light-emitting elements LD2 can be transferred from the donor substrate to the panel. For example, the second light-emitting element LD2 can be transferred to the primary first adhesive layer 1145a of the first gravure pattern IP1, and the first light-emitting element LD1 can be placed on the primary second adhesive layer 1145b of the second gravure pattern IP2.

[0228] Referring to Figures 18C and 19C, the first light-emitting element LD1 transferred to the primary second adhesive layer 1145b can be bonded to the donor substrate. This is because the adhesion of the primary second adhesive layer 1145b is relatively low. In this panel, due to the adhesion of the primary first adhesive layer 1145a, the second light-emitting element LD1 can be held transferred to the primary first adhesive layer 1145a of the first gravure pattern IP1.

[0229] Referring to Figure 18D, the donor substrate can remain parallel to the panel and rotate 180 degrees counterclockwise. The positions of the first electrode E1 and the second electrode E2 of each of the first light-emitting elements LD1 on the donor substrate can be interchanged.

[0230] Referring to Figures 18E and 19D, the first light-emitting elements LD1 can be transferred onto the panel. Each first light-emitting element LD1 can be transferred onto the primary first adhesive layer 1145a of the first gravure pattern IP1, while being spaced apart from the second light-emitting element LD2 by a first distance D1.

[0231] Referring to FIG19E, an etching process can be performed to improve the contact capability between the first electrodes 93a, 93b and the second electrodes 91a, 91b. The first adhesive layer 1145 located above the primary third insulating layer 40', excluding the first gravure patterns IP1 and IP2, can be removed. The first light-emitting elements LD1 and LD2 can be used as masks to remove the areas of the primary first adhesive layer 1145a that do not overlap with the light-emitting elements LD1 and LD2, thereby forming the first adhesive layer 45.

[0232] The first adhesive layer 45 may have a groove H formed in a region that does not overlap with the first light-emitting element LD1 and the second light-emitting element LD2. The primary second adhesive layer 1145b may be etched to a thickness similar to that of the first adhesive layer 45 to form the second adhesive layer 47.

[0233] Referring to FIG19F, the fourth insulating layer 50 and the fifth insulating layer 60 can be formed on the substrate 10 on which the first adhesive layer 45 and the second adhesive layer 47 are formed, and contact holes CH configured to expose a portion of the common power line 15 and a portion of the pixel driving circuit PD can be formed through the first insulating layer 20, the second insulating layer 30, the third insulating layer 40 and the fourth insulating layer 50. Next, the first pixel electrode 55a, the second pixel electrode 55b, the first common electrode 51a, the second common electrode 51b, the sixth insulating layer 70 and the transparent buffer layer 80 can be formed sequentially on the substrate 10 on which the fifth insulating layer 60 is formed.

[0234] As mentioned above, the display panel of this application can be configured with a second intaglio pattern IP2 to employ a secondary stamping method for transferring pairs of light-emitting elements LD1 and LD2 arranged (or oriented) in different directions.

[0235] If, for a pair of light-emitting elements including a first light-emitting element and a second light-emitting element, the first light-emitting element arranged in a first direction on the wafer is aligned on the donor substrate and then transferred to the panel, and the second light-emitting element arranged in a second direction on the wafer is aligned on the donor substrate and then transferred to the panel, then the alignment process from the wafer to the donor substrate may take a relatively long time.

[0236] In this application, by configuring the second intaglio pattern IP2, all light-emitting elements on the wafer can be aligned on the donor substrate at once, and the pairs of light-emitting elements can be arranged in different directions. Accordingly, the display panel of this application can have improved productivity (capacity reduction). In other words, the display panel of this application can increase the number of panels that can be produced within a specific time period.

[0237] By employing a secondary stamping method, the display panel of this application allows the pair of light-emitting elements arranged in different directions to be arranged closely together at a first distance less than the binocular resolution at the viewing distance, thereby preventing the viewer from perceiving blemishes caused by defects.

[0238] The display panel according to the embodiments of this application can prevent the viewer from perceiving stains caused by defects.

[0239] Furthermore, the display panel according to the embodiments of this application can improve the productivity in the process of transferring light-emitting elements.

[0240] Furthermore, the display panel according to the embodiments of this application can prevent excessive transfer of light-emitting elements onto the panel.

[0241] The benefits of this application are not limited to those described above, and other benefits not mentioned can be clearly understood by those skilled in the art to which this application pertains from the following description.

[0242] Although the embodiments of this disclosure have been described in detail above with reference to the accompanying drawings, this disclosure is not necessarily limited to these embodiments, and various changes and modifications can be made without departing from the technical spirit of this disclosure.

[0243] Therefore, the embodiments disclosed herein should be considered illustrative rather than limiting of the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments.

[0244] Accordingly, it should be understood that the above embodiments are illustrative and not limiting in any way.

[0245] The scope of this disclosure shall be interpreted as that of the claims attached, and all technical spirit within the scope of its equivalents shall be interpreted as being included within the scope of this disclosure.

[0246] These various embodiments described above can be combined to provide further embodiments. Such and other changes may be made to these embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but rather as encompassing all possible embodiments, including the full scope of equivalents claimed in these claims. Accordingly, these claims are not limited by this disclosure.

[0247] 10:Substrate 11: Gate electrode 13: Reflective layer 15: Shared power cord 20: First insulating layer 21: Semiconductor layer 23: Ohmic contact layer 30: Second insulating layer 31: Source electrode 33: Drain electrode 40, 140, 240: Third insulation layer / insulation layer 45: First adhesive layer 47: Second adhesive layer 50: Fourth Insulation Layer 51a: First common electrode 51b: Second common electrode 55a: First pixel electrode 55b: Second pixel electrode 60: Fifth insulation layer 70: Sixth Insulation Layer 80: Transparent Buffer Layer 91a, 91b: Second electrodes 93a, 93b: First electrode 94a, 94b: First semiconductor layer 96a, 96b: Active Layer 98a, 98b: Second semiconductor layer 100a:Protrusion 145a: First adhesive layer 145b: First adhesive layer 150: Fourth Insulation Layer 150a: First protrusion 151a: First common electrode 151b: Second common electrode 155a: First pixel electrode 155b: Second pixel electrode 160: Fifth Insulation Layer 160a: Second protrusion 170: Sixth Insulation Layer 170a: Third protuberance 180: Transparent buffer layer 245: First adhesive layer 247: Second adhesive layer 250: Fourth Insulation Layer 251b: Common Electrode 260: Fifth Insulation Layer 270: Sixth Insulation Layer 280: Transparent Buffer Layer AA: Display area Ca1, Cb1: Lower surface Ca2+, Cb2+: Upper surface Ca3: Bottom surface Ca4: Side surface CH: Contact Hole D1: First Distance D2: Second distance DP1: First hypothetical intaglio pattern DP2: Second dummy intaglio pattern E: Light-emitting area EP: Highlight the pattern H: Groove IA1: First pattern area IA1-1, IA1-2, IA1-3: Patterned areas IA2: Second pattern area IP1: First Intaglio Pattern IP2: Second Intaglio Pattern IP1-1, IP1-2, IP1-3 Gravure Pattern LD, LD1-1, LD1-2, LD2-1, LD2-2, LD3-1, LD3-2: Light-emitting elements LD1: First light-emitting element LD2: Second light-emitting element NA: Non-display area P: pixel PD: Pixel driving circuit SP: Subpixel unit SP1: First sub-pixel unit SP2: Second sub-pixel unit SP3: Third sub-pixel unit T: Transistor t1: First thickness t2: Second thickness t3: Third thickness [ ]

Claims

1. A display panel comprising: a substrate including a plurality of pixels, each of the pixels having a first pattern area and a second pattern area adjacent to the first pattern area; an insulating layer disposed on the substrate and including a first intaglio pattern disposed in the first pattern area; and a pair of light-emitting elements disposed on the first intaglio pattern of the insulating layer, wherein the first intaglio pattern has a length in a first direction and a length in a second direction, and each light-emitting area of ​​the pair of light-emitting elements is offset from a center of one of the first intaglio patterns along an extension line in one of the first direction or the second direction in a plurality of different directions.

2. The display panel as claimed in claim 1, wherein the display panel has a plane in a longitudinal direction and a plane in a width direction, and a cross section in a thickness direction, wherein a shortest distance between the centers of a plurality of adjacent pixels in the longitudinal direction or the width direction of the display panel is set as a first spacing, wherein a shortest distance between the centers of a plurality of light-emitting elements is set as a first distance, and wherein the first distance is less than or equal to half of the first spacing.

3. The display panel as claimed in claim 2, wherein the pair of light-emitting elements are arranged in the width direction of the display panel, and wherein the light-emitting areas of the pair of light-emitting elements are configured to be opposite to each other.

4. The display panel as claimed in claim 2, wherein the pair of light-emitting elements are arranged in the longitudinal direction of the display panel, and wherein the light-emitting areas of the pair of light-emitting elements are arranged in a diagonal direction.

5. The display panel as claimed in claim 1 further includes a first adhesive layer disposed between the first intaglio pattern of the insulating layer and the pair of light-emitting elements, wherein the first adhesive layer includes: an upper surface in contact with the pair of light-emitting elements; a lower surface in contact with the insulating layer; and a groove adjacent to the pair of light-emitting elements and defined by a bottom surface between the upper surface and the lower surface and a side surface extending between the upper surface and the bottom surface, wherein a first thickness is formed between the lower surface and the bottom surface, and a second thickness greater than the first thickness is formed between the upper surface and the lower surface.

6. The display panel as claimed in claim 5, wherein the insulating layer further includes a second intaglio pattern disposed on one side of the first intaglio pattern in the second pattern area.

7. The display panel as claimed in claim 6, wherein the first intaglio pattern is provided as a plurality of first intaglio patterns, wherein a shortest distance between a plurality of centers of the first intaglio patterns is set as a second spacing, wherein a shortest distance between the center of the first intaglio pattern and the center of the second intaglio pattern is set as a second distance, and wherein the second distance is less than or equal to half of the second spacing.

8. The display panel as claimed in claim 6 further includes a second adhesive layer located on the second intaglio pattern of the insulating layer, wherein the second adhesive layer includes: a lower surface in contact with the insulating layer; and an upper surface opposite to the lower surface of the second adhesive layer, and wherein a third thickness less than the second thickness is formed between the lower surface and the upper surface of the second adhesive layer.

9. The display panel as claimed in claim 6, wherein the first intaglio pattern comprises a 1-1 intaglio pattern and a 1-2 intaglio pattern, wherein the insulating layer further comprises a protruding pattern disposed in the first pattern region between the 1-1 intaglio pattern and the 1-2 intaglio pattern, and wherein the pair of light-emitting elements are respectively disposed in the 1-1 intaglio pattern and the 1-2 intaglio pattern.

10. The display panel as claimed in claim 9, wherein the area of ​​each of the 1-1 intaglio pattern and the 1-2 intaglio pattern is greater than the area of ​​the second intaglio pattern.

11. The display panel as claimed in claim 6, wherein the insulating layer further includes a first dummy intaglio pattern disposed in the second pattern region, and wherein the second intaglio pattern and the first dummy intaglio pattern are disposed on one side of the first intaglio pattern to correspond to each of the pair of light-emitting elements.

12. The display panel as claimed in claim 11, wherein the display panel has a plane in a longitudinal direction and a width direction and a cross section in a thickness direction, wherein the insulating layer further includes a second dummy intaglio pattern disposed in the second pattern region, and wherein the second dummy intaglio pattern is disposed on the plane to surround the first intaglio pattern, the second intaglio pattern and the first dummy intaglio pattern.

13. A method of manufacturing a display panel, comprising: preparing a substrate having an insulating layer comprising a first gravure pattern and a second gravure pattern formed thereon; forming a first adhesive layer on the first gravure pattern and a second adhesive layer on the second gravure pattern, wherein the second adhesive layer has an adhesive strength lower than that of the first adhesive layer; preparing a donor substrate having a first light-emitting element and a second light-emitting element disposed thereon; bonding the donor substrate to the substrate such that the first light-emitting element and the second light-emitting element are bonded to the first gravure pattern; and detaching from the substrate from the donor substrate, wherein the first gravure pattern has a length in a first direction and a length in a second direction different from the first direction, and each light-emitting region of the first light-emitting element and the second light-emitting element is offset from a center of the first gravure pattern along an extension line in one of the first or second directions in a plurality of different directions.

14. The method of manufacturing a display panel as described in claim 13, wherein bonding the donor substrate to the substrate to bond the first light-emitting element and the second light-emitting element to the first intaglio pattern further comprises: aligning the donor substrate and the substrate so that the first light-emitting element corresponds to the first adhesive layer and the second light-emitting element corresponds to the second adhesive layer; performing a first stamping of the donor substrate onto the substrate; the second light-emitting element remaining bonded to the donor substrate while disengaging from the substrate; rotating the donor substrate 180 degrees while maintaining a state facing the substrate; performing a second stamping of the 180-degree rotated donor substrate onto the substrate so that the second light-emitting element is spaced apart from the first light-emitting element and corresponds to the first adhesive layer; and disengaging from the substrate.

15. The method of manufacturing a display panel as described in claim 13, wherein, In the preparation of the donor substrate on which the first light-emitting element and the second light-emitting element are disposed, the light-emitting regions of the first light-emitting element and the second light-emitting element are offset from one of the extension lines of the donor substrate in a longitudinal direction or a width direction in the same direction.

16. The method of manufacturing a display panel as claimed in claim 13, wherein the display panel has a plane in a longitudinal direction and a width direction and a cross section in a thickness direction, and further includes a plurality of pixels, wherein each of the pixels includes the first intaglio pattern and the second intaglio pattern, wherein a shortest distance between the centers of a plurality of adjacent pixels in the longitudinal direction or the width direction of the display panel is set as a first spacing, wherein a shortest distance between the center of the first light-emitting element and the center of the second light-emitting element is set as a first distance, and wherein the first distance is less than or equal to half of the first spacing.

17. The method of manufacturing a display panel as described in claim 16, wherein the first light-emitting element and the second light-emitting element are arranged in the width direction of the display panel, and wherein the light-emitting areas of the first light-emitting element and the second light-emitting element are arranged opposite to each other.

18. The method of manufacturing a display panel as claimed in claim 16, wherein the first light-emitting element and the second light-emitting element are arranged in the longitudinal direction of the display panel, and wherein the light-emitting areas of the first light-emitting element and the second light-emitting element are arranged in a diagonal direction.

19. The method of manufacturing a display panel as claimed in claim 16, wherein the first intaglio pattern is provided as a plurality of first intaglio patterns, wherein a shortest distance between a plurality of centers of the first intaglio patterns is set as a second spacing, wherein a shortest distance between the center of the first intaglio pattern and the center of the second intaglio pattern is set as a second distance, and wherein the second distance is less than or equal to half of the second spacing.

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