Package structure and manufacturing method thereof
Patent Information
- Application Number
- TW114137083
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2025-09-12
- Filing Date
- 2025-09-25
- Publication Date
- 2026-10-11
- Estimated Expiration
- 2045-09-24
Smart Images

Figure TWG2TB001915684_001 
Figure TWG2TB001915684_002 
Figure TWG2TB001915684_003
Abstract
Claims
1. A packaging structure comprising: a substrate having a blind via and a first metal contact; a chip located in the blind via and having a second metal contact, wherein an upper surface of the chip is flush with an upper surface of the substrate; and a conductive structure located on the substrate and the chip and electrically connecting the first metal contact and the second metal contact, and comprising: a conductive adhesive layer directly contacting the first metal contact and the second metal contact; a metal layer located on the conductive adhesive layer and directly contacting the conductive adhesive layer; and a flexible substrate layer located on the conductive adhesive layer and the metal layer and directly contacting the conductive adhesive layer and the metal layer.
2. The packaging structure as described in claim 1 further includes: an isolation layer located on the substrate and disposed around the blind via.
3. The packaging structure as described in claim 1 further includes: a glass layer located on the conductive structure and in direct contact with the flexible substrate layer of the conductive structure.
4. The packaging structure as described in claim 3, wherein there is a gap between the glass layer and the wafer.
5. The package structure as described in claim 1 further includes: a plurality of solder bumps located on a lower surface of the substrate.
6. A method for manufacturing a package structure, comprising: drilling a blind via on a substrate; attaching a first metal contact around the blind via; placing a chip in the blind via, wherein the chip has a second metal contact; attaching a flexible substrate layer and a metal layer to a base plate; depositing a conductive adhesive layer on the metal layer to form a conductive structure; pressing the side of the base plate with the conductive structure against the side of the substrate with the chip; and removing the base plate so that the conductive structure directly contacts and electrically connects the first metal contact and the second metal contact.
7. The method of manufacturing the packaging structure as described in claim 6 further comprises: laminating a glass layer onto the flexible substrate layer.
8. The method of manufacturing the packaging structure as described in claim 7 further comprises: cutting the glass layer and the substrate into unit sizes, wherein the difference between the width of the glass layer and the width of the substrate is less than 0.1 mm.
9. The method of manufacturing the packaging structure as described in claim 6 further comprises: forming an isolation layer on the substrate.
10. The method of manufacturing the package structure as described in claim 6 further comprises: filling the blind hole with wafer adhesive before placing the wafer into the blind hole.
Citation Information
Patent Citations
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TW201101438A
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TW202335558A
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US20200219848A1
