Semiconductor structure and method for manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a gate insulating layer, a bottom conductive structure, a barrier layer, a first gate, and a second gate. The substrate has an opening. The opening includes a first sidewall, a second sidewall, and a bottom surface. The gate insulating layer includes a first sidewall spacer covering the first sidewall, a second sidewall spacer covering the second sidewall, and a bottom portion covering the bottom surface. The bottom conductive structure is located on the bottom portion of the gate insulating layer. The barrier layer is located on the top surface of the bottom conductive structure and contacts the first sidewall spacer and the second sidewall spacer. The first gate and the second gate are located on the top surface of the barrier layer and respectively contact the first sidewall spacer and the second sidewall spacer.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provide a base; An opening is formed in the substrate, the opening including a first sidewall, a second sidewall, and a bottom surface connecting the first sidewall and the second sidewall; a gate insulating layer is formed in the opening, the gate insulating layer including a first sidewall spacer covering the first sidewall, a second sidewall spacer covering the second sidewall, and a bottom portion covering the bottom surface; a bottom conductive structure is formed on the bottom portion of the gate insulating layer; a barrier layer is formed on the top surface of the bottom conductive structure, wherein the barrier layer contacts the first sidewall spacer and the second sidewall spacer; A gate layer is formed on the top surface of the barrier layer; and a portion of the gate layer is removed to form a first gate and a second gate that are separated from each other, wherein the first gate and the second gate respectively contact the first sidewall spacer and the second sidewall spacer.

2. The manufacturing method as described in claim 1, further comprising: A source layer, a host layer, and an epitaxial layer are defined in the substrate through multiple doping processes, wherein the host layer is located between the source layer and the epitaxial layer, and the top surface of the bottom conductive structure is lower than the top surface of the epitaxial layer.

3. The manufacturing method as claimed in claim 1, wherein the gate layer is formed in the opening and above the top surface of the substrate, wherein the bottom portion of the gate layer in the opening is removed by an etch-back process while the top portion of the gate layer above the top surface of the substrate is also removed, wherein after the etch-back process, the top surface of the first gate is lower than the top surface of the gate insulating layer.

4. The manufacturing method as described in claim 1, further comprising: An insulating filler material layer is formed on the gate insulating layer, the first gate and the second gate, and the barrier layer between the first gate and the second gate, wherein the top surface of the insulating filler material layer has a recess overlapping the opening; the portion of the insulating filler material layer extending beyond the opening is removed by an etching process, leaving an inner insulating layer between the first gate and the second gate, wherein the recess extends downward in the etching process to form a top trench at the top of the inner insulating layer, wherein the top trench exposes the first gate and the second gate; and a top conductive structure is formed in the top trench, wherein the top conductive structure connects the first gate and the second gate.

5. A semiconductor structure, comprising: A substrate includes an epitaxial layer, a host layer, and a source layer, wherein the host layer is located between the epitaxial layer and the source layer. The substrate has an opening that passes through the source layer and the host layer and extends into the epitaxial layer. The opening includes a first sidewall, a second sidewall, and a bottom surface connecting the first sidewall and the second sidewall. A gate insulating layer is located in the opening and includes a first sidewall spacer covering the first sidewall, a second sidewall spacer covering the second sidewall, and a bottom portion covering the bottom surface. A bottom conductive structure is located on the bottom portion of the gate insulating layer. A barrier layer is located on the top surface of the bottom conductive structure and contacts the first sidewall spacer and the second sidewall spacer. A first gate and a second gate are located on the top surface of the barrier layer and respectively contact the first sidewall spacer and the second sidewall spacer.

6. The semiconductor structure as described in claim 5, further comprising: An inner insulating layer is located between the first gate and the second gate, wherein the inner insulating layer contacts the barrier layer.

7. The semiconductor structure as described in claim 6, further comprising: A top conductive structure is located in a top trench on top of the inner insulating layer, wherein the top conductive structure connects the first gate and the second gate.

8. The semiconductor structure as claimed in claim 6, wherein the width of the inner insulating layer is smaller than the width of the barrier layer.

9. The semiconductor structure as claimed in claim 5, wherein the bottom conductive structure is surrounded by the first sidewall spacer, the second sidewall spacer, the bottom portion, and the barrier layer.

10. The semiconductor structure as claimed in claim 5, wherein the top surface of the first gate is lower than the top surface of the gate insulating layer.

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