Single-ended r / w SRAM

Abstract

A single-ended read / write static random access memory includes a cross-coupled transistor pair, a first transmission transistor, a second transmission transistor, a disturbance suppressor transistor, a pull-down transistor group, and a column control transistor. The cross-coupled transistor pair is used to store data in the storage node and the anti-storage node. The first and second transmission transistors are used to transmit data from the anti-storage node and the storage node to the transmission node, respectively. The pull-down transistor group provides discharge paths for the storage node and the anti-storage node. The column control transistor is used to control the electrical connection between the transmission node and the anti-bit line. The disturbance suppressor transistor is used to increase the threshold of the anti-storage node transition state to improve the stability of the stored data.

Claims

1. A single-ended read / write static random access memory (SRAM) comprising: a cross-coupled transistor pair receiving a power supply voltage, the cross-coupled transistor pair being electrically connected to a storage node and an anti-storage node; a first transmission transistor being electrically connected to the anti-storage node and a transmission node, and the first transmission transistor receiving a first write control signal; a second transmission transistor being electrically connected to the storage node and the transmission node, and the second transmission transistor receiving a second write control signal; and a disturbance suppression transistor being electrically connected to the anti-storage node and a disturbance suppression node, and the disturbance suppression transistor receiving the power supply voltage. A pull-down transistor group includes a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor. The first pull-down transistor is electrically connected to the storage node and the anti-storage node, and is grounded. The second pull-down transistor is electrically connected to the storage node, the anti-storage node, and the anti-disturbance node. The third pull-down transistor is electrically connected to the anti-disturbance node and the storage node, and is grounded. A column of control transistors is also included, electrically connected to the transmission node and an inverted bit line, and receives a column of control signals.

2. As in Request 1, a single-ended read / write static random access memory, wherein the cross-coupled transistor pair has a first cross-coupled transistor and a second cross-coupled transistor, the source of the first and second cross-coupled transistors receives the power supply voltage, the gate of the first cross-coupled transistor is electrically connected to the inverse storage node, the drain of the first cross-coupled transistor is electrically connected to the storage node, the gate of the second cross-coupled transistor is electrically connected to the storage node, and the drain of the second cross-coupled transistor is electrically connected to the inverse storage node.

3. As in request item 2, the single-ended read / write static random access memory, wherein the first cross-coupled transistor and the second cross-coupled transistor are high threshold voltage PMOS transistors.

4. As in Request 1, a single-ended read / write static random access memory, wherein the gate of the anti-disturbance transistor is electrically connected to the anti-storage node, the source of the anti-disturbance transistor is electrically connected to the anti-disturbance node, and the drain of the anti-disturbance transistor receives the power supply voltage.

5. As in request item 4, the single-ended read / write static random access memory, wherein the anti-disturbance transistor is a high threshold voltage NMOS transistor.

6. As in Request 4, a single-ended read / write static random access memory, wherein the drain of the first transmission transistor is electrically connected to the inverse storage node, the source of the first transmission transistor is electrically connected to the transmission node, the gate of the first transmission transistor receives the first write control signal, the drain of the second transmission transistor is electrically connected to the storage node, the source of the second transmission transistor is electrically connected to the transmission node, and the gate of the second transmission transistor receives the second write control signal.

7. The single-ended read / write static random access memory as described in request item 6, wherein the first transmission transistor and the second transmission transistor are low threshold voltage NMOS transistors.

8. As in Request 4, a single-ended read / write static random access memory, wherein one drain of the first pull-down transistor is electrically connected to the storage node, one gate of the first pull-down transistor is electrically connected to the inverted storage node, one source of the first pull-down transistor is grounded, one drain of the second pull-down transistor is electrically connected to the inverted storage node, one gate of the second pull-down transistor is electrically connected to the storage node, the source of the second pull-down transistor is electrically connected to the anti-disturbance node, one drain of the third pull-down transistor is electrically connected to the anti-disturbance node, one gate of the third pull-down transistor is electrically connected to the storage node, and one source of the third pull-down transistor is grounded, wherein the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor are high threshold voltage NMOS transistors.

9. The single-ended read / write static random access memory as claimed in claim 1 further includes a voltage selection circuit electrically connected to the cross-coupled transistor pair, the voltage selection circuit receiving the power supply voltage, the column control signal and an inverted column control signal, and the voltage selection circuit selectively transmitting the power supply voltage or a stepped-down version of the power supply voltage to the cross-coupled transistor pair under the control of the column control signal and the inverted column control signal.

10. The single-ended read / write static random access memory as claimed in claim 9, wherein the voltage selection circuit has a first voltage selection transistor, a load transistor, and a second voltage selection transistor, the source of the first voltage selection transistor receives the power supply voltage, the gate of the first voltage selection transistor receives the inverted column control signal, the drain of the first voltage selection transistor is electrically connected to the cross-coupled transistor pair, the source of the load transistor receives the power supply voltage, the gate and drain of the load transistor are electrically connected to the source of the second voltage selection transistor, the gate of the second voltage selection transistor receives the column control signal, and the drain of the second voltage selection transistor is electrically connected to the cross-coupled transistor pair.

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