Semiconductor device and method of forming the same

Abstract

The method includes forming a first gate structure and a second gate structure on a substrate, the first gate structure including a first source / drain region, and the second gate structure including a second source / drain region and a third source / drain region; forming a first silicide region along the first source / drain region, the first silicide region including a first metal; forming a first conductive material on the first silicide region; forming a second silicide region along the second source / drain region, the second silicide region including a second metal; forming a second conductive material on the second silicide region; forming a third opening to penetrate the substrate to the third source / drain region; forming a third silicide region along the third source / drain region; and filling the opening with a third conductive material, the third silicide region including a third metal, the third metal being different from the first metal.

Claims

1. A method for forming a semiconductor device, comprising: A first gate structure and a second gate structure are formed on a substrate. The first gate structure includes a first source / drain region, and the second gate structure includes a second source / drain region and a third source / drain region. An interlayer dielectric layer is formed on the front side of the first gate structure and the second gate structure. A first recess is etched to penetrate the interlayer dielectric layer to the first source / drain region. A first siliconized region is formed along the exposed surface of the first source / drain region, and the first siliconized region includes a first metal. A first conductive material is filled into the first recess. A second recess is etched to penetrate the interlayer dielectric layer to the second source / drain region. A second siliconized region is formed along the exposed surface of the second source / drain region, and the second siliconized region includes a second metal. A second conductive material is filled into the second recess. A front-side interconnect structure is formed on the front side of the first gate structure and the second gate structure; a third opening is formed to pass through the substrate to the third source / drain region; a third silicide region is formed along the exposed surface of the third source / drain region; a third conductive material is filled into the third opening, the third silicide region includes a third metal, and the third metal is different from the first metal; and a back-side interconnect structure is formed on the back side of the first gate structure and the second gate structure.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the first gate structure includes an n-type metal-oxide-semiconductor (MODS) and wherein the second gate structure includes a p-type MODS.

3. The method for forming a semiconductor device as claimed in claim 2, wherein the steps of etching the first recess and etching the second recess are performed simultaneously, the steps of forming the first silicide region and forming the second silicide region are performed simultaneously, and the steps of filling the first recess and filling the second recess are performed simultaneously.

4. A method of forming a semiconductor device as claimed in claim 3, wherein the first source / drain region comprises crystalline silicon, wherein the second source / drain region comprises crystalline silicon germanium, and wherein the first metal is the same as the second metal.

5. A method for forming a semiconductor device, comprising: A device layer is formed in a substrate, the device layer including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor including a first source / drain region and the second transistor including a second source / drain region; an interlayer dielectric layer is formed on the front side of the device layer; a first siliconized region is formed on the front side of the device layer and along the first source / drain region, and the first siliconized region includes a first metal; a second siliconized region is formed on the front side of the device layer and along the second source / drain region, and the second siliconized region includes a second metal; a first interconnect structure is formed on the interlayer dielectric layer, the first interconnect structure being coupled to the first siliconized region via a first contact plug and the first interconnect structure being coupled to the second siliconized region via a second contact plug; At least a portion of the substrate is removed to expose the back side of the device layer; a third silicide region is formed on the back side of the device layer along the first source / drain region, and the third silicide region includes a third metal; a fourth silicide region is formed on the back side of the device layer along the second source / drain region, and the fourth silicide region includes a fourth metal, wherein at least one of the first metal, the second metal, the third metal, and the fourth metal is different from the others; and a second interconnect structure is formed on the back side of the device layer, the second interconnect structure being coupled to the third silicide region via a first back side via, and the second interconnect structure being coupled to the fourth silicide region via a second back side via.

6. A method for forming a semiconductor device as claimed in claim 5, wherein the first metal is the same as the second metal, and the third metal is different from the fourth metal.

7. A method for forming a semiconductor device as claimed in claim 6, wherein the first metal, the second metal, and the third metal comprise titanium, and the fourth metal comprises nickel or platinum.

8. A semiconductor device, comprising: A device layer includes: a first transistor including a plurality of first source / drain regions, and the first transistor including an n-type metal-oxide-semiconductor (MODS); a second transistor including a plurality of second source / drain regions, and the second transistor including a first p-type MODS; and a third transistor including a plurality of third source / drain regions, and the third transistor including a second p-type MODS; a first interconnect structure located on the front side of the device layer; a first contact plug and a first metal silicide connecting one of the first source / drain regions to the first interconnect structure; a second contact plug and a second metal silicide connecting one of the second source / drain regions to the first interconnect structure; a third contact plug and a third metal silicide connecting one of the third source / drain regions to the first interconnect structure; and a second interconnect structure located on the back side of the device layer. A first via and a fourth metal silicate, connecting one of the first source / drain regions to the second interconnect structure; a second via and a fifth metal silicate, connecting one of the second source / drain regions to the second interconnect structure; and a third via and a sixth metal silicate, connecting one of the third source / drain regions to the second interconnect structure; wherein the plurality of silicate regions include the first metal silicate, the second metal silicate, the third metal silicate, the fourth metal silicate, the fifth metal silicate, and the sixth metal silicate, wherein the silicate regions of the first group include a first metal, the silicate regions of the second group include a second metal, and the first metal and the second metal are different.

9. The semiconductor device as claimed in claim 8, wherein the first metal silicide, the second metal silicide, and the fourth metal silicide comprise the first metal.

10. The semiconductor device as claimed in claim 9, wherein the fifth metal silicide and the sixth metal silicide comprise the second metal.

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