Flash memory with multi-level cell and method of manufacturing the same

Abstract

This invention proposes a flash memory with multiple storage cells, comprising a gate oxide layer on a substrate, a floating gate on the gate oxide layer, a source and a drain on opposite sides of the floating gate in the substrate, a control gate on the floating gate, and an inter-gate dielectric layer between the control gate and the floating gate. The floating gate has a first n-type doped region, a p-type doped region, and a second n-type doped region, the first n-type doped region and the second n-type doped region being adjacent to the source and the drain, respectively.

Claims

1. A flash memory having a multi-level storage cell, comprising: a substrate; a gate oxide layer located on the substrate; a first floating gate located on the gate oxide layer; a source and a first drain located on opposite sides of the first floating gate in a first direction in the substrate; a first control gate located above the first floating gate; and an inter-gate dielectric layer located between the first control gate and the first floating gate, wherein the first floating gate, the inter-gate dielectric layer, and the first control gate constitute a first multi-level storage cell; wherein the first floating gate has a first n-type doped region, a p-type doped region, and a second n-type doped region sequentially in the first direction, the first n-type doped region and the second n-type doped region being adjacent to the source and the first drain, respectively.

2. The flash memory having multiple storage units as described in claim 1, further comprising a second multiple storage unit located on one side of the first multiple storage unit in the first direction, wherein the source is a common source located between the first multiple storage unit and the second multiple storage unit, and further comprising a second drain located on the other side of the second multiple storage unit opposite to the common source.

3. A flash memory having multiple storage cells as described in claim 1, wherein the source is a self-aligned source formed in a trench on the surface of the substrate, the trench being flush with the sidewalls of the first and second multiple storage cells on both sides in the first direction.

4. The flash memory with multi-level storage cells as described in claim 1, wherein the gate dielectric layer is a silicon oxide-silicon nitride-silicon oxide three-layer composite structure.

5. The flash memory with multi-level storage units as described in claim 1, wherein the first floating gate and the first control gate are made of polysilicon.

6. The flash memory with multi-level storage units as described in claim 1, wherein the first n-type doped portion and the second n-type doped portion of the first floating gate are made of polycrystalline silicon, and the p-type doped portion of the first floating gate is made of epitaxial silicon.

7. A flash memory having multiple storage units as described in claim 1, wherein the first control gate, the gate-to-gate dielectric layer, and the sidewalls of the first floating gate are flush.

8. A method for manufacturing a flash memory with multiple storage cells, comprising: providing a substrate; sequentially forming a gate oxide layer and a first n-type doped polysilicon layer on the substrate; forming a p-type doped region in the first n-type doped polysilicon layer, the p-type doped region being in direct contact with the gate oxide layer; and sequentially forming an inter-gate dielectric layer and a second n-type doped polysilicon layer on the first n-type doped polysilicon layer and the p-type doped region; A photolithography process is performed to pattern the second n-type doped polysilicon layer, the gate dielectric layer, and the first n-type doped polysilicon layer, thereby forming a first multi-level memory cell. The first n-type doped polysilicon layer and the second n-type doped polysilicon layer are respectively patterned into a first floating gate and a first control gate during the photolithography process. The first floating gate has a first n-type doped region, a second n-type doped region, and a p-type doped region disposed between the first n-type doped region and the second n-type doped region. An ion implantation process is then performed to form a source and a first drain in the substrate on both sides of the first multi-level memory cell, respectively. The first n-type doped region is adjacent to the source, and the second n-type doped region is adjacent to the first drain.

9. A method for manufacturing a flash memory having multiple storage cells as described in claim 8, wherein the photolithography process patterns the second n-type doped polysilicon layer, the gate dielectric layer, and the first n-type doped polysilicon layer, thereby forming the first multiple storage cell and a second multiple storage cell, wherein the source is located between the second multiple storage cell and the first multiple storage cell, and the source is a common source for both.

10. A method for manufacturing a flash memory having multiple storage cells as described in claim 9, wherein the step of forming the source and the first drain in the ion implantation process comprises: forming lightly doped drains between the first and second multi-level storage cells and on opposite sides of the first and second multi-level storage cells respectively; and performing a self-aligned source process such that the lightly doped drain between the first and second multi-level storage cells forms the common source, and the lightly doped drains located on opposite sides of the first and second multi-level storage cells are respectively the first drain and a second drain.

11. A method for manufacturing a flash memory having multiple storage cells as described in claim 8, wherein the step of forming the p-type doped portion in the first n-type doped polysilicon layer comprises: sequentially forming a hard mask layer and a photoresist on the first n-type doped polysilicon layer; performing a photolithography process using the hard mask layer and the photoresist as a mask, thereby forming a slit in the first n-type doped polysilicon layer, the slit exposing the underlying gate oxide layer; and performing an epitaxial process to form a p-type in-situ doped epitaxial silicon in the slit, the p-type in-situ doped epitaxial silicon being the p-type doped portion of the first floating gate.

12. A method for manufacturing a flash memory having multiple storage cells as described in claim 8, wherein the step of forming the p-type doped region in the first n-type doped polysilicon layer comprises: forming a photoresist in the first n-type doped polysilicon layer; and performing an ion implantation process using the photoresist as a mask, thereby forming the p-type doped region in the first n-type doped polysilicon layer.

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