Adjustable mos capacitor element

Abstract

An adjustable metal-oxide-semiconductor (MOS) capacitor element is disclosed. The MOS capacitor element includes a gate terminal, a source terminal, a drain terminal, and a base terminal. The gate terminal receives a gate voltage. The source terminal receives a ground voltage. The drain terminal is electrically connected to the source terminal and receives the ground voltage. The base terminal receives a control voltage, which is different from the ground voltage. The capacitance value of the MOS capacitor element changes accordingly with the control voltage.

Description

Technical Field

[0001] This application relates to a metal-oxide-semiconductor (MOS) capacitor element, and more particularly to an MOS capacitor element packaged using an advanced packaging process. Prior Technology

[0002] Metal-oxide-semiconductor (MOS) capacitors are capacitor components implemented using transistors, typically used as filter elements in circuits. The capacitance of an MOS capacitor changes with the gate voltage. However, the capacitance of an MOS capacitor is not only affected by the gate control voltage, but also by process drift and operating temperature. This means that MOS capacitors cannot stably provide the required capacitance value for the circuit under different environments, resulting in poor circuit stability.

[0003] Therefore, how to provide a metal-oxide-semiconductor (MODS) with a stable capacitance value is one of the problems that this field seeks to solve. Summary of the Invention

[0004] To address the aforementioned technical problems, this application proposes a metal-oxide-semiconductor (MOS) capacitor element. By adjusting the voltage at the base terminal, the threshold voltage of the MOS capacitor element is changed, thereby instantly altering the capacitance value of the MOS capacitor element. This allows the MOS capacitor element to provide a stable capacitance value, achieving the effect of improving the circuit stability of the semiconductor device.

[0005] To achieve the above objectives, this application proposes an adjustable metal-oxide-semiconductor (MOSFET) element, comprising a gate terminal, a source terminal, a drain terminal, and a base terminal. The gate terminal receives a gate voltage. The source terminal receives a ground voltage. The drain terminal is electrically connected to the source terminal and receives the ground voltage. The base terminal receives a control voltage, which is different from the ground voltage. The capacitance value of the MOSFET element changes accordingly with the control voltage, and the MOSFET element is an N-type transistor.

[0006] Based on the above, this application enables the base terminal of the metal-oxide-semiconductor (MOS) capacitor to receive a control voltage but not a ground voltage, allowing the threshold voltage of the MOS capacitor to change accordingly with the control voltage. This, in turn, changes the capacitance value of the MOS capacitor in real time, making its capacitance value unaffected by process deviations and operating temperatures. Furthermore, the MOS capacitor provides a stable capacitance value, achieving the effect of better circuit stability in semiconductor devices using MOS capacitors. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of an embodiment of a metal-oxide-semiconductor element according to an embodiment of this application.

[0008] Figure 2 is a schematic diagram showing the change in unit capacitance of a metal-oxide-semiconductor element according to an embodiment of this application.

[0009] Figure 3 is a schematic diagram of a semiconductor device according to an embodiment of this application.

[0010] Figure 4 is a schematic diagram of the circuit architecture of a semiconductor device according to an embodiment of this application.

[0011] Figure 5 is a schematic diagram of the configuration of the frequency variable element according to an embodiment of this application.

[0012] Figure 6 is a schematic diagram of the matching adjustment circuit according to an embodiment of this application.

[0013] Figure 7 is a schematic diagram of the steps of the attribute matching method according to an embodiment of this application. Implementation

[0014] Please refer to Figure 1, which is a schematic diagram of an embodiment of the metal-oxide-semiconductor (MOS) capacitor 10 according to this application. The MOS capacitor 10 has a gate terminal G, a source terminal S, a drain terminal D, and a body terminal B. The gate terminal G is used to receive the gate voltage VG. The source terminal S is used to receive the ground voltage GND. The drain terminal D is electrically connected to the source terminal S and receives the ground voltage GND. The body terminal B receives a control voltage VB, which is different from the ground voltage GND. In this embodiment, the MOS capacitor 10 can be implemented by an N-type transistor, and this application is not limited thereto.

[0015] Compared to conventional metal-oxide-semiconductor (MOS) capacitors, the base terminal B of the MOS capacitor element 10 in this application is not grounded, and the base terminal B of the MOS capacitor element 10 is used to receive the control voltage VB. Therefore, the threshold voltage (or critical voltage) of the MOS capacitor element 10 changes accordingly with the control voltage VB, and the capacitance value of the MOS capacitor element 10 changes simultaneously with the threshold voltage. Thus, the capacitance value of the MOS capacitor element 10 can be changed according to the control voltage VB. That is, the MOS capacitor element 10 of this application further adjusts its capacitance value by adjusting the control voltage VB received at its base terminal B, so that the MOS capacitor element 10 can have a stable capacitance value unaffected by process deviations and operating temperatures, thereby achieving the effect of better circuit stability.

[0016] Please refer to Figure 2. Figure 2 shows the unit capacitance value changes of the metal-oxide-semiconductor (MOS) capacitor element 10 of this application and conventional MOS capacitors under different gate voltages VG. The gate voltage VG is in volts (V), and the unit capacitance value is nanofarads per square millimeter (nF / mm²). Component symbol N represents the unit capacitance value change of conventional MOS capacitors. Component symbol 11 represents the unit capacitance value change of the MOS capacitor element 10 of this application when the control voltage VB is 1 volt (V). Component symbol 12 represents the unit capacitance value change of the MOS capacitor element 10 of this application when the control voltage VB is 2 volts (V). Component symbol 13 represents the unit capacitance value change of the MOS capacitor element 10 of this application when the control voltage VB is 3 volts (V). Component symbol 14 represents the unit capacitance value change of the MOS capacitor element 10 of this application when the control voltage VB is 3.3 volts (V). As shown in Figure 2, compared to conventional metal-oxide-semiconductor (MOS) capacitors, the MOS capacitor element 10 of this application has different capacitance values ​​due to receiving different control voltages VB. Furthermore, the MOS capacitor element 10 of this application exhibits a more stable capacitance value than conventional MOS capacitors under different gate voltages VG. Therefore, the MOS capacitor element 10 of this application can maintain a stable capacitance value unaffected by process deviations and operating temperatures, thereby achieving better circuit stability.

[0017] Please refer to Figure 3, which is a schematic diagram of an embodiment of the semiconductor device of this application. The semiconductor device 100 has an electronic component layer 110 and a carrier layer 120. The electronic component layer 110 includes a plurality of electronic components and is disposed on the carrier layer 120. The carrier layer 120 is electrically connected to the electronic component layer 110. In this embodiment, the semiconductor device 100 is a semiconductor device packaged using a CoWoS (Chip-on-Wafer-on-Substrate) process, meaning that the electronic component layer 110 and the carrier layer 120 can be implemented through a semiconductor process and stacked before being packaged. In one embodiment, the electronic components are, for example, die components that implement a system on a chip (SoC) or a high-bandwidth memory (HBM), and this application is not limited thereto. In one embodiment, the carrier layer 120 may include a silicon interposer layer, a bridge die layer, a local silicon interconnect (LSI) layer, a redistribution layer (RDL), a semiconductor layer, a packaging layer, a board-connect layer, and / or a bonding layer. The carrier layer 120 may be electrically connected to the electronic component layer 110 directly or indirectly. For example, in an embodiment where the carrier layer 120 is a redistribution layer, a silicon interposer layer, a bridge die layer, and / or a local silicon interconnect layer may be provided between the carrier layer 120 and the electronic component layer 110. The carrier layer 120 may be electrically connected to the electronic component layer 110 through the silicon interposer layer, the bridge die layer, and / or the local silicon interconnect layer, and this application is not limited thereto.

[0018] Figure 4 is a schematic diagram of the circuit architecture of the semiconductor device 100 of this application. Figure 5 is a schematic diagram of the configuration of the frequency variable element. The semiconductor device 100 includes a frequency variable element 111, a matching control unit 130, and a matching adjustment circuit 121.

[0019] A frequency-variable element 111 is disposed on the electronic component layer 110 and is an electronic component with computing capabilities. The frequency-variable element 111 can operate in different operating states, such as overclocking, high-frequency, or low-frequency states, and this application is not limited thereto. In one embodiment, the frequency-variable element 111 may be, for example, a computing element (microprocessor element, microcontroller element, digital signal processor element, etc.), a power processing circuit element (voltage drop converter, filter element, rectifier circuit element, etc.), a signal transmitting element (transceiver), a switching element, or other element that generates a frequency phenomenon. This frequency phenomenon may be, for example, a fixed frequency, a non-fixed frequency, a variable frequency, an adjustable frequency, or any electrical frequency phenomenon, and this application is not limited thereto. The frequency-variable element 111 is disposed on a substrate 112, which carries the frequency-variable element 111. The substrate 112 is connected to the frequency-variable element 111.

[0020] Matching adjustment circuit 121 is connected to frequency variable element 111 and matching control unit 130. Matching adjustment circuit 121 has variable properties. In this embodiment, the property is capacitance value. In this embodiment, matching adjustment circuit 121 is disposed in substrate 112, and matching adjustment circuit 121 is disposed in electronic component layer 110 or carrier layer 120. In this embodiment, substrate 112 includes electronic component layer 110 or carrier layer 120 containing matching adjustment circuit 121. For example, when matching adjustment circuit 121 is disposed in electronic component layer 110, substrate 112 includes one or more layers in electronic component layer 110 that have matching adjustment circuit 121 and carry frequency variable element 111. That is, substrate 112 may include one or more layers between frequency variable element 111 and matching adjustment circuit 121 and the layer with matching adjustment circuit 121. For example, when the matching adjustment circuit 121 is disposed in the carrier layer 120, the substrate 112 includes a layer in the carrier layer 120 in which the matching adjustment circuit 121 is disposed, and one or more layers in the carrier layer 120 and the electronic component layer 110 in which the frequency variable element 111 is carried.

[0021] The matching control unit 130 is connected to the frequency variable element 111 and the matching adjustment circuit 121 . The matching control unit 130 is used to instantly detect the noise voltage of the frequency variable element 111 , and based on the noise voltage of the frequency variable element 111 determines whether to generate a control signal to adjust the properties of the matching adjustment circuit 121 through the control signal so that the zero pole of the substrate 112 matches the zero pole of the frequency variable element 111 . In this embodiment, the matching control unit 130 may be implemented by at least an existing noise detection circuit, a microcontroller element, or a microcontroller element and is not limited by this application. In this embodiment, the matching control unit 130 may be disposed in the electronic component layer 110 , the bearing layer 120 , or other intermediary layer that is electrically connected to the electronic component layer 110 and the bearing layer 120 , and is not limited by this application. In one embodiment, the matching control unit 130 may also be implemented by the frequency variable element 111 and is not limited by this application.

[0022] Since the frequency variable element 111 will operate in different operating states, causing the zero pole of the frequency variable element 111 to change with the operating state, the zero poles of the frequency variable element 111 and the substrate 112 cannot be maintained in a matching state. When the difference between the zero pole of the substrate 112 and the zero pole of the frequency variable element 111 is larger, the noise voltage of the frequency variable element 111 will increase accordingly. For example, the aliasing voltage of the bump (bump) connected to the substrate 112 of the frequency variable element 111 increases. Therefore, by detecting aliasing voltage, the zero-pole matching state between the substrate 112 and the frequency variable element 111 can be confirmed quickly and easily. At the same time, based on the operating state of the frequency variable element 111 , when the difference between the zero pole of the substrate 112 and the zero pole of the frequency variable element 111 is too large, the matching control unit 130 may match the zero pole of the substrate 112 by changing the capacitance value of the matching adjustment circuit 121 .

[0023] In one embodiment, the matching control unit 130 can determine whether the zeros and poles of the substrate 112 match the zeros and poles of the frequency variable element 111 by judging whether the noise voltage of the detected frequency variable element 111 is equal to or less than a threshold value. In one embodiment, since the zeros and poles of the frequency variable element 111 are different when operating in different operating states, the matching control unit 130 can determine its threshold value by judging the operating state of the detected frequency variable element 111, and the threshold value is the same or different for different zeros and poles. In another embodiment, the matching control unit 130 can dynamically adjust the properties of the matching adjustment circuit 121 and record the changes in noise voltage in real time until the minimum noise voltage is found, and then stop adjusting the capacitance value of the matching adjustment circuit 121. In this embodiment, the minimum noise voltage represents the zeros and poles of the substrate 112 as the best match for the frequency variable element 111. In one embodiment, the matching control unit 130 can determine whether to detect noise voltage by judging whether the operating state of the detected frequency variable element 111 changes. For example, when the matching control unit 130 determines that the frequency variable element 111 has changed from a high frequency state to a low frequency state, the matching control unit 130 then detects the noise voltage. In this way, the matching control unit 130 can avoid maintaining the noise voltage detection state for a long time, effectively reducing the overall power consumption of the semiconductor device 100.

[0024] Please refer to Figure 6, which is a schematic diagram of the matching adjustment circuit 121 of this application. The matching adjustment circuit 121 includes multiple capacitor elements 123 (123a~123n) connected in parallel. Each capacitor element 123 individually receives a bias control signal CVS (CVSa~CVSn) from the matching control unit 130. Each capacitor element 123 determines its capacitance value according to the received bias control signal CVS. One end of each capacitor element 123 is connected to terminal N1, and the other end is connected to terminal N2. In this embodiment, the capacitor element 123 can be implemented by the aforementioned metal-oxide-semiconductor capacitor element 10, and the bias control signal CVS can be implemented by the aforementioned control voltage VB. In this embodiment, the matching adjustment circuit 121 includes multiple capacitor elements 123 (123a~123n) connected in parallel, but the number of capacitor elements 123 is not limited to this embodiment, and the number of capacitor elements 123 can be one or more. In this way, the matching control unit 130 can determine the capacitance value of the capacitor element 123 by means of the bias control signal CVS, thereby increasing or decreasing the capacitance value of the matching adjustment circuit 121.

[0025] Please refer to Figure 7, which shows the attribute matching method of this application. It can be implemented by the aforementioned semiconductor device 100, and its steps include S100 to S400.

[0026] Step S100: Obtain the noise voltage. In this step, the matching control unit 130 detects the noise voltage of the frequency variable element 111 to confirm the current noise voltage of the frequency variable element 111. In one embodiment, the matching control unit 130 may further read the operating frequency of the frequency variable element 111.

[0027] Step S200: Determine whether to adjust the capacitance value of the matching adjustment circuit based on the noise voltage. In this step, the matching control unit 130 determines whether to adjust the capacitance value of the matching adjustment circuit 121 based on the noise voltage. In one embodiment, when the matching control unit 130 determines that the noise voltage is greater than a threshold value, the matching control unit 130 adjusts the capacitance value of the matching adjustment circuit 121. In one embodiment, the matching control unit 130 can dynamically adjust the capacitance value of the matching adjustment circuit 121 and record the change in noise voltage in real time until the minimum noise voltage is found, at which point the adjustment of the capacitance value of the matching adjustment circuit 121 stops. In one embodiment, the matching control unit 130 can determine whether to detect noise voltage by judging whether the operating state of the frequency variable element 111 changes. For example, when the matching control unit 130 determines that the frequency variable element 111 changes from a high-frequency state to a low-frequency state, the matching control unit 130 then detects the noise voltage. If step S200 determines yes, then in step S300, the matching control unit 130 adjusts the capacitance value of the matching adjustment circuit 121; otherwise, in step S400, the matching control unit 130 does not adjust the capacitance value of the matching adjustment circuit 121, keeping the inductance or capacitance value of the matching adjustment circuit 121 unchanged. After steps S300 and S400, the process returns to step S100.

[0028] Therefore, the attribute matching method of this application obtains the desired noise voltage by adjusting the capacitance value of the matching adjustment circuit 121, thereby matching the zeros and poles of the carrier layer 120 with the frequency variable element 111, achieving the effect of giving the semiconductor device better circuit stability.

[0029] In summary, the metal-oxide-semiconductor (MOS) capacitor and its semiconductor device of this application, by allowing the base terminal of the MOS capacitor to receive a control voltage but not a ground voltage, enables the threshold voltage of the MOS capacitor to change accordingly with the control voltage, thereby instantly changing the capacitance value of the MOS capacitor. This ensures that the MOS capacitor has a stable capacitance value unaffected by process deviations and operating temperatures, achieving better circuit stability in the semiconductor device using the MOS capacitor. Furthermore, by applying advanced processes, the matching adjustment circuit of the MOS capacitor and its semiconductor device of this application can be pre-installed on the substrate before packaging. The application uses a matching control unit to adjust the capacitance value of the matching adjustment circuit, allowing the capacitance value of the substrate to be dynamically adjusted. This enables the zeros and poles of the substrate to match the operating state of the frequency-variable element with the zeros and poles of the frequency-variable element, achieving better circuit stability in the semiconductor device.

[0030] 10: Metal-Oxide Semi-Capacitor Components 11, 12, 13, 14, N: Unit capacitance change 100: Semiconductor devices 110: Electronic Components Layer 111: Frequency Variable Component 112:Substrate 120: Bearing layer 121: Matching Adjustment Circuit 123, 123a~123n: Capacitor components 130: Matching control unit B: Basement CVS, CVSa~CVSn: Bias control signals D: Extreme G: Gate extreme GND: Grounding voltage N1, N2: Endpoints S: Source Extreme VG: Gate voltage VB: Control Voltage S100~S400: Steps

Claims

1. An adjustable metal-oxide-semiconductor capacitor element, comprising: One gate terminal receives a gate voltage; One source terminal receives a ground voltage; One of the suction terminals is electrically connected to the source terminal to receive the ground voltage; And a base terminal, receiving a control voltage that is different from the ground voltage; wherein, the capacitance value of the metal-oxide-semiconductor element changes accordingly with the control voltage, and the metal-oxide-semiconductor element is an N-type transistor.

2. The metal-oxide-semiconductor (MOS) capacitor element as described in claim 1, wherein, The threshold voltage of the metal-oxide-semiconductor element changes in response to the control voltage.

3. The metal-oxide-semiconductor element as described in claim 1, wherein, The metal-oxide-semiconductor element is disposed in a substrate of a semiconductor device to adjust the capacitance value of the substrate.

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