Fan-out panel-level packaging structure and its manufacturing method

Abstract

This invention relates to a fan-out panel-level packaging structure and its manufacturing method. The method involves first forming a redistribution circuit layer on a first substrate, then transferring it to a second substrate. A dielectric layer is formed on the second surface of the redistribution layer, and then fan-out openings are formed by recessing the second surface of the dielectric layer to complete the panel redistribution circuitry and drilling process. Next, the structure is transported to another production line where a wafer is placed to complete the subsequent wafer packaging process. Since the fan-out openings are formed before wafer placement, this fan-out panel-level packaging structure only needs to be transported once during manufacturing, eliminating the need for multiple round trips. This saves on transportation costs, reduces the risk of damage during transportation, and ultimately improves the overall yield.

Claims

1. A fan-out panel-level packaging structure, comprising: A single distributed line layer has a first surface and a second surface of a single distributed layer, and has a single distributed line; A dielectric layer having a first dielectric surface and a second dielectric surface opposite to each other, wherein the first dielectric surface is connected to the second surface of the redistribution layer; a plurality of wafer pads disposed on the first surface of the redistribution layer and connected to the redistribution circuitry; a plurality of fan-out vias formed recessed from the second surface of the dielectric layer and exposing a portion of the redistribution circuitry; a plurality of fan-out pads disposed on the fan-out vias and connected to the redistribution circuitry; a wafer connected to the wafer pads; a filler layer disposed on the first surface of the redistribution layer and covering the wafer pads; an encapsulating layer disposed on the filler layer and covering the wafer; wherein the fan-out vias are formed before the wafer is disposed.

2. The fan-out panel-level package structure as described in claim 1 further includes: an embedded component disposed in the redistribution layer and connected to the redistribution line.

3. The fan-out panel-level package structure as described in claim 2, wherein, The embedded component is either an integrated passive device (IPD) or a local silicon interconnect (LSI) chip.

4. A method for manufacturing a fan-out panel-level packaging structure, comprising the following steps: providing a first carrier board; wherein, The first carrier board has a first carrier board surface, and the first carrier board surface has a first release film, and the first release film is provided with a first seed layer; a redistribution circuit layer is formed on the first seed layer; wherein the redistribution circuit layer has a first redistribution layer surface and a second redistribution layer surface opposite to each other, and has a redistribution circuit; wherein the first redistribution layer surface is provided with a plurality of wafer pads, and the wafer pads are connected to the redistribution circuit; transferred to a second carrier board; wherein the second carrier board has a second carrier board surface, and the second carrier board surface has a second release film, and the second carrier board is disposed on the first redistribution layer surface through the second release film; the first carrier board is separated; the second redistribution layer surface is etched to remove the first seed layer; a dielectric layer is formed on the second redistribution layer surface; wherein the dielectric layer has a first dielectric layer surface and a second dielectric layer surface opposite to each other, and the first dielectric layer surface is connected to the second redistribution layer surface; A plurality of fan-out openings are formed in the dielectric layer; wherein the fan-out openings are recessed from the second surface of the dielectric layer and expose a portion of the redistribution circuitry; the circuitry is transferred to a third carrier board; wherein the third carrier board has a third carrier board surface and a third release film, and the third carrier board is disposed on the second surface of the dielectric layer through the third release film; the second carrier board is separated; a wafer is disposed on the wafer pads; wherein the wafer is connected to the wafer pads; a filler layer is disposed on the first surface of the redistribution layer; wherein the filler layer covers the wafer pads; an encapsulating layer is disposed on the filler layer; wherein the encapsulating layer covers the wafer; the third carrier board is separated; a plurality of fan-out pads are disposed in the fan-out openings; wherein the fan-out pads are connected to the redistribution circuitry.

5. A method for manufacturing the fan-out panel-level package structure as described in claim 4, wherein, An embedded element is provided in the redistribution line layer, and the embedded element is connected to the redistribution line.

6. A method for manufacturing a fan-out panel-level package structure as described in claim 5, wherein, The embedded component is either an integrated passive device (IPD) or a local silicon interconnect (LSI) chip.

7. A method for manufacturing a fan-out panel-level package structure as described in claim 4, wherein, Before separating the third carrier plate, it is first transferred to a fourth carrier plate; wherein the fourth carrier plate has a fourth carrier plate surface and the fourth carrier plate surface has a fourth release film, and the fourth carrier plate is disposed on the sealing layer through the fourth release film; wherein the fourth carrier plate is separated after a plurality of fan-out pads are disposed in the fan-out openings.

8. A method for manufacturing a fan-out panel-level package structure as described in claim 4, wherein, After the second carrier plate is separated and before the wafer is placed on the wafer pads, the third carrier plate is first cut into multiple strip-shaped carrier plates before the wafer is placed.

9. A method for manufacturing a fan-out panel-level package structure as described in claim 8, wherein, Before being transferred to the third carrier board, a protective film is first applied to the portion of the redistribution circuitry exposed by the fan-out openings, and then the circuitry is transferred to the third carrier board.

10. A method for manufacturing a fan-out panel-level package structure as described in claim 7, wherein, The fourth carrier plate is a strip-shaped carrier plate.

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