Manufacturing a semiconductor structure

Abstract

The example relates to a method of manufacturing a semiconductor structure. The method includes: depositing a first layer in contact with a first surface region of a substrate, the substrate having a first semiconductor material and the first layer having a second semiconductor material; depositing a second layer in contact with a second surface region of the substrate, the second surface region being substantially coplanar with and outside the first surface region, and the second layer having the first semiconductor material or a third semiconductor material; depositing a third layer in contact with the first layer and the second layer, the third layer having the first semiconductor material, the third semiconductor material, or a fourth semiconductor material; removing a portion of the third layer to expose a portion of the first layer; and removing at least a portion of the first layer to create a cavity between the substrate, the second layer, and the third layer.

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing semiconductor structures. [Previous Technology]

[0002] In some photonic integrated circuits (PICs), there are advantages to having a film of semiconductor material bounded by a dielectric material (such as air or a polymer material). Typically, such structures are fabricated by the following steps: depositing a first semiconductor material layer over the entire surface area of ​​a substrate; depositing a second semiconductor material layer over the entire surface area of ​​the first material layer; applying a photomask material to one or more portions of the second material layer and etching that layer to expose one or more portions of the first material layer. An etching process is then performed, in which an etchant material is passed through to the exposed portions of the first semiconductor material layer to etch it. This process is problematic because it requires careful control of the timing of applying the etchant material to the first material layer to achieve the desired dimensions. Furthermore, in some cases, it may be impossible to etch the material asymmetrically.

[0003] It is hoped that a more reliable method for manufacturing semiconductor structures can be provided. [Summary of the Invention]

[0004] One embodiment of this disclosure provides a method for manufacturing a semiconductor structure. The method includes: depositing a first layer in contact with a first surface region of a substrate, the substrate having a first semiconductor material and the first layer having a second semiconductor material; depositing a second layer in contact with a second surface region of the substrate, the second surface region being substantially coplanar with and outside the first surface region, and the second layer having the first semiconductor material or a third semiconductor material; depositing a third layer in contact with the first layer and the second layer, the third layer having the first semiconductor material or the third semiconductor material or a fourth semiconductor material; removing a portion of the third layer to expose a portion of the first layer; and removing at least a portion of the first layer to create a cavity between the substrate, the second layer, and the third layer.

[0005] Another aspect of this disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate of a first semiconductor material; a layer in contact with an outer surface region of the substrate; a layer in contact with the layer in contact with the outer surface region of the substrate, each of the layers having the first semiconductor material; and at least one of the following: a cavity, or a dielectric material, the at least one being bounded by the layers and an inner surface region of the substrate that is substantially coplanar with the outer surface region.

[0006] This disclosure further provides a photonic integrated circuit including a semiconductor structure.

Implementation Method

[0007] The examples described herein relate to methods for manufacturing semiconductor structures. In particular, but not exclusively, they relate to manufacturing films of semiconductor materials for use in photonic integrated circuits (PICs).

[0008] As will be described in detail below (for example), reference block 110 can be etched to create cavities with more precise shapes and sizes. This allows for greater design freedom and complexity in semiconductor structures used in PICs.

[0009] Figure 1 is a flowchart illustrating, in a general manner, a method 100 for manufacturing a semiconductor structure according to an example.

[0010] At block 102, a first layer is deposited, making it contact a first surface region of the substrate. The substrate has a first semiconductor material, and the first layer has a second semiconductor material.

[0011] At block 104, a second layer is deposited, making it contact a second surface region of the substrate. The second surface region is substantially coplanar with and outside the first surface region. The second layer has a first semiconductor material or a third semiconductor material different from the first semiconductor material. The first surface region may also be referred to as an inner surface region, and the second surface region may also be referred to as an outer surface region.

[0012] By saying that they are substantially coplanar, for example, by depositing a second surface layer such that it is in continuous contact with the area of ​​the substrate on which the first layer is deposited. Thus, the first surface area and the second surface area can be in the same plane as each other within acceptable manufacturing tolerances, which can be achieved by depositing the first and second layers separately.

[0013] In some instances, the first layer is deposited substantially across the entire surface area of ​​the substrate (e.g., except for the area of ​​the substrate clamped by the wafer jig of the reactor in which semiconductors are manufactured). In such instances, the second surface area is then exposed by removing the outer portion of the first layer outside the first surface area before depositing the second layer. This outer portion is removed, for example, by an etching process, which can be a dry etching process, a wet etching process, or a combination of both. In other instances, the first layer is deposited on the first surface area, rather than also on the second surface area (e.g., using a photomask).

[0014] A first layer is deposited to give it a first thickness, and a second layer is deposited to give it a second thickness substantially equal to the first thickness. In this way, the surface above the second layer is expected to be continuous with the surface above the first layer (within acceptable manufacturing tolerances). This provides a continuous (e.g., flat or planar) or nearly continuous surface on which another layer, such as the third layer described below with reference to block 106, is deposited. It is conceivable that each deposition process is subject to manufacturing tolerances, and the resulting upper surfaces may not be perfectly continuous (e.g., they cannot be formed together to form exactly flat surfaces or lie in the same plane as each other).

[0015] At block 106, a third layer is deposited, making it contact the first and second layers. The third layer has a first semiconductor material, or alternatively may have a third or fourth semiconductor material different from the first semiconductor material. For example, each of the third and fourth materials has gallium arsenide (GaAs), gallium nitride (GaN), or gallium antimonide (GaSb), and for example, substrate 202 has gallium arsenide (GaAs), gallium nitride (GaN), or gallium antimonide (GaSb).

[0016] As described above, it is conceivable that the upper surfaces of the first and second layers are substantially continuous within manufacturing tolerances. By depositing a third layer on a substantially continuous surface, the upper surface of the third layer is also substantially continuous (within the same tolerance) in order to provide, for example, a suitably flat or planar surface.

[0017] At block 108, remove a portion of the third layer to expose a portion of the first layer.

[0018] In some instances, removing a portion of the third layer includes selectively etching a portion of the third layer using a photomask. Such selective etching may comprise a dry etching process that is selective by means of the physical state of the etching process (e.g., by means of the physical effect of voltage sensing on the third layer), or it may be a wet etching process that is selective by means of a chemical preference for combining with another material (and thus selectively etching that material).

[0019] At block 110, at least a portion of the first layer is removed to create a cavity between the substrate, the second layer and the third layer.

[0020] In an example, removing at least a portion of the first layer involves applying an etchant that preferentially etches the second semiconductor material relative to the first semiconductor material. Because the first layer is surrounded by material (surrounded by the substrate, the second layer, and the third layer) that is etched by the etchant (if this occurs), and the etch rate is much lower than that of the first layer being etched by the etchant, the surrounding layers provide a so-called "termination etch," which allows the etching process to be performed without strict control over the timing of the etching process. Alternatively, the material properties surrounding the first layer provide a physical boundary to prevent any or any significant over-etching of the surrounding material. That is, material not intended to be etched will not be etched by the etchant to the extent that it impairs the performance of the resulting structure. Therefore, the side of the cavity created by removing at least a portion of the first layer can correspond to the side of the second layer (e.g., bounded by the side of the second layer). Since the cavity is partially etched into the second layer, this side of the cavity can have a substantially planar surface rather than a curved shape. Therefore, cavities with more precise shape and size can be created. This additional control over known techniques allows for greater design freedom and complexity in semiconductor structures.

[0021] In some examples, the cavity is, for example, an air-filled gap or space located between the third layer and the substrate in a first direction (perpendicular to the substrate plane) and between portions outside the second layer in a second direction (perpendicular to the first direction and parallel to the substrate plane). Thus, the sides of the cavity correspond to the surfaces of the substrate (e.g., a first surface region), at least one inner surface of the second layer, and the surface of the third layer (e.g., by these surface boundaries). In examples, the cavity is then at least partially filled with a material other than air, such as a dielectric material.

[0022] For the context, the method described above with reference to FIG1 is described with reference to a PIC. A PIC is an optical circuit that integrates two or more photonic devices (e.g., devices that use light to perform functions). A PIC may include components that perform functions, such functions including, for example: emitting light; detecting light; amplifying light; guiding light; reflecting light; diffracting light; mixing light of different wavelengths; separating light of different wavelengths; polarization conversion; optical filtering; power splitting; amplitude modulation; and phase modulation. A PIC can be considered as an optical analogue of an electronic circuit.

[0023] In some instances, the third layer is used as a membrane. Such a membrane can be "active" because it contains a gain material that can amplify the light passing through the membrane (e.g., a membrane laser), or passive because it is optically transparent or absorbs light passing through the membrane.

[0024] The commercially used material platform for PICs is indium phosphide (InP), which allows for the integration of active and passive optical functions on the same wafer; however, other material platforms (such as silicon (Si), gallium arsenide (GaAs) or lithium niobate (LiNBO3)) can be used as platforms for PICs.

[0025] An example of a PIC contains hundreds of components integrated on a single chip.

[0026] The examples described above in general terms will now be explained in detail using Figures 2a to 2g, which are a series of cross-sectional views showing the formation of the semiconductor structure 200 during a manufacturing process (such as the method 100 described above with reference to Figure 1).

[0027] Figure 2a illustrates a first semiconductor structure 200a comprising a substrate 202, which is typically a semiconductor wafer on which an additional epitaxial layer is grown or deposited. In the example described herein, the substrate 202 is a substantially pure indium phosphide (InP) substrate. That is, the substrate 202 primarily comprises InP. The substrate 202 may be pure InP (within acceptable purity tolerances) or may contain other materials (such as dopants or impurities) comprising at least 99% InP. For example, the substrate 202 may be doped with a dopant material such that the substrate can be considered n-type doped, or the substrate 202 may be doped with a dopant material such that the substrate 202 can be considered p-type doped, or the substrate 202 may be doped with a dopant material such that the substrate 202 can be considered semi-insulating.

[0028] In other examples, the substrate 202 has another semiconductor material. For example, the substrate 202 has gallium arsenide (GaAs), gallium nitride (GaN), or gallium antimonide (GaSb).

[0029] A first layer 204 of semiconductor material is deposited on a first surface of the substrate 202 (hereinafter referred to as the upper surface of the substrate 202). The first layer 204 has a material different from that of the substrate 202. For example, if the substrate 202 contains InP, the first layer 204 is a semiconductor material that does not contain InP. For example, the first layer 204 is a ternary or quaternary alloy containing InP and other binary semiconductor materials (such as gallium arsenide (GaAs), indium arsenide (InAs), aluminum arsenide (AlAs), and gallium phosphide (GaP)).

[0030] In the state shown in FIG. 2a, a first photomask 206 is applied to the upper surface of the first layer 204. The photomask 206 is arranged as an etchable photomask resistant to etching. The first photomask 206 is patterned to expose portions of the first layer 204. When an etchant is applied to the first layer 204, the etchant preferentially removes the first layer 204 relative to the first photomask 206; that is, the etchant is selective in its chemical or physical interaction with the material to remove the material, such that the first layer 204 is removed by the etchant at a rate greater than the first photomask 206 is removed by the etchant. For a given etchant, the ratio of the etching rate of the first layer 204 to the etching rate of the first photomask 206 is called selectivity.

[0031] Figure 2b shows a second semiconductor structure 200b after an etching process is applied to remove a portion of the first layer 204 above the first surface region 202b of the substrate 202.

[0032] The etching process for removing the first layer 204 may be wet etching (e.g., by immersing the first semiconductor structure 200a in a liquid chemical etchant) or dry etching (e.g., by exposing the surface above the first semiconductor structure 200a to a plasma or sputtering process) or a combination of wet etching and dry etching.

[0033] After removing the portion of the first layer 204 above the second surface region 202b of the substrate 202, an additional deposition process (sometimes called a regeneration process) is performed to deposit a second layer 208 of semiconductor material, bringing it into contact with the second surface region 202b of the substrate 202, as shown in FIG2c. The second layer 208 is deposited on the second surface region 202b, which is coplanar with the first surface region 202a of the substrate 202 and is outside the first surface region 202a. That is, the thicknesses of the first layer 204 and the second layer 208 are substantially equal, such that the upper surfaces of the layers are substantially flush. Similar to the explanation given above with reference to FIG1, that the thicknesses of the first layer 204 and the second layer 208 are substantially equal, such that the upper surfaces of the layers are substantially flush, means, for example, that within the manufacturing tolerances specified above, the individual thicknesses of the first and second layers are equal, and therefore within those same manufacturing tolerances, the upper surfaces are flush with each other or in a straight line.

[0034] As shown in FIG2c, the second layer 208 is formed between the first layer 204 and the second layer 208, including a so-called "butt joint", such that the second layer 208 is adjacent to the third semiconductor structure 200c of the first layer 204.

[0035] In this example, the second layer 208 comprises the same material as the substrate 202. In some examples, the second layer 208 is a substantially pure indium phosphide (InP) substrate. That is, the substrate 202 mainly comprises InP. The substrate 202 may be pure InP, or it may contain other materials such as dopants or impurities. For example, the substrate 202 may be doped with a dopant material such that the substrate can be considered n-type doped, or the substrate 202 may be doped with a dopant material such that the substrate 202 can be considered p-type doped.

[0036] After the second layer 208 is formed, the first photomask 206 is removed. Then, a third layer 210 is deposited to contact the first layer 204 and the second layer 208, as shown in FIG2d, which illustrates a fourth semiconductor structure 200d. The third layer 210 has a first semiconductor material. For example, the third layer may contain InP and may contain the same material as the substrate 202 and the second layer 208.

[0037] After forming the third layer 210, a second photomask 212 is defined on the third layer 210 to form a fifth semiconductor structure 200e as shown in FIG2e. The second photomask 212 includes one or more openings 214. The openings 214 provide a path for etchant material to pass through.

[0038] In the first etching process (which may be a wet etching process or a dry etching process), an etchant is applied to the portion of the third layer 210 exposed by the opening 214 in the second photomask 212. The resulting sixth semiconductor structure 200f is shown in FIG2f.

[0039] In the second etching process, an etchant is applied to the first layer 204. The etchant enters the first layer 204 through the opening 214 and the corresponding opening 214 formed in the third layer 210 by the first etching process.

[0040] A second etchant process applies an etchant that preferentially etches the first layer 204 relative to the substrate 202 and the second layer 208 to create a cavity 216 as shown in FIG. 2g. The cavity 216 may be an air gap located between the third layer 218 and the substrate 202 in a first direction (perpendicular to the plane of the substrate 202) and between the materials of the second layer 208 in a second direction (perpendicular to the first direction and parallel to the plane of the substrate 202). In other instances, the cavity 216 is subsequently filled with a material other than air. For example, the cavity 216 is at least partially filled with one or more of the following: phenylcyclobutene (BCB), polymethyl methacrylate (PMMA), or SU-8. In some instances, the cavity 216 (whether filled with air or at least partially filled with a dielectric material) may be considered as defining a side of the film (corresponding to the third layer) separated from the substrate 202.

[0041] The semiconductor structure 200 manufactured according to the manufacturing method 100 described above with reference to FIG1 and shown in FIG2g can be a component of a PIC. For example, the semiconductor structure 200 is a thin-film laser or a passive thin-film waveguide.

[0042] As those skilled in the art will understand, various techniques can be used to deposit semiconductor material layers based on the examples described herein. Such techniques may be referred to as regeneration techniques, and for example, metal-organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) processes may be used.

[0043] The above examples are to be understood as illustrative examples of the present invention. It should be understood that any feature described with respect to any example may be used alone or in combination with other described features, and may also be used in combination with one or more features of any other example or any combination of any other example. Furthermore, equivalents and modifications not described above may be used without departing from the scope of the appended claims. [Simplified Explanation of the Diagram]

[0045] FIG1 is a flowchart illustrating a method for manufacturing a semiconductor structure according to an example; and FIG2a to FIG2g are a series of cross-sectional views of the semiconductor structure during various stages of manufacturing according to the example.

Claims

1. A method of manufacturing a semiconductor structure, comprising: depositing a first layer in contact with a first surface region of a substrate, the substrate having a first semiconductor material and the first layer having a second semiconductor material; depositing a second layer in contact with a second surface region of the substrate, the second surface region being substantially coplanar with and outside the first surface region, and the second layer having the first semiconductor material or a third semiconductor material, wherein the first semiconductor material and the third semiconductor material have semiconductor properties; depositing a third layer in contact with the first layer and the second layer, the third layer having the first semiconductor material or the third semiconductor material or a fourth semiconductor material; removing a portion of the third layer to expose a portion of the first layer; and removing at least a portion of the first layer to create a cavity between the substrate, the second layer and the third layer, and filling the cavity at least partially with a dielectric material.

2. The method of claim 1, wherein the first semiconductor material comprises indium phosphide.

3. The method of claim 2, wherein the second semiconductor material is a ternary alloy or a quaternary alloy that does not contain indium phosphide.

4. The method of claim 1, wherein the first layer has a first thickness and the second layer has a second thickness substantially equal to the first thickness.

5. The method of claim 4, comprising: removing an outer portion of the first layer to expose the second surface region.

6. The method of claim 5, wherein the removal includes an etching process.

7. The method of claim 6, wherein the etching process is a dry etching process.

8. The method of claim 5, which includes depositing the second layer adjacent to one side surface of the first layer.

9. The method of claim 1, wherein removing a portion of the third layer comprises: selectively etching a portion of the third layer using a photomask.

10. The method of claim 9, wherein the selective etching comprises: a dry etching process, a wet etching process, or a combination of a wet etching process and a dry etching process.

11. The method of claim 1, wherein removing the at least portion of the first layer comprises: applying an etchant that preferentially etches the second material relative to the first material.

12. The method of claim 1, wherein at least one of the third semiconductor material or the fourth semiconductor material comprises one or more of the following: indium phosphide, gallium arsenide, gallium nitride or gallium antimonide.

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