electronic machines

Abstract

The purpose of this disclosure is to provide an electronic device with improved hermeticity. The electronic device disclosed includes a semiconductor substrate, a wafer, bumps, and sidewalls. The bumps connect a plurality of bonding pads disposed on opposing main surfaces of the semiconductor substrate and the wafer. The sidewalls include a porous metal layer that annularly surrounds the area where the plurality of bumps are disposed, connecting the semiconductor substrate and the wafer. The difference in thermal expansion coefficient between the wafer and the semiconductor substrate is 0.1 ppm / ℃ or more. The wafer is a semiconductor laser, and the semiconductor substrate has a driving circuit for driving the semiconductor laser.

Description

[Technical Field]

[0001] This disclosure relates to an electronic machine. [Previous Technology]

[0002] Electronic devices that flip-chip connect electronic circuit elements to a substrate are sealed, for example, with resin to prevent the intrusion of cutting water used when the electronic devices are monolithically assembled from semiconductor wafers.

[0003] However, when sealing electronic devices with resin, there are problems such as electrode contamination caused by resin, increased operating time due to resin injection into each electronic device, and increased amount of waste resin due to increased operating time.

[0004] Therefore, there exist electronic devices in which the electrodes of electronic circuit elements are connected to the electrodes of a substrate by gold-tin bonding, gold-silver bonding, gold-aluminum bonding, or gold-gold bonding, and the peripheral portion of the electronic circuit element and the opposing substrate are joined and sealed using the same connection method as the connection between the electrodes (for example, see Patent Document 1). An electronic device is characterized in that the wafer electrodes of the aforementioned electronic circuit elements are connected to the internal electrodes of the aforementioned substrate by gold-tin (Au-Sn) bonding, gold-silver (Au-Ag) bonding, gold-aluminum (Au-Al) bonding, or gold-gold (Au-Au) bonding, and the peripheral portion or the portion requiring sealing of the aforementioned electronic circuit element and the opposing substrate are joined and sealed using the same connection method as described above. [Prior Art Documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2004-214469 [Summary of the Invention]

[0006] [The problem the invention aims to solve]

[0007] However, in the aforementioned prior art, when there are uneven thicknesses or warping in electronic circuit components or substrates, gaps sometimes form in the metal of the sealing portion, reducing the airtightness of the electronic device. Therefore, this disclosure proposes an electronic device that can improve airtightness. [Technical Means for Solving the Problem]

[0008] According to this disclosure, an electronic device is provided. The electronic device includes a semiconductor substrate, a wafer, bumps, and sidewall portions. The bumps connect a plurality of bonding pads disposed on opposing main surfaces of the semiconductor substrate and the wafer to each other. The sidewall portions include a porous metal layer that annularly surrounds the area where the plurality of bumps are disposed, connecting the semiconductor substrate and the wafer.

Implementation Method

[0010] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. In addition, in the following embodiments, repeated descriptions are omitted by marking the same parts with the same symbols and the same shading lines.

[0011] [1. Cross-sectional structure of the electronic device] FIG1 is a cross-sectional explanatory diagram of the electronic device of the present disclosure embodiment. FIG2 is a cross-sectional explanatory diagram along line A-A shown in FIG1. ​​As shown in FIG1, the electronic device 1 disclosed herein includes a semiconductor substrate 2, a wafer 3, and bumps 4 that connect the bonding pads 21 and 31 disposed on the opposing main surfaces of the semiconductor substrate 2 and the wafer 3 to each other.

[0012] Furthermore, as shown in Figures 1 and 2, the electronic device 1 includes a sidewall portion comprising a porous metal layer 51 that annularly surrounds a region on which a plurality of bumps 4 are disposed, connecting the semiconductor substrate 2 and the wafer 3. Additionally, the electronic device 1 also has electrode pads 21 disposed between the sidewall portion 5 and the semiconductor substrate 2. The bonding pads 21 disposed between the sidewall portion 5 and the semiconductor substrate 2 are not connected to the internal circuitry of the semiconductor substrate 2.

[0013] The wafer 3 is, for example, a semiconductor laser, and has a plurality of bonding pads 31 on one side of a GaAs (gallium arsenide) substrate. Furthermore, the wafer 3 has a light-emitting portion of the semiconductor laser within the substrate. The light-emitting portion has a plurality of light-emitting elements arranged in a two-dimensional configuration to emit laser light. The light-emitting elements are connected to the bonding pads 31 within the wafer 3.

[0014] Furthermore, the electronic components of the chip 3 can be any electronic component other than the light-emitting part of the semiconductor laser. Also, the substrate of the chip 3 can be a semi-insulating substrate such as InP (indium phosphide).

[0015] The semiconductor substrate 2 is, for example, a Si (silicon) substrate, and has a driving circuit for driving the semiconductor laser inside. The semiconductor substrate 2 has a plurality of bonding pads 21 on one side of its main surface. The bonding pads 21 are connected to the driving circuit inside the semiconductor substrate 2. Alternatively, the electronic circuitry on the semiconductor substrate 2 can be any electronic circuit other than the driving circuitry for the semiconductor laser.

[0016] The electronic device 1 flip-chip mounts the chip 3 onto the semiconductor substrate 2, and electrically connects the driving circuit within the semiconductor substrate 2 and the semiconductor laser, i.e., the chip 3, via bumps 4. Furthermore, the space where the electronic device 1 provides the connecting pads 21 and 31 and the bumps 4 is sealed by the side wall portion 5.

[0017] Here, for example, when a chip 3 equipped with a semiconductor laser is flip-chip mounted on a semiconductor substrate 2 equipped with a semiconductor laser driving circuit and an electronic machine is manufactured, in a general manufacturing method, a plurality of driving circuits are first formed on a silicon wafer.

[0018] Subsequently, on each drive circuit, the connecting pads 21 and 31 disposed on the opposing main surfaces of the drive circuit and the chip 3 are connected to each other by a block-shaped metal bump stacked chip 3. Furthermore, each electronic device is diced into a Si wafer and monolithically processed.

[0019] In the step of monolithically assembling the Si wafer for each electronic device, the Si wafer is diced while being supplied with cutting water. If the cutting water intrudes between the semiconductor substrate 2 and the wafer 3, it will adversely affect the electronic device. Therefore, generally, the Si wafer is monolithically assembled for each electronic device after sealing each device with resin.

[0020] However, when sealing electronic devices with resin, there are problems such as electrode contamination caused by the resin, increased working time caused by injecting resin into each electronic device, and increased amount of resin that is discarded due to exceeding its service life caused by the increased working time.

[0021] Therefore, there is a technique that uses bumps to connect the bonding pads 21 and 31 on the opposing main surfaces of the semiconductor substrate 2 and the wafer 3 to each other, and uses the same connection method as the connection between the bonding pads 21 and 31 to seal the area where the bonding pads 21 and 31 and the bumps are provided.

[0022] Furthermore, in general flip-chip mounting, the chip 3 is mounted on the semiconductor substrate 2 by heating one side of a block of metal bumps such as Au (gold), Cu (copper) and solder that are pressed onto the opposite main surface of the semiconductor substrate 2 or the chip 3.

[0023] However, when the thermal expansion coefficients of the semiconductor substrate 2 and the wafer 3 differ by, for example, 0.1 ppm / ℃ or more, if bulk Au, Cu, and solder are used as bump materials, the following problems will occur.

[0024] For example, when using block Au as the material for the bump, in order to stably connect the semiconductor substrate 2 and the wafer 3 with different thermal expansion coefficients by means of the bump, it is necessary to heat to a high temperature of 300°C or higher and apply a high pressure of 100 MPa or higher between the semiconductor substrate 2 and the wafer 3.

[0025] Furthermore, when using bulk Cu as the bulk material, it is necessary to heat it to 380°C or higher. Thus, when using bulk Au or Cu as the bulk material, it is necessary to connect the bumps under high temperature and high pressure. Sometimes this high temperature and high pressure can damage the wafer 3, and sometimes it can reduce the reliability of the electronic device.

[0026] On the other hand, when solder is used as the material for bumps, although it allows for low-temperature and low-pressure bump connections compared to Au or Cu, the heat resistance and connection strength of solder are inferior to Au or Cu. Therefore, when electronic components such as semiconductor lasers mounted on the chip 3 cause thermal expansion of the chip 3 due to heat generation, solder bumps may cause open-circuit faults due to the difference in thermal expansion rates between the semiconductor substrate 2 and the chip 3, thereby reducing the reliability of the electronic device.

[0027] Furthermore, as described above, the semiconductor substrate 2 disclosed herein is a Si substrate with a thermal expansion coefficient of 5.7 ppm / ℃. On the other hand, the substrate of the wafer 3 disclosed herein is GaAs with a thermal expansion coefficient of 2.6 ppm / ℃.

[0028] Thus, the difference in thermal expansion coefficients between the semiconductor substrate 2 and the wafer 3 of the electronic device 1 is much greater than 0.1 ppm / ℃. Therefore, when the bump material of the electronic device 1 is block Au, Cu, or solder, the above-mentioned problems may occur, and the reliability may be reduced.

[0029] Furthermore, when the periphery of the area between the semiconductor substrate 2 and the wafer 3 that must be sealed is joined and sealed by surrounding a block of metal with a surface plated, if the thermal expansion rates of the semiconductor substrate 2 and the wafer 3 differ by, for example, 0.1 ppm / ℃ or more, cracks will occur in the sealed portion. As a result, the hermeticity of the electronic device is reduced.

[0030] Furthermore, if the semiconductor substrate 2 or the wafer 3 has uneven thickness or warping, then when stacking the semiconductor substrate 2 and the wafer 3, in the sealed portion, only the protruding surface of the plated film can be bonded to the semiconductor substrate 2 and the wafer 3.

[0031] As a result, the airtightness of the electronic device is reduced due to the gaps distributed in the sealing part. Furthermore, if the semiconductor substrate 2 and the wafer 3 are joined by increasing the temperature and pressure to prevent the generation of gaps in the sealing part, there is a risk that the adjacent tiny bumps in the electronic device may cause short circuit faults.

[0032] Therefore, the bump 4 of the electronic device 1 includes, for example, a porous metal layer 41 of Au. The porous metal layer 41 contains Au particles with a particle size of 0.005 μm to 1.0 μm and a purity of 99.9% by weight or more. Alternatively, the composition of the porous metal layer 41 may also be, for example, Cu, Ag (silver), or Pt (platinum) with a purity of 99.9% by weight or more.

[0033] The porous metal layer 41, containing metal particles with a particle size of 0.005 μm to 1.0 μm, can bond metals at temperatures below the melting point of bulk metals due to the size effect of the particle size. For example, the porous metal layer 41 can bond the semiconductor substrate 2 and the wafer 3 at temperatures of around 100°C when the composition is Au, around 250°C when the composition is Ag, and around 150°C when the composition is Cu. This reduces heat-induced damage to the wafer 3 in the electronic device 1, thereby improving reliability.

[0034] Furthermore, since the porous metal layer 41 is elastic, even if the wafer 3 expands at a different rate of thermal expansion than the semiconductor substrate 2 due to the heating of the semiconductor laser, it will still change elastically, thus suppressing the generation of open faults. In this way, the reliability of the electronic device 1 can be improved, for example, compared with the case of using solder bumps.

[0035] The electronic device 1 is manufactured by depositing the chip 3 onto a semiconductor substrate 2 on which bumps 4 are provided on the upper surface, so that the porous metal layer 41 of the bumps 4 is not melted and connected to the bonding pad 31, and the chip 3 is flip-chip mounted on the semiconductor substrate 2.

[0036] Furthermore, the electronic device 1 can also be manufactured by depositing a wafer 3 with bumps 4 including a porous metal layer 41 on its lower surface onto a semiconductor substrate 2, without melting the porous metal layer 41 of the bumps 4 and connecting the bonding pads 21, and then flip-mounting the wafer 3 onto the semiconductor substrate 2. Alternatively, the bumps 4 including the porous metal layer 41 can also be provided on both the semiconductor substrate 2 and the wafer 3 before the deposition.

[0037] When the bump 4 is disposed on the semiconductor substrate 2 side, a metal film 42 is provided between the porous metal layer 41 and the bonding pad 21 on the semiconductor substrate 2 side. Furthermore, when the bump 4 is disposed on the wafer 3 side, a metal film 42 is provided between the porous metal layer 41 and the bonding pad 31 on the wafer 3 side. Alternatively, the metal film 42 may also be disposed between the porous metal layer 41 and the bonding pad 21 on the semiconductor substrate 2 side, and between the porous metal layer 41 and the bonding pad 31 on the wafer 3 side, at least one of these two scenarios.

[0038] In this disclosure, by ensuring that the thickness ratio of the metal film 42 to the thickness in the direction orthogonal to the main surface of the semiconductor substrate 2 in the bump 4 is less than 10%, a fine pitch of 20 μm or less between the bumps 4 can be achieved. This fine pitch will be described later in comparison with the steps of forming the bumps 4.

[0039] Furthermore, the bump 4 also has a metal film 42 on the side surface (peripheral surface) of the porous metal layer 41. The material of the metal film 42 is expected to be the same as that of the porous metal layer 41. For example, when the material of the porous metal layer 41 is Au, it is expected that the metal film 42 is an Au film.

[0040] In this way, because the side of the porous metal layer 41 is coated with a metal film 42, the particles of the porous metal layer 41 can be prevented from collapsing and scattering. Therefore, the bump 4 can prevent adjacent bumps 4 from short-circuiting due to the scattering of particles of the porous metal layer 41.

[0041] Furthermore, when no metal film 42 is provided on the side of the porous metal layer 41, surface roughness is generated on the side of the porous metal layer 41, which has a softer surface, and unevenness in shape is generated between the bumps 4.

[0042] In contrast, since a metal film 42 harder than the porous metal layer 41 is provided on the side of the bump 4, the unevenness of the shape between the bumps 4 is suppressed, and all of them become uniform in shape. Moreover, since the side of the bump 4 is coated with a harder metal film 42, it can be further miniaturized and the spacing can be further refined.

[0043] Furthermore, when the bump 4 is used for flip-chip mounting of the wafer 3 relative to the semiconductor substrate 2, although it slightly damages the wafer in the thickness direction, it prevents the particles of the porous metal layer 41 from leaking to the outside of the metal film 42. As a result, the bump 4 can reduce the connection resistance because the particle density of the porous metal layer 41 inside the metal film 42 is increased.

[0044] Furthermore, the sidewall portion 5 of the electronic device 1 has the same structure as the bump 4. Specifically, the sidewall portion 5 includes a porous metal layer 51 of Au. The porous metal layer 51 includes Au particles with a particle size of 0.005 μm to 1.0 μm and a purity of 99.9% by weight or more. Alternatively, the composition of the porous metal layer 51 may also be, for example, Cu, Ag (silver), or Pt (platinum) with a purity of 99.9% by weight or more.

[0045] The porous metal layer 51, through the particle size effect described above, can bond metals at a temperature below the melting point of bulk metals. This reduces damage to the wafer 3 caused by heat during the formation of the porous metal layer 51, thereby improving the reliability of the electronic device 1.

[0046] Furthermore, since the porous metal layer 51 is elastic, even if the wafer 3 expands at a different rate of thermal expansion than the semiconductor substrate 2 due to the heating of the semiconductor laser, it will still change elastically, thus suppressing cracking in the sidewall portion 5. In this way, the electronic device 1 can improve the airtightness of the area where the connecting pads 21, 31 and bumps 4 are installed, which must be sealed.

[0047] Furthermore, due to the elastic change of the porous metal layer 51, even if there is uneven thickness or warping in the semiconductor substrate 2 or the wafer 3, when bonding the semiconductor substrate 2 and the wafer 3, it follows the surface shape change of the semiconductor substrate 2 or the wafer 3.

[0048] In this way, since the electronic device 1 can suppress the generation of gaps at the connection between the sidewall portion 5 and the semiconductor substrate 2, and at the connection between the sidewall portion 5 and the wafer 3, the airtightness can be improved.

[0049] Furthermore, as shown in FIG2, the sidewall portion 5 is arranged in a ring to surround the area where the connecting pads 21, 31 and bump 4 are provided and must be sealed. In this way, when the electronic device 1 experiences thermal expansion of the semiconductor substrate 2 or the wafer 3, the mechanical stress applied to the bump 4 provided at the corner can be mitigated.

[0050] Specifically, when the semiconductor substrate 2 or the wafer 3 undergoes thermal expansion, the amount of expansion and contraction due to temperature changes increases from the center of the main surface of the semiconductor substrate 2 or the wafer 3 towards the periphery. Therefore, if there is no sidewall portion 5, mechanical stress is applied to the protrusion 4 provided at the corner.

[0051] In contrast, since the periphery of the semiconductor substrate 2 and the wafer 3 is sealed by the sidewall portion 5, the expansion and contraction of the periphery of the semiconductor substrate 2 and the wafer 3 caused by temperature changes can be suppressed by the sidewall portion 5. In this way, the electronic device 1 can alleviate the mechanical stress applied to the bump 4 provided at the corner.

[0052] When the sidewall portion 5 is disposed on the semiconductor substrate 2 side, a metal film 52 is provided between the porous metal layer 51 and the bonding pads 21 on the main surface of the semiconductor substrate 2. Furthermore, when the sidewall portion 5 is disposed on the wafer 3 side, a metal film 52 is provided between the porous metal layer 51 and the bonding pads on the main surface of the wafer 3. Alternatively, the metal film 52 may also be disposed between the porous metal layer 51 and the bonding pads 21 on the main surface of the semiconductor substrate 2, and between the porous metal layer 51 and the bonding pads on the main surface of the wafer 3, at least one of the following:

[0053] In this disclosure, by ensuring that the thickness ratio of the metal film 52 relative to the thickness of the sidewall portion 5 in the direction orthogonal to the main surface of the semiconductor substrate 2 is less than 10%, a fine pitch of less than 20 μm can be achieved in the step of simultaneously forming the sidewall portion 5 and the bumps 4.

[0054] Furthermore, the sidewall portion 5 also has a metal film 52 on the side surface (peripheral surface) of the porous metal layer 51. The material of the metal film 52 is expected to be the same as that of the porous metal layer 51. For example, if the material of the porous metal layer 51 is Au, it is expected that the metal film 52 is an Au film.

[0055] In this way, since the sidewall portion 5 is coated with a metal film 52, the particles of the porous metal layer 51 can be prevented from collapsing and scattering. Therefore, the sidewall portion 5 can prevent adjacent bumps 4 from short-circuiting due to the scattering of particles of the porous metal layer 51.

[0056] Furthermore, when the metal film 52 is not provided on the side of the porous metal layer 51, the surface roughness is generated on the side of the porous metal layer 51, which has a softer surface, and the side shape of the side wall portion 5 is uneven.

[0057] In contrast, since a metal film 52 harder than the porous metal layer 51 is provided on the sidewall portion 5, unevenness in the sidewall shape is suppressed, and the sidewall portion becomes a uniform surface shape. Furthermore, since the sidewall portion 5 is coated with a harder metal film 52, it can be further miniaturized.

[0058] The electronic device 1 is manufactured by stacking a chip 3 without bumps 4a (see Figure 10) on a semiconductor substrate 2 with bumps 4 on its upper surface, so that the porous metal layer 41 of the bumps 4 is not melted and connected to the bonding pad 31, and the chip 3 is flip-chip mounted on the semiconductor substrate 2.

[0059] Furthermore, the electronic device 1 can also be manufactured by depositing a chip 3 with bumps 4a containing a porous metal layer 41 on its lower surface (see Figure 10) onto a semiconductor substrate 2 without bumps 4, so that the porous metal layer 41 of the bumps 4a is not molten and connected to the bonding pads 21, thereby flip-chip mounting the chip 3 onto the semiconductor substrate 2. Alternatively, the bumps 4 and 4a containing the porous metal layer 41 can also be provided on both the semiconductor substrate 2 and the chip 3 before the deposition.

[0060] [2. Formation Steps of Bumps and Sidewalls] Next, the formation steps of bumps and sidewalls disclosed herein will be described with reference to FIGS. 3 to 10. FIGS. 3 to 6 are explanatory diagrams showing the steps of forming bumps and sidewalls on a semiconductor substrate disclosed herein. FIGS. 7 to 10 are explanatory diagrams showing the steps of forming bumps and sidewalls on a wafer disclosed herein.

[0061] As shown in FIG3, when forming bumps 4 and sidewall portions 5 on the semiconductor substrate 2, firstly, a metal film 22 is formed on the upper surface of the bonding pads 21 disposed at the positions where bumps 4 will be subsequently formed on the semiconductor substrate 2. At the same time, a metal film 32 is also formed on the upper surface of the bonding pads 21 disposed at the positions where sidewall portions 5 will be subsequently formed, that is, on the upper surface of the bonding pads 21 disposed in the main surface of the semiconductor substrate 2 at the positions where they annularly surround the area where bumps 4 will be subsequently formed. As the material of the metal film 22, a metal with the same composition as the subsequently deposited metal film 64 (see FIG4) is selected. In this case, an Au metal film 22 is formed.

[0062] Subsequently, a photoresist layer 61 is formed on the surface of the semiconductor substrate 2 on the side where the bonding pad 21 and the metal film 22 are disposed. Then, using photolithography, a through-hole 62 is formed at the location where the bump 4 is formed in the photoresist layer 61, exposing the surface of the metal film 22. Simultaneously, a trench 63 is formed at the location where the sidewall portion 5 is formed, exposing the surface of the metal film 22.

[0063] At this time, the through holes 62 are formed with a center-to-center spacing of 20 μm (20 μm pitch). The through holes 62 are filled with paste 50 containing metal particles that serve as the porous metal layer 41 in subsequent steps. However, since the structure is a fine structure with a 20 μm pitch, if the paste 50 is filled directly in this state, there is a risk that the fine structure will be damaged and collapse.

[0064] Therefore, as shown in FIG4, a metal film 64 is formed, for example, by sputtering, on the upper surface of the photoresist layer 61, the side surface of the through-hole 62, the side surface of the trench 63, and the upper surface of the metal film 22. The metal film 64 is made of a metal with the same composition as the metal particles contained in the paste 50 subsequently filled into the through-hole 62. Here, an Au metal film 64 is formed.

[0065] In this way, since the photoresist layer 61 is hardened by coating the surface with a metal film 64, when the paste 50 containing metal particles is filled into the through hole 62, the fine structure can be prevented from collapsing.

[0066] Furthermore, if the thickness of the metal film 64 formed here is too thick, the opening of the through hole 62 will become narrow, making it difficult to fill the through hole 62 with the paste 50 containing metal particles. Therefore, here, a thinner metal film 64 (e.g., less than 1 μm thick) is formed, where the thickness of the metal film 64 relative to the depth D1 of the through hole 62, in other words, the thickness d1 of the direction orthogonal to the main surface of the semiconductor substrate 2 in the subsequently formed bump 4 is less than 10%.

[0067] For example, when forming bumps 4 with a height of 10 μm arranged at 20 μm intervals, the thickness of the metal film 64 is set to 0.2 μm. In this way, even when the metal film 64 is formed, the opening of the through hole 62 can be prevented from narrowing, so that the paste 50 containing metal particles can be fully filled into the through hole 62 in a subsequent step.

[0068] As a result, the metal film 64 is less than 10% of the thickness d1 of the thickness of the sidewall portion 5 in the direction orthogonal to the main surface of the semiconductor substrate 2 relative to the depth D2 of the trench 63, in other words, the thickness of the sidewall portion 5 formed subsequently is less than 10% relative to the depth D2 of the trench 63.

[0069] Next, as shown in FIG5, the through holes 62 and trenches 63 formed in the photoresist layer 61 are filled, for example, with a paste 50 containing Au particles with a purity of 99.9% by weight or more and a particle size of 0.005 μm to 1.0 μm. As a method for filling the through holes 62 and trenches 63 with paste 50, any method can be used, such as screen printing or spreading the dripped paste 50 with a squeegee.

[0070] Subsequently, after the paste 50 is dried and sintered, the photoresist layer 61 is peeled off by using a stripping solution or the like. Thereby, as shown in FIG6, an Au metal film 22, an Au metal film 42, and a porous metal layer 41 containing Au particles with a particle size of 0.005 μm to 1.0 μm are sequentially deposited on the surface of the bonding pad 21, and bumps 4 of the Au metal film 42 are also formed on the side of the porous metal layer 41.

[0071] At the same time, in a manner that surrounds the area forming the bump 4, a metal film 22 of Au, a metal film 52 of Au, and a porous metal layer 51 containing Au particles with a particle size of 0.005 μm to 1.0 μm are sequentially deposited, and a sidewall portion 5 of the metal film 52 of Au is also formed on the side of the porous metal layer 51.

[0072] Thus, the bump 4 has a metal film 42 between the metal film 22 on the connecting pad 21 and the porous metal layer 41, the thickness of which is less than 10% of the height D1 of the bump 4. Furthermore, a metal film 42 is also provided on the side of the porous metal layer 41 of the bump 4.

[0073] Furthermore, the sidewall portion 5 has a metal film 52 between the metal film 22 on the connecting pad 21 and the porous metal layer 51, the thickness of which is less than 10% of the height D2 of the sidewall portion 5. Moreover, the sidewall portion 5 also has a metal film 52 on the side of the porous metal layer 51.

[0074] The metal films 42 and 52 are formed on the upper surface of the photoresist layer 61, the sides of the through holes 62 and trenches 63 formed in the photoresist layer 61, and the surface of the metal film 22 to prevent the collapse of the fine structure of the bumps 4 and sidewall portions 5 patterned on the photoresist layer 61. In this way, the bumps 4 can be made to have a fine pitch of less than 20 μm.

[0075] Furthermore, since the metal film 22 is formed on the surface of the bonding pad 21 by sputtering, even if the bonding pad 21 is a metal with a different composition from the metal film 22, it is firmly bonded to the bonding pad 21.

[0076] Furthermore, the metal films 42 and 52 may also be formed of metals with different compositions than the porous metal layers 41 and 51. However, when formed of Au with the same composition, the porous metal layers 41 and 51 bond with the metal films 42 and 52 with a stronger adhesion than when they are disposed on other metal films with different compositions. In addition, when the porous metal layers 41 and 51 are composed of a component other than Au (e.g., Cu, Ag (silver), or Pt (platinum)), the metal films 42 and 52 may also use the same metals as the porous metal layers 41 and 51 (e.g., Cu, Ag (silver), or Pt (platinum)).

[0077] Next, the steps for forming the bump 4a and sidewall portion 5a shown in FIG10 on the wafer 3 will be described. As shown in FIG7, when forming the bump 4a and sidewall portion 5a on the wafer 3, firstly, a metal film 32 is formed on the upper surface of the bonding pad 31 located on the wafer 3 at the position where the bump 4a will be formed subsequently. At the same time, a metal film 32 is also formed on the upper surface of the bonding pad 31 located at the position where the sidewall portion 5a will be formed subsequently, that is, on the upper surface of the bonding pad 31 located in the main surface of the wafer 3 at the position where the area surrounding the bump 4a will be formed subsequently. As the material of the metal film 32, a metal with the same composition as the subsequently deposited metal film 74 (see FIG8) is selected. In this case, an Au metal film 32 is formed. In addition, the bonding pad 31 located at the position where the sidewall portion 5a will be formed subsequently is not connected to the circuit inside the wafer 3.

[0078] Subsequently, a photoresist layer 71 is formed on the surface of the wafer 3 on the side where the bonding pad 31 and the metal film 32 are disposed. Then, using photolithography, a through-hole 72 is formed at the location of the bump 4a in the photoresist layer 71, exposing the surface of the metal film 32. Simultaneously, a trench 73 is formed at the location of the sidewall portion 5a, exposing the surface of the metal film 32.

[0079] Subsequently, as shown in FIG8, a metal film 74 is formed, for example by sputtering, on the upper surface of the photoresist layer 71, the side surface of the through hole 72, the side surface of the trench 73, and the upper surface of the metal film 32. As the material of the metal film 74, Au with the same composition as the Au particles contained in the paste 50 subsequently filled into the through hole 72 is selected.

[0080] In this way, since the photoresist layer 71 is hardened by coating the surface with a metal film 43, when the paste 50 containing Au particles is filled into the through hole 72, the fine structure can be prevented from collapsing.

[0081] Furthermore, here, a metal film 74 is also formed with a depth D1 relative to the through hole 72. In other words, the thickness d1 of the subsequently formed bump 4a in the direction orthogonal to the main surface of the wafer 3 (the height D1 of the bump 4a) is less than 10% of the thickness of the film 74 (for example, less than 1 μm).

[0082] For example, when forming bumps 4 with a height of 10 μm arranged at 20 μm intervals, the thickness of the metal film 74 is set to 0.2 μm. In this way, even if the metal film 74 is formed, the opening of the through hole 72 can be prevented from narrowing, so the paste 50 containing metal particles can be fully filled into the through hole 72 in a subsequent step.

[0083] As a result, the metal film 74 is less than 10% of the thickness d1 of the direction orthogonal to the main surface of the wafer 3 in the sidewall portion 5a formed subsequently, relative to the depth D2 of the trench 73, in other words, the thickness d1 of the sidewall portion 5a is less than 10%.

[0084] Next, as shown in FIG9, the through holes 72 and trenches 73 formed in the photoresist layer 71 are filled, for example, with paste 50 containing Au particles with a purity of 99.9% by weight or more and a particle size of 0.005 μm to 1.0 μm.

[0085] Subsequently, after the paste 50 is dried and sintered, the photoresist layer 71 is peeled off by using a stripping solution or the like. Thereby, as shown in FIG10, an Au metal film 32, an Au metal film 42, and a porous metal layer 41 containing Au particles with a particle size of 0.005 μm to 1.0 μm are sequentially deposited on the surface of the bonding pad 31, and bumps 4a of the Au metal film 42 are also formed on the side of the porous metal layer 41.

[0086] At the same time, in a manner that surrounds the area forming the protrusion 4a, a metal film 32 of Au, a metal film 52 of Au, and a porous metal layer 51 containing Au particles with a particle size of 0.005 μm to 1.0 μm are sequentially deposited, and a sidewall portion 5a of the metal film 52 of Au is also formed on the side of the porous metal layer 51.

[0087] Thus, the bump 4a has a metal film 42 between the metal film 22 on the connecting pad 31 and the porous metal layer 41, the thickness of which is less than 10% of the height D1 of the bump 4a. Furthermore, a metal film 42 is also provided on the side of the porous metal layer 41 of the bump 4a.

[0088] Furthermore, the sidewall portion 5a has a metal film 52 between the metal film 32 on the connecting pad 31 and the porous metal layer 51, the thickness of which is less than 10% of the height D2 of the sidewall portion 5a. Moreover, the sidewall portion 5a also has a metal film 52 on the side of the porous metal layer 51.

[0089] The metal films 42 and 52 are formed on the upper surface of the photoresist layer 71, the sides of the through holes 72 and trenches 73 formed in the photoresist layer 71, and the surface of the metal film 22 to prevent the collapse of the fine structure of the bumps 4a and sidewall portions 5a patterned on the photoresist layer 71. In this way, the bumps 4a, like the bumps 4 on the semiconductor substrate 2, can be finely pitched with a spacing of less than 20 μm.

[0090] In the above embodiment, although the case in which a chip 3 without bumps 4a and sidewall portion 5a is mounted on a semiconductor substrate 2 with bumps 4 and sidewall portion 5 and the case in which a chip 3 with bumps 4a and sidewall portion 5a is mounted on a semiconductor substrate 2 without bumps 4 and sidewall portion 5 have been described, this is only one example.

[0091] The electronic device disclosed herein can also be configured such that a wafer 3 having bumps 4a and sidewalls 5a is mounted on a semiconductor substrate 2 having bumps 4a and sidewalls 5a. In this configuration, the thickness ratio of the metal films 42 and 52 relative to half the thickness of the bumps 4, 4a and sidewalls 5, 5a in the direction orthogonal to the main surface of the semiconductor substrate 2 and the wafer 3 is set to less than 10%, preferably less than 5%.

[0092] Furthermore, in the above embodiment, although the case where the substrate of the wafer 3 is a substrate other than Si is described, if the substrate of the wafer 3 has a different coefficient of thermal expansion than the semiconductor substrate 2, it may also be Si doped with impurities.

[0093] The chip 3, which has the light-emitting part of the semiconductor laser described above, and the semiconductor substrate 2, which has the driving circuit of the semiconductor laser, are mounted, for example, in a ranging device such as a ToF (Time of Flight) sensor or a structure lamp. When the light-emitting part of the semiconductor laser is mounted in a ranging device, it functions, for example, as a light source for a ToF sensor or a light source for a structure lamp.

[0094] [3. Effect] The electronic device 1 has a semiconductor substrate 2, a wafer 3, bumps 4, and a sidewall portion 5. The bumps 4 connect a plurality of bonding pads 21, 31 disposed on opposite main surfaces of the semiconductor substrate 2 and the wafer 3 to each other. The sidewall portion 5 includes a porous metal layer 51 that annularly surrounds the area where the plurality of bumps 4 are disposed, connecting the semiconductor substrate 2 and the wafer 3. Thereby, the electronic device 1 can improve its hermeticity.

[0095] The thermal expansion rate of the wafer 3 differs from that of the semiconductor substrate 2 by more than 0.1 ppm / ℃. Therefore, even if the wafer 3 heats up and expands at a different thermal expansion rate than the semiconductor substrate 2, the porous metal layer 51 of the sidewall portion 5 can elastically change, thus suppressing the formation of cracks or gaps in the sidewall portion 5. Furthermore, since the sidewall portion 5 elastically changes shape following the wafer 3 or semiconductor substrate 2 even if there are thickness inconsistencies or warping in the wafer 3 or semiconductor substrate 2, its hermeticity can be improved.

[0096] The chip 3 is a semiconductor laser. The semiconductor substrate 2 has a driving circuit for driving the semiconductor laser. In this way, even if the electronic device 1 expands the chip 3 with a different thermal expansion rate than the semiconductor substrate 2 due to the heat generated by the light emitted by the semiconductor laser, the porous metal layer 51 of the sidewall portion 5 will also change elastically, thereby improving the airtightness.

[0097] The porous metal layer 51 contains metal particles with a particle size of 0.005 μm to 1.0 μm. Due to the size effect of the metal particles, the porous metal layer 51 can bond metals at temperatures below the melting point of bulk metals. Therefore, in the peripheral area of ​​the region where the bonding pads 21, 31 and bumps 4 are provided, the electronic device 1 connects the semiconductor substrate 2 and the wafer 3 using the porous metal layer 51, which allows for lower-temperature metal bonding, thereby reducing heat-induced damage and improving hermeticity.

[0098] The sidewall portion 5 has at least one of the following: between the porous metal layer 51 and the bonding pad 21 disposed on the semiconductor substrate 2, and between the porous metal layer 51 and the bonding pad 31 disposed on the wafer 3, and a metal film 52 on the side of the porous metal layer 51. In this way, the electronic device 1 can improve its airtightness by preventing the porous metal layer 51 from collapsing due to the metal film 52 disposed on the side of the porous metal layer 51.

[0099] The thickness ratio of the metal film 52 disposed between the porous metal layer 51 and the bonding pad 21 disposed on the semiconductor substrate 2, and between the porous metal layer 51 and the bonding pad 31 disposed on the wafer 3, relative to the thickness of the sidewall portions 5, 5a in the direction orthogonal to the main surface, is less than 10%. This prevents the trenches 63, 73 formed on the patterned sidewall portions 5, 5a of the photoresist layers 61, 71 from becoming narrowed due to the formation of the metal film 52. As a result, the trenches 63, 73 patterned on the photoresist layers 61, 71 can be appropriately filled with paste 50 containing metal particles that form the material of the sidewall portions 5, 5a.

[0100] The thickness ratio of the metal film 52 disposed between the porous metal layer 51 and the bonding pad 21 disposed on the semiconductor substrate 2, and between the porous metal layer 51 and the bonding pad 31 disposed on the wafer 3, relative to half the thickness of the sidewall portions 5, 5a in the direction orthogonal to the main surface, is less than 10%. Therefore, in the case of an electronic device where the semiconductor substrate 2 and the wafer 3 are connected by the sidewall portions 5, 5a, the trenches 63, 73 formed in the patterned sidewall portions 5, 5a of the photoresist layers 71, 71, are prevented from becoming narrowed due to the formation of the metal film 52. As a result, the trenches 63, 73 patterned in the photoresist layers 61, 71 can be appropriately filled with paste 50 containing metal particles that constitute the material of the sidewall portions 5, 5a.

[0101] Bumps 4 and 4a have a porous metal layer 41 and a metal film 42. The porous metal layer 41 is formed of the same material as the porous metal layer 51 of the sidewall portions 5 and 5a. The metal film 42 is disposed between the porous metal layer 41 and the bonding pad 21 disposed on the semiconductor substrate 2, and between the porous metal layer 41 and the bonding pad 31 disposed on the wafer 3, and on the side surface of the porous metal layer 41. In this way, since bumps 4 and 4a and sidewall portions 5 and 5a can be formed simultaneously, no additional steps are required for bonding and sealing. By forming sidewall portions 5 and 5a, the semiconductor substrate 2 and the wafer 3 can be bonded and sealed.

[0102] The thickness ratio of the metal film 42 disposed between the porous metal layer 41 and the connecting pads 21 and 23 relative to the thickness of the bumps 4 and 4a in the direction orthogonal to the main surface of the semiconductor substrate 2 is less than 10%. This prevents the through-holes 62 and 72 formed by the bumps 4 and 4a patterned in the photoresist layers 61 and 71 from becoming narrowed due to the formation of the metal film 42. As a result, the through-holes 62 and 72 patterned in the photoresist layers 61 and 71 can be appropriately filled with paste 50 containing metal particles that are the material of the bumps 4 and 4a.

[0103] The thickness of the metal film 42 disposed between the porous metal layer 41 and the connecting pads 21 and 23 is less than 10% of the thickness of the bumps 4 and 4a in the direction orthogonal to the main surface of the semiconductor substrate 2. Therefore, in the case of an electronic device where the semiconductor substrate 2 and the wafer 3 are connected by bumps 4 and 4a, the through-holes 62 and 72 formed by the bumps 4 and 4a patterned in the photoresist layers 61 and 71 are prevented from becoming narrowed due to the formation of the metal film 42. As a result, the through-holes 62 and 72 patterned in the photoresist layers 61 and 71 can be appropriately filled with paste 50 containing metal particles that are the material of the bumps 4 and 4a.

[0104] The porous metal layers 41 and 51 and the metal films 42 and 43 are made of the same type of metal. This improves the bonding strength between the porous metal layers 41 and 51 and the metal films 42 and 43.

[0105] The porous metal layers 41 and 51 are made of porous metals containing gold, silver, platinum or copper with a purity of 99.9% by weight or higher. This allows for a lower connection resistance between the bonding pads 21 of the semiconductor substrate 2 and the bonding pads 31 of the wafer 3.

[0106] In addition, the effects described in this instruction manual are for illustrative purposes only and are not limited, and may be other effects.

[0107] Alternatively, the present technology may also be configured as follows: (1) An electronic device comprising: a semiconductor substrate; a wafer; bumps that connect a plurality of bonding pads disposed on opposing main surfaces of the semiconductor substrate and the wafer to each other; and a sidewall portion comprising a porous metal layer that annularly surrounds the area of ​​the plurality of bumps, connecting the semiconductor substrate and the wafer. (2) The electronic device of (1) above, wherein the difference in thermal expansion coefficient between the wafer and the semiconductor substrate is 0.1 ppm / ℃ or more. (3) The electronic device of (1) or (2) above, wherein the wafer is a semiconductor laser; and the semiconductor substrate has a driving circuit for driving the semiconductor laser. (4) The electronic device of any one of (1) to (3) above, wherein the porous metal layer comprises metal particles with a particle size of 0.005 μm to 1.0 μm. (5) An electronic device as described in any one of (1) to (4) above, wherein the sidewall portion has: a metal film disposed between the porous metal layer and the bonding pad disposed on the semiconductor substrate, and between the porous metal layer and the bonding pad disposed on the wafer, and on the side of the porous metal layer. (6) An electronic device as described in (5) above, wherein the metal film disposed between the porous metal layer and the bonding pad disposed on the semiconductor substrate, and between the porous metal layer and the bonding pad disposed on the wafer, has a film thickness ratio of less than 10% relative to the thickness of the sidewall portion in a direction orthogonal to the main surface. (7) The electronic device of (5) above, wherein the metal film disposed between the porous metal layer and the bonding pad disposed on the semiconductor substrate, and between the porous metal layer and the bonding pad disposed on the wafer, has a thickness ratio of less than 10% relative to half the thickness of the sidewall portion in the direction orthogonal to the main surface. (8) The electronic device of any one of (1) to (7) above, wherein the bump has: a porous metal layer formed of the same material as the porous metal layer of the sidewall portion; and a metal film disposed between the porous metal layer and the bonding pad disposed on the semiconductor substrate, and between the porous metal layer and the bonding pad disposed on the wafer, and on the side surface of the porous metal layer. (9) In the electronic device of (8) above, the thickness ratio of the metal film disposed between the porous metal layer and the connecting pad to the thickness of the bump in the direction orthogonal to the main surface is less than 10%. (10) In the electronic device of (8) above, the thickness ratio of the metal film disposed between the porous metal layer and the connecting pad to half the thickness of the bump in the direction orthogonal to the main surface is less than 10%.(11) The electronic device of any one of (5) to (10) above, wherein the materials of the porous metal layer and the metal film are of the same kind. (12) The electronic device of any one of (1) to (11) above, wherein the material of the porous metal layer is a porous metal containing gold, silver, platinum or copper with a purity of 99.9% by weight or more. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a cross-sectional diagram illustrating the electronic device according to an embodiment of the present disclosure. Figure 2 is a cross-sectional diagram along line A-A shown in Figure 1. Figure 3 is an explanatory diagram showing the steps of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure. Figure 4 is an explanatory diagram showing the steps of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure. Figure 5 is an explanatory diagram showing the steps of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure. Figure 6 is an explanatory diagram showing the steps of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure. Figure 7 is an explanatory diagram showing the steps of forming bumps and sidewalls on a wafer according to the present disclosure. Figure 8 is an explanatory diagram showing the steps of forming bumps and sidewalls on a wafer according to the present disclosure. Figure 9 is an explanatory diagram showing the steps of forming bumps and sidewalls on a wafer according to the present disclosure. Figure 10 is an explanatory diagram showing the steps of forming bumps and sidewalls on a wafer according to the present disclosure.

Claims

1. An electronic device comprising: a semiconductor substrate; a wafer; bumps that connect a plurality of bonding pads disposed on opposing main surfaces of the semiconductor substrate and the wafer to each other; and a sidewall portion comprising a porous metal layer that annularly surrounds the area where the plurality of bumps are disposed, connecting the semiconductor substrate and the wafer.

2. The electronic device of claim 1, wherein the thermal expansion coefficients of the aforementioned wafer and the aforementioned semiconductor substrate differ by more than 0.1 ppm / ℃.

3. The electronic device of claim 1, wherein the chip is a semiconductor laser; and the semiconductor substrate has a driving circuit for driving the semiconductor laser.

4. The electronic device of claim 1, wherein the porous metal layer comprises metal particles with a particle size of 0.005 μm to 1.0 μm.

5. The electronic device of claim 1, wherein the sidewall portion has: a metal film disposed between the porous metal layer and the bonding pad disposed on the semiconductor substrate, and between the porous metal layer and the bonding pad disposed on the wafer, and on the side of the porous metal layer.

6. The electronic device of claim 5, wherein the metal film disposed between the porous metal layer and the bonding pad disposed on the semiconductor substrate, and between the porous metal layer and the bonding pad disposed on the wafer, has a film thickness ratio of less than 10% relative to the thickness of the sidewall portion in a direction orthogonal to the main surface.

7. The electronic device of claim 5, wherein the metal film disposed between the porous metal layer and the bonding pad disposed on the semiconductor substrate, and between the porous metal layer and the bonding pad disposed on the wafer, has a film thickness ratio of less than 10% relative to half the thickness of the sidewall portion in the direction orthogonal to the main surface.

8. The electronic device of claim 1, wherein the bump has: a porous metal layer formed of the same material as the porous metal layer of the sidewall portion; and a metal film disposed between the porous metal layer and a bonding pad disposed on the semiconductor substrate, and between the porous metal layer and a bonding pad disposed on the wafer, and on the side surface of the porous metal layer.

9. The electronic device of claim 8, wherein the thickness ratio of the metal film disposed between the porous metal layer and the connecting pad to the thickness of the bump in the direction orthogonal to the main surface is less than 10%.

10. The electronic device of claim 8, wherein the thickness ratio of the metal film disposed between the porous metal layer and the connecting pad to half the thickness of the bump in the direction orthogonal to the main surface is less than 10%.

11. The electronic device of claim 5, wherein the materials of the porous metal layer and the metal film are of the same kind of metal.

12. The electronic device of claim 1, wherein the material of the aforementioned porous metal layer is a porous metal comprising gold, silver, platinum or copper with a purity of 99.9% by weight or more.

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