Package structure and manufacturing method thereof

Abstract

A packaging structure includes a carrier board, a die, and a first rewiring structure. The carrier board has a first surface and a second surface opposite to the first surface. The carrier board includes an insulating body and carrier through-holes (TCVs) embedded in the insulating body. The die is disposed on the first surface of the carrier board. The die has an active surface and a rear surface opposite to the active surface. The die has conductive pillars formed on the active surface. The active surface faces away from the insulating body. The die is electrically connected to the TCVs. The first rewiring structure is disposed on the second surface of the carrier board.

Description

[Technical Field]

[0001] The present invention relates to a packaging structure and a method for manufacturing the same, and more particularly to a packaging structure having a carrier plate through-hole and a method for manufacturing the same. [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integrated density stems from the repeated reduction in the minimum feature size, allowing more components to be integrated into a given area. Recently, there has been a growing demand for miniaturization, higher speeds, greater bandwidth, and stronger heat dissipation capabilities. Consequently, the need for smaller and more innovative semiconductor die packaging technologies has increased. [Summary of the Invention]

[0003] A packaging structure includes a carrier board, a die, and a first rewiring structure. The carrier board has a first surface and a second surface opposite to the first surface. The carrier board includes an insulating body and carrier board through-holes embedded in the insulating body. The die is disposed on the first surface of the carrier board. The die is electrically connected to the carrier board through-holes. The first rewiring structure is disposed on the second surface of the carrier board.

Implementation Method

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] Other features and processes may also be included. For example, a test structure may be included to illustrate verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate to enable testing of the 3D package or 3DIC, use of probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0008] Figures 1A to 1E are schematic cross-sectional views illustrating the manufacturing process of a carrier plate C1 according to some embodiments of the present disclosure. Referring to Figure 1A, an insulating body 100 is provided on a sacrificial film SF. In some embodiments, the sacrificial film SF is made of an organic material. For example, the sacrificial film SF is made of polymeric materials such as acetal, acrylic acid, cellulose, acetate, polyethylene, polystyrene, ethylene, nylon, polyolefin, polyester, silicone, paraffin, or combinations thereof. In some embodiments, the insulating body 100 is made of a dielectric material. For example, the insulating body 100 is made of inorganic materials such as ceramics or glass. In some embodiments, the insulating body 100 is made of aluminum nitride (AlN), alumina (Al2O3), silicon nitride (Si3N4), silicon carbide (SiC), etc. In some embodiments, the insulating body 100 is free of filler. In some embodiments, the insulating body 100 is an electrical insulator. In other words, the insulating body 100 is not conductive. In some embodiments, the insulating body 100 is not thermally insulating. In other words, the insulating body 100 is thermally conductive. In some embodiments, the Young's modulus of the insulating body 100 is in the range of about 50 GPa to about 700 GPa. For example, when the insulating body 100 is made of AlN, Al2O3, Si3N4, SiC, or glass, the Young's modulus of the insulating body 100 is about 302 GPa to about 348 GPa, about 344 GPa to about 408 GPa, about 166 GPa to about 297 GPa, about 401 GPa to about 700 GPa, or about 50 GPa to about 90 GPa, respectively. In some embodiments, the hardness of the insulating body 100 is in the range of about 5 Moh's to about 10 Moh's. In some embodiments, the thermal expansion coefficient (CTE) of the insulating body 100 is in the range of about 2.6 ppm / °C to about 9.7 ppm / °C. In some embodiments, the thermal conductivity of the insulating body 100 is in the range of about 0.96 W / m·K to about 350 W / m·K. In some embodiments, the insulating body 100 has a thickness t100 in the range of about 50 μm to about 1000 μm. In some embodiments, the insulating body 100 has a first surface 100a and a second surface 100b opposite to the first surface 100a. As shown in FIG1A, the sacrificial film SF is bonded to the second surface 100b of the insulating body 100.

[0009] In some embodiments, the insulating body 100 has a plurality of openings OP formed therein. The openings OP can be formed by, for example, laser drilling, mechanical drilling, etching, etc. As shown in FIG1A, each opening OP extends from a first surface 100a of the insulating body 100 to a second surface 100b of the insulating body 100. That is, each opening OP penetrates through the insulating body 100. For example, the depth DOP of each opening OP is substantially equal to the thickness t100 of the insulating body 100. In some embodiments, the depth DOP of each opening OP is in the range of about 50 μm to about 1000 μm. In some embodiments, the opening OP partially exposes the sacrificial film SF. In some embodiments, each opening OP has sloping sidewalls SWOP. That is, the first diameter DAOP of each opening OP at the first surface 100a of the insulating body 100 is different from the second diameter DBOP of each opening OP at the second surface 100b. For example, as shown in FIG1A, the first diameter DAOP of each opening OP is larger than the second diameter DBOP of each opening OP. That is, each opening OP may be in the form of a conical frustum. However, this disclosure is not limited thereto. In some alternative embodiments, each opening OP may have substantially straight sidewalls SWOP. That is, the first diameter DAOP of each opening OP may be substantially equal to the second diameter DBOP of each opening OP, and each opening OP may be in the form of a cylinder. In some embodiments, the first diameter DAOP is in the range of about 20 μm to about 500 μm, and the second diameter DBOP is in the range of about 5 μm to about 500 μm. In some embodiments, two adjacent opening OPs are formed with a pitch p1 in the range of about 100 μm to about 1000 μm. It should be noted that throughout this disclosure, the pitch of two adjacent elements refers to the distance between the centers of the two adjacent elements.

[0010] Referring to FIG1B, a seed material layer 112a is conformally formed on the insulating body 100. In other words, the seed material layer 112a is formed on the insulating body 100 and within the opening OP. For example, the seed material layer 112a covers the first surface 100a of the insulating body 100 and extends into the opening OP to cover the sidewall SWOP of the opening OP. In some embodiments, the seed material layer 112a also covers the exposed portion of the sacrificial film SF. As shown in FIG1B, the seed material layer 112a is in solid contact with the insulating body 100. The seed material layer 112a can be formed by sputtering processes, physical vapor deposition (PVD) processes, etc. In some embodiments, the seed material layer 112a consists of two sublayers (not shown). The first sublayer may contain titanium, titanium nitride, tantalum, tantalum nitride, other suitable materials, or combinations thereof. On the other hand, the second sublayer may contain copper, copper alloys, or other suitable material selections.

[0011] Referring to FIG1C, a conductive material layer 114a is deposited on the seed material layer 112a. For example, the conductive material layer 114a is formed on the seed material layer 112a located on top of the first surface 100a of the insulating body 100 and on the seed material layer 112a located within the opening OP. In some embodiments, the conductive material layer 114a is formed by a plating process. The plating process is, for example, an electroplating process, an immersion plating process, etc. In some embodiments, the conductive material layer 114a is made of aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof.

[0012] Referring to Figures 1C and 1D, a portion of the seed material layer 112a and a portion of the conductive material layer 114a are removed to form the seed layer 112 and the conductive layer 114 respectively in each opening OP of the insulating body 100. In some embodiments, the portions of the seed material layer 112a and the conductive material layer 114a are removed until the first surface 100a of the insulating body 100 is exposed. For example, the portions of the seed material layer 112a and the conductive material layer 114a located above the first surface 100a of the insulating body 100 are removed to form the seed layer 112 and the conductive layer 114. In some embodiments, the portions of the seed material layer 112a and the conductive material layer 114 are removed by a planarization process, an etching process, etc. Planarization processes include, for example, chemical mechanical polishing (CMP) processes, mechanical grinding processes, etc. Etching processes include, for example, anisotropic etching processes (e.g., dry etching) or isotropic etching processes (e.g., wet etching). In some embodiments, the remaining seed layer 112 and the remaining conductive material layer 114a within the same opening OP are collectively referred to as a carrier via (TCV) 110. As shown in FIG1D, a plurality of TCVs 110 are embedded in the insulating body 100.

[0013] Referring to Figures 1D and 1E, the sacrificial film SF is removed to expose the second surface 100b of the insulating body 100, thereby obtaining the carrier plate C1. In some embodiments, the sacrificial film SF is removed by an etching process, a stripping process, etc. In some embodiments, the carrier plate C1 includes the insulating body 100 and a TCV 110. The TCV 110 is embedded in the insulating body 100. For example, the insulating body 100 laterally encapsulates the TCV 110. In some embodiments, since the TCV 110 is formed by filling the opening OP with a seed layer 112 and a conductive material layer 114, the geometry of the TCV 110 is substantially the same as that of the opening OP of the insulating body 100. For example, the height H110 of each TCV 110 is substantially the same as the depth DOP of each opening OP (shown in Figure 1A). As shown in Figure 1E, each TCV 110 penetrates through the insulating body 100. In other words, the height H110 of each TCV 110 is substantially equal to the thickness t100 of the insulating body 100. In some embodiments, the height H110 of each TCV 110 is in the range of about 50 μm to about 1000 μm. In some embodiments, each TCV 110 has a sloping sidewall SW110. That is, the first diameter DA110 of each TCV 110 is different from the second diameter DB110 of each TCV 110. For example, as shown in FIG1E, the first diameter DA110 of each TCV 110 is larger than the second diameter DB110 of each TCV 110. That is, each TCV 110 may be in the form of a frustum of a cone. However, this disclosure is not limited thereto. In some alternative embodiments, depending on the shape of the opening OP of the insulating body 100, the TCV 110 may have a substantially straight sidewall SW110. That is, the first diameter DA110 of each TCV 110 may be substantially equal to the second diameter DB110 of each TCV 110, and each TCV 110 may be cylindrical. In some embodiments, the first diameter DA110 is in the range of about 20 μm to about 500 μm, and the second diameter DB110 is in the range of about 5 μm to about 500 μm. In some embodiments, two adjacent TCVs 110 are formed to have a pitch p2 in the range of about 100 μm to about 1000 μm.

[0014] In some embodiments, each TCV 110 has a seed layer 112 and a conductive layer 114 surrounded by the seed layer 112. In some embodiments, the seed layer 112 is in physical contact with the insulating body 100. That is, each TCV 110 is in physical contact with the insulating body 100. As shown in FIG1E, the top surface T110 and bottom surface B110 of the TCV 110 are exposed by the insulating body 100. For example, the top surface T110 of the TCV 110 is substantially coplanar with the first surface 100a of the insulating body 100. Similarly, the bottom surface B110 of the TCV 110 is substantially coplanar with the second surface 100b of the insulating body 100. In some embodiments, the top surface T110 of the TCV 110 and the first surface 100a of the insulating body 100 are collectively referred to as the first surface S1 of the carrier C1. On the other hand, the bottom surface B110 of TCV 110 and the second surface 100b of insulating body 100 are collectively referred to as the second surface S2 of carrier plate C1. In some embodiments, the first surface S1 of carrier plate C1 is opposite to the second surface S2 of carrier plate C1.

[0015] As described above, the TCV 110 is formed by an electroplating process. Compared with TCVs formed by electroless plating processes or conductive paste filling processes, the TCV 110 formed by the electroplating process has higher conductivity, higher throughput, and higher quality (i.e., no voids within the TCV 110). This effectively reduces the total cost of manufacturing the substrate C1 while ensuring the quality of the substrate C1.

[0016] It should be noted that the process shown in Figures 1A to 1E is one method of manufacturing the carrier plate C1. Another method of manufacturing the carrier plate C1 will be described below with reference to Figures 2A to 2E.

[0017] Figures 2A to 2E are schematic cross-sectional views illustrating the manufacturing process of a carrier plate C1 according to some alternative embodiments of the present disclosure. Referring to Figure 2A, an insulating body 100 is provided. The insulating body 100 in Figure 2A is similar to the insulating body 100 in Figure 1A, and therefore will not be described again herein. However, as shown in Figure 2A, the openings OP do not penetrate the insulating body 100. For example, the depth DOP of each opening OP is less than the thickness t100 of the insulating body 100. Additionally, the sacrificial film in Figure 1A is omitted in Figure 2A. In other words, the second surface 100b of the insulating body 100 is exposed in Figure 2A.

[0018] Referring to Figures 2B to 2D, the steps shown in Figures 2B to 2D are similar to the steps shown in Figures 1B to 1D, so they will not be described again in this document.

[0019] Referring to Figures 2D and 2E, a portion of the insulating body 100 is removed to expose the bottom surface B110 of the TCV 110, thereby obtaining the carrier plate C1. For example, a planarization process or an etching process is performed on the insulating body 100 from the second surface 100b shown in Figure 2D until the bottom surface B110 of the TCV 110 is exposed. Planarization processes include, for example, CMP processes, mechanical polishing processes, etc. Etching processes include, for example, anisotropic etching processes (e.g., dry etching) or isotropic etching processes (e.g., wet etching). In some embodiments, the TCV 110 may be slightly planarized or etched from the bottom surface B110 of the TCV 110 to further reduce the total thickness of the carrier plate C1. It should be noted that although Figures 1A to 1E and Figures 2A to 2E show two different methods for manufacturing the carrier plate C1, the structure of the carrier plate C1 obtained by these two methods can be substantially the same.

[0020] In some embodiments, the carrier board C1 can be used in various applications. For example, the carrier board C1 can be incorporated into various package structures to serve as a support mechanism while simultaneously providing electrical paths. The applications of the carrier board C1 will be described below in conjunction with Figures 3A to 3G, 4A to 4G, and 5.

[0021] Figures 3A to 3G are schematic cross-sectional views illustrating the manufacturing process of a package structure 10 according to some embodiments of the present disclosure. Referring to Figure 3A, a carrier board C1 as shown in Figures 1E and 2E is provided. Subsequently, a plurality of wiring patterns 200 are formed on a first surface S1 of the insulating body 100. For example, the wiring patterns 200 are formed to physically contact the top surface T110 of the TCV 110 to provide an electrical connection with the TCV 110. In some embodiments, the wiring patterns 200 are formed by performing an etching process after a plating process. Plating processes include, for example, electroplating processes, electroless plating processes, immersion plating processes, etc. Etching processes include, for example, anisotropic etching processes (e.g., dry etching) or isotropic etching processes (e.g., wet etching). In some embodiments, the wiring patterns 200 comprise copper, nickel, titanium, combinations thereof, etc.

[0022] Referring to FIG3B, a plurality of through insulating vias (TIVs) 300 are formed on the wiring pattern 200. In some embodiments, the TIVs 300 are formed by the following steps. First, a seed material layer (not shown) is conformally formed on the wiring pattern 200 and the first surface S1 of the carrier C1. In some embodiments, the seed material layer comprises a titanium / copper composite layer and is formed by a sputtering process. Thereafter, a photoresist layer (not shown) with openings is formed on the seed material layer, and the openings of the photoresist layer expose the intended locations of the subsequently formed TIVs 300. Then, a plating process is performed to form a metal material layer (e.g., a copper layer) on the seed material layer exposed by the openings of the photoresist layer. The photoresist layer and the underlying seed material layer are then removed to form the TIVs 300.

[0023] As shown in FIG. 3B, a die 400 is disposed on a first surface S1 of a carrier plate C1. In some embodiments, the die 400 is disposed by a pick-and-place process, etc. In some embodiments, the die 400 is attached to the first surface S1 of the carrier plate C1 by an adhesive layer AD. For example, the adhesive layer AD is sandwiched between the die 400 and the first surface S1 of the carrier plate C1 to fix the die 400 in place. In some embodiments, the adhesive layer AD covers some of the wiring patterns 200 in the wiring pattern 200. In other words, some of the wiring patterns 200 are located directly under the die 400. In some embodiments, the adhesive layer AD includes a die attach film (DAF), etc. In some embodiments, each die 400 includes a semiconductor substrate 402 and a plurality of conductive pillars 404. In some embodiments, the semiconductor substrate 402 is made of silicon or germanium. However, this disclosure is not limited thereto. The semiconductor substrate 402 may also contain other suitable semiconductor materials, such as elements from Group III, Group IV, and / or Group V of the periodic table. As shown in FIG3B, conductive pillars 404 are disposed on the semiconductor substrate 402. For example, conductive pillars 404 protrude from the semiconductor substrate 402. Conductive pillars 404 may be copper pillars or other suitable metal pillars. In some embodiments, the die 400 further includes interconnect structures (not shown) embedded in or located between the conductive pillars 404 and the semiconductor substrate 402, and a plurality of conductive pads (not shown).

[0024] In some embodiments, the grain 400 has an active surface AS and a rear surface RS opposite to the active surface AS. As shown in FIG3B, the rear surface RS of the grain 400 is attached to the adhesive layer AD while the active surface AS of the grain 400 faces upward. In some embodiments, the active surface AS of the grain 400 is exposed to the atmospheric environment.

[0025] In some embodiments, the TIV 300 is formed prior to the placement of the die 400. However, this disclosure is not limited thereto. In some alternative embodiments, the die 400 may be placed prior to the formation of the TIV 300.

[0026] Referring to FIG3C, an encapsulation body 500 is formed on the first surface S1 of the carrier C1 to encapsulate the TIV 300 and the grain 400 laterally. In some embodiments, the encapsulation body 500 comprises a molding compound, a molding underfill, a resin (e.g., epoxy resin), etc. In some alternative embodiments, the encapsulation body 500 comprises a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, etc. In some embodiments, the encapsulation body 500 comprises a filler. The filler may be particles made of silicon dioxide, aluminum dioxide, etc. In some embodiments, the encapsulation body 500 is formed by the following steps. First, an insulating material (not shown) is formed on the wiring pattern 200 and the first surface S1 of the carrier C1 by a molding process to encapsulate the TIV 300 and the grain 400. The molding process includes, for example, a transfer molding process, a compression molding process, etc. During the molding process, the conductive pillar 404 is encapsulated by an insulating material. In other words, the conductive pillar 404 is not exposed and is well protected by the insulating material. Subsequently, the insulating material is polished until the top surface of the TIV 300 and the top surface of the conductive pillar 404 are exposed to form the encapsulation 500. In some embodiments, the insulating material is polished by a mechanical polishing process and / or a CMP process. In some embodiments, some portions of the TIV 300 and some portions of the conductive pillar 404 are also lightly polished. As shown in FIG3C, after the polishing process, the TIV 300 penetrates through the encapsulation 500.

[0027] Referring to FIG3D, a redistribution structure 600 is formed on the TIV 300, the die 400, and the encapsulation 500. In some embodiments, the redistribution structure 600 includes a plurality of conductive patterns 602, a plurality of vias 604, and a dielectric layer 606. In some embodiments, the conductive patterns 602 and vias 604 are formed by an etching process performed after a plating process. The plating process includes, for example, an electroplating process, an electroless plating process, an immersion plating process, etc. The etching process includes, for example, anisotropic etching processes (e.g., dry etching) or isotropic etching processes (e.g., wet etching). In some embodiments, the conductive patterns 602 and the underlying vias 604 are formed simultaneously. In some embodiments, the materials of the conductive patterns 602 and the vias 604 include aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. In some embodiments, the dielectric layer 606 encapsulates the conductive patterns 602 and the vias 604. In some embodiments, dielectric layer 606 is a polymer layer made of PBO, PI, BCB, or combinations thereof. For simplicity, dielectric layer 606 is shown as a bulky layer in FIG3D; however, it should be understood that dielectric layer 606 may be composed of multiple dielectric layers.

[0028] As shown in FIG3D, the via 604 is in solid contact with the conductive pillars 404 of the TIV 300 and the die 400. In other words, the via 604 provides electrical connections between the redistribution structure 600 and the TIV 300, and between the redistribution structure 600 and the die 400. In some embodiments, the die 400 is electrically connected to the TCV 110 of the carrier C1 sequentially via the redistribution structure 600, the TIV 300, and the wiring pattern 200.

[0029] Referring to Figures 3D and 3E, the structure shown in Figure 3D is flipped so that the second surface S2 of the carrier plate C1 faces upward. Thereafter, a redistribution structure 700 is formed on the second surface S2 of the carrier plate C1. In some embodiments, the redistribution structure 700 includes a plurality of conductive patterns 702, a plurality of vias 704, and a dielectric layer 706. The conductive patterns 702, vias 704, and dielectric layer 706 of the redistribution structure 700 are similar to the conductive patterns 602, vias 604, and dielectric layer 606 of the redistribution structure 600, respectively, and therefore will not be described in detail herein. For simplicity, the dielectric layer 706 is shown as a block layer in Figure 3E; however, it should be understood that the dielectric layer 706 may be composed of multiple dielectric layers. The conductive patterns 702 and the dielectric layers 706 are stacked alternately. In some embodiments, two adjacent conductive patterns 702 in the vertical direction are electrically connected to each other via a via 704 sandwiched between the two adjacent conductive patterns 702. As shown in FIG3E, the bottommost conductive pattern 702 is in solid contact with the bottom surface B110 of the TCV 110. In other words, the redistribution structure 700 is electrically connected to the TCV 110 via the bottommost conductive pattern 702. In some embodiments, the dielectric layer 706 exposes the topmost conductive pattern 702. It should be noted that although FIG3A to FIG3E show that the wiring pattern 200, TIV 300, die 400, encapsulation 500 and redistribution structure 600 are formed on the carrier C1 prior to the formation of the redistribution structure 700, this disclosure is not limited thereto. In some alternative embodiments, the redistribution structure 700 may be formed on the carrier C1 prior to the wiring pattern 200, TIV 300, die 400, encapsulation 500 and redistribution structure 600.

[0030] Referring to FIG3F, a plurality of conductive terminals 800 are formed on the redistribution structure 700. For example, conductive terminals 800 are formed on the topmost conductive pattern 702 exposed by the dielectric layer 706. In some embodiments, conductive terminals 800 are solder balls, ball grid array (BGA) balls, etc. In some embodiments, conductive terminals 800 are made of a conductive material with low resistivity (e.g., Sn, Pb, Ag, Cu, Ni, Bi or alloys thereof).

[0031] Referring to Figures 3F and 3G, the structure shown in Figure 3F is flipped over and a monolithization process is performed on the structure to obtain the package structure 10. In some embodiments, the monolithization process typically involves cutting using a rotation blade and / or a laser beam. In other words, the monolithization process includes laser dicing, mechanical dicing, laser grooving, other suitable processes, or combinations thereof.

[0032] Figures 4A to 4G are schematic cross-sectional views illustrating the manufacturing process of the package structure 20 according to some alternative embodiments of the present disclosure. Referring to Figure 4A, a carrier plate C1' is provided. In some embodiments, the carrier plate C1' in Figure 4A is similar to the carrier plate C1 in Figures 1E and 2E, and therefore will not be described in detail herein. The difference between the carrier plate C1' in Figure 4A and the carrier plate C1 in Figures 1E and 2E is that the pitch p2 between two adjacent TCVs 110 in the carrier plate C1' shown in Figure 4A is greater than the pitch p2 between two adjacent TCVs 110 in the carrier plate C1 shown in Figures 1E and 2E. Subsequently, a cavity CV is formed in the insulating body 100. In other words, the insulating body 100 of the carrier plate C1' has a cavity CV. In some embodiments, the cavity CV is formed by laser drilling, mechanical drilling, etching, etc. In some embodiments, the cavity CV is formed between adjacent TCVs 110. In other words, the cavity CV is surrounded by TCVs 110. In some embodiments, the depth DCV of the cavity CV is less than the depth DOP of each opening OP. Similarly, the depth DCV of the cavity CV is also less than the height H110 of each TCV 110. That is, the cavity CV does not penetrate the insulating body 100. For example, the depth DCV of the cavity CV is in the range of about 50 μm to about 750 μm. In some embodiments, the sidewall SWCV of the cavity CV is inclined. In some embodiments, the first surface 100a of the insulating body 100, the top surface T110 of the TCV 110, the sidewall SWCV of the cavity CV, and the bottom surface BCV of the cavity CV are collectively referred to as the first surface S1 of the carrier plate C1'.

[0033] Referring to FIG4B, a grain 400 is disposed within the cavity CV. In some embodiments, the grain 400 in FIG4B is similar to the grain 400 in FIG3B, and therefore will not be described in detail herein. As shown in FIG4B, the grain 400 is positioned such that the active surface AS of the grain 400 faces upward. On the other hand, the rear surface RS of the grain 400 is bonded to the bottom surface BCV of the cavity CV via an adhesive layer AD. As described above, the bottom surface BCV is considered to be part of the first surface S1 of the carrier plate C1', and therefore the grain 400 is considered to be disposed on the first surface S1 of the carrier plate C1'. In some embodiments, the adhesive layer AD includes a grain bonding film, etc.

[0034] Referring to FIG4C, an encapsulation body 500 is formed in the cavity CV to laterally encapsulate the die 400. That is, both the die 400 and the encapsulation body 500 are located within the cavity CV, and at least a portion of the encapsulation body 500 is sandwiched between the die 400 and the insulating body 100. In some embodiments, the encapsulation body 500 in FIG4C is similar to the encapsulation body 500 in FIG3C, and therefore will not be described in detail herein. As shown in FIG4C, the encapsulation body 500 exposes the top surface of the conductive pillars 404 of the die 400 for future electrical connection.

[0035] Referring to FIG4D, a redistribution structure 600 is formed on the insulating body 100, TCV 110, die 400, and encapsulation 500. In some embodiments, the redistribution structure 600 includes a plurality of conductive patterns 602, a plurality of vias 604, and a dielectric layer 606. In some embodiments, the conductive patterns 602, vias 604, and dielectric layer 606 in FIG4D are similar to the conductive patterns 602, vias 604, and dielectric layer 606 in FIG3D, and therefore will not be described in detail herein. As shown in FIG4D, the vias 604 are in solid contact with the conductive pillars 404 of the TCV 110 and the die 400. In other words, the vias 604 provide electrical connections between the redistribution structure 600 and the TCV 110, and between the redistribution structure 600 and the die 400. In some embodiments, the die 400 is electrically connected to the TCV 110 of the carrier C1' via the redistribution structure 600.

[0036] Referring to Figures 4D and 4E, the structure shown in Figure 4D is flipped over so that the second surface S2 of the carrier plate C1' faces upward. Thereafter, a redistribution structure 700 is formed on the second surface S2 of the carrier plate C1'. In some embodiments, the redistribution structure 700 includes a plurality of conductive patterns 702, a plurality of vias 704, and a dielectric layer 706. In some embodiments, the conductive patterns 702, vias 704, and dielectric layer 706 in Figure 4E are similar to those in Figure 3E, and therefore will not be described further herein.

[0037] Referring to FIG4F, a plurality of conductive terminals 800 are formed on the redistribution structure 700. In some embodiments, the conductive terminals 800 in FIG4F are similar to the conductive terminals 800 in FIG3F, and therefore will not be described in detail herein.

[0038] Referring to Figures 4F and 4G, the structure shown in Figure 4F is flipped over and a monolithization process is performed on the structure to obtain the package structure 20. In some embodiments, the monolithization process typically involves cutting using a rotating blade and / or a laser beam. In other words, the monolithization process includes laser dicing, mechanical dicing, laser grooving, other suitable processes, or combinations thereof.

[0039] FIG5 is a schematic cross-sectional view of a package structure 30 according to some alternative embodiments of the present disclosure. Referring to FIG5, the package structure 30 includes a carrier board C1, a plurality of wiring patterns 200, a die 400, a redistribution structure 700, a plurality of connectors 900, and an underfill layer 1000. In some embodiments, the carrier board C1, wiring patterns 200, die 400, and redistribution structure 700 in FIG5 are similar to the carrier board C1, wiring patterns 200, die 400, and redistribution structure 700 in FIG3G, and therefore will not be described in detail herein.

[0040] As shown in FIG. 5, a die 400 is disposed on a first surface S1 of a carrier plate C1. In some embodiments, the die 400 is placed face down. In other words, the die 400 is positioned such that the active surface AS of the die 400 faces down. In some embodiments, the die 400 is bonded to a wiring pattern 200 by flip-chip bonding. For example, the conductive post 404 of the die 400 is attached to the wiring pattern 200 via a connector 900. In some embodiments, the connector 900 is made of a conductive material with low resistivity (e.g., Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof).

[0041] In some embodiments, the underfill layer 1000 laterally encapsulates the wiring pattern 200, the conductive pillars 404 of the die 400, and the connectors 900 to protect these components. In some embodiments, the underfill layer 1000 further covers a portion of each sidewall of the semiconductor substrate 402 of the die 400. In some embodiments, the material of the underfill layer 1000 is an insulating material and may include resin (e.g., epoxy resin), filler material, stress release agent (SRA), adhesion promoter, other materials, or combinations thereof. In some embodiments, the underfill layer 1000 is optional.

[0042] As shown in FIG5, the redistribution structure 700 and the conductive terminal 800 are sequentially disposed on the second surface S2 of the carrier plate C1. In some embodiments, the TCV 110 enables an electrical connection between the die 400 on the first surface S1 of the carrier plate C1 and the redistribution structure 700 on the second surface S2 of the carrier plate C1.

[0043] Figures 6A to 6E are schematic cross-sectional views of the manufacturing process of the carrier plate C2 according to some alternative embodiments of the present disclosure. Referring to Figure 6A, an insulating body 100 is provided on the sacrificial film SF. In some embodiments, the insulating body 100 and the sacrificial film SF in Figure 6A are similar to the insulating body 100 and the sacrificial film SF in Figure 1A, and therefore will not be described in detail herein.

[0044] Referring to FIG6B, a plurality of TCVs 110a are formed in the opening OP of the insulating body 100. In some embodiments, the TCVs 110a are prefabricated and placed in the opening OP of the insulating body 100. For example, the TCVs 110a are prefabricated conductive pillars or conductive struts. In some embodiments, the TCVs 110a are placed upright on the sacrificial film SF. The prefabricated TCVs 110a can be placed in the opening OP by various processes. These processes will be described below with reference to FIGS. 7A to 7D.

[0045] Figures 7A to 7D are schematic cross-sectional views of various methods of placing TCV 110a in the opening OP of the insulating body 100 shown in Figure 6B.

[0046] Referring to FIG7A, a stencil ST is provided on the insulating body 100. In some embodiments, the stencil ST has a plurality of holes AP, and each hole AP exposes a corresponding opening OP of the insulating body 100. After the stencil ST is provided, a plurality of pre-fabricated TCVs 110a are placed on the stencil ST. Subsequently, a scraper SC is provided on the stencil ST and the TCVs 110a. In some embodiments, the scraper SC moves along the span of the insulating body 100 and scrapes the TCVs 110a above the stencil ST into the holes AP of the stencil ST and the opening OP of the insulating body 100 during its movement. For example, the TCVs 110a are capable of rolling on the upper surface of the stencil ST, and the scraper SC can easily drive the TCVs 110a into the holes AP of the stencil ST and the opening OP of the insulating body 100.

[0047] Referring to FIG7B, a mesh plate ST is provided on the insulating body 100. In some embodiments, the mesh plate ST has a plurality of holes AP, and each hole AP exposes a corresponding opening OP of the insulating body 100. After the mesh plate ST is provided, a plurality of pre-fabricated TCVs 110a are placed on the mesh plate ST. Subsequently, the insulating body 100 is tilted, thus driving the TCVs 110a into the holes AP of the mesh plate ST and the opening OP of the insulating body 100 by gravity. For example, the TCVs 110a are able to roll on the upper surface of the mesh plate ST, and gravity causes the TCVs 110a to fall into the holes AP of the mesh plate ST and the opening OP of the insulating body 100. In some embodiments, the insulating body 100 vibrates while tilting. In other words, the TCVs 110a are subjected to a specific vibration frequency to further aid the rolling of the TCVs 110a.

[0048] Referring to FIG7C, a stencil ST is provided on the insulating body 100. In some embodiments, the stencil ST has a plurality of holes AP, and each hole AP exposes a corresponding opening OP of the insulating body 100. After the stencil ST is provided, a plurality of pre-fabricated TCVs 110a are placed on the stencil ST. Thereafter, a suction mechanism (not shown) above the stencil ST and the TCVs 110a is opened to suction the TCVs 110a upward. After the TCVs 110a are suctioned upward and float in the air, the suction mechanism is closed, so that the TCVs 110a will fall into the holes AP of the stencil ST and the openings OP of the insulating body 100 due to gravity. The above process can be repeated multiple times until each opening OP accommodates one TCV 110a.

[0049] Referring to FIG7D, the TCV 110a is placed into the opening OP of the insulating body 100 by a pick-and-place process. For example, the pre-fabricated TCV 110a is picked up one by one by the placement tool TL, and the pre-fabricated TCV 110a is placed one by one into the opening OP of the insulating body 100 by the placement tool TL.

[0050] Although the process of placing TCV 110a into the opening OP of the insulating body 100 is shown as a separate process in Figures 7A to 7D, this disclosure is not limited thereto. In some alternative embodiments, at least two of the processes shown in Figures 7A to 7D may be combined to place TCV 110a into the opening OP of the insulating body 100.

[0051] Referring back to FIG6B, the height H110a of each TCV 110a is substantially the same as the depth DOP of each opening OP. In some embodiments, the height H110a of each TCV 110a is in the range of about 50 μm to about 1000 μm. In some embodiments, each TCV 110a has a substantially straight sidewall SW110a. That is, the first diameter DA110a of each TCV 110a may be substantially equal to the second diameter DB110a of each TCV 110a, and each TCV 110a may be cylindrical. As shown in FIG6B, the first diameter DA110a of each TCV 110a is smaller than the first diameter DAOP of each opening OP. At the same time, the first diameter DA110a and the second diameter DB110a of each TCV 110a are substantially equal to the second diameter DBOP of each opening OP. However, this disclosure is not limited thereto. In some alternative embodiments, both the first diameter DA110a and the second diameter DB110a of each TCV 110a are smaller than the first diameter DAOP and the second diameter DBOP of each opening OP. In some embodiments, the first diameter DA110a and the second diameter DB110a are in the range of about 50 μm to about 300 μm. In some embodiments, two adjacent TCV 110a are formed to have a pitch p2 in the range of about 100 μm to about 1000 μm.

[0052] Referring to FIG6C, a filler material layer 120a is formed on the insulating body 100. In some embodiments, the filler material layer 120a covers a first surface 100a of the insulating body 100 and fills an opening OP of the insulating body 100. In some embodiments, a TCV 110a located in the opening OP of the insulating body 100 is encapsulated by the filler material layer 120a. In other words, the TCV 110a is not exposed and is well protected by the filler material layer 120a. In some embodiments, the filler material layer 120a is made of an organic material. For example, the filler material layer 120a is made of polymeric materials such as acetal, acrylic acid, cellulose, acetic acid, polyethylene, polystyrene, ethylene, nylon, polyolefin, polyester, silicone, paraffin, or combinations thereof. In some alternative embodiments, the filler material layer 120a is made of a molding compound. When the filler material layer 120a is made of a molding compound, the filler material layer 120a may also contain fillers. The filler may be particles made of silicon dioxide, aluminum dioxide, etc. In some embodiments, the filler material layer 120a is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (PVD), etc. Alternatively, the filler material layer 120a may be formed by transfer molding, compression molding, or any other suitable molding process. In some embodiments, the Young's modulus of the filler material layer 120a is in the range of about 3 GPa to about 30 GPa. For example, when the filler material layer 120a is made of a polymeric material, the Young's modulus of the filler material layer 120a is in the range of about 3 GPa to about 5 GPa. Alternatively, when the filler layer 120a is made of a molding compound, the Young's modulus of the filler layer 120a is in the range of about 15 GPa to about 30 GPa.

[0053] Referring to Figures 6C and 6D, a portion of the filler material layer 120a is removed to form a plurality of filler patterns 120 in the opening OP of the insulating body 100. In some embodiments, the portion of the filler material layer 120a is removed until the top surface T110a of the TCV 110a is exposed. For example, the filler material layer 120a above the first surface 100a of the insulating body 100 is removed to form the filler patterns 120. In some embodiments, the portion of the filler material layer 120a is removed by a planarization process, an etching process, etc. Planarization processes include, for example, CMP processes, mechanical polishing processes, etc. Etching processes include, for example, anisotropic etching processes (e.g., dry etching) or isotropic etching processes (e.g., wet etching). In some embodiments, the filler patterns 120 are sandwiched between each TCV 110a and the insulating body 100.

[0054] Referring to Figures 6D and 6E, the sacrificial film SF is removed to expose the second surface 100b of the insulating body 100, thereby obtaining the carrier plate C2. In some embodiments, the sacrificial film SF is removed by an etching process, a stripping process, etc. In some embodiments, the carrier plate C2 includes the insulating body 100, TCV 110a, and filler pattern 120. The TCV 110a is embedded in the insulating body 100 and the filler pattern 120. For example, each filler pattern 120 laterally encapsulates the corresponding TCV 110a, and the insulating body 100 laterally encapsulates the filler pattern 120. In some embodiments, the insulating body 100 and the filler pattern 120 are made of different materials. As shown in Figure 6E, each TCV 110a and each filler pattern 120 penetrates through the insulating body 100. In other words, the height H110a of each TCV 110a and the height H120 of each filler pattern 120 are substantially equal to the thickness t100 of the insulating body 100. For example, the height H110a of each TCV 110a and the height H120 of each fill pattern 120 are in the range of about 50 μm to about 1000 μm.

[0055] As shown in FIG6E, each filler pattern 120 is sandwiched between each TCV 110a and the insulating body 100. In other words, the filler pattern 120 is in physical contact with the insulating body 100 and the TCV 110a. In some embodiments, since the filler pattern 120 is formed by filling the gap between the opening OP of the insulating body 100 and the TCV 110a, the geometry of the filler pattern 120 depends on the geometry of the opening OP and the TCV 110a. For example, the inner sidewall ISW 120 of each filler pattern 120 follows the contour of the sidewall SW 110a of the corresponding TCV 110a that is in physical contact with the filler pattern 120. Similarly, the outer sidewall OSW 120 of each filler pattern 120 follows the contour of the sidewall SWOP of the corresponding opening OP of the insulating body 100. In other words, each filler pattern 120 has an inner sidewall ISW120 that contacts the corresponding TCV 110a and an outer sidewall OSW120 that contacts the insulating body 100. As described above, each TCV 110a has a substantially straight sidewall SW110a. Since the inner sidewall ISW120 of the filler pattern 120 follows the contour of the sidewall SW110a of the TCV 110a, the inner sidewall ISW120 of each filler pattern 120 is also substantially straight. On the other hand, as described above, each opening OP of the insulating body 100 has a sloping sidewall SWOP. Since the outer sidewall OSW120 of the filler pattern 120 follows the contour of the sidewall SWOP of the opening, the outer sidewall OSW120 of each filler pattern 120 is sloping. In some embodiments, the Young's modulus of the filler pattern 120 is in the range of about 3 GPa to about 30 GPa. For example, when the infill pattern 120 is made of a polymeric material, the Young's modulus of the infill pattern 120 is in the range of about 3 GPa to about 5 GPa. Alternatively, when the infill pattern 120 is made of a molding compound, the Young's modulus of the infill pattern 120 is in the range of about 15 GPa to about 30 GPa.

[0056] As shown in FIG6E, the top surface T110a of TCV 110a and the top surface T120 of the filling pattern 120 are substantially coplanar with the first surface 100a of the insulating body 100. Similarly, the bottom surface B110a of TCV 110a is substantially coplanar with the second surface 100b of the insulating body 100. In some embodiments, the top surface T110a of TCV 110a, the top surface T120 of the filling pattern 120, and the first surface 100a of the insulating body 100 are collectively referred to as the first surface S1 of the carrier plate C2. On the other hand, the bottom surface B110a of TCV 110a and the second surface 100b of the insulating body 100 are collectively referred to as the second surface S2 of the carrier plate C2. As described above, the second diameter DB110a of each TCV 110a is substantially equal to the second diameter DBOP of each opening OP of the insulating body 100. In this way, the filler pattern 120 is not exposed at the second surface 100b of the insulating body 100 (i.e., not exposed at the second surface S2 of the carrier plate C2). However, this disclosure is not limited thereto. In some alternative embodiments, when the second diameter DB110a of the TCV 110a is smaller than the second diameter DBOP of the opening OP of the insulating body 100, the bottom surface of the filler pattern 120 will be exposed at the second surface 100b of the insulating body 100. In this case, the bottom surface of the filler pattern 120 may be included as part of the second surface S2 of the carrier plate C2. In some embodiments, the first surface S1 of the carrier plate C2 is opposite to the second surface S2 of the carrier plate C2.

[0057] As described above, the TCV 110a is prefabricated and placed in the opening OP of the insulating body 100. The prefabricated TCV 110a enables higher conductivity, higher yield, and higher quality (i.e., there are no voids within the TCV 110a). In this way, the total cost of manufacturing the carrier plate C2 can be effectively reduced and the quality of the carrier plate C2 can be ensured.

[0058] Figures 8A to 8E are schematic cross-sectional views of the manufacturing process of a carrier plate C2 according to some alternative embodiments of the present disclosure.

[0059] Referring to FIG8A, an insulating body 100 is provided. The insulating body 100 in FIG8A is similar to the insulating body 100 in FIG6A, and therefore will not be described again herein. However, as shown in FIG8A, the opening OP does not penetrate the insulating body 100. For example, the depth DOP of each opening OP is less than the thickness t100 of the insulating body 100. In addition, the sacrificial film in FIG6A is omitted in FIG8A. In other words, the second surface 100b of the insulating body 100 is exposed in FIG8A.

[0060] Referring to Figures 8B to 8D, the steps shown in Figures 8B to 8D are similar to those shown in Figures 6B to 6D, and therefore will not be described again in this document.

[0061] Referring to Figures 8D and 8E, a portion of the insulating body 100 is removed to expose the bottom surface B110a of the TCV 110a, thereby obtaining the carrier plate C2. For example, a planarization process or an etching process is performed on the insulating body 100 from the second surface 100b shown in Figure 8D until the bottom surface B110a of the TCV 110a is exposed. Planarization processes include, for example, CMP processes, mechanical polishing processes, etc. Etching processes include, for example, anisotropic etching processes (e.g., dry etching) or isotropic etching processes (e.g., wet etching). In some embodiments, the TCV 110a may be slightly planarized or etched from the bottom surface B110a of the TCV 110a to further reduce the total thickness of the carrier plate C2. It should be noted that although Figures 6A to 6E and Figures 8A to 8E show two different methods for manufacturing the carrier plate C2, the structure of the carrier plate C2 obtained by these two methods can be substantially the same.

[0062] In some embodiments, the carrier board C2 can be used in a variety of applications. For example, the carrier board C2 can be incorporated into various package structures to serve as a support structure while simultaneously providing electrical paths. The applications of the carrier board C2 will be described below with reference to Figures 9 to 11.

[0063] FIG9 is a schematic cross-sectional view of a package structure 40 according to some alternative embodiments of the present disclosure. Referring to FIG9, the package structure 40 in FIG9 is similar to the package structure 10 in FIG3G, and therefore similar elements are indicated by the same reference numerals and will not be described again herein. The difference between the package structure 40 shown in FIG9 and the package structure 10 in FIG3G is that the carrier C1 in FIG3G is replaced by the carrier C2 in FIG9. That is, the carrier C2 in FIG6E and FIG8E is incorporated into the package structure 40 shown in FIG9. As shown in FIG9, the TCV 110a and the fill pattern 120 of the carrier C2 are in solid contact with the wiring pattern 200. In other words, the TCV 110a is well protected by the fill pattern 120 and can provide electrical connection between the first surface S1 and the second surface S2 of the carrier C2 (i.e., between the die 400 and the redistribution structure 700 and between the TIV 300 and the redistribution structure 700).

[0064] FIG10 is a schematic cross-sectional view of a package structure 50 according to some alternative embodiments of the present disclosure. Referring to FIG10, the package structure 50 in FIG10 is similar to the package structure 20 in FIG4G, and therefore similar elements are indicated by the same reference numerals and will not be described again herein. The difference between the package structure 50 shown in FIG10 and the package structure 20 in FIG4G is that the carrier plate C1' in FIG4G is replaced by the carrier plate C2' in FIG10. In some embodiments, the carrier plate C2' in FIG10 is similar to the carrier plate C2 in FIG6E and FIG8E, and will not be described again herein. The difference between the carrier plate C2' in FIG10 and the carrier plate C2 in FIG6E and FIG8E is that the pitch p2 between two adjacent TCV 110a in the carrier plate C2' shown in FIG10 is greater than the pitch p2 between two adjacent TCV 110a in the carrier plate C2 shown in FIG6E and FIG8E. In addition, a cavity CV is formed in the insulating body 100. As shown in FIG. 10, the fill pattern 120 of the carrier C2' is in solid contact with the redistribution structure 600. For example, the fill pattern 120 of the carrier C2' is in solid contact with the dielectric layer 606 of the redistribution structure 600. In some embodiments, the TCV 110a is well protected by the fill pattern 120 and is able to provide electrical connection between the first surface S1 and the second surface S2 of the carrier C2' (i.e., between the die 400 and the redistribution structure 700).

[0065] FIG11 is a schematic cross-sectional view of a package structure 60 according to some alternative embodiments of the present disclosure. Referring to FIG11, the package structure 60 in FIG11 is similar to the package structure 30 in FIG5, and therefore similar elements are indicated by the same reference numerals and will not be described again herein. The difference between the package structure 60 shown in FIG11 and the package structure 30 in FIG5 is that the carrier C1 in FIG5 is replaced by the carrier C2 in FIG11. That is, the carrier C2 in FIG6E and FIG8E is incorporated into the package structure 60 shown in FIG11. As shown in FIG11, the TCV 110a and the fill pattern 120 of the carrier C2 are in solid contact with the wiring pattern 200. In other words, the TCV 110a is well protected by the fill pattern 120 and can provide electrical connection between the first surface S1 and the second surface S2 of the carrier C2 (i.e., between the die 400 and the redistribution structure 700).

[0066] Figures 12A to 12E are schematic cross-sectional views illustrating the manufacturing process of a carrier plate C3 according to some alternative embodiments of the present disclosure. Referring to Figure 12A, an insulating body 100 is provided on the sacrificial film SF. In some embodiments, the insulating body 100 and the sacrificial film SF in Figure 12A are similar to those in Figure 6A, and therefore will not be described again herein. However, in Figure 12A, the pitch p3 between two adjacent openings OP is greater than the pitch p1 between two adjacent openings OP in Figure 6A.

[0067] Referring to FIG12B, a plurality of TCVs 110b are formed in the opening OP of the insulating body 100. The method of forming the TCVs 110b in FIG12B and the materials are similar to those of forming the TCVs 110a in FIG6B, and therefore will not be described in detail herein. Referring to FIG12B, the height H110b of each TCV 110b is greater than the depth DOP of each opening OP. That is, each TCV 110b is locally located in the corresponding opening OP and protrudes from the opening OP of the insulating body 100. For example, each TCV 110b protrudes above the first surface 100a of the insulating body 100. In some embodiments, the height H110b of each TCV 110b is in the range of about 100 μm to about 1000 μm. In some embodiments, each TCV 110b has a substantially straight sidewall SW110b. That is, the first diameter DA110b of each TCV 110b may be substantially equal to the second diameter DB110b of each TCV 110b, and each TCV 110b may be cylindrical. As shown in FIG12B, the first diameter DA110b of each TCV 110b is smaller than the first diameter DAOP of each opening OP. Simultaneously, the first diameter DA110b and the second diameter DB110b of each TCV 110b are substantially equal to the second diameter DBOP of each opening OP. However, this disclosure is not limited thereto. In some alternative embodiments, both the first diameter DA110b and the second diameter DB110b of each TCV 110b are smaller than the first diameter DAOP and the second diameter DBOP of each opening OP. In some embodiments, the first diameter DA110b and the second diameter DB110b are in the range of about 50 μm to about 300 μm. That is, the aspect ratio (i.e., the ratio of height H110b to the first diameter DA110b / second diameter DB110b) is in the range of about 1 to about 10. In some embodiments, the pitch p4 between two adjacent TCVs 110b is substantially equal to the pitch p3 between two adjacent openings OP (shown in FIG12A).

[0068] Referring to FIG12C, a filling material layer 120a is formed on the insulating body 100. The method of forming the filling material layer 120a in FIG12C and the material are similar to those in FIG6C, and therefore will not be described in detail herein. In some embodiments, the filling material layer 120a covers the first surface 100a of the insulating body 100 and fills the opening OP of the insulating body 100. In some embodiments, the TCV 110b is laterally encapsulated by the filling material layer 120a.

[0069] Referring to Figures 12C and 12D, a portion of the filler material layer 120a is removed to form a plurality of filler patterns 120 in the opening OP of the insulating body 100. In some embodiments, the portion of the filler material layer 120a is removed until the first surface 100a of the insulating body 100 is exposed. For example, the filler material layer 120a above the first surface 100a of the insulating body 100 is removed to form the filler patterns 120. In some embodiments, the portion of the filler material layer 120a is removed by a planarization process, an etching process, etc. Planarization processes include, for example, CMP processes, mechanical polishing processes, etc. Etching processes include, for example, anisotropic etching processes (e.g., dry etching) or isotropic etching processes (e.g., wet etching). In some embodiments, the filler patterns 120 are sandwiched between each TCV 110b and the insulating body 100. In other words, the TCV 110b protrudes from the filler patterns 120.

[0070] Referring to Figures 12D and 12E, the sacrificial film SF is removed to expose the second surface 100b of the insulating body 100, thereby obtaining the carrier plate C3. In some embodiments, the sacrificial film SF is removed by an etching process, a stripping process, etc. In some embodiments, the carrier plate C3 includes the insulating body 100, the TCV 110b, and the filler pattern 120. The TCV 110b is partially embedded in the insulating body 100 and the filler pattern 120. For example, each filler pattern 120 laterally encapsulates a portion of the corresponding TCV 110b, and the insulating body 100 laterally encapsulates the filler pattern 120. In some embodiments, the insulating body 100 and the filler pattern 120 are made of different materials. As shown in Figure 12E, each filler pattern 120 penetrates through the insulating body 100. In other words, the height H120 of each filler pattern 120 is substantially equal to the thickness t100 of the insulating body 100. On the other hand, each TCV 110b not only penetrates the insulating body 100, but also protrudes outward on the first surface 100a of the insulating body 100. That is, the height H110b of each TCV 110b is greater than the thickness t100 of the insulating body 100.

[0071] As shown in FIG12E, each filler pattern 120 is sandwiched between each TCV 110b and the insulating body 100. In other words, the filler pattern 120 is in physical contact with the insulating body 100 and the TCV 110b. In some embodiments, since the filler pattern 120 is formed by filling the gap between the opening OP of the insulating body 100 and the TCV 110b, the geometry of the filler pattern 120 depends on the geometry of the opening OP and the TCV 110b. For example, the inner sidewall ISW 120 of each filler pattern 120 follows the contour of the sidewall SW 110b of the corresponding TCV 110b that is in physical contact with the filler pattern 120. Similarly, the outer sidewall OSW 120 of each filler pattern 120 follows the contour of the sidewall SWOP of the corresponding opening OP of the insulating body 100. In other words, each filler pattern 120 has an inner sidewall ISW120 that contacts the corresponding TCV 110b and an outer sidewall OSW120 that contacts the insulating body 100. As described above, each TCV 110b has a substantially straight sidewall SW110b. Since the inner sidewall ISW120 of the filler pattern 120 follows the contour of the sidewall SW110b of the TCV 110b, the inner sidewall ISW120 of each filler pattern 120 is also substantially straight. On the other hand, each opening OP of the insulating body 100 has a sloping sidewall SWOP (shown in FIG. 12A). Since the outer sidewall OSW120 of the filler pattern 120 follows the contour of the sidewall SWOP of the opening, the outer sidewall OSW120 of each filler pattern 120 is sloping. In some embodiments, the Young's modulus of the filler pattern 120 is in the range of about 3 GPa to about 30 GPa. For example, when the infill pattern 120 is made of a polymeric material, the Young's modulus of the infill pattern 120 is in the range of about 3 GPa to about 5 GPa. Alternatively, when the infill pattern 120 is made of a molding compound, the Young's modulus of the infill pattern 120 is in the range of about 15 GPa to about 30 GPa.

[0072] As shown in FIG12E, the top surface T120 of the filling pattern 120 is substantially coplanar with the first surface 100a of the insulating body 100. However, the top surface T110b of the TCV 110b is located at a horizontal height higher than the horizontal height of the top surface T120 of the filling pattern 120 and the first surface 100a of the insulating body 100. On the other hand, the bottom surface B110b of the TCV 110b is substantially coplanar with the second surface 100b of the insulating body 100. As described above, the second diameter DB110b of each TCV 110b is substantially equal to the second diameter DBOP of each opening OP of the insulating body 100. In this way, the filling pattern 120 is not exposed at the second surface 100b of the insulating body 100. However, this disclosure is not limited thereto. In some alternative embodiments, when the second diameter DB110b of TCV 110b is smaller than the second diameter DBOP of the opening OP of the insulating body 100, the bottom surface of the fill pattern 120 will be exposed at the second surface 100b of the insulating body 100.

[0073] In some embodiments, the TCV 110b is prefabricated and placed in the opening OP of the insulating body 100. Prefabricated TCV 110b enables higher conductivity, higher yield, and higher quality (i.e., no voids within the TCV 110b). This effectively reduces the total cost of manufacturing the carrier plate C3 and ensures the quality of the carrier plate C3.

[0074] In some embodiments, the carrier C3 can be used in a variety of applications. For example, the carrier C3 can be incorporated into various package structures to serve as a support structure while simultaneously providing an electrical path. The applications of the carrier C3 will be described below with reference to Figures 13A to 13F, Figure 14 and Figure 15.

[0075] Figures 13A to 13F are schematic cross-sectional views illustrating the manufacturing process of a package structure 70 according to some alternative embodiments of the present disclosure. Referring to Figure 13A, a carrier plate C3 as shown in Figure 12E is provided. A die 400 is then disposed on the carrier plate C3. For example, the die 400 is disposed on a first surface 100a of an insulating body 100. In some embodiments, the die 400 is disposed via a pick-and-place process, etc. In some embodiments, the die 400 is disposed between TCVs 110b. For example, as shown in Figure 13A, the die 400 is surrounded by protrusions of the TCVs 110b. In some embodiments, the die 400 is attached to the carrier plate C3 by an adhesive layer AD. For example, the adhesive layer AD is sandwiched between the die 400 and the first surface 100a of the insulating body 100 to hold the die 400 in place. In some embodiments, each die 400 includes a semiconductor substrate 402 and a plurality of conductive pillars 404. In some embodiments, the semiconductor substrate 402 and conductive pillar 404 in FIG13A are similar to those in FIG3B, and therefore will not be described in detail herein. In some embodiments, the die 400 has an active surface AS and a rear surface RS opposite to the active surface AS. As shown in FIG13A, the rear surface RS of the die 400 is attached to the adhesive layer AD while the active surface AS of the die 400 faces upward. In some embodiments, the active surface AS of the die 400 is exposed to the atmospheric environment.

[0076] Referring to FIG13B, an encapsulation body 500 is formed on the first surface 100a of the insulating body 100 to laterally encapsulate the grains 400 and the protruding portions of each TCV 110b. That is, the encapsulation body 500 encapsulates at least a portion of each TCV 110b (i.e., the portion of each TCV 110b located above the first surface 100a of the insulating body 100). In some embodiments, the method of forming the encapsulation body 500 in FIG13B and the materials are similar to those in FIG3C, and therefore will not be described in detail herein. As shown in FIG13B, the first portion of the TCV 110b encapsulated by the encapsulation body 500 and the second portion of the same TCV 110b encapsulated by the filled pattern 120 are integrally formed, and the sidewalls of the first portion are aligned with the sidewalls of the second portion.

[0077] Referring to FIG13C, a redistribution structure 600 is formed on the TCV 110b, the die 400, and the encapsulation 500. In some embodiments, the redistribution structure 600 includes a plurality of conductive patterns 602, a plurality of vias 604, and a dielectric layer 606. In some embodiments, the conductive patterns 602, vias 604, and dielectric layer 606 in FIG13C are similar to the conductive patterns 602, vias 604, and dielectric layer 606 in FIG3D, and therefore will not be described in detail herein. As shown in FIG13C, the vias 604 are in solid contact with the conductive pillars 404 of the TCV 110b and the die 400. In other words, the vias 604 provide electrical connections between the redistribution structure 600 and the TCV 110b, and between the redistribution structure 600 and the die 400. In some embodiments, the die 400 is electrically connected to the TCV 110b of the carrier C3 via the redistribution structure 600.

[0078] Referring to Figures 13C and 13D, the structure shown in Figure 13C is flipped over so that the second surface 100b of the insulating body 100 faces upward. Thereafter, a redistribution structure 700 is formed on one side of the carrier plate C3. For example, the redistribution structure 700 is formed on the second surface 110b of the insulating body 100 and the bottom surface B110b of the TCV 110b. In some embodiments, the redistribution structure 700 includes a plurality of conductive patterns 702, a plurality of vias 704, and a dielectric layer 706. In some embodiments, the conductive patterns 702, vias 704, and dielectric layer 706 in Figure 13D are similar to those in Figure 3E, and therefore will not be described further herein. As shown in Figure 13D, the bottommost conductive pattern 702 is in solid contact with the bottom surface B110b of the TCV 110b. In other words, the redistribution structure 700 is electrically connected to the TCV 110b via the bottommost conductive pattern 702. In some embodiments, the dielectric layer 706 exposes the topmost conductive pattern 702.

[0079] Referring to FIG13E, a plurality of conductive terminals 800 are formed on the redistribution structure 700. In some embodiments, the conductive terminals 800 in FIG13E are similar to the conductive terminals 800 in FIG3F, and therefore will not be described in detail herein.

[0080] Referring to Figures 13E and 13F, the structure shown in Figure 13E is flipped over and a monolithization process is performed on the structure to obtain the package structure 70. In some embodiments, the monolithization process typically involves cutting using a rotating blade and / or a laser beam. In other words, the monolithization process includes laser dicing, mechanical dicing, laser grooving, other suitable processes, or combinations thereof. In some embodiments, by introducing a carrier board C3 with protruding TCV 110b into the package structure 70, the conventional step of forming a through-insulating layer via (TIV) can be omitted. This reduces manufacturing costs and the process complexity of forming the package structure 70.

[0081] FIG14 is a schematic cross-sectional view of a package structure 80 according to some alternative embodiments of the present disclosure. Referring to FIG14, the package structure 80 includes a carrier board C3, a plurality of TIVs 300s, a die 400, an encapsulation 500, a redistribution structure 600, a redistribution structure 700, a plurality of conductive terminals 800, and an adhesive layer AD. That is, the carrier board C3 in FIG12E is incorporated into the package structure 80 shown in FIG14. In some embodiments, the carrier board C3, TIVs 300s, die 400s, encapsulation 500s, redistribution structures 600s, redistribution structures 700s, conductive terminals 800s, and adhesive layer AD in FIG14 are similar to the carrier board C3, TIVs 300s, die 400s, encapsulation 500s, redistribution structures 600s, redistribution structures 700s, conductive terminals 800s, and adhesive layer AD in FIG3G, and therefore will not be described in detail herein.

[0082] As shown in FIG. 14, the carrier plate C3 is disposed on one side of the redistribution structure 600. On the other hand, the TIV 300, die 400, encapsulation 500, redistribution structure 700, conductive terminal 800, and adhesive layer AD are disposed on the other side of the redistribution structure 600. In some embodiments, the TCV 110b is electrically insulated from the TIV 300, die 400, redistribution structure 600, redistribution structure 700, and conductive terminal 800. In some embodiments, the carrier plate C3 serves as a heat exchanger. For example, the TCV 110b serves as a thermal dissipation fin to transfer heat from the interior of the encapsulation structure 80 to the exterior of the encapsulation structure 80.

[0083] FIG15 is a schematic cross-sectional view of a probe card 90 according to some alternative embodiments of the present disclosure. Referring to FIG15, the probe card 90 includes a carrier plate C3, a redistribution structure 700, and a plurality of conductive terminals 800. That is, the carrier plate C3 in FIG12E is incorporated into the probe card 90 shown in FIG15. In some embodiments, the carrier plate C3, redistribution structure 700, and conductive terminals 800 in FIG15 are similar to the carrier plate C3, redistribution structure 700, and conductive terminals 800 in FIG3G, and therefore will not be described in detail herein. As shown in FIG15, the TCV 110b of the carrier plate C3 is electrically connected to the redistribution structure 700 and the conductive terminals 800. As shown in FIG15, the TCV 110b has a rounded tip. However, the present disclosure is not limited thereto. In some alternative embodiments, the TCV 110b may have a sharp tip or a flat tip. In some embodiments, the TCV 110b is used as a probe of the probe card 90 to perform electrical tests on other electronic devices.

[0084] According to some embodiments of this disclosure, a packaging structure includes a carrier board, a die, and a first rewiring structure. The carrier board has a first surface and a second surface opposite to the first surface. The carrier board includes an insulating body and a carrier board through-hole (TCV) embedded in the insulating body. The die is disposed on the first surface of the carrier board. The die is electrically connected to the TCV. The first rewiring structure is disposed on the second surface of the carrier board.

[0085] According to some embodiments of this disclosure, the packaging structure further includes an encapsulation body and a second rewiring structure. The encapsulation body laterally encapsulates the die. The second rewiring structure is located on the encapsulation body and the die.

[0086] According to some embodiments of the present disclosure, the insulating body has a cavity, the die and the encapsulation are located in the cavity, and the die is electrically connected to the carrier board through a second rewiring structure.

[0087] According to some embodiments of the present disclosure, the packaging structure further includes a through-insulating layer via (TIV) through the encapsulation, wherein the die is electrically connected to the carrier via via the second rewiring structure and the through-insulating layer via.

[0088] According to some embodiments of the present disclosure, each of the carrier plate perforations includes a seed layer and a conductive layer disposed on the seed layer, and the seed layer is in contact with the insulating body entity.

[0089] According to some embodiments of the present disclosure, each of the said carrier plate perforations has inclined sidewalls.

[0090] According to some embodiments of the present disclosure, each of the said carrier plate perforations has substantially straight sidewalls.

[0091] According to some embodiments of the present disclosure, the carrier plate further includes a filler pattern sandwiched between each of the carrier plate perforations and the insulating body.

[0092] According to some embodiments of the present disclosure, each of the filling patterns has an inner sidewall that contacts the corresponding perforation of the carrier plate and an outer sidewall that contacts the insulating body, the inner sidewall of each of the filling patterns being substantially straight and the outer sidewall of each of the filling patterns being inclined.

[0093] According to some embodiments of the present disclosure, the Young's modulus of the filling pattern is in the range of about 3 GPa to about 30 GPa.

[0094] According to some alternative embodiments of the present disclosure, a packaging structure includes a carrier board, a die, and a redistribution structure. The carrier board includes an insulating body and carrier through-holes (TCVs) partially located in the insulating body. The height of each TCV is greater than the thickness of the insulating body. The die is disposed on the carrier board. The redistribution structure is disposed on at least one side of the carrier board.

[0095] According to some alternative embodiments of the present disclosure, the carrier plate further includes a filler pattern sandwiched between each of the carrier plate perforations and the insulating body.

[0096] According to some alternative embodiments of the present disclosure, each of the said carrier plate perforations has substantially straight sidewalls.

[0097] According to some alternative embodiments of the present disclosure, the packaging structure further includes an encapsulator that laterally encapsulates the die.

[0098] According to some alternative embodiments of the present disclosure, the encapsulation body also encapsulates at least a portion of each of the carrier plate perforations.

[0099] According to some embodiments of the present disclosure, a method of manufacturing a packaging structure includes at least the following steps: providing a carrier plate having a first surface and a second surface opposite to the first surface; placing a die on the first surface of the carrier plate; laterally encapsulating the die using an encapsulator; forming a redistribution structure on the second surface of the carrier plate; providing the carrier plate by at least the following steps: providing an insulating body having an opening therein; forming a carrier plate through-hole (TCV) in the opening.

[0100] According to some embodiments of the present disclosure, forming the carrier plate through-hole in the opening includes at least the following steps: forming a seed material layer on the insulating body and within the opening, the seed material layer being in contact with the insulating body. forming a conductive material layer on the seed material layer. removing a portion of the conductive material layer and a portion of the seed material layer until the insulating body is exposed, thereby forming the seed layer and the conductive layer within the opening.

[0101] According to some embodiments of the present disclosure, forming the carrier plate perforation in the opening includes at least the following steps: placing the pre-fabricated carrier plate perforation into the opening of the insulating body.

[0102] According to some embodiments of the present disclosure, the carrier plate further includes forming a filling pattern in the opening of the insulating body, the filling pattern being sandwiched between each of the carrier plate perforations and the insulating body.

[0103] According to some embodiments of the present disclosure, the method of manufacturing the encapsulation structure further includes forming a cavity in the insulating body. The depth of the cavity is less than the depth of each of the openings, and the die and the encapsulant are formed within the cavity.

[0104] The features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] Figures 1A to 1E are schematic cross-sectional views illustrating the manufacturing process of a carrier board according to some embodiments of the present disclosure. Figures 2A to 2E are schematic cross-sectional views illustrating the manufacturing process of a carrier board according to some alternative embodiments of the present disclosure. Figures 3A to 3G are schematic cross-sectional views illustrating the manufacturing process of a package structure according to some embodiments of the present disclosure. Figures 4A to 4G are schematic cross-sectional views illustrating the manufacturing process of a package structure according to some alternative embodiments of the present disclosure. Figure 5 is a schematic cross-sectional view illustrating a package structure according to some alternative embodiments of the present disclosure. Figures 6A to 6E are schematic cross-sectional views illustrating the manufacturing process of a carrier board according to some alternative embodiments of the present disclosure. Figures 7A to 7D are schematic cross-sectional views illustrating various methods of placing a carrier board through a via (TCV) in the opening of the insulating body shown in Figure 6B. Figures 8A to 8E are schematic cross-sectional views illustrating the manufacturing process of a carrier board according to some alternative embodiments of the present disclosure. Figure 9 is a schematic cross-sectional view illustrating a package structure according to some alternative embodiments of the present disclosure. Figure 10 is a schematic cross-sectional view of a package structure according to some alternative embodiments of the present disclosure. Figure 11 is a schematic cross-sectional view of a package structure according to some alternative embodiments of the present disclosure. Figures 12A to 12E are schematic cross-sectional views of a carrier board manufacturing process according to some alternative embodiments of the present disclosure. Figures 13A to 13F are schematic cross-sectional views of a package structure manufacturing process according to some alternative embodiments of the present disclosure. Figure 14 is a schematic cross-sectional view of a package structure according to some alternative embodiments of the present disclosure. Figure 15 is a schematic cross-sectional view of a probe card according to some alternative embodiments of the present disclosure.

Claims

1. A packaging structure, comprising: A carrier plate having a first surface and a second surface opposite to the first surface, wherein the carrier plate includes an insulating body and carrier plate perforations embedded in the insulating body; A grain is disposed on the first surface of the carrier plate, wherein the grain has an active surface and a rear surface opposite to the active surface, the grain has conductive pillars formed on the active surface, the active surface faces away from the insulating body, and the grain is electrically connected to the carrier plate through a hole. And a first wiring structure is disposed on the second surface of the carrier board.

2. The encapsulation structure as described in claim 1, further comprising: Encapsulation body, which laterally encapsulates the grain; And a second wiring structure, located on the encapsulation and the die.

3. The packaging structure as claimed in claim 2, wherein the insulating body has a cavity, the die and the encapsulation are located within the cavity, and the die is electrically connected to the carrier board via a second rewiring structure.

4. A packaging structure, comprising: A carrier board, comprising an insulating body and carrier board perforations partially located in the insulating body, wherein the height of each carrier board perforation is greater than the thickness of the insulating body; a die disposed on the carrier board, wherein the die has an active surface and a rear surface opposite to the active surface, the die has conductive pillars formed on the active surface, and the active surface faces away from the insulating body; and a redistribution structure disposed on at least one side of the carrier board.

5. The packaging structure as claimed in claim 4, wherein the carrier plate further includes a filler pattern sandwiched between each of the carrier plate through-holes and the insulating body.

6. A method for manufacturing a packaging structure, comprising: A carrier board having a first surface and a second surface opposite to the first surface is provided, comprising: providing an insulating body having an opening therein; and forming a carrier board through-hole in the opening; placing a die on the first surface of the carrier board, wherein the die has an active surface and a rear surface opposite to the active surface, the die having conductive pillars formed on the active surface, and the active surface facing away from the insulating body; laterally encapsulating the die using an encapsulator; and forming a redistribution structure on the second surface of the carrier board.

7. A packaging structure, comprising: A carrier plate, including carrier plate perforations; a die disposed on the carrier plate, wherein the die has a semiconductor substrate and conductive pillars disposed on the semiconductor substrate, and the conductive pillars face away from the carrier plate; and an encapsulator, which laterally encapsulates the die.

8. The packaging structure as claimed in claim 7 further includes an insulating layer through-hole disposed next to the die, wherein the insulating layer through-hole penetrates the encapsulation.

9. A packaging structure, comprising: A carrier board includes an insulating body and carrier board perforations protruding from the insulating body, wherein the height of each carrier board perforation is greater than the thickness of the insulating body; a die disposed on the carrier board, wherein the die has an active surface facing away from the insulating body and the die has conductive pillars formed on the active surface; and a redistribution structure disposed on at least one side of the carrier board.

10. A method for manufacturing a packaging structure, comprising: A carrier board is provided, comprising: providing an insulating body having an opening therein; and forming a carrier board through-hole in the opening; placing a die on the carrier board, wherein the die has a semiconductor substrate and conductive pillars disposed on the semiconductor substrate, and the semiconductor substrate is located between the conductive pillars and a portion of the insulating body; and forming a redistribution structure on the carrier board relative to the die side.

Images