Methods for forming sacrificial capping layer for gate protection

Abstract

A method includes providing a substrate comprising a plurality of metal gate stacks and a plurality of source / drain contact regions alternately arranged along one surface of the substrate, and having a dielectric spacer separating each source / drain contact region from an adjacent metal gate stack. Each source / drain contact region is recessed in an opening between adjacent metal gate stacks such that the source / drain contact region provides a bottom of the recess, and the dielectric spacer provides a plurality of sidewalls. An etch stop layer is formed on the substrate such that the etch stop layer conformally covers the plurality of metal gate stacks, the plurality of sidewalls of each recess, and the bottom, and a sacrificial layer is formed over each metal gate stack and on at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source / drain contact region, and then the sacrificial layer is removed from each metal gate stack and the sidewall of each recess.

Description

Technical Field

[0001] This invention relates generally to the manufacture of semiconductor devices, and more particularly to a method for forming a sacrificial capping layer for gate protection. [Related Applications]

[0002] This disclosure asserts priority to U.S. Provisional Patent Application No. 63 / 179,098, filed April 23, 2021, the entire contents of which are incorporated herein by reference. Prior Technology

[0003] Advances in semiconductor technology rely on continuous improvements in manufacturing processes. Innovations in semiconductor technology have led to the introduction of new types of structures, such as FinFET devices and stacked structures (e.g., 3D NAND devices). However, these new structures also introduce the need for new manufacturing solutions to overcome existing detrimental manufacturing challenges. The inventors recognize that one such challenge arises from damage to the overlay layers and corrosion of spacers on the gate sidewalls caused by semiconductor plasma processing techniques. For example, dry etching processes, such as reactive ion etching (RIE), can be used to open contacts in conventional mid-stage (MOL) processes. Typically, dry etching processes can be very aggressive to certain layers in semiconductor processes. A typical dry etching process includes a plasma source that generates an ion sea, which is accelerated by ion bombardment of sensitive device layers. As a result, this plasma etching process can cause damage to the underlying material, especially when opening high aspect ratio contact holes. This damage to the underlying material can then lead to uncontrolled variations in device electrical performance and yield losses. Summary of the Invention

[0004] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices.

[0005] A method is provided, comprising providing a substrate including a plurality of metal gate stacks and a plurality of source / drain contact regions alternately arranged along one surface of the substrate, and having a dielectric spacer separating each source / drain contact region from an adjacent metal gate stack. Each source / drain contact region is recessed in an opening between adjacent metal gate stacks such that the source / drain contact region provides a bottom of the recess, and the dielectric spacer provides a plurality of sidewalls of the recess. An etch stop layer is formed on the substrate such that the etch stop layer conformally covers the plurality of metal gate stacks, the plurality of sidewalls of each recess, and the bottom of each recess, and a sacrificial layer is formed over each metal gate stack and on at least a portion of each sidewall of each recess. The etch stop layer is removed from the bottom of each recess to expose the source / drain contact region, and then the sacrificial layer is removed from each metal gate stack and the sidewall of each recess.

[0006] The state (2) includes a method of the state (1), wherein the step of forming the sacrificial layer includes forming the sacrificial layer having a first thickness on top of each metal gate stack and a second thickness on the sidewall of each recess, the first thickness being greater than the second thickness.

[0007] The state (3) includes the method of the state (1), wherein the step of forming the sacrificial layer includes forming the sacrificial layer on each sidewall such that the thickness of the sacrificial layer decreases from the upper part of the recess to the bottom of the recess.

[0008] The state (4) includes a method of the state (1), wherein the step of forming the sacrificial layer includes preferentially forming the sacrificial layer on top of each metal gate stack relative to the sidewall of each recess.

[0009] The method of the state sample (5) includes the state sample (4), wherein the step of preferentially forming the sacrificial layer includes performing an atomic layer deposition (ALD) process under process conditions that reduce the diffusion of reactant gases into the depression.

[0010] The process conditions (6) include at least one of the following: the concentration of the reactant gas, the gas exposure time, the substrate temperature, and the substrate rotation speed.

[0011] The method of the state sample (7) comprising the state sample (4) wherein the step of preferentially forming the sacrificial layer comprises rotating the substrate while exposing the substrate to a gas to form the sacrificial layer.

[0012] The state (8) includes a method of the state (7), which further includes setting a rotation speed of the substrate to provide a predetermined preferential deposition of the sacrificial layer on top of each metal gate stack.

[0013] The method of the state (9) comprising the state (1) wherein the step of forming the etch stop layer comprises forming a layer comprising silicon nitride, silicon oxide or silicon oxynitride.

[0014] The state sample (10) includes a method of the state sample (1), wherein the step of forming the sacrificial layer includes forming a layer comprising a metal oxide (MO X), a metal nitride (MN X) or a metal oxynitride.

[0015] The method of the state (11) comprising the state (4) wherein the step of preferentially forming the sacrificial layer comprises forming a sacrificial capping layer having a thickness ranging from 0.5 nm to about 10 nm on the top of each metal gate stack.

[0016] The state (12) includes a method of the state (11), wherein the step of preferentially forming the sacrificial layer includes forming a sacrificial capping layer having a thickness ranging from 2 nm to about 5 nm on the top of each metal gate stack.

[0017] Another embodiment (13) provides a method comprising providing a substrate including a source / drain contact region, an alternative metal gate stack, a spacer on a sidewall of the alternative metal gate stack, and an etch stop layer on the spacer. A sacrificial capping layer is formed over the alternative metal gate stack, the sacrificial capping layer having a first thickness on top of the alternative metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness. The etch stop layer and the sacrificial capping layer are removed using a plasma etching process.

[0018] A method of comprising a state (13) in which the etch stop layer comprises a silicon nitride, a silicon oxide, or a silicon oxynitride.

[0019] The method of comprising state (13) in state (15), wherein the sacrificial capping layer comprises a metal oxide (MO X), a metal nitride (MN X) or a metal oxynitride.

[0020] The method of comprising state (13) in state (16), wherein the sacrificial capping layer comprises AlN, TiN or TiO X.

[0021] The method of the state (17) comprising the state (13) wherein the substrate is rotated during the formation of the sacrificial capping layer.

[0022] The state (18) includes a method of the state (13), wherein the step of removing the sacrificial cover layer includes using a wet etching chemical.

[0023] Another embodiment (19) provides a method comprising providing a substrate including a source / drain contact region, an alternative metal gate (RMG) stack, a low-k spacer on one sidewall of the RMG stack, and an etch stop layer on the spacer. A sacrificial capping layer comprising TiO2 is formed on the RMG stack, the sacrificial capping layer having a first thickness on top of the RMG stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness. The etch stop layer is removed using a plasma etching process, and the sacrificial capping layer is removed using a wet etching chemical.

[0024] The method of comprising state (20) including state (19) wherein the step of forming the sacrificial capping layer comprises preferentially depositing titanium tetrakis (dimethylamido) titanium (TDMAT) and ozone (O3) sequentially exposed to a process pressure of about 1 Torr to about 3 Torr and a substrate temperature of about 100°C to about 150°C and a substrate rotation speed of about 10 RPM to about 50 RPM by atomic layer deposition (ALD) on the top of each RMG stack.

[0025] It should be noted that the Summary Statement does not specify every embodiment and / or additional novel aspects of the invention within the scope of this disclosure or the claims. Instead, the Summary Statement provides only a preliminary discussion of different embodiments and corresponding key points of novelty relative to the prior art. For additional details and / or possible perspectives regarding the Summary Statement and embodiments, the reader can refer to the "Description" section and the corresponding illustrations in the Summary Statement, as further discussed below. Simple Explanation of the Diagram

[0026] The various aspects of this disclosure can be best understood from the following detailed embodiments when read in conjunction with the accompanying drawings. It is worth noting that, according to industry standard embodiments, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased for clarity of discussion.

[0027] According to an exemplary embodiment of the present disclosure, FIG1A shows a partial cross-sectional fin view of a semiconductor device along the fin direction during manufacturing; FIG1B shows a cross-sectional gate view of the semiconductor device along a direction orthogonal to the fin direction; FIG1C shows a top view of the semiconductor in an exemplary embodiment of the present disclosure.

[0028] Figures 2A-2B respectively illustrate cross-sectional fin and gate views of a semiconductor device during a subsequent stage of manufacturing in an exemplary embodiment according to the present disclosure;

[0029] Figures 3A-3B respectively illustrate cross-sectional fin and gate views of a semiconductor device during a subsequent stage of manufacturing in an exemplary embodiment according to the present disclosure;

[0030] Figures 4A-4B respectively illustrate cross-sectional fin and gate views of a semiconductor device during a subsequent stage of manufacturing in an exemplary embodiment according to this disclosure;

[0031] Figures 5A-5B respectively illustrate cross-sectional fin and gate views of a semiconductor device during a subsequent stage of manufacturing in an exemplary embodiment according to the present disclosure;

[0032] Figures 6A-6B respectively illustrate cross-sectional fin and gate views of a semiconductor device during a subsequent stage of manufacturing in an exemplary embodiment according to the present disclosure;

[0033] Figures 7A-7B respectively illustrate cross-sectional fin and gate views of a semiconductor device during a subsequent stage of manufacturing in an exemplary embodiment according to this disclosure; and

[0034] Figures 8A-8B show partial cross-sectional views of a semiconductor device 100 during the next manufacturing stage after the removal of the sacrificial cover layer 110, according to an exemplary embodiment of the present disclosure. Implementation

[0035] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely exemplary and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various examples. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments and / or configurations discussed. Additionally, for ease of description, spatially relative terms such as "top," "bottom," "below," "under," "lower," "above," and "above" may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0036] This application discloses a method for preventing damage to semiconductor regions during plasma etching. The proposed integration method involves forming a sacrificial capping layer directly on top of the semiconductor region to be protected. This sacrificial capping layer is designed to protect the semiconductor region during the plasma etching process, which would otherwise damage the semiconductor region. This sacrificial capping layer can be removed later in the process using a gentle wet cleaning process.

[0037] The embodiments of this application can be applied to various types of devices, such as finned transistors and stacked memory devices. Specific embodiments of the above-described process will be described below using Figures 1-8.

[0038] Figure 1A shows a partial cross-sectional view of a semiconductor device during manufacturing along the fin direction, and Figure 1B shows a cross-sectional view of the semiconductor device along a direction orthogonal to the fin direction. Figure 1C shows a top view of cut lines 1A-1A shown in Figure 1A and cut lines 1B-1B shown in Figure 1B, all of which are embodiments of the present invention. Figure 1A is a partial cross-sectional view and does not show the underlying fins and substrate.

[0039] As shown in Figures 1A-1C, at this stage of the process, the semiconductor device 100 has undergone most of the front-end process (FEOL) manufacturing. For example, as shown in Figure 1B, a transistor structure with a plurality of fins 109 is formed on a substrate 111.

[0040] In various embodiments, substrate 111 may comprise silicon, silicon germanide, silicon carbide, and compound semiconductors such as gallium nitride, gallium arsenide, indium arsenide, and indium phosphide. Substrate 111 may comprise a semiconductor wafer, which may include a semiconductor epitaxial layer having a heteroepitaxial layer. For example, in one or more embodiments, one or more heteroepitaxial layers comprising compound semiconductors may be formed over the semiconductor substrate. In various embodiments, a portion or all of substrate 111 may be amorphous, polycrystalline, or monocrystalline. In various embodiments, substrate 111 may be doped, undoped, or comprise regions of both doped and undoped materials.

[0041] A plurality of fins 109 can be formed by epitaxial growth from substrate 111, or by using an etch-back process, thereby leaving a plurality of fins 109. The plurality of fins 109 can be isolated from each other by shallow isolation regions 112. Therefore, the shallow isolation regions 112 and the plurality of fins 109 can form an alternating pattern.

[0042] In one embodiment, the shallow isolation region 112 can be formed by depositing an oxide filler material after patterning the plurality of fins 109, and then planarizing it, for example, using a chemical mechanical planarization process. After planarization, the shallow isolation region 112 may sink to make the plurality of fins 109 protrude.

[0043] A plurality of virtual gates 102 are formed on the substrate 111 and the plurality of fins 109. In one embodiment, the plurality of virtual gates 102 can be formed by patterning an amorphous silicon or polycrystalline silicon layer deposited over the plurality of fins 109.

[0044] Next, a plurality of spacers 101 are formed on the sidewalls of the plurality of dummy gates 102. The plurality of spacers 101 can be formed by depositing an insulating layer followed by an anisotropic etching process. For example, a reactive ion etching (RIE) process can be used to form the spacers 101. The material of the insulating layer is selected so that it is selectively not etched during the removal of the plurality of dummy gates 102 in a later process, for example, not etched by chemicals such as TMAH or NH4OH. In one example, the spacers 101 may contain a low-k material.

[0045] Next, epitaxial regions 103 are grown above a plurality of fins 109 located between a plurality of virtual gates 102 to form raised source / drain regions. Due to the growth pattern of the corresponding epitaxial material, the upper surface of the raised source / drain regions can form a faceted surface.

[0046] In one or more embodiments, the epitaxial region 103 can be formed in a single epitaxial growth process. In other embodiments, the growth of the epitaxial region 103 can involve a multi-stage process. For example, it can begin by growing an initial epitaxial layer to a predetermined thickness on a plurality of fins 109 with a first dopant, followed by growing a second layer with a second dopant. For example, the second dopant can be higher than the first dopant. Similarly, different layers can have different compositions, such as germanium or other compounds. The epitaxial growth process can use any type of epitaxial process, including molecular beam epitaxy (MBE) or various types of chemical vapor deposition (CVD).

[0047] In one or more embodiments, for example due to lattice mismatch, epitaxial regions 103 may be grown to introduce strain into a plurality of fins 109.

[0048] In one or more embodiments, the source / drain (S / D) region can be formed by, for example, implantation / annealing process doping of fins and regions of epitaxial region 103.

[0049] Figures 2A-2B show cross-sectional views of the semiconductor device 100 during subsequent stages of manufacturing after the etch stop layer (ESL) 105 has been formed over the semiconductor device 100. Figure 2A shows a cut line similar to that in Figure 1A, and Figure 2B shows a cut line similar to that in Figure 1B.

[0050] ESL 105 can be conformally deposited across the entire wafer surface. In various embodiments, ESL 105 comprises silicon nitride, silicon oxide, or silicon oxynitride. In various embodiments, ESL 105 can have a thickness ranging from 0.5 nm to about 10 nm. In one embodiment, ESL 105 can have a thickness ranging from 2 nm to about 5 nm.

[0051] Figures 3A-3B show partial cross-sectional views of a semiconductor device 100 during fabrication after the deposition of oxide 106 according to one embodiment of the present invention. Figure 3A shows a cut line similar to that in Figure 1A, and Figure 3B shows a cut line similar to that in Figure 1B.

[0052] Referring to Figures 3A and 3B, oxide 106 is filled between a plurality of dummy gates 102. Oxide 106 is overfilled above the top surface of ESL 105 and above the plurality of dummy gates 102.

[0053] In various embodiments of the semiconductor device 100, oxide 106 may be a flowable oxide comprising spin-coated glass. In one example, a layer comprising borosilicate glass (BPSG), phosphosilicone glass (PSG), borosilicate glass (BSG), arsenic silicate glass (ArSG), or other glass types may be deposited and heated to reflow. In one or more embodiments, oxide 106 may also comprise, for example, an oxide of tetraethoxysilane (TEOS), fluorinated TEOS (FTEOS), organosilicon glass (OSG), fluorosilicone glass (FSG), or spin-coated glass (SOG).

[0054] According to one embodiment of the present invention, Figures 4A-4B show cross-sectional views of a semiconductor device 100 during manufacturing after the formation of a replacement metal gate (RMG). Figure 4A shows a cut line similar to that in Figure 1A, while Figure 4B shows a cut line similar to that in Figure 1B.

[0055] As shown in Figures 4A and 4B, the oxide 106 is planarized to expose the underlying ESL 105. The ESL 105 can be removed using an anisotropic etching process to expose a plurality of dummy gates 102. The plurality of dummy gates 102 are then removed, for example, using a wet etching process or a plasma process. During the removal of the plurality of dummy gates 102, the spacer 101 maintains the shape of the gate stack. During the etching process, the oxide 106 protects the area beneath the epitaxial region 103.

[0056] After removing the plurality of dummy gates 102, the inner walls of the plurality of spacers 101 are exposed, leaving cavities. These cavities are filled with replacement gate material 107. After the replacement gate material 107 is in place, a contact cover 108 is formed. The contact cover 108 can be formed using a self-aligning process, thereby selectively forming the contact cover 108 only above the replacement gate material 107.

[0057] The replacement gate material 107, together with the contact cap 108, forms a replacement metal gate (RMG) stack 102'. The RMG stack 102' helps to set the work function of the gate and form the final gate electrode of the semiconductor device 100.

[0058] Figures 5A-5B show partial cross-sectional views of a semiconductor device 100 during the next stage of manufacturing after the removal of oxide 106 according to one embodiment of the present invention. Figure 5A shows a cut line similar to that in Figure 1A, while Figure 5B shows a cut line similar to that in Figure 1B.

[0059] As shown in Figure 5A, etching oxide 106 leaves empty, unfilled trenches or recessed features. In various embodiments, the oxide etching process can be a wet etching process or a dry etching process, such as reactive ion etching (RIE) or any process currently known in the semiconductor manufacturing industry. Etching oxide 106 exposes ESL 105 left between a plurality of spacers 101, which serve as liner for replacement gate material 107 and contact caps 108.

[0060] Figures 6A-6B show partial cross-sectional views of a semiconductor device 100 during the next manufacturing stage after the deposition of the sacrificial capping layer 110, according to an embodiment of the present invention. Figure 6A illustrates a cut line similar to that in Figure 1A, while Figure 6B illustrates a cut line similar to that in Figure 1B.

[0061] The sacrificial capping layer 110 can be preferentially deposited on top of the RMG stack 102', which includes a contact cap 108 and an alternative gate material 107. As schematically shown in Figures 6A-6B, the thickness of the sacrificial capping layer 110 on the contact cap 108 can be greater than the thickness on the ESL 105 on the spacer 101, and the thickness of the sacrificial capping layer 110 on the ESL 105 on the spacer 101 can decrease from the upper part of the spacer 101 to the lower part of the spacer 101. In various embodiments, the sacrificial capping layer 110 can include metal oxides (MO x), metal nitrides (MN x), and metal oxynitrides, such as AlO x, AlN, TiN, TiO x, etc., where "M" represents an elemental metal such as aluminum, titanium, tantalum, etc.

[0062] In various embodiments, the sacrificial capping layer 110 on top of the contact cap 108 may have a thickness ranging from 0.5 nm to about 10 nm. In one embodiment, the sacrificial capping layer 110 may have a thickness ranging from 2 nm to about 5 nm.

[0063] In one embodiment of the semiconductor device 100, the sacrificial capping layer 110 is formed using a vapor deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) such as metal-organic CVD (MOCVD), and other such processes.

[0064] In one embodiment, the preferential deposition of the sacrificial capping layer 110 on top of the RMG stack 102' can be achieved using an ALD process, under process conditions that reduce the diffusion of reactant gases into the trenches or recesses between the plurality of RMG stacks 102'. Process conditions may include reactant gas concentration, gas exposure time, substrate temperature, and substrate rotation speed. In one example, the substrate can be rotated during gas exposure, and the rotation speed optimized to achieve the desired preferential deposition. In some examples, higher rotation speeds can result in increased preferential deposition on top of the RMG stack 102'. Therefore, the shape of the sacrificial capping layer 110 is adjustable, and the sacrificial capping layer 110 can have a first thickness on top of the replacement metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness.

[0065] In one example, a sacrificial capping layer 110 containing TiO2 can be preferentially deposited on top of the RMG stack 102' by using sequential exposure to tetrakis(dimethylamido)titanium (TMDAT) and ozone (O3) at a process pressure between about 1 Torr and about 3 Torr, a substrate temperature between about 100°C and about 150°C, and a rotation speed between about 10 RPM and about 50 RPM.

[0066] Figures 7A-7B show partial cross-sectional views of a semiconductor device 100 during the next manufacturing stage after an ESL etching process, according to an embodiment of the present invention. Figure 7A illustrates a cut line similar to that in Figure 1A, while Figure 7B illustrates a cut line similar to that in Figure 1B.

[0067] The ESL etching process removes the remaining ESL 105 on the plurality of spacers 101, which serve as liner for the replacement gate material 107 and contact cap 108. In various embodiments, the remaining ESL 105 is removed using a plasma process, such as reactive ion etching (RIE). The RIE process has poor etch selectivity for the contact cap 108 and spacers 101, while the sacrificial capping layer 110 protects the contact cap 108 and the underlying plurality of spacers 101 from plasma damage during the highly anisotropic RIE process.

[0068] Figures 8A-8B show partial cross-sectional views of a semiconductor device 100 during the next stage of manufacturing after the removal of the sacrificial capping layer 110, according to one embodiment of the present invention. Figure 8A shows a cut line similar to that in Figure 1A, while Figure 8B shows a cut line similar to that in Figure 1B.

[0069] The removal of the sacrificial capping layer 110 can be performed by an etching process, such as wet etching, which is effective and does not damage the contact cap 108, the plurality of spacers 101, and the epitaxial region 103. In one example, wet etching may involve a sulfur peroxide mixture (SPM) between about 70ºC and about 110ºC.

[0070] In the foregoing description, specific details, such as the particular geometry of the processing system and the description of the various components and processes used therein, have been set forth. However, it should be understood that the techniques described herein can be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been presented for illustrative purposes to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional structure are denoted by the same reference numerals, and therefore any redundant description may be omitted.

[0071] Various techniques have been described as multiple discrete operations to aid in understanding the various embodiments. The order of the description should not be interpreted as implying that these operations must be sequential. In fact, these operations need not be performed in the order shown. The described operations may be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0072] As used herein, "substrate" or "wafer" generally refers to an object processed according to the present invention. The substrate may contain material portions or structures of a device, particularly a semiconductor or other electronic device, and may be, for example, a semiconductor wafer, a trace, or a substrate structure consisting of a layer or overlay (e.g., a thin film) on a substrate. Therefore, the substrate is not limited to any particular substrate structure, underlying layer or overlay, patterned or unpatterned, but is contemplated to include any such layer or substrate structure and any combination of layers and / or substrate structures. This description may refer to specific types of substrates, but such references are for illustrative purposes only.

[0073] Those skilled in the art will also understand that many variations can be made to the operation of the above-described techniques while still achieving the same objectives of the present invention. Such variations are intended to be covered by the scope of this disclosure. Therefore, the foregoing description of embodiments of the present invention is not intended to be limiting. Rather, any limitation on embodiments of the present invention is set forth in the following claims.

[0074] 100: Semiconductor devices 101: Spacer 102: Virtual Gate 102': Replacement Metal Gate (RMG) Stack 103: Epitaxial region 105: Etching Stop Layer (ESL) 106: Oxides 107: Alternative gate materials 108: Contact Cover 109: Fins 110: Sacrifice Overlay 111:Substrate 112: Shallow isolation area

Claims

1. A method of forming a sacrificial layer for gate protection, the method comprising: providing a substrate, the substrate including a plurality of metal gate stacks and a plurality of source / drain contact regions alternately arranged along one surface of the substrate, and having a dielectric spacer separating each source / drain contact region from an adjacent metal gate stack, wherein each source / drain contact region is recessed in an opening between adjacent metal gate stacks such that the source / drain contact region provides a bottom of the recess, and the dielectric spacer provides a plurality of sidewalls of the recess; forming an etch stop layer on the substrate such that the etch stop layer conformally covers the plurality of metal gate stacks, the plurality of sidewalls of each recess, and the bottom of each recess; forming a sacrificial layer over each metal gate stack and on at least a portion of each sidewall of each recess; The etch stop layer is removed from the bottom of each recess, and the sacrificial layer is left on at least a portion of each sidewall of each recess to expose the source / drain contact area; and the sacrificial layer is removed from each metal gate stack and the sidewall of each recess using a wet etching chemical.

2. The method of forming a sacrificial layer for gate protection as claimed in claim 1, wherein the step of forming the sacrificial layer includes forming the sacrificial layer having a first thickness on top of each metal gate stack and a second thickness on the sidewall of each recess, the first thickness being greater than the second thickness.

3. The method for forming a gate protection sacrificial layer as claimed in claim 1, wherein the step of forming the sacrificial layer includes forming the sacrificial layer on each sidewall such that the thickness of the sacrificial layer decreases from the upper part of the recess to the bottom of the recess.

4. The method of forming a sacrificial layer for gate protection as claimed in claim 1, wherein the step of forming the sacrificial layer includes preferentially forming the sacrificial layer on top of each metal gate stack relative to the sidewall of each recess.

5. The method for forming a gate protection sacrificial layer as claimed in claim 4, wherein the step of preferentially forming the sacrificial layer includes performing an atomic layer deposition (ALD) process under process conditions that reduce the diffusion of reactant gases into the depression.

6. The method for forming a gate protection sacrificial layer as claimed in claim 5, wherein the process conditions include at least one of the following: the concentration of the reactant gas, the gas exposure time, the substrate temperature, and the substrate rotation speed.

7. The method for forming a gate protection sacrificial layer as claimed in claim 4, wherein the step of preferentially forming the sacrificial layer includes rotating the substrate while exposing it to a gas to form the sacrificial layer.

8. The method of forming a gate protection sacrificial layer as claimed in claim 7, further comprising setting a rotational speed of the substrate to provide a predetermined preferential deposition of the sacrificial layer on top of each metal gate stack.

9. The method for forming a gate protection sacrificial layer as claimed in claim 1, wherein the step of forming the etch stop layer comprises forming a layer comprising silicon nitride, silicon oxide, or silicon oxynitride.

10. The method for forming a sacrificial layer for gate protection as claimed in claim 1, wherein the step of forming the sacrificial layer comprises forming a layer comprising a metal oxide (MOX), a metal nitride (MNX), or a metal oxynitride.

11. The method of forming a sacrificial layer for gate protection as claimed in claim 4, wherein the step of preferentially forming the sacrificial layer comprises forming a sacrificial capping layer having a thickness ranging from 0.5 nm to about 10 nm on the top of each metal gate stack.

12. The method of forming a sacrificial layer for gate protection as claimed in claim 11, wherein the step of preferentially forming the sacrificial layer comprises forming a sacrificial capping layer having a thickness ranging from 2 nm to about 5 nm on the top of each metal gate stack.

13. A method of forming a sacrificial capping layer for gate protection, the method comprising: providing a substrate including a source / drain contact region, an alternative metal gate stack, a spacer on a sidewall of the alternative metal gate stack, and an etch stop layer on the spacer; forming a sacrificial capping layer over the alternative metal gate stack, the sacrificial capping layer having a first thickness on top of the alternative metal gate stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness, the sacrificial capping layer being formed only on a portion of the alternative metal gate stack to expose an exposed portion of the etch stop layer; removing the exposed portion of the etch stop layer using a plasma etching process, while simultaneously leaving the sacrificial capping layer on the etch stop layer; and removing the sacrificial capping layer using a wet etching chemical.

14. The method of forming a sacrificial capping layer for gate protection as claimed in claim 13, wherein the etch stop layer comprises silicon nitride, silicon oxide, or silicon oxynitride.

15. The method of forming a sacrificial capping layer for gate protection as claimed in claim 13, wherein the sacrificial capping layer comprises a metal oxide (MOX), a metal nitride (MNX), or a metal oxynitride.

16. The method of forming a sacrificial capping layer for gate protection as described in claim 13, wherein the sacrificial capping layer comprises AlN, TiN, or TiOX.

17. The method for forming a sacrificial capping layer for gate protection as claimed in claim 13, wherein the substrate is rotated during the formation of the sacrificial capping layer.

18. A method of forming a sacrificial capping layer for gate protection, the method comprising: providing a substrate including a source / drain contact region, an alternative metal gate (RMG) stack, a low-k spacer located on a sidewall of the RMG stack, and an etch stop layer located on the spacer; forming a sacrificial capping layer comprising TiO2 on the RMG stack, the sacrificial capping layer having a first thickness on top of the RMG stack and a second thickness on the etch stop layer, the first thickness being greater than the second thickness, the sacrificial capping layer being formed only on a portion of the RMG stack to expose an exposed portion of the etch stop layer; removing the exposed portion of the etch stop layer using a plasma etching process, while simultaneously leaving the sacrificial capping layer on the etch stop layer; and removing the sacrificial capping layer using a wet etching chemical.

19. The method of forming a gate protection sacrificial capping layer as claimed in claim 18, wherein the step of forming the sacrificial capping layer comprises preferentially depositing titanium tetrakis (dimethylamido) titanium (TDMAT) and ozone (O3) sequentially exposed to a process pressure of about 1 Torr to about 3 Torr, a substrate temperature of about 100°C to about 150°C, and a substrate rotation speed of about 10 RPM to about 50 RPM by atomic layer deposition (ALD) on the top of each RMG stack.

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