Method of forming a metal liner for interconnect structures

Abstract

A method of forming a component includes forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal pad on the barrier layer. The SAM is removed after selectively depositing the metal pad on the barrier layer.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to a method for forming metal pads for interconnect structures. More specifically, the embodiments of this disclosure relate to a method for selectively depositing metal pad layers. Prior Technology

[0002] As transistors and interconnects are scaled up to 3 nm nodes and beyond, several challenges hinder improvements in power and performance. Interconnects consist of metal lines that carry current within the same element layer and metal dielectric windows that carry current between layers. Reducing the spacing narrows both the width and increases resistance, as well as the voltage drop across the circuit, thereby affecting circuit speed and increasing power consumption.

[0003] While transistor performance increases with scaling, the situation differs for interconnect metals. Due to size reduction, interconnect window resistance can increase tenfold. This increase in interconnect window resistance leads to resistive-capacitive (RC) delay, consequently reducing performance and increasing power consumption. Conventional copper interconnect structures include a barrier layer deposited on the gap sidewalls. This barrier layer provides the interposer window with sidewalls made of dielectric material, providing good adhesion and preventing copper diffusion into the dielectric layer, as well as preventing other unfavorable interactions between the dielectric layer and the metal pads deposited on the barrier layer. The metal pads deposited on the barrier layer adhere to the barrier layer, facilitating subsequent copper (Cu) filling in the gaps between the sidewalls. Copper is deposited in the remaining volume of the gaps. Due to its high resistivity, the barrier layer typically contributes the most to the interposer window resistance. Previous approaches have primarily focused on reducing the thickness of the barrier layer or seeking barrier layers with lower resistivity to reduce the interposer window resistance. Increased inter-window resistance remains a problem, especially in smaller features where the percentage of barrier layers on the sidewalls within the inter-window volume increases. Therefore, a method for depositing metallic layers is needed that improves interconnect performance, for example, by reducing inter-window resistance. Summary of the Invention

[0004] The embodiments of this disclosure relate to a method for forming microelectronic components. In one or more embodiments, the method includes: forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap including sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the SAM; selectively depositing metal pads on the barrier layer on the sidewalls, the thickness of the metal pads deposited on the sidewalls being greater than the thickness of the metal pads deposited on the bottom; removing the SAM after selectively depositing the metal pads on the barrier layer; and performing a gap-filling process on the metal pads. Simple Explanation of the Diagram

[0005] To understand in detail the above-described features of the invention, the invention briefly outlined above can be described more specifically with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the invention and should therefore not be considered as limiting the scope of the invention, as other equivalent embodiments are permissible under this disclosure.

[0006] Figure 1A illustrates a portion of a microelectronic component during the manufacturing stage of one or more embodiments of this disclosure, wherein a passivation layer is formed on the bottom of the gap;

[0007] Figure 1B illustrates the barrier layer formed after the passivation layer shown in Figure 1A is formed;

[0008] Figure 1C illustrates the padding layer formed on the barrier layer formed in Figure 1B;

[0009] Figure 1D illustrates the second liner layer formed on the liner layer formed in Figure 1C;

[0010] Figure 1E illustrates the removal of the passivation layer formed in Figure 1A after the second liner layer in Figure 1D is formed;

[0011] Figure 2A illustrates a portion of a microelectronic component during the manufacturing stage of one or more embodiments of this disclosure, having a first passivation layer formed on the bottom of a gap according to one or more embodiments of this disclosure;

[0012] Figure 2B illustrates the barrier layer formed over the gap in Figure 2A;

[0013] Figure 2C illustrates the removal of the passivation layer formed in Figure 2A.

[0014] Figure 2D illustrates the second passivation layer formed on the barrier layer formed in Figure 2B.

[0015] Figure 2E illustrates the padding layer on the barrier layer formed in Figure 2B;

[0016] Figure 2F illustrates the second cushioning layer formed on the cushioning layer formed in Figure 2E;

[0017] Figure 2G illustrates the structure of Figure 2F after the second passivation layer has been removed.

[0018] Figure 3 illustrates a process flow diagram of a method for manufacturing a microelectronic component according to one or more embodiments of this disclosure; and

[0019] Figure 4 illustrates a process flow diagram of a method for manufacturing a microelectronic component according to one or more embodiments of this disclosure. Implementation

[0020] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure may include other embodiments and may be practiced or performed in various ways.

[0021] The terms "substrate" and "wafer" used in this specification and the accompanying claims are used interchangeably and both refer to the surface or a portion thereof on which a process can be performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may also refer only to a portion of the substrate. Furthermore, reference to deposition on a substrate may mean a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0022] As used herein, "substrate" refers to any substrate on which a film treatment is performed during a manufacturing process, or the surface of a material formed on a substrate. For example, substrate surfaces on which treatments are performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and other metallic materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation (or otherwise generating or grafting target chemical moieties to impart chemical functionality), annealing, and / or baking of the substrate surface. In addition to directly treating the film on the substrate's own surface, any of the film treatment steps disclosed in this disclosure may also be performed on a substrate layer formed on the substrate, as further detailed below, and the term "substrate surface" is intended to include this substrate layer as indicated by the context. Thus, for example, when a film / layer or part of a film / layer has already been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. The composition of a given substrate surface will depend on the film to be deposited and the specific chemicals used.

[0023] The terms "reactive gas," "precursor," "reactant," and the like are used interchangeably in this specification and the accompanying claims to mean a gas containing species capable of reacting with the substrate surface. For example, a first "reactive gas" may simply be adsorbed onto the surface of the substrate and may undergo further chemical reaction with a second reactive gas.

[0024] Some embodiments of this disclosure provide methods for improving interconnect performance. The interconnect includes metal traces that carry current in the same element layer and metal dielectric windows that carry current between layers. These traces and dielectric windows are formed in gaps formed in the element using a conductive metal such as copper or cobalt. In one or more embodiments, the dielectric layer includes at least one feature that defines a gap including sidewalls and a bottom. In one or more embodiments, the gap includes metal traces and metal dielectric windows. In one or more embodiments, the metal traces have sidewalls and a bottom. In one or more embodiments, the metal dielectric windows have sidewalls and a bottom. Unless otherwise stated, the term "bottom of the gap" as used in this specification and the appended claims means the bottom of the metal dielectric window, which is closest to the substrate.

[0025] Embodiments of this disclosure provide methods for forming interconnect structures in the fabrication of microelectronic components. In one or more embodiments, the microelectronic component described herein includes at least one top interconnect structure interconnected with at least one bottom interconnect structure. Embodiments of this disclosure provide microelectronic components with improved interconnect performance (e.g., reduced interlayer window resistance) and methods for fabricating microelectronic components.

[0026] This document describes a method for forming a microelectronic component with reference to Figures 1A to 1E and Figures 2A to 2G. Figure 3 is a flowchart of an example method for forming the microelectronic component shown in Figures 1A to 1E. Figure 4 is a flowchart of an example method for forming the microelectronic component shown in Figures 2A to 2G.

[0027] Referring to Figures 1A through 1D, a portion of a microelectronic component 100 during the manufacturing phase is shown. In Figure 1A, the microelectronic component 100 includes a substrate 110, a barrier layer 120 on the substrate 110, a metal pad 130 on the barrier layer 120, a conductive fill gap 140, an alumina etch stop layer 142, and a dielectric layer 145 on the alumina etch stop layer 142, the dielectric layer 145 including at least one feature defining a gap 146 comprising a sidewall 148 and a bottom 149. According to one or more embodiments, a passivation layer (e.g., a self-assembled monolayer (SAM)) 150 is formed on the bottom 149 of the gap. It will be understood that in one or more embodiments, the conductive fill gap 140 forms a metal line that carries current in the same component layer.

[0028] In one or more embodiments, substrate 110 is a wafer, such as a semiconductor substrate. In one or more embodiments, substrate 110 is an etch stop layer on a wafer. In one or more embodiments, substrate 110 is an alumina etch stop layer on a wafer. In one or more embodiments, barrier layer 120 comprises tantalum nitride (TaN). In one or more embodiments, barrier layer 120 comprises tantalum nitride (TaN) formed by ALD. In one or more embodiments, metal pad 130 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, metal pad 130 comprises one or more of a monolayer of ruthenium (Ru) or a monolayer of cobalt (Co). In one or more embodiments, a portion of metal pad 130 is etched. In one or more embodiments, SAM 150 is deposited on the etched portion of metal pad 130. In one or more embodiments, conductive fill gap 140 comprises one or more of copper (Cu) or cobalt (Co). In one or more embodiments, the etch stop layer 142 comprises one or more of aluminum oxide, silicon nitride, and aluminum nitride.

[0029] In one or more embodiments, dielectric layer 145 is a low-k dielectric layer. In some embodiments, dielectric layer 145 comprises silicon oxynitride (SiO₂x). In one or more embodiments, dielectric layer 145 comprises SiO₂xH₂y (CH₂z). In other embodiments, dielectric layer 145 comprises porous or carbon-doped SiO₂x. In some embodiments, the dielectric layer is a porous or carbon-doped SiO₂x with a k value less than about 5. In other embodiments, dielectric layer 145 is a multilayer structure. For example, in one or more embodiments, dielectric layer 145 comprises a multilayer structure having one or more of a dielectric layer, an etch stop layer, and a hard mask layer.

[0030] In one or more embodiments, dielectric layer 145 includes at least one feature that defines a gap 146 comprising sidewalls 148 and a bottom 149. For illustrative purposes, the figures show a substrate with a single feature; however, those skilled in the art will understand that there may be more than one feature. The shape of feature 145 may be any suitable shape, including but not limited to trenches, cylindrical dielectric windows that carry current between layers when filled with metal, and lines that carry current in the same element layer. In some embodiments, the feature defines a gap 146 in dielectric layer 145. In some embodiments, gap 146 defines a dielectric window portion 146V and a line portion 146L, but the embodiments shown are not intended to be limiting. The term "feature" as used herein means any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom, and tips having a top and two sidewalls. Features may have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1 or 40:1.

[0031] In one or more embodiments, SAM 150 is formed on the metal liner 130. In one or more embodiments, SAM 150 is deposited by exposing the bottom 149 of the gap to hydrocarbons carried in argon (Ar) gas. In one or more embodiments, SAM 150 comprises unsaturated hydrocarbons.

[0032] Without being bound by theory, we believe that the d-orbitals of metallic materials begin to share electrons with the sp² orbitals of unsaturated hydrocarbons. Therefore, in some embodiments, the unsaturated hydrocarbon comprises at least one compound in which there is at least one double bond between two carbon atoms. In some embodiments, the unsaturated hydrocarbon comprises at least one compound in which there is at least one parabond between two carbon atoms. In other words, in some embodiments, the unsaturated hydrocarbon comprises at least one compound having the general formula R'=R” or R'≡R”. In some embodiments, the unsaturated hydrocarbon compound contains only one unsaturated bond. Without being bound by theory, we believe that multiple unsaturated bonds increase the likelihood of polymerization and increase the difficulty of removing the barrier layer without damaging the surrounding substrate material.

[0033] In some embodiments, R' and R" are the same. In some embodiments, R' and R" are independent C2-C6 groups. A "C2-C6 group" as used herein comprises 2 to 6 carbon atoms. In some embodiments, R' and R" comprise only carbon and hydrogen atoms. In some embodiments, R' and R" do not contain any surface-reactive portion. In some embodiments, the unsaturated hydrocarbon compound does not contain an unsaturated bond with a terminal carbon. In some embodiments, the unsaturated hydrocarbon compound comprises 4 to 12 carbon atoms. In some embodiments, R' and / or R" are linear molecules (e.g., straight-chain unsaturated hydrocarbons). In some embodiments, R' and / or R" are branched. In some embodiments, the unsaturated hydrocarbon compound comprises or is substantially composed of 3-hexyne. The term "substantially composed of" as used herein means that the unsaturated hydrocarbon is greater than or equal to about 95%, 98%, 99%, or 99.5% in moles of the compound. In some embodiments, the unsaturated hydrocarbon compound comprises or is substantially composed of 5-decyne.

[0034] In some embodiments, the substrate is immersed in unsaturated hydrocarbon vapor. In some embodiments, the processing conditions for exposing the substrate to unsaturated hydrocarbons can be controlled.

[0035] In some embodiments, the pressure in the processing chamber is controlled. The pressure in the processing chamber can be any suitable pressure used to form the barrier layer. In some embodiments, the pressure in the processing chamber is maintained at less than or equal to about 80 Torr, less than or equal to about 70 Torr, less than or equal to about 60 Torr, less than or equal to about 50 Torr, less than or equal to about 40 Torr, less than or equal to about 30 Torr, less than or equal to about 20 Torr, less than or equal to about 15 Torr, less than or equal to about 10 Torr, or less than or equal to about 5 Torr. In some embodiments, the pressure in the processing chamber is maintained at about 10 Torr, about 20 Torr, about 30 Torr, about 40 Torr, or about 50 Torr.

[0036] In one or more embodiments, an argon (Ar) gas flow is configured to carry unsaturated hydrocarbons from a container to a processing chamber. In some embodiments, the flow rate of the argon (Ar) gas configured to carry unsaturated hydrocarbons into the processing chamber is controlled. The argon (Ar) gas flow rate can be any suitable flow rate for forming the passivation layer. In some embodiments, the argon (Ar) gas flow rate is in the range of about 50 sccm to about 100 sccm, or in the range of about 75 sccm to about 100 sccm. In one or more embodiments, the argon (Ar) gas flow rate is about 600 sccm. In some embodiments, the flow rate of argon (Ar) gas is less than or equal to about 600 sccm, less than or equal to about 500 sccm, less than or equal to about 400 sccm, less than or equal to about 300 sccm, less than or equal to about 250 sccm, less than or equal to about 200 sccm, less than or equal to about 150 sccm, less than or equal to about 100 sccm, less than or equal to about 75 sccm, or less than or equal to about 50 sccm.

[0037] In some embodiments, the immersion period for exposing unsaturated hydrocarbons to the substrate is controlled. The immersion period can be any suitable cycle for forming the barrier layer. In some embodiments, the immersion period is greater than or equal to about 10 s, greater than or equal to about 20 s, greater than or equal to about 30 s, greater than or equal to about 45 s, greater than or equal to about 60 s, greater than or equal to about 80 s, greater than or equal to about 120 s, greater than or equal to about 150 s, or greater than or equal to about 200 s. In some embodiments, the immersion period is about 60 s. In some embodiments, the immersion period is about 200 s.

[0038] In one or more embodiments, when the unsaturated hydrocarbons are in a container such as an ampoule or cylinder, the unsaturated hydrocarbons are in a liquid phase, and the unsaturated hydrocarbons are delivered from the container to the chamber in a carrier gas. In some embodiments, when the container has a pressure of about 0.1 Torr, the unsaturated hydrocarbons are in a saturated gaseous phase in the container. In one or more embodiments, the temperature of the container is lower than the temperature in the processing chamber. In one or more embodiments, a carrier gas such as argon (Ar) carries the saturated gaseous unsaturated hydrocarbons from the container to the processing chamber. In some embodiments, the temperature of the processing chamber is controlled when exposed to the unsaturated hydrocarbons. The temperature of the processing chamber may also be referred to as the operating temperature. In some embodiments, the temperature of the processing chamber is in the range of about 200°C to about 300°C. In some embodiments, the temperature of the processing chamber is less than or equal to 300°C, less than or equal to 275°C, less than or equal to 250°C, less than or equal to 225°C, or less than or equal to 200°C.

[0039] Referring to Figure 1B, the barrier layer 160 is shown on the SAM 150, above the sidewalls 148 and bottom 149 of the gap 146. In one or more embodiments, the barrier layer 160 has the same properties as the barrier layer 120. In one or more embodiments, the deposition of the barrier layer 160 is substantially normal when the SAM 150 is absent. In one or more embodiments, the barrier layer 160 is formed on the sidewalls 148 and the bottom 149 of the gap 146. As used herein, a "substantially normal" layer refers to a layer with approximately the same thickness everywhere (e.g., on the top, middle, and bottom of the sidewalls 148 and on the bottom 149 of the gap 146). The thickness variation of a substantially normal layer is less than or equal to about 5%, 2%, 1%, or 0.5%. In one or more embodiments, the barrier layer 160 is selectively deposited on at least a portion of the sidewalls 148. In one or more embodiments, the barrier layer 160 is selectively deposited on at least a portion of the bottom 149. In one or more embodiments, the barrier layer 160 may cover the entire sidewall 148.

[0040] In one or more embodiments, a barrier layer 160 is selectively deposited by atomic layer deposition (ALD), the thickness of which is in the range of about 2 Å to about 10 Å. In some embodiments, the barrier layer 160 is deposited in a single ALD cycle. In other embodiments, the barrier layer 160 is deposited in 1 to 20 ALD cycles. In one or more embodiments, each of the 1 to 20 ALD cycles is configured to deposit a barrier layer 160 with a thickness of about 0.5 Å.

[0041] In one or more embodiments, when the barrier layer 160 is formed on the bottom 149 and the sidewall 148, the thickness of the barrier layer 160 on the sidewall 148 is in a ratio to the thickness of the barrier layer 160 on the bottom 149, and this ratio is greater than 6. In one or more embodiments, this ratio is greater than 5, greater than 4, greater than 3, greater than 2, or greater than 1. In one or more embodiments, when SAM 150 is present, the thickness of the barrier layer 160 on the sidewall 148 is in the range of 5 Å to 20 Å. In one or more embodiments, the thickness of the barrier layer 160 on the bottom 149 is less than or equal to 5 Å. In one or more embodiments, the thickness of the barrier layer 160 on the bottom 149 is less than or equal to 4 Å, less than or equal to 3 Å, less than or equal to 2 Å, or less than or equal to 1 Å.

[0042] Referring to Figure 1C, the first metal pad 170 shown is on the barrier layer 160 shown in Figure 1B. In one or more embodiments, the first metal pad 170 has the same properties as the metal pad 130. In one or more embodiments, the metal pad 170 is selectively deposited on the sidewall 148 of the microelectronic component. In one or more embodiments, the first metal pad 170 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the first metal pad 170 comprises one or more of a monolayer of ruthenium (Ru) or a monolayer of cobalt (Co). In one or more embodiments, the first metal pad 170 comprises a monolayer of ruthenium (Ru). In one or more embodiments, the first metal pad 170 comprises a monolayer of ruthenium (Ru) selectively deposited on the sidewall. In one or more embodiments, the first metal pad 170 comprises a multilayer film having a first pad film composed of a first metal M1 and a second pad film composed of a second metal M2. In one or more embodiments, the first metal liner 170 includes a first metal M1 (including ruthenium (Ru)) and a second metal M2 (including cobalt (Co)).

[0043] Embodiments of this disclosure advantageously provide methods for forming microelectronic components that reduce the resistance of the interposer windows by at least 20% compared to the resistance of the interposer windows in microelectronic components with non-selectively deposited metal pads. In one or more embodiments, the resistance of the interposer windows of the microelectronic components described herein is reduced by at least 15%, at least 10%, or at least 5% compared to the resistance of the interposer windows in microelectronic components with non-selectively deposited metal pads.

[0044] Ruthenium (Ru) was deposited on the sidewalls and bottom using a typical deposition process. We found that when using a known deposition process with a time interval of 40 seconds, the Ruthenium (Ru) layer deposited on the sidewalls had a thickness of 10 angstroms, and the Ruthenium (Ru) layer deposited on the bottom had a thickness of approximately 3.87 angstroms. In one or more embodiments, the ratio of the thickness of the Ruthenium (Ru) layer on the sidewalls to the thickness of the Ruthenium (Ru) layer on the bottom was approximately 2.6.

[0045] We have found that selective deposition of a monolayer of ruthenium (Ru) according to embodiments of the method described herein increases the ratio of the thickness of the metal pad on the sidewalls to the thickness of the metal pad on the bottom. In one or more embodiments, the thickness of the metal pad on the sidewalls is greater than the thickness of the metal pad on the bottom.

[0046] In one or more embodiments, when the metal pad 170 comprises a monolayer of ruthenium (Ru) selectively deposited on the sidewall 148, the thickness of the metal pad on the sidewall 148 is in a ratio greater than 3 to the thickness of the metal pad on the bottom 149. In one or more embodiments, the ratio of the thickness of the metal pad on the sidewall 148 to the thickness of the metal pad on the bottom 149 is greater than 4, greater than 5, greater than 6, or greater than 7.

[0047] In one or more embodiments, when the metal liner 170 comprises a monolayer of selectively deposited ruthenium (Ru), the thickness of the metal liner 170 on the sidewall 148 is in the range of 5 angstroms to 20 angstroms. In one or more embodiments, when the metal liner 170 comprises a monolayer of selectively deposited ruthenium (Ru), the thickness of the metal liner 170 on the bottom 149 is less than or equal to 5 angstroms. In one or more embodiments, when the metal liner 170 comprises a monolayer of selectively deposited ruthenium (Ru), the thickness of the metal liner 170 on the bottom 149 is less than or equal to 4 angstroms, less than or equal to 3 angstroms, less than or equal to 2 angstroms, or less than or equal to 1 angstrom.

[0048] In one or more embodiments, a metal liner 170 containing ruthenium (Ru) is selectively deposited using a selective ruthenium (Ru) deposition process. Selective ruthenium (Ru) deposition on the sidewalls includes a cyclic deposition process, comprising a ruthenium deposition step using a ruthenium (Ru) precursor carried by a carrier gas such as argon (Ar). In one or more embodiments, selective ruthenium (Ru) deposition further includes an annealing or processing step performed while hydrogen (H₂) is flowed and, where appropriate, a second gas (e.g., argon (Ar)) is flowed. In one or more embodiments, selective ruthenium (Ru) deposition is performed in a substrate processing chamber, wherein the deposition step is performed when the chamber is at a first pressure, and the annealing step is performed when the substrate processing chamber is at a second pressure greater than the first pressure. In one or more embodiments, the first pressure is in the range of 1 Torr to 5 Torr. In some embodiments, the first pressure is in the range of 1 Torr to 4 Torr or 1 Torr to 3 Torr. In one or more embodiments, the second pressure is in the range of 10 Torr to 150 Torr. In some embodiments, the second pressure is in the range of 10 Torr to 40 Torr or 10 Torr to 30 Torr. Therefore, according to one or more embodiments, the cyclic deposition process includes a deposition step and an annealing / treatment step. In the deposition step, a ruthenium precursor (e.g., any suitable organometallic precursor, such as ruthenium tricarboxycyclohexadiene, Ru 3(CO) 9) is flowed in a carrier gas and a reactant gas (e.g., Ar and / or H 2) for 2 to 10 seconds (e.g., 3 to 6 seconds) to form a post-deposited ruthenium layer. In the annealing or treatment step, the post-deposited ruthenium layer is annealed or treated for 30 to 90 seconds (e.g., 40 to 70 seconds) in the presence of a flowing gas (e.g., >90% H 2 and a second gas such as Ar). This cyclic deposition process, including the deposition step and the annealing or treatment step, is repeated several times to obtain the desired film thickness.

[0049] Referring to Figure 1D, in one or more embodiments, the second metal pad 180 shown is on the first metal pad 170. In one or more embodiments, the second metal pad 180 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the second metal pad 180 comprises one or more of a monolayer of ruthenium (Ru) or a monolayer of cobalt (Co). In one or more embodiments, the metal pad 180 comprises a monolayer of cobalt (Co) selectively deposited on the sidewalls. In one or more embodiments, when the metal pad 180 comprises a monolayer of deposited cobalt (Co), the thickness of the metal pad 180 on the sidewall 148 is in the range of 5 angstroms to 20 angstroms. In one or more embodiments, when the metal pad 180 comprises a monolayer of deposited cobalt (Co), the thickness of the metal pad 180 on the bottom 149 is less than or equal to 5 angstroms. In one or more embodiments, when the metal liner 180 comprises a monolayer deposited cobalt (Co), the thickness of the metal liner 180 on the bottom 148 is in the range of 5 angstroms to 20 angstroms.

[0050] In one or more embodiments, the second metal pad 180 comprises a multilayer film having a first pad film composed of a first metal M1 and a second pad film composed of a second metal M2. In one or more embodiments, the second metal pad 180 comprises a first metal M1 (including ruthenium (Ru)) and a second metal M2 (including cobalt (Co)). In one or more embodiments, when the second metal pad 180 comprises a first metal M1 containing ruthenium (Ru) and a second metal M2 containing cobalt (Co), the combined thickness of the multilayer film on the sidewall 148 is in the range of 10 to 20 angstroms. In one or more embodiments, when the second metal pad 180 comprises a first metal M1 containing ruthenium (Ru) and a second metal M2 containing cobalt (Co), the combined thickness of the multilayer film on the bottom 149 is in the range of 5 to 20 angstroms.

[0051] In one or more embodiments, the microelectronic component 100 includes one or more of a first metal pad 170 and a second metal pad 180. In one or more embodiments, the first metal pad 170 and the second metal pad 180 are the same. In one or more embodiments, the first metal pad 170 and the second metal pad 180 are different.

[0052] In some embodiments, the bimetallic gasket film comprises an alloy of two metals in a single layer. In some embodiments, the bimetallic gasket film comprises alternating layers of two metals M1 and M2, or a first metal gasket film and a second metal gasket film. In one or more embodiments, the two metals comprise two metals selected from the group consisting of (M1)Co and (M2)tantalum (Ta), (M1)Co and (M2)molybdenum (Mo), (M1)Ru and (M2)Ta, (M1)Ru and (M2)W, (M1)Ru and (M2)Mo, (M1)Co and (M2)Ru, and (M1)Ru and (M2)Co. In one or more embodiments, the thickness of the two metal films is less than 20 angstroms.

[0053] According to one or more embodiments, bimetallic liner films can be formed by various deposition methods, including alternating and / or co-current precursors of ALD / CVD / PE-ALD, precursors with multi-metallic ligands, dopant implantation, and / or thermal diffusion. Bimetallic liner films can be formed in a single processing chamber or multiple processing chambers. In one or more embodiments, bimetallic liner films can be treated by various methods including thermal treatment, plasma treatment, and / or chemical treatment.

[0054] Advantageously, the bimetallic gasket film according to one or more embodiments is ultrathin (e.g., 20 angstroms or less thick), providing better interfacial adhesion and mobility between two metals, such as a barrier layer and a gap-filling metal. The bimetallic gasket film and method described according to one or more embodiments can be used in metal contact, interconnect, and overlay applications. The bimetallic gasket film according to one or more embodiments is thinner than current gaskets, which are typically thicker than 20 angstroms and at most 30 angstroms. In some embodiments, the thickness of the gasket film composed of the two metals ranges from 10 to 20 angstroms, 10 to 19 angstroms, 10 to 18 angstroms, 10 to 17 angstroms, 10 to 16 angstroms, 10 to 15 angstroms, 10 to 14 angstroms, 10 to 13 angstroms, or 10 to 12 angstroms. The bimetallic liner films described in this paper extend metal filling and coverage to advanced nodes, such as Cu reflow at 3nm / 2nm nodes, low resistivity in middle-of-the-line (MOL) and back-end-of-line (BEOL) processes, and memory. The methods described in this paper can also simplify current complex integrated systems to single-chamber or multi-chamber processes using CVD / ALD / PVD / PEALD / ion implantation.

[0055] In one or more embodiments, a barrier layer and / or a metal film can be deposited by ALD. In a typical ALD process, an alternating pulse or flow of precursor "A" and precursor "B" can be used to deposit the film. The surface continues to be alternately exposed to reactants "A" and "B" until the desired film thickness is achieved. However, instead of pulsed delivery of reactants, gases can flow simultaneously from one or more gas delivery heads or nozzles and / or movable gas delivery heads, such that the substrate is sequentially exposed to each of the reactive gases. Of course, the above-described ALD cycle is only an example of various ALD process cycles in which a deposited layer is formed by alternating layers of precursors and co-reactants.

[0056] In one or more embodiments, the co-reactant is in vapor or gas form. The reactant can be delivered using a carrier gas. The carrier gas, flushing gas, deposition gas, or other process gas may contain nitrogen, hydrogen, argon, neon, helium, or combinations thereof. The various plasmas described herein, such as nitrogen plasma or inert gas plasmas, and / or such plasmas contain a plasma co-reactant gas, can be ignited from the plasma co-reactant gas.

[0057] In one or more embodiments, various process gases can be pulsed into the inlet via a gas channel and enter the central channel from various orifices or outlets. In one or more embodiments, the deposition gas can be pulsed sequentially to and through the nozzle. Alternatively, as described above, the gas can flow simultaneously through the gas supply nozzle or head, and the substrate and / or gas supply head can be moved to sequentially expose the substrate to the gas.

[0058] In one or more embodiments, a multi-chamber process is used to deposit a barrier layer material and a liner film, wherein the barrier layer material (e.g., tantalum nitride (TaN)) is separated from the bimetallic liner film. In other embodiments, a single-chamber method is used, wherein all processes occur in one chamber, and the different layers / films are separated during processing by gas rinsing.

[0059] Some embodiments of the present invention relate to barrier applications, such as copper barrier applications. Barrier layers formed by one or more embodiments can be used as copper barriers. Suitable barrier layers for copper barrier applications include, but are not limited to, TaN and MnN. Suitable dopants for copper barrier applications include, but are not limited to, Ru, Cu, Co, Mn, Al, Ta, Mo, Nb, V, or combinations thereof. Plasma treatment can be used after doping to promote the formation of intermetallic compounds between the substrate and the dopant, remove film impurities, and increase the density of the barrier layer. In other embodiments, post-treatment may include, but is not limited to, physical vapor deposition (PVD), thermal annealing, chemical enhancement, or the like. In some copper barrier applications, high-frequency plasma (defined as greater than about 14 MHz or about 40 MHz or greater) can be used with any inert gas, including, but not limited to, one or more of neon (Ne), hydrogen (H₂), and argon (Ar). In one or more embodiments, higher plasma frequencies (above 13.56 MHz) can be used to prevent low-k damage. In some embodiments, the barrier layer is a copper barrier and contains Ru-doped TaN.

[0060] Suitable precursors for depositing the backing layer include metal-containing precursors, such as carbonyl-containing and cyclopentadiene-containing precursors. In non-limiting examples, if the backing layer is RuCo, the Ru-containing precursor may be dodecyltriruthenium(CO)12, and the Co-containing precursor may be dicobalt(hexacarbonyl)tert-butylacetylene (CCTBA). If the backing layer is TaRu, the Ta-containing precursor may be pentapenta(dimethylamino)tantalum (PDMAT). Other suitable precursors are known to those skilled in the art. Organic species from the organic precursor used for the backing layer may be partially incorporated into the underlying layer (e.g., a barrier or dielectric layer), which can improve adhesion at the interface between the backing layer and the underlying layer.

[0061] The term "chemical vapor deposition" as used in this article refers to a process in which the substrate surface is simultaneously or substantially simultaneously exposed to a precursor and / or co-reagent. "Substantially simultaneously" as used in this article means that the exposure of the co-flow or precursor largely overlaps.

[0062] Bimetallic pad films can be formed by depositing alternating layers of two metals or co-reacting two metal precursors using CVD, PVD, or ALD. Depending on the pad metal used, co-reactants or co-precursors can be used to deposit the bimetallic pad film. In one or more embodiments, ion implantation can be used to fuse the second metal into the pad film composed of the first metal. In other embodiments, physical vapor deposition (PVD) co-processing can be used to add the second metal to a doped pad film formed over a barrier layer. In other embodiments, the bimetallic pad film can be annealed in an atmosphere containing the second metal to allow thermal diffusion of the second metal into the bimetallic pad film of the first metal, thereby forming a bimetallic pad film over a barrier layer.

[0063] In one or more embodiments, a PVD process involving sputtering can be used to incorporate a second metal into a liner film containing a first metal. For example, a PVD process containing cobalt (Co) can implant Co into a ruthenium film to form a liner film containing ruthenium and cobalt.

[0064] In some embodiments, a plasma post-treatment step may be used after exposing a bimetallic liner containing a first metal to a second metal precursor, with or without a co-reactant. According to one or more embodiments, the plasma contains any suitable inert gas known to those skilled in the art. In one or more embodiments, the plasma contains one or more of helium (He), argon (Ar), ammonia (NH3), hydrogen (H2), and nitrogen (N2). In some embodiments, the plasma may contain a mixture of Ar and H2, for example, a mixture with an Ar:H2 molar ratio in the range of 1:1 to 1:5. The plasma power may be in the range of about 200 to about 1000 watts. The plasma power may be in the range of 350 kHz to 40 MHz. The plasma treatment time may be from 5 seconds to 60 seconds, for example, in the range of 10 seconds to 30 seconds. In some embodiments, the pressure during plasma treatment may be in the range of 0.5 to 50 Torr, for example, 1 to 10 Torr. In some embodiments, the wafer pitch can be in the range of 100 mils to 600 mils.

[0065] In one or more embodiments, the bimetallic liner film comprising a first metal may be exposed to a second metal precursor during deposition; that is, the second metal precursor may be used sequentially in an ALD cycle to provide a liner film composed of two metals on the barrier layer. In various embodiments, the duration of exposure to the second metal-containing precursor may range from 1 to 60 seconds, for example, from 3 to 30 seconds or from 5 to 10 seconds. Longer exposure to the second metal precursor will increase the amount of the second metal in the bimetallic liner film. In one or more embodiments, the bimetallic liner film is formed by a cyclic deposition process.

[0066] Referring to Figure 1E, in one or more embodiments, SAM 150 has been removed from the structure shown in Figure 1D using the methods described herein. In one or more embodiments, removing SAM 150 includes a plasma processing process, which includes allowing one or more of hydrogen (H₂) or argon (Ar) to flow. In one or more embodiments, the plasma processing process includes increasing the density of the barrier layer 160. In one or more embodiments, the gap-filling process includes filling the gaps 146 shown in Figure 1E with one or more of copper (Cu) or cobalt (Co).

[0067] Referring to Figures 2A and 2B, a portion of a microelectronic component 200 at various manufacturing stages according to an alternative embodiment of this disclosure is shown. In one or more embodiments, the microelectronic component 200 includes a substrate 210, a barrier layer 220 on the substrate 210, a metal pad 230 on the pad layer 220, a conductive fill gap 240, an alumina etch stop layer 242, and a dielectric layer 245 on the alumina etch stop layer 242, the dielectric layer 245 including at least one feature defining a gap 246 including a sidewall 248 and a bottom 249. In one or more embodiments, a first passivation layer (e.g., a first self-assembled monolayer (SAM)) 250 is formed on the bottom 249 of the gap.

[0068] In one or more embodiments, the microelectronic components shown in Figures 1A to 1E and Figures 2A to 2G have the same characteristics, including materials, manufacturing methods, dimensions, etc. In one or more embodiments, the substrate 210, the barrier layer 220 on the substrate, the metal pad 230 on the pad layer 220, the conductive fill gap 240, the alumina etch stop layer 242, and the dielectric layer 245 on the alumina etch stop layer 242 include at least one feature defining a gap 246 including a sidewall 248 and a bottom 249. A first SAM 250 is formed by flowing hydrocarbons carried in argon (Ar) gas. In one or more embodiments, the first SAM 250 comprises unsaturated hydrocarbons. In one or more embodiments, the first SAM 250 is deposited on the dielectric layer 245.

[0069] Referring to Figure 2B, the barrier layer 260 is shown on the first SAM 250, on the sidewall 248, and on the bottom 249 of the gap 246. In Figure 2C, the first SAM 250 has been removed. In one or more embodiments, removing the first SAM 250 includes a plasma processing process, which includes allowing one or more of hydrogen (H2) or argon (Ar) to flow. In one or more embodiments, the plasma processing process includes increasing the density of the barrier layer 260.

[0070] Referring now to Figure 2D, after the removal of the first SAM 250, a second passivation layer (e.g., a second self-assembled monolayer (SAM)) 255 is formed on the bottom 249 of the gap, on the barrier layer 260, and on the bottom 249 of the gap. In one or more embodiments, the first SAM 250 and the second SAM 255 are the same. In one or more embodiments, the first SAM 250 and the second SAM 255 are different. Referring now to Figure 2E, a first metal pad 270 is deposited on the barrier layer 260. Referring now to Figure 2F, in one or more embodiments, a second metal pad 280 is formed on the first metal pad 270.

[0071] Referring to Figure 2G, the second SAM 255 has been removed. In one or more embodiments, the first SAM 250 and the second SAM 255 may be removed by the same process. In one or more embodiments, removing one or more of the first SAM and the second SAM includes a plasma processing process, including allowing one or more of hydrogen (H2) or argon (Ar) to flow. In one or more embodiments, the plasma processing process includes increasing the density of the barrier layer 260.

[0072] Figure 3 illustrates a process flow diagram of method 300 for forming a microelectronic component. Figure 3 illustrates a method for forming any of the microelectronic components of one or more embodiments shown in Figures 1A to 1E. Referring to Figure 3, method 300 includes forming a dielectric layer on a substrate in operation 310. The dielectric layer includes at least one feature defining a gap including sidewalls and a bottom. In operation 320, method 300 includes selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. In operation 330, method 300 includes forming a barrier layer on the SAM. In operation 340, method 300 includes selectively depositing a metal pad on the barrier layer. In operation 340, in some embodiments, the thickness of the metal pad deposited on the sidewalls is greater than the thickness of the metal pad deposited on the bottom. In operation 350, method 300 includes removing the SAM after selectively depositing the metal pad on the barrier layer. In operation 360, method 300 includes performing a gap-filling process on the metal pad. The gap filling process may include forming one or more of the interlayer window and the line to form an interconnect in the component.

[0073] Figure 4 illustrates a process flow diagram of a method 400 for forming a microelectronic component. Figure 4 also illustrates a method for forming any one of the microelectronic components shown in Figures 2A through 2G, representing one or more embodiments. Referring to Figure 4, method 400 includes forming a dielectric layer on a substrate in operation 410. The dielectric layer includes at least one feature defining a gap including sidewalls and a bottom. In operation 420, method 400 includes selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap. In operation 430, method 400 includes forming a barrier layer on the first SAM. In operation 440, method 400 includes removing the first SAM after forming the barrier layer. In operation 450, method 400 includes selectively depositing a second self-assembled monolayer (SAM) on the barrier layer after removing the first SAM. In operation 460, method 400 includes selectively depositing a metal pad on the barrier layer. In operation 460, in some embodiments, the thickness of the metal pad deposited on the sidewalls is greater than the thickness of the metal pad deposited on the bottom. In operation 470, method 400 includes removing the second SAM after selectively depositing a metal pad on the barrier layer. In operation 480, method 400 includes performing a gap-filling process on the metal pad. The gap-filling process may include forming one or more of a via window and a line to form an interconnect in the device.

[0074] In one or more embodiments, the methods described herein include optional post-processing operations. Optional post-processing operations may be, for example, processes that modify membrane properties (e.g., annealing) or further membrane deposition processes (e.g., additional ALD or CVD processes) to grow additional membranes. In some embodiments, optional post-processing operations may be processes that modify the properties of the deposited membrane. In some embodiments, optional post-processing operations include annealing the freshly deposited membrane. In some embodiments, annealing is performed at temperatures in the range of about 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. The annealing environment in some embodiments includes one or more of an inert gas (e.g., nitrogen molecules (N₂), argon (Ar)) or a reducing gas (e.g., hydrogen molecules (H₂) or ammonia (NH₃)) or an oxidant or peroxide such as, but not limited to, oxygen (O₂), ozone (O₃). Annealing may be performed for any suitable duration. In some embodiments, the film is annealed for a predetermined time ranging from about 15 seconds to about 90 minutes or from about 1 minute to about 60 minutes. In some embodiments, annealing the freshly deposited film increases density, reduces resistivity, and / or increases the purity of the metal backing layer.

[0075] In some embodiments, the substrate is moved from a first chamber to a separate next chamber for further processing. The substrate may be moved directly from the first chamber to a separate processing chamber, or it may be moved from the first chamber to one or more transfer chambers and then to a separate processing chamber. In some embodiments, the deposition of a barrier layer and a dopant film may be performed in a single chamber, followed by post-processing in a separate chamber. Therefore, the processing apparatus may include multiple chambers communicating with a transfer station. Apparatus of this type may be referred to as a "clustering tool" or "clustering system" and the like.

[0076] Generally, a clustering tool is a modular system comprising multiple chambers that perform processes including substrate centering and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, the clustering tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can house a robot that can transport the substrate between and within the processing chamber and the loading gate chamber. The transfer chamber is typically maintained under vacuum conditions, providing an intermediate stage for transporting the substrate from one chamber to another and / or placing it in the loading gate chamber at the front end of the clustering tool. Two well-known clustering tools applicable to this disclosure are Centura® and Endura®, which are available from Applied Materials, Inc., Santa Clara, California. However, the precise arrangement and combination of the chambers can be modified for the purpose of performing specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic deposition including deposition steps, annealing or processing steps, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, plasma nitriding, degassing, orientation, hydroxylation and other substrate processes. By performing the process in a chamber on a cluster tool, contamination of the substrate surface by atmospheric impurities can be avoided, and oxidation can not occur before the deposition of subsequent films.

[0077] According to one or more embodiments, the substrate is continuously under vacuum or "loading gate" conditions and is not exposed to ambient air while moving from one substrate to the next. The transfer chamber is thus under vacuum and "evacuated" under vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a flushing gas to remove some or all of the reactants (e.g., reactants). According to one or more embodiments, flushing gas is injected at the outlet of the deposition chamber to prevent reactants (e.g., reactants) from moving from the deposition chamber to the transfer chamber and / or other processing chambers. Thus, the inert gas flow forms a curtain at the outlet of the chamber.

[0078] Substrates can be processed in a single substrate deposition chamber, wherein a single substrate is loaded, processed, and unloaded before processing another substrate. Similar to a transport system, substrates can also be processed continuously, wherein multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and the associated transport system can form a straight path or a curved path. Alternatively, the processing chamber can be a rotating rack in which multiple substrates move around a central axis and are exposed to processes such as deposition, etching, annealing, and cleaning along the entire rotating rack path.

[0079] During processing, the substrate may be heated or cooled. This heating or cooling can be accomplished by any suitable means, including but not limited to changing the temperature of the substrate support and the flowing heating or cooling gas toward the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to change the substrate temperature conductively. In one or more embodiments, the gas used for heating or cooling (reactive gas or inert gas) locally changes the substrate temperature. In some embodiments, the heater / cooler is disposed in a chamber adjacent to the substrate surface to change the substrate temperature by convection.

[0080] The substrate can be stationary or rotated during processing. The rotating substrate can be rotated continuously or in discrete steps (around a substrate axis). For example, the substrate can be rotated throughout the entire process, or it can be rotated slightly between exposures to different reaction or purging gases. Rotating the substrate during processing (continuously or in discrete steps) can help produce more uniform deposition or etching by minimizing, for example, the effects of localized variations in gas flow geometry.

[0081] Another aspect of this disclosure relates to a non-transitory computer-readable medium containing instructions that, when executed by a controller of a processing system, cause the processing system to perform operations of the methods described herein. In one embodiment, the non-transitory computer-readable medium contains instructions that, when executed by a controller of a processing system, cause the processing system to perform operations of the methods described herein with respect to Figures 1A to 1E, 2A to 2G, 3, and 4.

[0082] Throughout this specification, the terms "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that at least one embodiment of this disclosure includes a specific feature, structure, material, or characteristic described in connection with the embodiment. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" in multiple places throughout this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0083] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

[0084] 100: Microelectronic components 110:Substrate 120: Barrier Layer 130: Metal gasket 140: Conductive filling gap 142: Alumina Etching Stop Layer 145: Dielectric layer 146: Gap 146L: Circuit Section 146V: Intercalation window portion 148: Sidewall 149: Bottom 150: Self-assembled single layer 160: Barrier Layer 170: First metal gasket 180: Second metal gasket 200: Microelectronic Components 210:Substrate 220: Padding layer 230: Metal gasket 240: Conductive filler gap 242: Alumina Etching Stop Layer 245: Dielectric layer 246: Gap 248: Sidewall 249: Bottom 250: First self-assembled monolayer 255: Second self-assembled monolayer 260: Barrier Layer 270: First metal gasket 280: Second metal gasket 300: Method 310: Operation 320: Operation 330: Operation 340: Operation 350: Operation 360: Operation 400: Method 410: Operation 420: Operation 430: Operation 440: Operation 450: Operation 460: Operation 470: Operation 480: Operation

[0085] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a microelectronic device, the method comprising the steps of: forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap having sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap by exposing the bottom of the gap to a hydrocarbon carried by a carrier gas; forming a barrier layer on the bottom of the gap and on the sidewalls; selectively depositing a first metal pad on the sidewalls and on the barrier layer on the bottom of the gap, the thickness of the first metal pad deposited on the sidewalls being greater than the thickness of the first metal pad deposited on the bottom; selectively depositing a second metal pad on the first metal pad to form a bimetallic pad, the second metal pad comprising a metal different from the first metal pad, wherein the thickness of the bimetallic pad on the sidewalls is in the range of 10 Å to 20 Å, and the thickness on the bottom is in the range of 5 Å to 20 Å; After selectively depositing the second metal liner on the first metal liner, the SAM is removed; and a gap filling process is performed on the second metal liner.

2. The method as described in claim 1, wherein the hydrocarbon is selected from the group consisting of linear unsaturated hydrocarbons and branched unsaturated hydrocarbons, the general formula of the hydrocarbon is selected from the group consisting of R'=R” or R'≡R”, and R' and R” include carbon and hydrocarbon atoms.

3. The method as described in claim 1, wherein the SAM comprises a first SAM deposited on the dielectric layer.

4. The method as described in claim 1, wherein the first metal pad is selectively deposited on one sidewall of the microelectronic element.

5. The method as described in claim 4, wherein the first metal pad comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), and tantalum (Ta).

6. The method as claimed in claim 5, wherein when the first metal pad comprises a monolayer of ruthenium (Ru) selectively deposited on the sidewall, the thickness of the first metal pad on the sidewalls is in a ratio to the thickness of the first metal pad on the bottom, the ratio being greater than 3.

7. The method as described in claim 6, wherein the selective ruthenium (Ru) deposition step on the sidewall comprises the following steps: performing a cyclic deposition process using a ruthenium (Ru) precursor carried by a carrier gas to form a deposited ruthenium layer.

8. The method as described in claim 7, wherein the steps of the cyclic deposition process further include the steps of: annealing the deposited ruthenium layer while allowing hydrogen (H2) to flow, and annealing the deposited ruthenium layer.

9. The method of claim 8, wherein the cyclic deposition process is performed in a substrate processing chamber under a first pressure to form the deposited ruthenium layer, and the deposited ruthenium layer is annealed when the substrate processing chamber is under a second pressure higher than the first pressure.

10. The method as described in claim 5, wherein the first metal pad includes a first metal M1 and the second metal pad includes a second metal M2.

11. The method as described in claim 10, wherein the first metal M1 comprises ruthenium (Ru) and the second metal M2 comprises cobalt (Co).

12. The method as claimed in claim 11, wherein when the first metal M1 contains ruthenium (Ru) selectively deposited on the sidewall, the thickness of the metal pad thickness on the sidewalls is in a ratio to the thickness of the metal pad thickness on the bottom, the ratio being greater than 3.

13. The method as described in claim 1, wherein the step of removing the SAM comprises the following steps: a plasma treatment process comprising allowing one or more of hydrogen (H2) or argon (Ar) to flow.

14. The method as described in claim 13, wherein the plasma processing steps include the step of increasing the density of the barrier layer.

15. The method as described in claim 1, wherein the gap filling process includes the step of filling the gap with one or more of copper (Cu) or cobalt (Co).

16. The method as described in claim 2, wherein the hydrocarbon comprises 5-decyne.

17. The method as described in claim 2, wherein the hydrocarbon comprises 3-hexyne.

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