Systems and methods for transition encoding with protected key

Abstract

An encoding method may include: receiving a sequence of data bits at an encoder; performing a first transformation encoding on the data bits at the encoder to generate an encoded data bit sequence based on a key; performing protection encoding on the key at the encoder to generate key-protected data; performing a second transformation encoding on the key-protected data at the encoder to generate encoded key-protected data; and transmitting an encoded transmission bit sequence to a receiver, the encoded transmission bit sequence including the encoded data bit sequence and the encoded key-protected data.

Description

Technical Field

[0001] Cross - Reference to Related Applications:

[0002] This application claims priority and the benefit of U.S. Provisional Patent Application No. 63 / 227,278, filed on July 29, 2021, the entire content of which is incorporated herein by reference.

[0003] This application is generally related to transform coding, and more particularly to systems and methods for transform coding with a protection key.

Background Art

[0004] Electronic devices using serial data transmission rely on providing error - free information from a transmitter to a receiver. In addition, some serial data transmission techniques rely on keys to encode and then decode serial data. Since the encoding and decoding processes rely on keys, if the receiver receives an incorrect or wrong key, the error in the key will propagate into the data, and the serial data cannot be correctly decoded. Therefore, a technique for ensuring the reliability and integrity of keys is needed.

Summary of the Invention

[0005] According to some embodiments, a coding method is described, which may include the following steps: receiving a sequence of data bits at an encoder; performing a first transform coding on the data bits at the encoder to generate an encoded data bit sequence based on a key; performing a protection coding on the key at the encoder to generate a key - protected data; performing a second transform coding on the key - protected data at the encoder to generate an encoded key - protected data; and sending an encoded transmission bit sequence to a receiver, the encoded transmission bit sequence including the encoded data bit sequence and the encoded key - protected data.

[0006] The key - protected data may include a parity bit.

[0007] The step of generating the encoded key - protected data may include inverting the parity bit.

[0008] The method may further include: at the encoder, selecting the key as a value whose most significant bit (MSB) is a constant; and removing the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

[0009] The constant may be zero.

[0010] The key protection data may include a plurality of parity bits.

[0011] The plurality of parity bits may be calculated according to a Hamming code.

[0012] The step of generating the encoded key protection data may include inverting at least one of the plurality of parity bits.

[0013] The method may further include: at the encoder, selecting the key as a value whose one of the most significant bits is a constant; and removing the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

[0014] The step of generating the encoded key protection data may further include: inserting one or more bits of the inverted parity bits at a front end of the modified key, and inserting one or more bits of the inverted parity bits at a rear end of the modified key.

[0015] According to some embodiments, an encoder is described, which includes: an input configured to receive a sequence of data bits; a processor configured to perform a plurality of operations, the plurality of operations including: performing a first transformation encoding on the data bits to generate an encoded data bit sequence based on a key; performing a protection encoding on the key to generate a key protection data; and performing a second transformation encoding on the key protection data to generate an encoded key protection data; and an output configured to send an encoded transmission bit sequence to a receiver, the encoded transmission bit sequence including the encoded data bit sequence and the encoded key protection data.

[0016] The key protection data may include a parity bit.

[0017] The operation of generating the encoded key protection data may include: inverting the parity bit.

[0018] This operation may further include: selecting, at the encoder, the key as a value of a most significant bit that is a constant; and removing the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

[0019] The constant may be zero.

[0020] The key protection data may include a plurality of parity bits.

[0021] The plurality of parity bits may be calculated according to a Hamming code.

[0022] The operation of generating the encoded key protection data may include inverting at least one of the plurality of parity bits.

[0023] This operation may further include: selecting, at the encoder, the key as a value whose one most significant bit is a constant; and removing the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

[0024] The operation of generating the encoded key protection data further includes: inserting one or more bits of the inverted parity bits at a front end of the modified key, and inserting one or more bits of the inverted parity bits at a rear end of the modified key.

[0025] The scope of the present invention is defined by the scope of the patent application for the invention, which is incorporated herein by reference. By considering the following detailed description of one or more embodiments, those of ordinary skill in the art to which the present invention pertains will obtain a more complete understanding of the embodiments of the present invention, as well as the realization of its additional effects. First, a brief description of the drawings will be referred to.

Embodiments

[0028] Aspects of some embodiments of the present disclosure and methods for implementing these aspects can be more easily understood by referring to the detailed description of the embodiments and the drawings. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. Instead, these embodiments are provided as examples to make the present disclosure more thorough and complete, and to fully convey the aspects of the present disclosure to those of ordinary skill in the art to which the present invention pertains. Therefore, processes, elements, and techniques that are unnecessary for those of ordinary skill in the art to which the present invention pertains to fully understand the aspects of the present disclosure may not be described.

[0029] In digital communication, an encoder encodes data bits (e.g., data packets) and sends the encoded data bits to a decoder. The decoder then decodes the encoded data bits so that the data bits can be used by the system, such as a television, a display device, a computer, etc. According to one technique, the encoded data bits can be serialized and transmitted from the encoder to the decoder via a serial digital data link. The serial digital data can be transmitted together with a separate clock signal accompanying the serial digital data, or the serial digital data can be transmitted together with a clock signal embedded in the serial digital data signal (i.e., without a separate clock signal).

[0030] Transition encoding is a method of transmitting a serial digital data signal without a separate clock signal. Transition encoding relies on the presence of data transitions in the data bit sequence, where the data bits transition or change from zero to one or from one to zero. In other words, in order for the decoder to correctly utilize the received data, a certain amount of transitions must occur in the data bit sequence. However, if the run-length in a data sequence exceeds a certain limit, the decoder may not be able to correctly decode the data and the system will not receive the data it is supposed to receive. The run-length is the number of consecutive 1s or 0s in a sequence of data bits. For example, in the sequence of exemplary data bits 10100111001 shown in FIG. 1, the run-length between each transition is represented as 1, 2, or 3. For example, in the case of three consecutive 1s, the run-length is 3.

[0031] Some conversion encoding techniques include keys (e.g., scrambling keys) that can be used when encoding data bits to maintain the integrity of the encoded data bit sequence when the data is transmitted over a serial data link. In this case, the encoder generates a key, performs conversion encoding on the data bits based on the key, and adds the key to the encoded data bit sequence to generate a transmission bit sequence for sending to the receiver. When the decoder receives the encoded transmission bits, the decoder uses the key to decode the received transmission bits. If the key is damaged during transmission, the decoder will not be able to decode the transmitted data bits and may result in error propagation. In other words, errors in the key will carry over to errors in the entire data, resulting in the entire data stream being unavailable. Therefore, embodiments of the present disclosure describe techniques for improving the reliability of key transmission. In addition, it may be desirable to protect the key without changing the conversion attributes of the encoding sequence (e.g., not exceeding the encoding run length limit).

[0032] Exemplary conversion encoding techniques include encoding 31 groups of 6-bit data words and a key that is also 6 bits. Thus, according to this embodiment, the transmission bit sequence includes 192 bits, where 186 bits are data and 6 bits are the key. The 6-bit key can be represented by D, and D can be a word different from all 31 words of the original data word string or a word different from the complement of the 31 original data word strings. Thus, the value of D can be selected, and an exclusive OR (“XOR”) operation can be applied to D and each of the 31 words. Thus, for example, each word of the 186 data bits can be represented as x1, x2, …, x31, and the XOR operation can be applied to each word x1, x2, …, x31 and the key D to produce x1^D, x2^D, …, x31^D. Thus, by performing conversion encoding on a data word string sequence {x1, x2, …, x31}, the encoded data word string will become {D, x1^D, x2^D, …, x31^D}, where the first data word is the key D, followed by the XOR operation of each of the 31 data words with the key D. Thus, the transmission data sequence stream becomes 32 words long, where 192 bits are serialized and transmitted over a serial data link. According to this exemplary conversion encoding technique, the run length can be limited to 10. The details of determining the run length of this conversion encoding technique are not relevant to the present invention and will not be elaborated here.

[0033] When the decoder receives the transmission data sequence, the decoder obtains the key D and performs an XOR operation on each encoded string (i.e., each of the 31 strings). Thus, by performing an exclusive OR operation of D with the first encoded string x1^D, D is canceled, leaving only x1, i.e., the first string. The same XOR operation is performed on all 31 encoded strings to decode these 31 strings. Thus, if an error is introduced in the key D, the error will propagate to each of the 31 strings because the decoder will perform the XOR operation using the wrong (i.e., incorrect) key D.

[0034] According to various embodiments of the present disclosure, techniques for protecting the integrity of the key D will be described. In other words, methods and techniques for error detection and / or error correction can be implemented by the encoder and applied to the key D such that if an error occurs in the key D (e.g., during transmission), the decoder will be able to detect the error in the key D and thus not apply the wrong key D to decode the data stream. Instead, for example, the decoder can wait for another key D that does not contain an error to arrive. In other embodiments, the decoder can not only detect the presence of an error but also correct the error, so that the decoder does not have to discard the key D and wait for the next key, but corrects the wrong key so that the decoder can now immediately use the corrected key. Note that the techniques for protecting key integrity described in the present disclosure are applicable to various encoding and / or decoding techniques known to those of ordinary skill in the art to which the present invention pertains. Such encoding and / or decoding techniques can include using different logical operations, different string sizes, different numbers of strings, etc.

[0035] Generally speaking, a parity bit can be included in the encoded data to help detect the presence of errors. An example is generating an even parity bit and including the even parity bit in the encoded data. For example: If there are n bits d1 to dn in a given string (e.g., a 6-bit key) or block, then the even parity bit p can be generated or calculated by performing an XOR operation on the bits d1 to dn. Thus, the even parity bit p of d1 to dn can be expressed as: p = d1 ⊕ d2 ⊕ d3 ⊕ … ⊕ dn, and the encoded block including the even parity bit p can be expressed as: {d1, d2, d3, ……, dn, p}. Therefore, the dependency between the data bits and the parity bit can be written as d1 ⊕ d2 ⊕ d3 ⊕ … ⊕ dn ⊕ p = 0. In other words, if the dependency representation is equal to 0 in the case of an even parity bit, then the data bits d1 to dn may not contain errors. On the other hand, if the dependency representation is equal to 1, then one of the data bits d1 to dn may contain an error.

[0036] More complex block codes can be constructed by including multiple parity bits. For example: Hamming codes can be used, such as: (7,4) Hamming codes. In the (7,4) Hamming code, three parity bits can be implemented in the encoded data bit block. In this case, the parity bits p1, p2, p3 can be generated as: p1 = d1 ⊕ d2 ⊕ d4, p2 = d1 ⊕ d3 ⊕ d4, p3 = d2 ⊕ d3 ⊕ d4, and the dependency between the parity bits and the data bits can be expressed as: d1 ⊕ d2 ⊕ d4 ⊕ p1 = 0, d1 ⊕ d3 ⊕ d4 ⊕ p2 = 0, d2 ⊕ d3 ⊕ d4 ⊕ p3 = 0.

[0037] Another example of a parity bit is an odd parity bit. For the odd parity pb, applying an XOR operation to the data bits and the odd parity bit to get 1 can be expressed as d1 ⊕ d2 ⊕ d3 ⊕ … ⊕ dn ⊕ pb = 1. Thus, the odd parity bit pb can be generated as: pb = inv(d1 ⊕ d2 ⊕ d3 ⊕ … ⊕ dn). In other words, the odd parity bit is the inverse of the exclusive OR operation result of all data bits. [

[0038] ]In conversion encoding, the odd parity bit contains some useful features. For example, if the section consists of an odd number of bits, i.e., n is odd, then there is a guaranteed transition in the data bit section. In other words, if d1 = 0, d2 = 0, d3 = 0, d4 = 0, and d5 = 0, then pb = inv(d1 ⊕ d2 ⊕ d3 ⊕ d4 ⊕ d5) = inv(0 ⊕ 0 ⊕ 0 ⊕ 0 ⊕ 0) = inv(0) = 1. Therefore, if an odd parity bit is inserted at the end of the code, the section code is 000001, which contains a transition. Similarly, if d1 = 1, d2 = 1, d3 = 1, d4 = 1, and d5 = 1, then pb = inv(d1 ⊕ d2 ⊕ d3 ⊕ d4 ⊕ d5) = inv(1 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 1) = inv(1) = 0. Therefore, the section code is 111110, which also includes a transition. Therefore, in the worst case where bits d1 to dn are all 1 or all 0, where n is odd, the run length is limited to n, and the inclusion of the odd parity bit guarantees a transition. [

[0039] ]Now returning to the exemplary conversion encoding technique using 31 groups of 6-bit strings and the 6-bit key D, the concept of using an odd parity bit may be applied to the key D to detect errors, and in some embodiments, to detect and correct errors. According to this example, the key D includes 6 bits and the most significant bit ("MSB") (i.e., the 6th bit) of the value of the key D is always zero. Therefore, according to an embodiment of the present disclosure, the 6th bit of the key D can be removed and replaced with an odd parity bit instead of zero. For example, the decoder knows that the MSB of the value of the key D is always zero. Therefore, when the decoder receives the encoded key D, even if the actual value of the MSB (i.e., 0) is replaced by the odd parity bit, the decoder can remove the parity bit from the MSB and replace it with 0 during the decoding process. [

[0040] ]Therefore, by removing 0 from the MSB of the key D and replacing it with an odd parity bit, the encoded key D now includes 5 bits corresponding to the key data, and 1 bit for the odd parity bit (i.e., the 6th bit). For example, the key D can be represented as D = d1, d2, d3, d4, d5, pb, where pb corresponds to the odd parity bit, where pb = inv(d1 ⊕ d2 ⊕ d3 ⊕ d4 ⊕ d5). Accordingly, the relationship between the odd parity bit and the five data bits is: d1 ⊕ d2 ⊕ d3 ⊕ d4 ⊕ d5 ⊕ pb = 1. Therefore, if any one of the data bits of the key D has an error, the odd parity dependency will no longer hold, and thus an error in one of the data bits d1, d2, d3, d4, or d5 will be indicated.

[0041] In addition, the run length is limited to 5. As described above, in the worst case where all data bits d1 to d5 are 1, the odd parity bit is zero, or if all data bits d1 to d5 are zero, the odd parity bit is 1. Therefore, the run length is not greater than 5, which falls within the run length limit of 10 as previously indicated for the exemplary transform coding technique. However, although the implementation of one odd parity bit can detect the presence of an error, the specific location of the error cannot be determined in this example. It should be noted that the above embodiments are merely examples at the level of illustrative embodiments and are not intended to be limiting. Therefore, the same or similar techniques can be applied to other scenarios where the string has different numbers of bits, different run length limits, etc. For example: In other embodiments, a string can have 8 bits and the run length limit may be 9.

[0042] According to another embodiment of the present disclosure, multiple parity bits can be included in the key D to further improve the integrity of the key. For example: Similar to the exemplary key D including 6 bits above, where the MSB is always zero, the 6th bit can be discarded and four additional odd parity bits can be included. Therefore, the new key D is 9 bits, where 5 bits are data bits and 4 bits are parity bits. In some embodiments, four odd parity bits can be generated and inserted into the section. For example: The four odd parity bits can be generated as follows: pb1 = inv(d1⊕d2⊕d3), pb2 = inv(d1⊕d3⊕d4), pb3 = inv(d2⊕d3⊕d5), pb4 = inv(d3⊕d4⊕d5).

[0043] Therefore, by generating and including four parity bits, if one of the data bits has an error, the dependency relationship of the parity bits will no longer hold, thus revealing the presence of an error. In addition, since there are four parity bits, depending on which dependency relationships no longer hold, the system can determine which one of the five data bits is in error and then correct the error bit. For example: If the error is in d1, the dependency relationships including pb1 and pb2 will be invalid. If the error is in d2, the dependency relationships including pb1 and pb3 will be invalid. If the error occurs in d3, the dependency relationships including pb1, pb2, pb3, and pb4 will be invalid. If the error is in d4, the dependency relationships including pb2 and pb4 will be invalid. If the error is in d5, the dependency relationships including pb3 and pb4 will be invalid. Therefore, the system can accurately locate the error bit and then correct the error bit. Since the bit is binary, if the error bit is zero, it becomes one, and if it is one, it becomes zero. In some embodiments, if there are two errors in the data bits, the system can detect the error but cannot accurately determine the error bit to correct the error. Instead, only the error will be detected.

[0044] In some embodiments, a 9-bit key is arranged such that the first two bits and the last two bits are parity bits and the middle five bits are data bits. Thus, a key including odd parity bits can be represented as pb1, pb2, d1, d2, d3, d4, d5, pb3, pb4. By arranging the data bits and parity bits in this way, the run length can be limited to 5 and the transitions in key D can be guaranteed. FIG. 2 shows a diagram of each combination of the data bits of key D. Since there are 5 data bits, there are 32 possible combinations. As shown by the shaded blocks, when all data bits are zero and when all data bits are 1, the run length is limited to 5. Thus, the run length limit meets the run length limit of 10 for the exemplary transform coding techniques described in this disclosure, and thus, the likelihood of errors and error propagation in the serial data link can be reduced.

[0045] FIG. 3 shows a flowchart of steps for encoding a sequence of data bits according to various embodiments of the present disclosure. According to one embodiment, an encoder is configured to receive a sequence of data bits that are to be encoded and transmitted to a receiver (302). In some embodiments, the data can be packets of data, while in other embodiments, the data can be any serial data with an embedded clock signal. The sequence of data bits received at the encoder can be encoded by performing a first transform coding on the data bits to generate an encoded sequence of data bits based on a key (304). In some embodiments, the numerical value of the key can be used to perform an XOR operation with the data bits to generate the encoded sequence of data bits. Thus, when the data bits are to be decoded, the decoder relies on the key to perform the decoding operation. Therefore, the key is very important and the integrity of the key should be protected so that, for example, errors are not introduced into the key during transmission. In addition, if the key results in an error, the presence of the error needs to be detected and the error corrected in some cases. Thus, the encoder can be configured to perform a protection coding on the key to generate key protection data (306).

[0046] In some embodiments, the key protection data is a parity bit. For example: an odd parity bit can be generated by performing an exclusive OR operation on each bit of the key and taking the inverse of the result. Thus, if the key includes bits d1, d2, …, dn, the odd parity bit (pb) can be represented as: pb = inv(d1 ⊕ d2 ⊕ … ⊕ dn).

[0047] Once the odd parity bit is generated, the encoder can perform a second transform encoding on the key-protected data (e.g., the odd parity bit) to generate the encoded key-protected data (308). In some embodiments, the encoded key-protected data can be represented as key bits with the key-protected data. In other words, if the key-protected data is the odd parity bit pb, and the key includes odd bits d1, d2, ……, dn, where n is odd, then the encoded key-protected data can be represented as d1, d2, ……, dn, pb. In other embodiments where the parity bit is calculated according to Hamming code, the encoded key-protected data can be represented as, for example, d1, d2, ……, dn, p1, p2, p3. Once the encoded key-protected data is generated, the encoded data bit sequence and the encoded key-protected data can be combined into an encoded transmission bit sequence and sent to the receiver (310). The transmitter and the receiver can be coupled to a serial data link, and the encoded transmission bit sequence can be transmitted from the transmitter to the receiver through the serial data link. In some embodiments, the receiver can include a decoder that receives the encoded transmission bit sequence and decodes it using the key. To reduce error propagation, the integrity of the key can be verified by using the included key-protected data (e.g., the odd parity bit) to ensure that the value of the key corresponds to the odd parity bit.

[0048] FIG. 4 is a flowchart showing the steps for encoding key-protected data according to various embodiments of the present disclosure. According to one embodiment, a key can be selected such that it can be used to encode the key-protected data. For example, the encoder can select a key such that the most significant bit (MSB) of the value of the key is a constant (e.g., always one or always zero) (402). Thus, by selecting a key in which the MSB is always the same value, the MSB does not necessarily have to be sent to the receiver, since the receiver can be configured to know that the MSB of the value of the key is always the same value. For example, if the selected key is a 6-bit value and the MSB of the 6 bits (i.e., the 6th bit) is always zero, then the 6th bit can be deleted. Instead, the key-protected data (e.g., the odd parity bit) can be used to replace the MSB, thereby better utilizing the bandwidth occupied by the bits. Thus, a modified key can be generated and the modified key can be included in the transmission bits (404).

[0049] In some embodiments, the key-protected data can include multiple parity bits, which improves the integrity of the key by being able to detect multiple errors in the key and correct the errors. For example, in some embodiments, the key-protected data can include Hamming code. Thus, catastrophic error propagation at the receiver can be reduced by optimizing serial data transmission while meeting the run length requirements.

[0050] FIG. 5 is an exemplary block diagram of an electronic system 500. By way of example and not limitation, system 500 can be a television or a display device, and can at least include a transmitter 502 and a receiver 504, which are configured to communicate with each other via, for example, a high-speed digital serial link 506. In some embodiments, transmitter 502 can include an encoder 508 that obtains data (e.g., digital data) from another source (e.g., an external source) that can be generated within or received by system 500, encodes the data, and then transmits the encoded data to receiver 504. Receiver 504 can communicate with a display driver that controls, for example, pixels in a display device to emit light according to the received data. Receiver 504 can include a decoder 510 that receives the encoded data from transmitter 502 via link 506 and decodes the encoded data so that the data can be utilized by system 500. In some embodiments, encoder 508 can be a transform encoder that performs transform encoding, such as according to the techniques described in various embodiments of the present disclosure. However, in other embodiments, encoder 508 can be configured to perform other digital encoding techniques known to those of ordinary skill in the art to which the present invention pertains. It should be noted that the illustrated electronic system 500 is merely one example of an electronic system that utilizes high-speed serial data transmission that depends on the accuracy of the transmitted data, but those of ordinary skill in the art to which the present invention pertains will understand that other systems can also be contemplated.

[0051] Unless otherwise specified, in all the figures and the description of the specification, the same element numbers, text elements, or combinations thereof represent the same elements, and thus their descriptions will not be repeated. In addition, for the sake of clarity, parts that are not relevant or not related to the description of the embodiments may not be shown.

[0052] In the figures, for clarity, the relative sizes of elements, layers, and regions may be exaggerated. In addition, the use of cross-hatching and / or shading in the figures is generally used to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not represent or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements of the figure, and / or any other property, attribute, characteristic, etc.

[0053] In the detailed description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various illustrative embodiments can be practiced without these specific details or with one or more equivalent configurations. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various illustrative embodiments.

[0054] It should be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "coupled to" another element, layer, region, or component, it can be directly formed on, on, connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, on, connected to, or coupled to the other element, layer, region, or component such that one or more intermediate elements, layers, regions, or components can exist. Additionally, this can collectively represent direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected to" or "electrically coupled to" another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, or component, and / or components or intermediate layers, regions, or components may be present. However, "directly connected to / directly coupled to" means that a component is directly connected or coupled to another component without an intermediate component. Meanwhile, other expressions describing the relationship between components, such as "between," "immediately between," or "adjacent to" and "directly adjacent to," can be similarly interpreted. Furthermore, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present. For the purposes of this disclosure, prior to the element list, the phrase "at least one" modifies the entire element list and not each individual element in the list. For example, "at least one of X, Y, and Z" and "select at least one from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ or any variation thereof. Similarly, for example, "at least one of A and B" can be understood to mean "A, B, or A and B". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" can include A, B, or A and B. It should be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part described below can be referred to as a second element, component, region, layer, or part without departing from the spirit and scope of this disclosure. Referring to an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used herein to distinguish different categories or groups of elements. For simplicity, the terms "first", "second", etc. can respectively denote "first category (or first group)", "second category (or second group)", etc. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit this disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes", and "including" specify the presence of the feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximating terms and not terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by one of ordinary skill in the art to which this invention pertains. As used herein, "about" or "approximately" is an inclusive statement of a stated value and the average within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art to which this invention pertains, taking into account the measurement in question and the associated error measurements and the particular quantities (i.e., the limits of the measurement system). For example: "about" can mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value. Further, "may" as used in describing embodiments of this disclosure refers to "one or more embodiments of this disclosure".

[0059] When one or more embodiments can be implemented differently, a particular processing order can be performed in an order different from that described. For example: two consecutively described processes can be performed substantially simultaneously or in an order opposite to that order.

[0060] An electronic or electrical device and / or any other relevant device or component according to embodiments of the invention described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and / or hardware. For example: various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. Further, various components of these devices can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Circuit hardware can include, for example, application specific integrated circuits (ASICs), general or special purpose central processing units (CPUs) configured to execute instructions stored in a non-transitory storage medium, digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field programmable gate arrays (FPGAs).

[0061] In addition, various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a device that can be implemented in a computing storage using a standard storage device, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. In addition, those of ordinary skill in the art to which the present invention pertains should recognize that, without departing from the spirit and scope of the embodiments of the present invention, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed over one or more other computing devices.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that terms, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the disclosure of the present invention, and should not be interpreted as idealized or overly formal meanings, unless expressly defined herein.

[0063] The embodiments described herein are merely examples, and those of ordinary skill in the art to which the present invention pertains can recognize various alternative embodiments from the specific disclosures, which are also intended to fall within the scope of this disclosure. Therefore, the embodiments are limited only by the following claims for patent and their equivalents.

Brief Description of the Drawings

[0026] FIG. 1 shows an example of a sequence of data bits undergoing transformation in data according to various embodiments of the present disclosure. FIG. 2 shows a table of exemplary code words according to various embodiments of the present disclosure. FIG. 3 shows a flowchart of steps for encoding a sequence of data bits according to various embodiments of the present disclosure. FIG. 4 shows a flowchart of steps for encoding key-protected data according to various embodiments of the present disclosure. FIG. 5 is a block diagram of an electronic system according to various embodiments of the present disclosure.

[0027] The embodiments of the present disclosure and their advantages are best understood by reference to the following detailed description. Unless otherwise indicated, throughout the description of the drawings and the specification, the same reference numerals represent the same elements, and thus their description will not be repeated. In the drawings, for clarity, the relative sizes of elements, layers, and regions may be exaggerated.

Claims

1. An encoding method comprising the following steps: A sequence of data bits is received at an encoder; a first transformation encoding is performed on the data bits at the encoder to generate an encoded sequence of data bits based on a key; the key is protected by encoding at the encoder to generate key-protected data; the key-protected data is further transformed by encoding at the encoder to generate encoded key-protected data; and an encoded transmission bit sequence is transmitted to a receiver, the encoded transmission bit sequence including the encoded data bit sequence and the encoded key-protected data; wherein the key-protected data includes a parity bit.

2. The method of claim 1, wherein the step of generating the encoded key protection data includes inverting the parity bit.

3. The method as described in claim 2, further comprising: At the encoder, the key is selected as a value whose most significant bit (MSB) is a constant. And remove the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

4. The method as described in request item 3, wherein the constant is zero.

5. The method as described in claim 1, wherein the key-protected data includes a plurality of the parity bits.

6. The method as described in claim 5, wherein the plurality of parity check bits are calculated according to a Hamming code.

7. The method of claim 5, wherein the step of generating the encoded key-protected data includes inverting at least one of the plurality of parity bits.

8. The method as described in claim 7, further comprising: At the encoder, the key is selected as a value whose most significant bit is a constant; And remove the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

9. The method as described in claim 8, wherein the step of generating the encoded key-protected data further comprises: One or more bits of the parity bit that will be reversed are inserted at the beginning of the modified key, and one or more bits of the parity bit that will be reversed are inserted at the end of the modified key.

10. An encoder comprising: One input is configured to receive a sequence of data bits; A processor is configured to perform a plurality of operations, the plurality of operations including: performing a first transformation encoding on the data bits to generate an encoded sequence of data bits based on a key; performing a protection encoding on the key to generate key-protected data; performing a second transformation encoding on the key-protected data to generate encoded key-protected data; and an output configured to transmit an encoded transmission bit sequence to a receiver, the encoded transmission bit sequence including the encoded data bit sequence and the encoded key-protected data; wherein the key-protected data includes a parity bit.

11. The encoder as described in claim 10, wherein the operation of generating the encoded key-protected data includes: Reverse the parity check bit.

12. The encoder as described in claim 11, wherein the operation further includes: At the encoder, the key is selected as a value whose most significant bit is a constant. And remove the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

13. The encoder as described in claim 12, wherein the constant is zero.

14. The encoder as claimed in claim 10, wherein the key-protected data includes a plurality of the parity bits.

15. The encoder as claimed in claim 14, wherein the plurality of parity check bits are calculated according to a Hamming code.

16. The encoder as claimed in claim 14, wherein the operation of generating the encoded key-protected data includes inverting at least one of the plurality of parity bits.

17. The encoder as described in claim 16, wherein the operation further includes: At the encoder, the key is selected as a value whose most significant bit is a constant. And remove the most significant bit from the key to generate a modified key, wherein the encoded transmission bit sequence includes the modified key.

18. The encoder as described in claim 17, wherein the operation of generating the encoded key-protected data further includes: One or more bits of the parity bit that are reversed are inserted into the front end of the modified key, and one or more bits of the parity bit that are reversed are inserted into the end of the modified key.

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