Semiconductor device packaging methods

Abstract

This disclosure relates to methods and apparatus for forming thin-profile semiconductor device packages. In some embodiments, a patterned glass or silicon substrate is formed by laser ablation to create a structure for subsequent formation of interconnects therethrough. The substrate is then used as a framework for forming the semiconductor device package, which may have one or more embedded dies therein. In some embodiments, an insulating layer is formed on the substrate by laminating a pre-formed insulating film onto the substrate. The insulating film can be pre-formed by laser ablation to form a structure therein, and the sidewalls of the formed structure are then selectively cured.

Description

Technical Field

[0001] The embodiments disclosed herein are generally related to semiconductor device packaging and methods of forming the same. More specifically, the embodiments described herein relate to the structure of thin-profile semiconductor device packages and methods of forming the same. Prior Technology

[0002] The ongoing advancements in semiconductor device technology have led to smaller semiconductor components and increased circuit density. To meet the growing demand for scaling semiconductor devices while simultaneously improving performance, integrating these components and circuits into complex 3D semiconductor device packages results in a significant reduction in device footprint and enables shorter, faster connections between components. These packages can integrate, for example, semiconductor wafers and multiple other electronic components for mounting on circuit boards.

[0003] Conventionally, semiconductor devices have been packaged and manufactured on organic packaging substrates due to the ease of forming features and connections in organic packaging substrates and the relatively low packaging manufacturing cost associated with organic composites. However, with the increase in circuit density and the further miniaturization of semiconductor devices, the use of organic packaging substrates has become impractical because the material structure resolution is limited and cannot maintain the requirements of device scaling and associated performance.

[0004] Recently, passive silicon interposers have been used as redistribution layers in the fabrication of 2.5D and / or 3D packages to compensate for some of the limitations associated with organic packaging substrates. The use of silicon interposers is driven by the heterogeneous integration requirements of high bandwidth density, low-power chip-to-chip communications, and advanced packaging applications. However, forming features (such as through-silicon vias; TSVs) in silicon interposers remains challenging and costly. Specifically, the high cost is imposed by high aspect ratio silicon via etching, chemical mechanical planarization, and semiconductor back-end of line (BEOL) interconnects.

[0005] Therefore, this technology requires improved semiconductor device packaging structures and their formation methods for advanced packaging applications. Summary of the Invention

[0006] The embodiments disclosed herein relate to the structure and method of forming a thin-profile semiconductor device package.

[0007] In some embodiments, a method for forming a semiconductor device package is provided. The method includes patterning one or more features into a silicon substrate, the one or more features including a first interlayer window; placing a pre-constructed insulating film on the substrate, the pre-constructed insulating film including a flowable, polymer-based dielectric material, the pre-constructed insulating film further including a second interlayer window formed therein, the second interlayer window being aligned with the first interlayer window after placement of the pre-constructed insulating film; laminating the pre-constructed insulating film onto the substrate; curing the pre-constructed insulating film; and forming a conductive layer extending through the first and second interlayer windows.

[0008] In some embodiments, a method for forming a semiconductor device package is provided. The method includes patterning one or more features into a silicon substrate, the one or more features including at least a first interlayer window; placing the substrate onto a first pre-constructed insulating film, the first pre-constructed insulating film including a second interlayer window, the second interlayer window being aligned with the first interlayer window after the substrate is placed; placing a second pre-constructed insulating film onto the substrate, the second pre-constructed insulating film including a third interlayer window, the third interlayer window being aligned with the first interlayer window after the second pre-constructed insulating film is placed; laminating the first pre-constructed insulating film and the second pre-constructed insulating film onto the substrate; curing the first pre-constructed insulating film and the second pre-constructed insulating film; and forming a conductive layer extending through at least the first interlayer window, the second interlayer window, and the third interlayer window.

[0009] In some embodiments, a method for forming a semiconductor device package is provided. The method includes patterning one or more features into a silicon substrate, the one or more features including at least a first interlayer window; placing the substrate onto a first pre-constructed insulating film, the first pre-constructed insulating film including a second interlayer window, the second interlayer window being aligned with the first interlayer window after the substrate is placed; exposing the first pre-constructed insulating film and the substrate to a first lamination process; placing a second pre-constructed insulating film onto the substrate, the second pre-constructed insulating film including a third interlayer window, the third interlayer window being aligned with the first interlayer window after the second pre-constructed insulating film is placed; exposing the first pre-constructed insulating film, the substrate, and the second pre-constructed insulating film to a second lamination process; curing the first pre-constructed insulating film and the second pre-constructed insulating film; and forming a conductive layer extending through at least the first interlayer window, the second interlayer window, and the third interlayer window. Simple Explanation of the Diagram

[0010] Therefore, the above-described features of this disclosure can be understood in detail by referring to the embodiments, which provide a more specific description of the disclosure briefly outlined above, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and should not be construed as limiting the scope of this disclosure, and other equally effective embodiments are permissible.

[0011] Figure 1 illustrates a flowchart of a process for forming a semiconductor device package, according to the embodiments described herein.

[0012] Figure 2 illustrates a flowchart of a substrate construction process for forming a semiconductor device package, according to the embodiments described herein.

[0013] Figures 3A to 3D schematically illustrate cross-sectional views of a substrate at different stages of the substrate fabrication process depicted in Figure 2, according to the embodiments described herein.

[0014] Figures 4A through 4F schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to the embodiments described herein.

[0015] Figures 5A through 5F schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to the embodiments described herein.

[0016] Figures 6A through 6E schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to the embodiments described herein.

[0017] Figures 7A to 7D schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to the embodiments described herein.

[0018] Figure 8 illustrates a schematic top view of a substrate with the process structure depicted in Figures 2, 3A to 3D, 4A to 4F, 5A to 5F, 6A to 6E, and 7A to 7D, according to the embodiments described herein.

[0019] Figure 9 illustrates a process flow diagram for forming an embedded die-mount device with through-device windows and contact holes, according to the embodiments described herein.

[0020] Figures 10A through 10K schematically illustrate cross-sectional views of embedded die-mount components at different stages of the process depicted in Figure 9, according to the embodiments described herein.

[0021] Figure 11 illustrates a process flow diagram for forming an embedded die-mount device with through-device windows and contact holes, according to the embodiments described herein.

[0022] Figures 12A through 12G schematically illustrate cross-sectional views of embedded die-mount components at different stages of the process depicted in Figure 11, according to the embodiments described herein.

[0023] Figure 13 illustrates a flowchart of a process for forming interconnects in an embedded die assembly, according to the embodiments described herein.

[0024] Figures 14A through 14H schematically illustrate cross-sectional views of embedded die-on assemblies at different stages of the interconnect formation process depicted in Figure 13, according to the embodiments described herein.

[0025] Figure 15 illustrates a flowchart of a process for forming a redistribution layer on an embedded die component and then packaging it for simplification, according to the embodiments described herein.

[0026] Figures 16A through 16L schematically illustrate cross-sectional views of embedded die-mount components at different stages of forming a redistribution layer followed by encapsulation as depicted in Figure 15, according to embodiments described herein.

[0027] Figure 17 illustrates a flowchart of another process for forming a redistribution layer on an embedded die assembly and then unifying it, according to the embodiments described herein.

[0028] Figures 18A through 18C schematically illustrate cross-sectional views of embedded die-mount components at different stages of forming a redistribution layer followed by encapsulation as depicted in Figure 17, according to embodiments described herein.

[0029] Figure 19 illustrates a process flow diagram of an insulating film used for pre-constructing a substrate separate from a semiconductor device package, according to the embodiments described herein.

[0030] Figures 20A to 20C schematically illustrate cross-sectional views of the insulating film at different stages of the fabrication process depicted in Figure 19, according to the embodiments described herein.

[0031] Figures 21A to 21B schematically illustrate exemplary apparatus for use in conjunction with the processes of Figures 19 and 20A to 20C, according to embodiments described herein.

[0032] Figure 22 illustrates a process flow diagram for forming an insulating layer on a substrate, according to the embodiments described herein.

[0033] Figures 23A through 23G schematically illustrate cross-sectional views of embedded die-on-die components at different stages of the process depicted in Figure 22, according to the embodiments described herein.

[0034] Figures 24A and 24B schematically illustrate cross-sectional views of a stack of dynamic random access memory (DRAM) comprising a plurality of semiconductor element packages formed using the processes depicted in Figures 1 through 23G, according to embodiments described herein.

[0035] For ease of understanding, the same element symbols have been used to denote common elements in the figures where possible. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Implementation

[0036] This disclosure relates to methods and apparatus for forming thin-profile semiconductor device packages. In some embodiments, a substrate is constructed or shaped by microblasting to enable the formation of interconnects throughout the substrate. In another embodiment, the substrate is constructed by direct laser patterning. Subsequently, the substrate is used as a package frame for forming a package in which one or more semiconductor devices, in which one or more dies are disposed, are packaged. In yet another embodiment, the substrate is used as a frame for a stack of semiconductor devices, such as a dynamic random access memory (DRAM) stack.

[0037] The methods and apparatus disclosed herein further include novel thin-profile semiconductor device packages designed to replace more conventional package structures that utilize a glass fiber-filled epoxy framework and a silicon interposer as redistribution layers. Generally, the scalability of current packages is limited by the stiffness and flatness of the materials used to form various package structures (e.g., epoxy molding compounds, FR-4 and FR-5 grade woven fiberglass cloths with epoxy adhesives, and the like). The inherent properties of these materials make it difficult to pattern fine (e.g., less than 50 μm) features within them. Furthermore, due to the thermal properties of current package materials, poor coefficient of thermal expansion (CTE) matching can occur between the package substrate, the molding compound, and any semiconductor dies integrated therein. Therefore, current package structures require larger solder bumps with greater spacing to mitigate any warpage caused by poor CTE matching. Consequently, conventional packages are characterized by a low die-to-package area ratio and low through-package bandwidth, resulting in reduced overall power efficiency. The methods and apparatus disclosed herein provide semiconductor device packaging that overcomes many of the disadvantages associated with the aforementioned conventional packaging architectures.

[0038] Figure 1 illustrates a flowchart of a representative method 100 for forming a thin-profile semiconductor device package. Method 100 has multiple operations 110, 120, 130, and 140. Each operation is described in more detail with reference to Figures 2 through 16L. The method may include one or more additional operations that are performed before any of the defined operations, between two of the defined operations, or after all the defined operations (unless the context precludes this possibility).

[0039] Generally, method 100 includes constructing a substrate at operation 110 for use as a package frame, as described in more detail with reference to Figures 2, 3A to 3D, 4A to 4F, 5A to 5F, 6A to 6E, 7A to 7D, and 8. At operation 120, an in-cell die assembly having one or more embedded dies and an insulating layer is formed, as described in more detail with reference to Figures 9 and 10A to 10K, 11 and 12A to 12G, and 22 and 23A to 23G. At operation 130, one or more interconnects are formed in and / or through the in-cell die assembly for interconnecting the in-cell die frame assembly, as described in more detail with reference to Figures 13 and 14A to 14H. At operation 140, a first redistribution layer is formed on the embedded die assembly to reposition the contact points of the interconnects to desired lateral positions on the surface of the embedded die assembly. In some embodiments, in addition to the first redistribution layer, one or more additional redistribution layers may be formed prior to the individual packaging of the embedded die assembly, as described in more detail with reference to Figures 15 and 16A to 16L and Figures 1 and 18A to 18C.

[0040] Figure 2 illustrates a flowchart of a representative method 200 for constructing a substrate to serve as a framework during the formation of a semiconductor device package. Figures 3A through 3D schematically illustrate cross-sectional views of the substrate 302 at different stages of the substrate construction process 200 represented in Figure 2. Therefore, for clarity, Figures 2 and 3A through 3D are described together herein.

[0041] Method 200 begins with operation 210 and the corresponding figure 3A. The substrate 302 is formed of any suitable framework material, including but not limited to group III-V compound semiconductor materials, silicon, and crystalline silicon (e.g., Si). <100> or Si <111> The substrate 302 can be made of silicon oxide, germanium silicon, doped or undoped silicon, doped or undoped polycrystalline silicon, silicon nitride, quartz, borosilicate glass, glass, sapphire, alumina, or ceramics. In some embodiments, the substrate 302 is a monocrystalline p-type or n-type silicon substrate. In some embodiments, the substrate 302 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, the substrate 302 is a p-type or n-type silicon solar cell substrate. The substrate 302 may further have a polygonal or circular shape. For example, the substrate 302 may comprise a generally square silicon substrate having a lateral dimension between about 120 mm and about 180 mm, with or without chamfered edges. In another example, the substrate 302 may comprise a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example, about 300 mm.

[0042] Unless otherwise stated, the embodiments and examples described herein are performed on a substrate having a thickness between about 50 μm and about 1000 μm (e.g., between about 90 μm and about 780 μm). For example, substrate 302 has a thickness between about 100 μm and about 300 μm, such as between about 110 μm and about 200 μm. In another example, substrate 302 has a thickness between about 60 μm and about 160 μm, such as between about 80 μm and about 120 μm.

[0043] Prior to operation 210, substrate 302 may be cut and separated from bulk material by wire sawing, scribing and breaking, mechanical abrasive sawing, or laser cutting. Cutting typically results in mechanical defects or deformations on the surface of the substrate, such as scratches, microcracks, chips, and other mechanical defects. Therefore, at operation 210, substrate 302 is exposed to a first damage removal process to smooth and planarize the substrate surface and remove any mechanical defects in preparation for subsequent fabrication and packaging operations. In some embodiments, substrate 302 may be further thinned by adjusting the process parameters of the first damage removal process. For example, the thickness of substrate 302 may decrease with increasing exposure to the first damage removal process.

[0044] The damage removal process at operation 210 includes exposing substrate 302 to a substrate polishing process and / or an etching process, followed by a rinsing and drying process. In some embodiments, operation 210 includes a chemical mechanical polishing (CMP) process. In some embodiments, the etching process is a wet etching process that includes a buffered etching process that is selective for removing desired materials (e.g., contaminants and other unwanted compounds). In other embodiments, the etching process is a wet etching process utilizing an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the wet etching process. In some embodiments, substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, substrate 302 is immersed in an aqueous KOH etching solution for etching.

[0045] In some embodiments, the etching solution is heated to a temperature between about 30°C and about 100°C, such as between about 40°C and about 90°C, during the etching process. For example, the etching solution is heated to a temperature of about 70°C. In another embodiment, the etching process at operation 210 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes. The thickness of the substrate 302 is adjusted by controlling the time the substrate 302 is exposed to the etchant (e.g., etching solution) used during the etching process. For example, the final thickness of the substrate 302 decreases with increased exposure to the etchant. Alternatively, the substrate 302 may have a greater final thickness with reduced exposure to the etchant.

[0046] At operations 220 and 230, the now planarized and substantially defect-free substrate 302 has one or more features, such as interlayer windows 303 and cavities 305, in which it is patterned and smoothed (one cavity 305 and four interlayer windows 303 are depicted in the lower cross-section of the substrate 302 in Figure 3B). The interlayer windows 303 are used to form direct contact electrical interconnects through the substrate 302, and the cavities 305 are used to receive one or more semiconductor dies and enclose (i.e., embed) the one or more semiconductor dies therein. Figures 4A to 4C, 5A to 5C, 6A to 6C, and 7A to 7B illustrate cross-sectional views of the substrate 302 at different stages of the feature formation and damage or defect removal (e.g., smoothing) processes according to the embodiments described herein. Therefore, operations 220 and 230 will now be described in more detail with reference to Figures 4A to 4C, 5A to 5C, 6A to 6C and 7A to 7B.

[0047] In embodiments where substrate 302 has a thickness of less than about 200 μm (e.g., about 100 μm or about 50 μm), substrate 302 may first be coupled to an optional carrier plate 406 as depicted in Figures 4A and 5A. Carrier plate 406 provides mechanical support for substrate 302 during substrate fabrication process 200 and prevents substrate 302 from breaking. Carrier plate 406 is formed of any suitable chemically and thermally stable rigid material, including but not limited to glass, ceramics, metals, or the like. Carrier plate 406 has a thickness between about 1 mm and about 10 mm, such as between about 2 mm and about 5 mm. In some embodiments, carrier plate 406 has a textured surface. In other embodiments, carrier plate 406 has a ground or smoothed surface.

[0048] Substrate 302 may be coupled to carrier plate 406 via adhesive layer 408. Adhesive layer 408 is formed of any suitable temporary adhesive material, including but not limited to wax, glue, or similar adhesive materials. Adhesive layer 408 is applied to carrier plate 406 by mechanical rolling, pressing, lamination, spin coating, or doctor blade application. In some embodiments, adhesive layer 408 is a water-soluble or solvent-soluble adhesive layer. In other embodiments, adhesive layer 408 is a UV-release adhesive layer. In still other embodiments, adhesive layer 408 is a heat-release adhesive layer. In these embodiments, the adhesive properties of adhesive layer 408 degrade after exposure to heat treatment, for example, by exposing adhesive layer 408 to temperatures above 110°C (e.g., above 150°C). Adhesive layer 408 may further include one or more additional films (not shown), such as liners, base films, pressure-sensitive films, and other suitable layers.

[0049] In some embodiments, after the substrate 302 is bonded to the carrier plate 406, a resist film is coated onto the substrate 302 to form a resist layer 404, as depicted in Figures 4A and 5A. In embodiments where the substrate 302 has a thickness greater than about 200 μm (e.g., about 250 μm), the resist layer 404 is formed on the substrate 302 without first coupling the substrate 302 to the carrier plate 406. The resist layer 404 is used to transfer the desired pattern onto the substrate 302, and is formed on the substrate 302 during subsequent processing operations. After patterning, the resist layer 404 protects selected areas of the underlying substrate 302 during later construction operations.

[0050] The substrate 302 generally has a generally flat surface on which the resist layer 404 is formed. In some embodiments (such as those illustrated in Figure 5A), the resist layer 404 is bonded to the substrate 302 via a resist adhesive layer 409. The resist adhesive layer 409 is formed of any suitable temporary adhesive material, including but not limited to polyvinyl alcohol, a triester containing 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and other water-soluble or solvent-soluble materials. In some embodiments, the resist adhesive layer 409 is formed of a different material from the adhesive layer 408. In some embodiments, the resist adhesive layer 409 is substantially similar in composition to the adhesive layer 408. The resist adhesive layer 409 is applied to the substrate 302 by mechanical rolling, pressing, lamination, spin coating, or doctor blade application. In other embodiments, the resist layer 404 is formed of a temporary adhesive material, such as polyvinyl alcohol, thereby allowing the resist layer 404 to be directly coated and bonded to the surface of the substrate 302. The resist layer 404 may include one or more layers, for example, a first resist layer and a second resist layer (not shown).

[0051] In some embodiments (such as the one illustrated in Figure 4A), the resist layer 404 is a photosensitive layer (e.g., a photoresist). The resist layer 404 may include a solvent, a photoresist resin, and a photoacid generator. The photoresist resin may be any positive or any negative photoresist resin. Representative photoresist resins include acrylates, phenolic varnish resins, poly(methyl methacrylate), and poly(olefin sulfone). Other photoresist resins may also be used. Upon exposure to electromagnetic radiation, the photoacid generator generates charged substances, such as acidic cations and anions. The photoacid generator may also generate polarized substances. The photoacid generator makes the resin sensitive to electromagnetic radiation. Representative photoacid generators include sulfonic acid compounds, such as sulfonated salts, sulfonated esters, and sulfoxyketones. Other suitable photoacid generators include onium salts, such as aryl diazonium salts, halonium salts, aromatic strontium salts, and sulfonium salts or selenium salts. Other representative photoacid generators include nitrobenzene esters, S-triazine derivatives, ionic monazine sulfonates, perfluoroalkyl sulfonates, aryl trifluoroethers and their derivatives and analogs, pyrogallol derivatives, and alkyl disulfonates. Other photoacid generators may also be used. In some embodiments (such as the embodiment illustrated in Figure 5A), the resist layer 404 is a laser-sensitive resist.

[0052] After the resist layer 404 is formed, the substrate 302 on which the resist layer 404 is formed is exposed to electromagnetic radiation to pattern the resist layer 404, as depicted in Figures 4B and 5B. In the embodiment illustrated in Figure 4B, the substrate 302 on which the resist layer 404 is formed is exposed to electromagnetic radiation in the ultraviolet (UV) range. A portion of the resist layer 404 is selectively exposed, and a portion of the resist layer 404 is selectively not exposed to UV radiation. After exposure to UV radiation, the selectively exposed portions of the resist layer 404 are structurally weakened (illustrated by shading), while the selectively unexposed portions maintain their structural integrity. In some embodiments, a mask 412 with the desired pattern is formed on or adjacent to the photosensitive resist layer 404 before UV radiation exposure. In other embodiments, the mask 412 is a master photomask positioned between the resist layer 404 and the UV radiation source. Mask 412 is configured to transfer the desired pattern of UV radiation onto resist layer 404. Mask 412 is formed of any suitable polymer material, including but not limited to PTFE, PVDP, FEP, polyimide or the like.

[0053] In the embodiment illustrated in Figure 5B, the substrate 302 on which the laser-sensitive resist layer 404 is formed is exposed to electromagnetic radiation generated by the laser source 307 rather than by a UV radiation source. Thus, patterning is achieved by targeted laser ablation without the use of a mask. The laser source 307 can be any suitable type of laser used for patterning the resist layer 404. In some instances, the laser source 307 is a femtosecond green laser. In other instances, the laser source 307 is a femtosecond UV laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the resist layer 404. For example, the laser source 307 can generate a pulsed laser beam 310 having a frequency between 100 kHz and 1200 kHz, such as between about 200 kHz and about 1000 kHz. The laser beam 307 is generally configured to form any desired pattern in the resist layer 404. It is further anticipated that the electromagnetic radiation at the operating site may alternatively include electron beams or ion beams, rather than laser beams.

[0054] The resist layer 404 can be formed from any material having suitable hardness after the resist layer 404 has been patterned, such as after exposing a negative photoresist to electromagnetic radiation to cause cross-linking of the material in the resist. Generally, after the resist layer 404 has been patterned (e.g., deposited, exposed, and developed), the resist layer 404 needs to have one or more desired mechanical properties. In some embodiments, the resist layer 404 is formed from a material having a Shore A hardness value between 40 and 90, such as between 60 and 70, after patterning. For example, the resist layer 404 is formed from a material having a Shore A hardness value of about 65 after patterning. In some embodiments, the resist layer 404 is formed from a material having a tensile strength between about 0.5 MPa and about 10 MPa, such as between about 1 MPa and about 8 MPa, after patterning. For example, the resist layer 404 may be formed of a material having a tensile strength of about 7 MPa after patterning. In some embodiments, the resist layer 404 is formed of a polydimethylsiloxane material. In other embodiments, the resist layer 404 is formed of polyvinyl alcohol, a triester containing 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, or the like.

[0055] After patterning the resist layer 404, the substrate 302 on which the resist layer 404 is formed is microblasted to form the desired pattern in the substrate 302, as depicted in Figures 4C and 5C. During the microblasting process, a stream of powder particles 309 is propelled toward the substrate 302 using a high-pressure carrier gas to remove exposed portions of the substrate 302 and / or layers formed thereon. The microblasting process is performed using any suitable substrate abrasion system.

[0056] The microblasting process is determined by the material properties of the powder particles 309, the momentum of the powder particles impacting the exposed surface of the substrate 302, and the material properties of the substrate 302 along with (where applicable) the selectively exposed portions of the resist layer 404. To achieve the desired substrate patterning characteristics, adjustments are made to the following: the type and size of the powder particles 309, the size of the feeder nozzle of the abrasive system and its distance from the substrate 302, the pressure of the carrier gas used to propel the powder particles 309 (which is related to velocity and flow rate), and the density of the powder particles 309 in the fluid flow. For example, the required fluid pressure for the carrier gas propelling the powder particles 309 toward the substrate 302 is determined based on the materials of the substrate 302 and the powder particles 309, for the desired fixed microblasting element nozzle orifice size. In some embodiments, the fluid pressure used for microblasting the substrate ranges from about 50 psi to about 150 psi (e.g., from about 75 psi to about 125 psi) to achieve a carrier gas and particle velocity between about 300 m / s and about 1000 m / s and / or a flow rate between about 0.001 m / s and about 0.002 m / s. For example, during microblasting, the fluid pressure of the inert gas (e.g., nitrogen (N2), CDA, argon) used to propel the powder particles 309 during microblasting is about 95 psi to achieve a carrier gas and particle velocity of about 2350 m / s. In some embodiments, the feeder nozzle for microblasting the substrate 302 has an inner diameter between about 0.1 mm and about 2.5 mm, and is positioned at a distance between about 1 mm and about 5 mm from the substrate 302, such as between about 2 mm and about 4 mm. For example, the feeder nozzle is positioned at a distance of about 3 mm from the substrate 302 during microblasting.

[0057] Generally, the microblasting process is performed using powder particles 309 with sufficient hardness and a high melting point to prevent the particles from sticking to the substrate 302 and / or any layers formed thereon when in contact. For example, the microblasting process is performed using powder particles 309 formed of ceramic materials. In some embodiments, the powder particles 309 used in the microblasting process are formed of alumina (Al₂O₃). In another embodiment, the powder particles 309 are formed of silicon carbide (SiC). Other suitable materials are also contemplated for the powder particles 309. The size range of the powder particles 309 is generally between about 15 μm and about 60 μm in diameter, such as between about 20 μm and about 40 μm in diameter. For example, the powder particles 309 have an average particle size of about 27.5 μm in diameter. In another example, the powder particles 309 have an average particle size of about 23 μm in diameter.

[0058] The effectiveness of the microblasting process at operation 220, as depicted in Figures 4C and 5C, further depends on the material properties of the resist layer 404. Using a material with too high a Shore A hardness may cause undesirable bounce of the powder particles 309 between the sidewalls of the resist layer 404, thereby reducing the velocity at which the powder particles 309 bombard the substrate 302 and ultimately reducing the effectiveness of the powder particles 309 in etching or removing exposed areas of the substrate 302. Conversely, using a material with too low a Shore A hardness may cause the powder particles 309 to undesirably adhere to the resist layer 404. As described above, a Shore A hardness value between approximately 40 and approximately 90 is expected for the resist layer 404 material.

[0059] In embodiments where the resist layer 404 is a photoresist (such as the embodiment depicted in Figure 4C), the substrate 302 remains unexposed at the start of the microblasting process. Therefore, powder particles 309 first bombard the surface of the photoresist, causing material from UV-exposed and structurally weakened portions of the photoresist to be expelled and removed. The powder particles 309 eventually penetrate and remove the fragile, UV-exposed portions to form pores in the resist layer 404, thereby exposing the desired areas of the substrate 302 while other areas remain shielded by the unexposed portions of the photoresist. Microblasting then continues until the powder particles 309 expel and remove the required amount or depth of material from the exposed areas of the substrate 302, thereby forming the desired pattern in the substrate 302. In embodiments where the patterned resist layer 404 is ablated by laser (such as the embodiment depicted in Figure 5C), the desired area of ​​the substrate 302 is already exposed by the holes in the resist layer 404 prior to the microblasting process. Therefore, it is expected that the resist layer 404 will be removed with minimal or no removal during microblasting.

[0060] The aforementioned process for forming features in substrate 302 at operation 220 may cause undesirable mechanical defects, such as chips and cracks, on the surface of substrate 302. Therefore, after performing operation 220 to form the desired features in substrate 302, substrate 302 is exposed to a second damage removal and cleaning process at operation 230 to smooth the surface of substrate 302 and remove undesirable debris, followed by peeling off the resist layer 404 and, if necessary, debonding substrate 302 from carrier plate 406. Figures 4D to 4F and 5D to 5F illustrate cross-sectional views of substrate 302 at different stages of the second damage removal, cleaning, resist peeling, and substrate debonding processes according to the embodiments described herein. Therefore, operation 230 will now be described in more detail with reference to Figures 4D to 4F and 5D to 5F.

[0061] The second damage removal process at operation 230 is generally similar to the first damage removal process at operation 210, and includes exposing the substrate 302 to an etching process, followed by rinsing and drying. The etching process is performed for a predetermined duration to smooth the surface of the substrate 302, specifically the surface exposed to the microblasting process. In another embodiment, the etching process is used to remove unwanted debris retained from the microblasting process. Residual powder particles adhering to the substrate 302 can be removed during the etching process. Figures 4D and 5D illustrate the substrate 302 after debris removal and surface smoothing.

[0062] In some embodiments, the etching process is a wet etching process utilizing a buffered etching process, which preferentially etches the substrate surface relative to the resist layer 404 material. For example, the buffered etching process is selective for polyvinyl alcohol. In other embodiments, the etching process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the wet etching process. In some embodiments, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching. The etching solution can be further heated to a temperature between about 40°C and about 80°C, such as between about 50°C and about 70°C, during the etching process. For example, the etching solution is heated to a temperature of about 60°C. The etching process can be isotropic or anisotropic. In another embodiment, the etching process at operation 230 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes.

[0063] After debris has been removed and the substrate surface has been smoothed, substrate 302 is exposed to a resist stripping process. The stripping process is used to decouple the resist layer 404 from substrate 302, as depicted in Figures 4E and 5E. In some embodiments, a wet process is used to decouple the resist layer 404 from substrate 302 by dissolving / solubilizing the resist adhesive layer 409. Other types of etching processes are also contemplated for releasing the resist adhesive layer 409. In some embodiments, a mechanical rolling process is used to physically peel the resist layer 404 or the resist adhesive layer 409 from substrate 302. In some embodiments, an ashing process is used to remove the resist layer 404 from substrate 302 by using, for example, an oxygen plasma-assisted process.

[0064] Following the resist stripping process, substrate 302 is exposed to an optional carrier debonding process, as depicted in Figures 4F and 5F. The use of the carrier debonding process depends on whether substrate 302 is coupled to carrier plate 406 and the type of adhesive material used to couple substrate 302 to carrier plate 406. As described above and depicted in Figures 4A to 4F and 5A to 5F, in embodiments where substrate 302 has a thickness of less than about 200 μm, substrate 302 is coupled to carrier plate 406 for mechanical support during feature formation at operation 220. Substrate 302 is coupled to carrier plate 406 via adhesive layer 408. Therefore, after microblasting and subsequent substrate etching and resist stripping, substrate 302 coupled to carrier plate 406 is exposed to the carrier debonding process to debond substrate 302 from carrier plate 406 by releasing adhesive layer 408.

[0065] In some embodiments, the adhesive layer 408 is released by exposing the substrate 302 to a baking process. The substrate 302 is exposed to a temperature between about 50°C and about 300°C, such as between about 100°C and about 250°C. For example, the substrate 302 is exposed to a temperature between about 150°C and about 200°C (such as about 160°C) for a desired period of time to release the adhesive layer 408. In other embodiments, the adhesive layer 408 is released by exposing the substrate 302 to UV radiation.

[0066] Figures 4F and 5F illustrate the substrate 302 after operations 210-230 are completed. The cross-section of the substrate 302 in Figures 4F and 5F depicts a single cavity 305 formed therethrough and surrounded on either side by two mesoscopic windows 303. Figure 8 depicts a schematic top view of the substrate 302 after the operations described with reference to Figures 4A to 4F and 5A to 5F are completed, as described in more detail below.

[0067] Figures 6A to 6E illustrate schematic and cross-sectional views of substrate 302 during alternative sequences of operations 220 and 230 (similar to those described above). The alternative sequences depicted for operations 220 and 230 involve patterning substrate 302 on two principal opposing surfaces (compared to only one surface), thereby increasing efficiency during the construction of substrate 302. The embodiments depicted in Figures 6A to 6E encompass substantially all of the processes described with reference to Figures 4A to 4F and 5A to 5F. For example, Figure 6A corresponds to Figures 4A and 5A, Figure 6B corresponds to Figures 4B and 5B, Figure 6C corresponds to Figures 4C and 5C, Figure 6D corresponds to Figures 4D and 5D, and Figure 6E corresponds to Figures 4F and 5F. However, unlike the previous embodiments, the embodiment of operation 220 depicted in Figures 6A to 6E includes a substrate 302 having two resist layers 404 formed on its main opposing surfaces 606, 608, rather than a single resist layer 404 formed on a single surface. Therefore, the processes performed during operations 210-230 will need to be performed at the same time (i.e., simultaneously), or sequentially on both sides of the substrate during each operation. Although Figures 6A to 6E only illustrate the formation of the interlayer window 303, the processes described herein can also be used to form a cavity 305, or a cavity 305 and an interlayer window 303.

[0068] Therefore, after exposing the resist layer 404 on one side of the substrate 302 (such as the side including surface 608) to electromagnetic radiation for patterning, the substrate 302 may be flipped so that the resist layer 404 on the opposite surface 606 is also exposed to electromagnetic radiation for patterning, as depicted in Figure 6B. Similarly, after performing a microblasting process on surface 608 of the substrate 302, the substrate 302 may be flipped so that microblasting can be performed against the opposite surface 606, as depicted in Figure 6C. Subsequently, the substrate 302 is exposed to a second damage removal and cleaning process and a resist stripping process, as depicted in Figures 6D to 6E. By performing a microblasting process on the main opposing surfaces 606 and 608 of the substrate 302 using two resist layers 404 and abutting against surfaces 606 and 608, the potential gradual refinement of features formed therein caused by the microblasting process can be reduced or eliminated, and the efficiency of the process used to construct the substrate 302 can be improved.

[0069] Figures 7A through 7D illustrate schematic, cross-sectional views of substrate 302 during an alternative sequence of operations 220 and 230, wherein a desired pattern is formed in substrate 302 by direct laser ablation. As depicted in Figure 7A, substrate 302 (such as a solar panel or even a semiconductor wafer) is placed on a support 706 of a laser ablation system (not shown). Support 706 may be any suitable rigid and flat or textured (e.g., constructed) surface for providing mechanical support to substrate 302 during laser ablation. In some embodiments, support 706 includes an electrostatic chuck for electrostatically holding substrate 302 to support 706. In some embodiments, support 706 includes a vacuum chuck for vacuum holding substrate 302 to support 706. After substrate 302 is placed on support 706, a desired pattern is formed in substrate 302 by laser ablation, as depicted in Figure 7B.

[0070] The laser ablation system may include any suitable type of laser source 307 for patterning the substrate 302. In some instances, the laser source 307 is an infrared (IR) laser. In some instances, the laser source 307 is a picosecond UV laser. In other instances, the laser source 307 is a femtosecond UV laser. In still other instances, the laser source 307 is a femtosecond green laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the substrate 302. For example, the laser source 307 may generate a pulsed laser beam 310 having a frequency between 5 kHz and 500 kHz, such as between 10 kHz and about 200 kHz. In one example, laser source 307 is configured to deliver a pulsed laser beam with a wavelength between about 200 nm and about 1200 nm, a pulse duration between about 10 ns and about 5000 ns, and an output power between about 10 watts and about 100 watts. Laser source 307 is configured to form any desired pattern and features in substrate 302, including cavity 305 and interlayer window 303.

[0071] Similar to microblasting, the direct laser patterning process of substrate 302 may create undesirable mechanical defects on the surface of substrate 302, including chips and cracks. Therefore, after the desired features are formed in substrate 302 by direct laser patterning, substrate 302 is exposed to a second damage removal and cleaning process, generally similar to the embodiments described above. Figures 7C to 7D illustrate the structured substrate 302 before and after the second damage removal and cleaning process, resulting in a smoothed substrate 302 having a cavity 305 formed therein and four interlayer windows 303.

[0072] Referring back to Figures 2 and 3D, after removing mechanical defects in substrate 302 at operation 230, in some embodiments, substrate 302 may be exposed to an oxidation process at operation 240 to grow or deposit an insulating oxide film (i.e., layer) 314 on a desired surface of substrate 302. For example, oxide film 314 may be formed on all surfaces of substrate 302 such that it surrounds substrate 302. Insulating oxide film 314 acts as a passivation layer on substrate 302 and provides a protective external barrier layer against corrosion and other forms of damage. In some embodiments, the oxidation process is a thermal oxidation process. Thermal oxidation processes are performed at temperatures between about 800°C and about 1200°C, such as between about 850°C and about 1150°C. For example, thermal oxidation processes are performed at temperatures between about 900°C and about 1100°C, such as between about 950°C and about 1050°C. In some embodiments, the thermal oxidation process is a wet oxidation process using water vapor as the oxidant. In some embodiments, the thermal oxidation process is a dry process using molecular oxygen as the oxidant. It is contemplated that the substrate 302 can be exposed to any suitable oxidation process at operation 240 to form an oxide film 314 thereon. The oxide film 314 generally has a thickness between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. For example, the oxide film 314 has a thickness between about 300 nm and about 2 μm, such as about 1.5 μm.

[0073] In some embodiments, at operation 240, substrate 302 is exposed to a metallization process to form a metal cladding layer 316 on one or more of its surfaces. In some embodiments, the metal cladding layer 316 is formed on substantially all of the outer surfaces of substrate 302, such that the metal cladding layer 114 substantially surrounds substrate 302. The metal cladding layer 316 acts as a reference layer (e.g., a ground layer or voltage supply layer) and is disposed on substrate 302 to protect subsequently formed interconnects from electromagnetic interference and also to shield electronic signals from the semiconductor material (Si) used to form substrate 302. In some embodiments, the metal cladding layer 316 includes a conductive metal layer, including nickel, aluminum, gold, cobalt, silver, palladium, tin, or the like. In some embodiments, the metal cladding layer 316 includes a metal layer, including alloys or pure metals, including nickel, aluminum, gold, cobalt, silver, palladium, tin, or the like. The metal cladding layer 316 generally has a thickness between about 50 nm and about 10 μm, such as between about 100 nm and about 5 μm.

[0074] In some instances, at least a portion of the metal cladding layer 316 comprises a deposited nickel (Ni) layer formed by direct displacement or displacement electroplating on the surface of a substrate 302 (e.g., an n-Si substrate or a p-Si substrate). For example, the substrate 302 is exposed to a nickel displacement electroplating bath having a composition comprising 0.5 M NiSO₄ and NH₄OH for cycles between approximately 2 minutes and approximately 4 minutes at a temperature between approximately 60°C and approximately 95°C and a pH of approximately 11. Exposing the silicon substrate 302 to an aqueous electrolyte containing nickel ions in the absence of a reducing agent results in a localized oxidation / reduction reaction at the surface of the substrate 302, leading to the metallization of nickel on it. Thus, nickel displacement electroplating allows for the selective formation of a thin and pure nickel layer on the silicon material of the substrate 400 using a stable solution. Furthermore, the process is self-limiting, and therefore, the reaction stops once all surfaces of the substrate 302 have been electroplated (e.g., there is no residual silicon on which nickel can be formed). In some embodiments, the nickel metal cladding layer 316 can be used as a seed layer for electroplating additional metal layers, such as for electroplating nickel or copper by electroless plating and / or electrolytic plating methods. In other embodiments, the substrate 302 is exposed to an SC-1 pre-cleaning solution and an HF oxide etching solution prior to the nickel displacement plating bath to promote adhesion of the nickel metal cladding layer 316 to it.

[0075] In subsequent packaging operations, the metal cladding layer 316 may be coupled to one or more connection points (e.g., interconnects) formed within the resulting semiconductor device package to connect the metal cladding layer 316 to a common ground. For example, interconnects may be formed on one or opposite sides of the resulting semiconductor device package to connect the metal cladding layer 316 to ground. Alternatively, the metal cladding layer 316 may be connected to a reference voltage, such as a power supply voltage.

[0076] Figure 8 illustrates a schematic top view of a constructed substrate 302 according to one embodiment. As described above with reference to Figures 2, 3A to 3D, 4A to 4F, 5A to 5F, 6A to 6E, and 7A to 7D, the substrate 302 can be constructed during operations 210-240. The substrate 302 is illustrated as having two quadrilateral cavities 305, each cavity 305 being surrounded by a plurality of interlayer windows 303. In some embodiments, each cavity 305 is surrounded by two columns 801, 802 of interlayer windows 303 arranged along each edge 306a-306d of the quadrilateral cavity 305. Although ten interlayer windows are depicted in each column 801, 802, it is contemplated that any desired number of interlayer windows 303 can be formed in a single column. Additionally, any desired number and arrangement of cavities 305 and mesoscopic windows 303 can be formed in the substrate 302 during operation 220. For example, the substrate 302 may have more or fewer than two cavities 305 formed therein. In another example, the substrate 302 may have more or fewer than two rows of mesoscopic windows 303 formed along each edge 306a-306d of the cavity 305. In yet another example, the substrate 302 may have two or more rows of mesoscopic windows 303, wherein the mesoscopic windows 303 in each row are staggered and misaligned with those in another row.

[0077] In some embodiments, the cavity 305 and the interlayer window 303 have a depth equal to the thickness of the substrate 302, thereby forming a hole (e.g., through the thickness of the substrate 302) on opposite surfaces of the substrate 302. For example, depending on the thickness of the substrate 302, the cavity 305 and the interlayer window 303 formed in the substrate 302 may have a depth between about 50 μm and about 1 mm, such as between about 100 μm and about 200 μm, such as between about 110 μm and about 190 μm. In other embodiments, the cavity 305 and / or the interlayer window 303 may have a depth equal to or less than the thickness of the substrate 302, thereby forming a hole in only one surface (e.g., a side) of the substrate 302.

[0078] In some embodiments, depending on the size of one or more semiconductor dies 1026 (shown in Figure 10B) to be embedded in cavity 305 during packaging fabrication (described in more detail below), each cavity 305 has a lateral dimension ranging from about 3 mm to about 50 mm, such as between about 8 mm and about 12 mm, such as between about 9 mm and about 11 mm. The semiconductor die generally comprises a plurality of integrated electronic circuits formed on and / or within a substrate material (such as a semiconductor material). In some embodiments, cavity 305 is sized to have a lateral dimension generally similar to the lateral dimension of the die 1026 to be embedded therein. For example, each cavity 305 is formed to have a lateral dimension greater than that of the die 1026 by less than about 150 μm, such as less than about 120 μm, such as less than 100 μm. Reducing the size variation of the cavity 305 and the grains 1026 embedded therein will reduce the amount of gap-filling material subsequently used.

[0079] In some embodiments, each mesoscopic window 303 has a diameter ranging from about 50 μm to about 200 μm, such as between about 60 μm and about 130 μm, such as between about 80 μm and about 110 μm. The minimum spacing 807 between the center of a mesoscopic window 303 in column 801 and the center of an adjacent mesoscopic window 303 in column 802 is between about 70 μm and about 200 μm, such as between about 85 μm and about 160 μm, such as between about 100 μm and 140 μm. Although the embodiments are described with reference to Figure 8, the structural fabrication process described above with reference to operations 210-240 and Figures 2, 3A to 3B, 4A to 4C, 5A to 5C, 6A to 6C and 7A to 7B can be used to form patterned features with any desired depth, lateral dimensions and morphology in the substrate 302.

[0080] After constructing substrate 302, one or more packages are formed around substrate 302 using substrate 302 as a framework. Figures 9 and 11 illustrate flowcharts of representative methods 900 and 1100 for fabricating intermediate in-cell die assembly 1002 around substrate 302 prior to final package formation. Figures 10A to 10K schematically illustrate cross-sectional views of substrate 302 at different stages of method 900 depicted in Figure 9, and Figures 12A to 12G schematically illustrate cross-sectional views of substrate 302 at different stages of method 1100 depicted in Figure 11. For clarity, Figures 9 and 10A to 10K are described together herein, and Figures 11 and 12A to 12G are described together herein.

[0081] Generally, method 900 begins with operation 902 and Figure 10A, wherein a first side 1075 of substrate 302, having the desired features formed therein (e.g., surface 606, which may have an oxide layer or metal overlay formed thereon), is placed on a first insulating film 1016a. In some embodiments, the first insulating film 1016a comprises one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 1016a comprises one or more layers formed of a flowable stacking material. In the embodiment depicted in Figure 10A, the first insulating film 1016a includes a flowable layer 1018a. The flowable layer 1018a may be formed of an epoxy resin containing ceramic fillers, such as an epoxy resin filled with (e.g., containing) silica (SiO2) particles. Other examples of ceramic fillers or particles that can be used to form the other layers of the flowable layer 1018a and the insulating film 1016a include aluminum nitride (AlN), alumina (Al₂O₃), silicon carbide (SiC), silicon nitride (Si₃N₄), Sr₂Ce₂Ti₅O₁₆, zirconium silicate (ZrSiO₄), wollastonite (CaSiO₃), beryllium oxide (BeO), cerium dioxide (CeO₂), boron nitride (BN), calcium copper titanium oxide (CaCu₃Ti₄O₁₂), magnesium oxide (MgO), titanium dioxide (TiO₂), zinc oxide (ZnO), and the like. In some examples, the ceramic filler used to form the flowable layer 1018a has particles with a size ranging from about 40 nm to about 1.5 μm, such as those between about 80 nm and about 1 μm. For example, the ceramic filler used to form the flowable layer 1018a has particles with a size range between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm. In some embodiments, the ceramic filler used to form the flowable layer 1018a includes particles having a size less than about 25% of the width or diameter of the desired feature (e.g., a mesoscopic window, cavity, or through-assembly mesoscopic window), such as less than about 15% of the width or diameter of the desired feature.

[0082] The flowable layer 1018a typically has a thickness of less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the flowable layer 1018a has a thickness between about 10 μm and about 25 μm. In some embodiments, the insulating film 1016a further includes one or more support layers. For example, the insulating film 1016a includes a polyethylene terephthalate (PET) or similar lightweight plastic support layer 1022a. However, any suitable combination of layers and insulating materials is contemplated for use in the insulating film 1016a. In some embodiments, the entire insulating film 1016a has a thickness of less than about 120 μm, such as less than about 90 μm.

[0083] The substrate 302 (coupled to an insulating film 1016a on its first side 1075, and specifically, a flowable layer 1018a coupled to the insulating film 1016a) may further be placed, as appropriate, on a carrier 1024 for providing mechanical support during subsequent processing operations. This carrier is formed of any suitable mechanically and thermally stable material. For example, the carrier 1024 is formed of polytetrafluoroethylene (PTFE). In another example, the carrier 1024 is formed of PET.

[0084] At operation 904 and depicted in Figure 10B, one or more semiconductor dies 1026 are placed within a cavity 305 formed in the substrate 302, such that the semiconductor die 1026 is now bound on one side (a single semiconductor die 1026 is depicted in Figure 10B) by an insulating film 1016a. In some embodiments, the die 1026 is a multi-purpose die having integrated circuitry formed on its active surface 1028. The die 1026 is placed within the cavity 305 and positioned on the surface of the insulating film 1016a exposed through the cavity 305. In some embodiments, the die 1026 is placed on an adhesive layer (not shown) disposed on or formed on the insulating film 1016a.

[0085] After the die 1026 is placed within the cavity 305, a first protective film 1060 is placed on the second side 1077 (e.g., surface 608) of the substrate 302 at operation 906 and in Figure 10C. The protective film 1060 is coupled to the second side 1077 of the substrate 302 and faces the first insulating film 1016a such that it contacts and covers the active surface 1028 of the die 1026 disposed within the cavity 305. In some embodiments, the protective film 1060 is formed of a material similar to that of the support layer 1022a. For example, the protective film 1060 is formed of PET, such as biaxial PET. However, the protective film 1060 can be formed of any suitable protective material. In some embodiments, the protective film 1060 has a thickness between about 50 μm and about 150 μm.

[0086] At operation 908, substrate 302 is exposed to the lamination process. The substrate 302 now has an insulating film 1016a fixed on a first side 1075 and a protective film 1060 fixed on a second side 1077, and further has a die 1026 disposed therein. During the lamination process, substrate 302 is exposed to high temperatures, causing the flowable layer 1018a of the insulating film 1016a to soften and flow into open pores or volumes between the insulating film 1016a and the protective film 1060, such as into the interlayer windows 303 and gaps 1051 between the inner wall of cavity 305 and the die 1026. Therefore, the semiconductor die 1026 becomes at least partially embedded within the materials of the insulating film 1016a and substrate 302, as depicted in Figure 10D.

[0087] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a cycle between about 5 seconds and about 1.5 minutes, such as between about 30 seconds and about 1 minute. In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 50 psig while simultaneously applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1016a for a cycle between about 5 seconds and about 1.5 minutes. For example, the lamination process is performed at a pressure between about 5 psig and about 40 psig and a temperature between about 100°C and about 120°C for a cycle between about 10 seconds and about 1 minute. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 20 seconds.

[0088] At operation 910, the protective film 1060 is removed and the substrate 302 (now with the laminated insulating material of the flowable layer 1018a at least partially surrounding the substrate 302 and one or more grains 1026) is placed on the second protective film 1062. As depicted in Figure 10E, the second protective film 1062 is coupled to a first side 1075 of the substrate 302 such that the second protective film 1062 is disposed abutting against (e.g., adjacent to) the insulating film 1016a. In some embodiments, the substrate 302 (now coupled to the protective film 1062) may be placed on a carrier 1024 for providing additional mechanical support on the first side 1075, as appropriate. In some embodiments, the protective film 1062 is placed on the carrier 1024 before being coupled to the substrate 302, and the protective film 1062 is now laminated together with the insulating film 1016a. Generally, protective film 1062 is substantially similar in composition to protective film 1060. For example, protective film 1062 may be formed from PET, such as biaxial PET. However, protective film 1062 may be formed from any suitable protective material. In some embodiments, protective film 1062 has a thickness between about 50 μm and about 150 μm.

[0089] After coupling the substrate 302 to the second protective film 1062, at operation 912 and in Figure 10F, a second insulating film 1016b, substantially similar to the first insulating film 1016a, is placed on the second side 1077 of the substrate 302, thereby replacing the protective film 1060. In some embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that the flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the grains 1026 within the cavity 305. In some embodiments, placing the second insulating film 1016b on the substrate 302 may form one or more pores between the insulating film 1016b and the laminated insulating material partially surrounding the flowable layer 1018a of one or more grains 1026. The second insulating film 1016b may comprise one or more layers formed of a flowable, polymer-based dielectric material. As depicted in Figure 10F, the second insulating film 1016b includes a flowable layer 1018b, which is similar to the flowable layer 1018a described above. The second insulating film 1016b may further include a support layer 1022b formed of a material similar to the support layer 1022a (such as PET or other lightweight plastic materials).

[0090] At operation 914, a third protective film 1064 is placed on top of the second insulating film 1016b, as depicted in Figure 10G. Generally, the protective film 1064 is substantially similar in composition to protective films 1060 and 1062. For example, the protective film 1064 is formed of PET, such as biaxial PET. However, the protective film 1064 can be formed of any suitable protective material. In some embodiments, the protective film 1064 has a thickness between about 50 μm and about 150 μm.

[0091] In operation 916 and Figure 10H, substrate 302 is exposed to the second lamination process. Now, the substrate 302 has an insulating film 1016b and a support layer 1064 fixed on the second side 1077, and a protective film 1062 and an optional carrier 1024 fixed on the first side 1075. Similar to the lamination process in operation 908, substrate 302 is exposed to high temperatures, causing the flowable layer 1018b of the insulating film 1016b to soften and flow into any open pores or volumes between the insulating film 1016b and the laminated insulating material of the flowable layer 1018a, thereby integrating itself with the insulating material of the flowable layer 1018a. Therefore, cavity 305 and interlayer window 303 become filled (e.g., packaged, sealed) with insulating material, and the semiconductor die 1026 previously placed within cavity 305 becomes completely embedded within the insulating material of the flowable layers 1018a and 1018b.

[0092] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a cycle between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10 psig and about 150 psig while simultaneously applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1016b for a cycle between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 20 psig and about 100 psig and a temperature between about 100°C and about 120°C for a cycle between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 5 minutes.

[0093] Following lamination, at operation 918, the substrate 302 is detached from the carrier 1024 and the protective films 1062, 1064 are removed, resulting in a laminated embedded die assembly 1002. As depicted in Figure 10I, the embedded die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or interlayer windows 303 formed therein and filled with a flowable layer 1018a, 1018b of insulating dielectric material, and an embedded die 1026 within the cavity 305. The insulating dielectric material of the flowable layers 1018a, 1018b covers the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302 (e.g., the two main surfaces 606, 608) and all sides of the embedded semiconductor die 1026. In some instances, support layers 1022a and 1022b are also removed from the embedded die assembly 1002 at operation 918. Generally, support layers 1022a and 1022b, carrier 1024, and protective films 1062 and 1064 are removed from the embedded die assembly 1002 by any appropriate mechanical process such as stripping them.

[0094] After removing the support layers 1022a, 1022b and the protective films 1062, 1064, the embedded die assembly 1002 is exposed to a curing process to allow the insulating dielectric material of the flowable layers 1018a, 1018b to be fully cured (i.e., through chemical reaction and cross-linking), thereby forming a cured insulating layer 1018. The insulating layer 1018 generally surrounds the substrate 302 and the semiconductor die 1026 embedded therein. For example, the insulating layer 1018 contacts or encapsulates at least 1075, 1077 of the substrate 302 (including surfaces 606, 608) and at least six sides or surfaces of each semiconductor die 1026 having a rectangular prism shape, as illustrated in Figure 10I (i.e., only four surfaces 1028 and 1029 are shown in the 2D view).

[0095] In some embodiments, a curing process is performed at a high temperature to fully cure the embedded die component 1002. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a cycle between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a cycle between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a cycle of about 30 minutes. In another embodiment, the curing process at operation 918 is performed under or near ambient (e.g., atmospheric) pressure conditions.

[0096] After curing, at operation 920, one or more through-device vias 1003 are drilled through the embedded die assembly 1002 to form channels through the entire thickness of the embedded die assembly 1002 for subsequent interconnect formation. In some embodiments, the embedded die assembly 1002 may be placed on a carrier (such as carrier 1024) to provide mechanical support during the formation of the through-device vias 1003 and subsequent contact holes 1032. The through-device vias 1003 are drilled through vias 303 that have been formed in the substrate 302 and subsequently filled with an insulating layer 1018. Thus, the through-device vias 1003 may be circumferentially surrounded by the insulating layer 1018 filled within the vias 303. By lining the insulating layer 1018 with ceramic-filled epoxy resin material on the walls of the interlayer window 303, compared with other conventional interconnect structures utilizing conventional interlayer window insulating liners or films, the capacitive coupling between the conductive silicon-based substrate 302 and the interconnect 1444 (described with reference to Figures 13 and 14E to 14H), and (therefore) the capacitive coupling between adjacently positioned interlayer windows 303 and / or redistribution connectors 1644 (described with reference to Figures 15 and 16H to 16L), is significantly reduced in the completed package 1602 (refer to Figures 15 and 16H to 16L). Furthermore, the flowable nature of the epoxy resin material enables more consistent and reliable encapsulation and insulation, thereby enhancing electrical performance by minimizing leakage current in the completed package 1602.

[0097] In some embodiments, the through-device interface window 1003 has a diameter of less than about 100 μm, such as less than about 75 μm. For example, the through-device interface window 1003 has a diameter of less than about 60 μm, such as less than about 50 μm. In some embodiments, the through-device interface window 1003 has a diameter between about 25 μm and about 50 μm, such as between about 35 μm and about 40 μm. In some embodiments, the through-device interface window 1003 is formed using any suitable mechanical process. For example, the through-device interface window 1003 is formed using a mechanical drilling process. In some embodiments, the through-device interface window 1003 is formed through the embedded die device 1002 by laser ablation. For example, the through-device interface window 1003 is formed using an ultraviolet laser. In some embodiments, the laser source for laser ablation has a frequency between about 5 kHz and about 500 kHz. In some embodiments, the laser source is configured to deliver a pulsed laser beam with a pulse duration between approximately 10 ns and approximately 100 ns, wherein the pulse energy is between approximately 50 microjoules (μJ) and approximately 500 μJ. The use of epoxy resin materials with small ceramic filler particles further facilitates more precise and accurate laser patterning of small-diameter mesoscopic windows (such as mesoscopic window 1003), as the small ceramic filler particles exhibit reduced laser light reflection, scattering, diffraction, and transmission away from the area where the mesoscopic window will be formed during the laser ablation process.

[0098] In operation 922 and Figure 10K, one or more contact holes 1032 are drilled through the insulating layer 1018 to expose one or more contacts 1030 formed on the active surface 1028 of each embedded die 1026. By laser ablation, the contact holes 1032 are drilled through the insulating layer 1018, such that all outer surfaces of the semiconductor die 1026 are covered and surrounded by the insulating layer 1018, and the contacts 1030 are exposed. Thus, the contacts 1030 are exposed by forming the contact holes 1032. In some embodiments, the laser source may generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In some embodiments, the laser source is configured to deliver a pulsed laser beam with a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and a pulse energy between about 10 μJ and about 300 μJ. In some embodiments, CO2, green light, or UV laser is used to drill the contact hole 1032. In some embodiments, the contact hole 1032 has a diameter between about 5 μm and about 60 μm, such as a diameter between about 20 μm and about 50 μm.

[0099] After the contact hole 1032 is formed, the embedded die assembly 1002 is exposed to a decontamination process at operation 922 to remove any unwanted residues and / or debris resulting from laser ablation during the formation of the through-device interface window 1003 and the contact hole 1032. The decontamination process thus cleans the through-device interface window 1003 and the contact hole 1032 and fully exposes the contacts 1030 on the active surface 1028 of the embedded die 1026 for subsequent metallization. In some embodiments, the decontamination process is a wet decontamination process. Any suitable aqueous etchant, solvent, and / or combination thereof can be used in the wet decontamination process. In one example, a potassium permanganate (KMnO4) solution can be used as the etchant. Depending on the residue thickness, the exposure of the embedded die assembly 1002 to the wet decontamination process at operation 922 can be varied. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process can be a plasma decontamination process using an O2:CF4 gas mixture. The plasma decontamination process may involve generating plasma by applying a power of approximately 700 W and allowing O2:CF4 to flow at a ratio of approximately 10:1 (e.g., 100:10 sccm) for a time period between approximately 60 seconds and approximately 120 seconds. In another embodiment, the decontamination process is a combination of wet and dry processes.

[0100] After the cleaning process at operation 922, the embedded die assembly 1002 is ready for forming interconnect paths therein, as described below with reference to Figures 13 and 14A to 14H.

[0101] As described above, Figures 9 and 10A through 10K illustrate a representative method 900 for forming an intermediate embedded die assembly 1002. Figures 11 and 12A through 12G illustrate an alternative method 1100, which is generally similar to method 900 but has fewer operations. Method 1100 generally comprises seven operations 1110 to 1170. However, operations 1110, 1120, 1160, and 1170 of method 1100 are generally similar to operations 902, 904, 920, and 922 of method 900, respectively. Therefore, for clarity, only operations 1130, 1140, and 1150 (described in Figures 12C, 12D, and 12E, respectively) are described herein.

[0102] After one or more semiconductor dies 1026 are placed onto the surface of the insulating film 1016a exposed via cavity 305, prior to lamination, at operation 1130 and in Figure 12C, a second insulating film 1016b is positioned on a second side 1077 (e.g., surface 608) of the substrate 302. In some embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that a flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 within cavity 305. In some embodiments, a second carrier 1025 is attached to a support layer 1022b of the second insulating film 1016b to provide additional mechanical support during subsequent processing operations. As depicted in Figure 12C, one or more holes 1050 are formed between insulating films 1016a and 1016b via a mesoscopic window 303 and a gap 1051 between the semiconductor grain 1026 and the inner wall of the cavity 305.

[0103] In operation 1140 and Figure 12D, substrate 302 is exposed to a single lamination process. Substrate 302 is now fixed to insulating films 1016a and 1016b and has a die 1026 disposed therein. During the single lamination process, substrate 302 is exposed to high temperatures, causing the flowable layers 1018a and 1018b of insulating films 1016a and 1016b to soften and flow into open pores or volumes between insulating films 1016a and 1016b, such as into the interlayer window 303 and gap 1051 between the inner wall of cavity 305 and the die 1026. Therefore, the semiconductor die 1026 becomes embedded within the materials of insulating films 1016a and 1016b and within the interlayer window 303 filled with that material.

[0104] Similar to the lamination process described with reference to Figures 9 and 10A through 10K, the lamination process at operation 1140 can be a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In another embodiment, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a cycle between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 150 psig while simultaneously applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film layers 1016a and 1016b for a cycle between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 psig and about 100 psig and a temperature between about 100°C and about 120°C for a cycle between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of approximately 110°C and takes about 5 minutes.

[0105] At operation 1150, one or more support layers of insulating films 1016a and 1016b are removed from substrate 302, resulting in a laminated in-die assembly 1002. As depicted in Figure 12E, the in-die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or interlayer windows 303 formed therein and filled with a flowable layer 1018a, 1018b of insulating dielectric material, and an in-die 1026 within the cavity 305. The insulating material covers the substrate 302 such that it covers at least two surfaces or sides of the substrate 302, for example, surfaces 606, 608. In one example, support layers 1022a, 1022b are removed from the in-die assembly 1002, thereby detaching the in-die assembly 1002 from the carriers 1024, 1025. Generally, the support layers 1022a, 1022b and the carriers 1024, 1025 are removed by any appropriate mechanical process, such as peeling them off.

[0106] After removing the support layers 1022a and 1022b, the embedded die assembly 1002 is exposed to the curing process to allow the insulating dielectric material of the flowable layers 1018a and 1018b to fully cure. Curing the insulating material results in the formation of a cured insulating layer 1018. As depicted in Figure 12E and similar to operation 918 corresponding to Figure 10I, the insulating layer 1018 generally surrounds the substrate 302 and the semiconductor die 1026 embedded therein.

[0107] In some embodiments, a curing process is performed at a high temperature to fully cure the embedded die component 1002. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a cycle between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a cycle between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a cycle of about 30 minutes. In another embodiment, the curing process at operation 1150 is performed under or near ambient (e.g., atmospheric) pressure conditions.

[0108] Following curing at operation 1150, method 1100 is generally similar to operations 920 and 922 of method 900. For example, the embedded die assembly 1002 has one or more through-device interface windows 1003 and one or more contact holes 1032 that penetrate the insulating layer 1018. Subsequently, the embedded die assembly 1002 is exposed to a cleaning process, after which the embedded die assembly 1002 is prepared for forming interconnect paths therein, as described below.

[0109] Figure 13 illustrates a flowchart of a representative method 1300 for forming electrical interconnects through the embedded die assembly 1002. Figures 14A through 14H schematically illustrate cross-sectional views of the embedded die assembly 1002 at different stages of the process of method 1300 depicted in Figure 13. Therefore, for clarity, Figures 13 and 14A through 14H are described together herein.

[0110] In some embodiments, the electrical interconnects formed through the embedded die assembly 1002 are made of copper. Therefore, method 1300 may begin as operation 1310 and Figure 14A, where the embedded die assembly 1002 (having through-device interface window 1003 and contact via 1032 formed therein) has an adhesive layer 1440 and / or a seed layer 1442 formed thereon. Figure 14H depicts an enlarged partial view of the adhesive layer 1440 and seed layer 1442 formed on the embedded die assembly 1002 for reference. An adhesive layer 1440 may be formed on desired surfaces of the insulating layer 1018 (such as the primary surfaces 1005, 1007 of the embedded die assembly 1002) and on the active surfaces 1028 of the contact holes 1032 on each die 1026 and on the inner walls of the through-assembly interlayer windows 1003 to facilitate adhesion and block the diffusion of the subsequently formed seed layer 1442 and copper interconnects 1444. Therefore, in some embodiments, the adhesive layer 1440 functions as an adhesive layer; in another embodiment, the adhesive layer 1440 functions as a barrier layer. However, in both embodiments, the adhesive layer 1440 will be described hereinafter as an "adhesive layer".

[0111] In some embodiments, the optional adhesive layer 1440 may be formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In some embodiments, the adhesive layer 1440 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the adhesive layer 1440 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesive layer 1440 may be formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or the like.

[0112] The seed layer 1442 may be formed on the adhesive layer 1440 or directly on the insulating layer 1018 (e.g., without forming the adhesive layer 1440). The seed layer 1442 is formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In some embodiments, the seed layer 1442 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the seed layer 1442 has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In some embodiments, the seed layer 1442 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesive layer 1440, the seed layer 1442 is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, or the like. In some embodiments, a molybdenum adhesion layer 1440 is formed on the embedded die assembly, combined with a copper seed layer 1442. The combination of Mo-Cu adhesion and seed layer enables improved adhesion to the surface of the insulating layer 108 and reduces undercutting of conductive interconnects during subsequent seed layer etching processes at operation 1370.

[0113] At operations 1320 and 1330 (corresponding to Figures 14B and 14C, respectively), a spin-coated / spray-coated or dry resist film 1450 (such as a photoresist) is coated onto the two main surfaces 1005 and 1007 of the embedded die assembly 1002, and subsequently patterned. In some embodiments, the resist film 1450 is patterned by selective exposure to UV radiation. In some embodiments, an adhesion promoter (not shown) is coated onto the embedded die assembly 1002 prior to the formation of the resist film 1450. The adhesion promoter improves the adhesion between the resist film 1450 and the embedded die assembly 1002 by creating an interfacial adhesive layer for the resist film 1450 and by removing any moisture from the surface of the embedded die assembly 1002. In some embodiments, the adhesion promoter is formed from bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0114] In operation 1340 and Figure 14D, the embedded die assembly 1002 is exposed to a resist film development process. As depicted in Figure 14D, the development of the resist film 1450 results in the exposure of the through-assembly interface window 1003 and contact via 1032, on which the adhesive layer 1440 and seed layer 1442 are now formed. In some embodiments, the film development process is a wet process, such as a wet process that includes exposing the resist to a solvent. In some embodiments, the film development process is a wet etching process utilizing an aqueous etching process. In other embodiments, the film development process is a wet etching process utilizing a buffered etching process selective for the desired material. Any suitable combination of wet solvents or wet etchants can be used in the resist film development process.

[0115] At operations 1350 and 1360 (corresponding to Figures 14E and 14F, respectively), interconnects 1444 are formed via the exposed through-assembly vias 1003 and contact holes 1032, and then the resist film 1450 is removed. Interconnects 1444 are formed by any suitable method, including electroplating and electrodeposition. In some embodiments, the resist film 1450 is removed via a wet process. As depicted in Figures 14E and 14F, after removal of the resist film 1450, the formed interconnects 1444 fill the through-assembly vias 1003 and contact holes 1032 and / or cover their inner circumferential walls and protrude from surfaces 1005, 1007, and 1028 of the embedded die assembly 1003. In some embodiments, interconnects 1444 are formed of copper. In other embodiments, interconnect 1444 may be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin or the like.

[0116] In operation 1370 and Figure 14G, the embedded die assembly 1002 having interconnects 1444 formed therein is exposed to an adhesive layer and / or seed layer etching process to remove the adhesive layer 1440 and the seed layer 1442. In some embodiments, the seed layer etching is a wet etching process, which includes rinsing and drying the embedded die assembly 1002. In some embodiments, the seed layer etching process is a buffered etching process selective for the desired material (such as copper, tungsten, aluminum, silver, or gold). In other embodiments, the etching process is an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the seed layer etching process.

[0117] After the seed layer etching process at 1370, one or more electrically functional packages can be singled from the embedded die assembly 1002. Alternatively, the embedded die assembly 1002 may have one or more redistribution layers 1658 and / or 1660 (shown in Figures 16K to 16L) formed thereon as needed, so that the contacts of the interconnect 1444 can be rerouted to desired locations on the surface of the embedded die assembly 1002. Figure 15 illustrates a flowchart of a representative method 1500 for forming the redistribution layer 1658 on the embedded die assembly 1002. Figures 16A to 16L schematically illustrate cross-sectional views of the embedded die assembly 1002 at different stages of the method 1500 depicted in Figure 15. Therefore, for clarity, Figures 15 and 16A to 16L are described together herein.

[0118] Method 1500 is generally similar to methods 900, 1100, and 1300 described above. Generally, method 1500 begins with operation 1502 and Figure 16A, where an insulating film 1616 is placed on the embedded die assembly 1002 and subsequently laminated. The insulating film 1616 may be generally similar to insulating film 1016 and includes one or more layers formed of a polymer-based flowable dielectric material. In some embodiments, as depicted in Figure 16A, the insulating film 1616 includes a flowable layer 1618 and one or more support layers 1622. In some embodiments, the insulating film 1616 may include an epoxy resin flowable layer 1618 containing ceramic filler and one or more support layers 1622. In another example, the insulating film 1616 may include a light-definable polyimide flowable layer 1618 and one or more support layers 1622. The light-definable material properties of polyimide enable the formation of smaller (e.g., narrower) interlayer windows through the resulting interconnect layers. However, any suitable combination of layers and insulating materials is contemplated for use in the insulating film 1616. For example, the insulating film 1616 may comprise a non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and / or silicon nitride flowable layers 1618. Examples of suitable materials for one or more support layers 1622 include PET and polypropylene (PP).

[0119] In some instances, the flowable layer 1618 comprises a polymer-based flowable dielectric material different from the flowable layers 1018a and 1018b described above. For example, flowable layer 1018 may comprise an epoxy resin containing ceramic fillers, and flowable layer 1618 may comprise a photodefinable polyimide. In another instance, flowable layer 1618 is formed of an inorganic dielectric material different from flowable layers 1018a and 1018b. For example, flowable layers 1018a and 1018b may comprise an epoxy resin containing ceramic fillers, and flowable layer 1618 may comprise a silicon dioxide layer.

[0120] The insulating film 1616 has a thickness of less than about 200 μm, such as between about 10 μm and about 180 μm. For example, the insulating film 1616 having a flowable layer 1618 and a PET support layer 1622 has a total thickness between about 50 μm and about 100 μm. In some embodiments, the flowable layer 1618 has a thickness of less than about 60 μm, such as between about 5 μm and about 50 μm, such as about 20 μm. The insulating film 1616 is placed on the surface of an embedded die assembly 1002 having exposed interconnects 1444, which are coupled to contacts 1030 on the active surface 1028 of the die 1026 and / or coupled to metallized through-assembly interlayer windows 1003, such as the main surface 1005.

[0121] After the insulating film 1616 is placed, the embedded die assembly 1002 is exposed to a lamination process generally similar to that described in reference operations 908, 916, and 1140. The embedded die assembly 1002 is exposed to a high temperature to soften the flowable layer 1618, which is then bonded to the insulating layer 1018 formed on the embedded die assembly 1002. Thus, in some embodiments, the flowable layer 1618 becomes integrated with the insulating layer 1018 and forms an extension thereto. The integration of the flowable layer 1618 with the insulating layer 1018 results in an extended and integrated insulating layer 1018 covering the previously exposed interconnect 1444. Therefore, the bonded flowable layer 1618 and the insulating layer 1018 will be collectively described herein as the insulating layer 1018. However, in other embodiments, the lamination and subsequent curing of the flowable layer 1618 forms a second insulating layer (not shown) on the insulating layer 1018. In some instances, this second insulating layer is formed of a material layer different from the insulating layer 1018.

[0122] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a cycle between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10 psig and about 100 psig while simultaneously applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1616 for a cycle between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 30 psig and about 80 psig and a temperature between about 100°C and about 120°C for a cycle between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 5 minutes. In another instance, lamination processes were performed at pressures between approximately 30 psig and approximately 70 psig, such as approximately 50 psig.

[0123] In operation 1504 and Figure 16, the support layer 1622 and carrier 1624 are removed from the embedded die assembly 1002 by a mechanical process. After removal of the support layer 1622 and carrier 1624, the embedded die assembly 1002 is exposed to a curing process to allow the newly extended insulating layer 1018 to fully cure. In some embodiments, the curing process is generally similar to the curing processes described with reference to operations 918 and 1150. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a cycle between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a cycle between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a cycle of about 30 minutes. In another embodiment, the curing process at operation 1504 is performed under or near ambient pressure conditions.

[0124] Next, in operation 1506 and Figure 16C, the embedded die assembly 1002 is selectively patterned by laser ablation. Laser ablation at operation 1506 forms a redistribution interface window 1603 through the newly extended insulating layer 1018 and exposes the desired interconnects 1444 for redistribution of their contacts. In some embodiments, the redistribution interface window 1603 has a diameter between about 5 μm and about 60 μm, such as a diameter between about 10 μm and about 50 μm, such as a diameter between about 20 μm and about 45 μm. In some embodiments, the laser ablation process at operation 1506 is performed using a CO2 laser. In some embodiments, the laser ablation process at operation 1506 is performed using a UV laser. In some embodiments, the laser ablation process at operation 1506 is performed using a green laser. For example, a laser source can generate a pulsed laser beam with a frequency between about 100 kHz and about 1000 kHz. In one instance, the laser source is configured to deliver a pulsed laser beam with a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and a pulse energy between about 10 μJ and about 300 μJ.

[0125] After patterning the embedded die assembly 1002, the embedded die assembly 1002 is exposed to a decontamination process generally similar to the decontamination processes at operations 922 and 1170. During the decontamination process at operation 1506, unwanted residues and debris formed by laser ablation during the formation of the redistribution interlayer window 1603 are removed from the redistribution interlayer window 1603 to clean (e.g., clean) its surface for subsequent metallization. In some embodiments, the decontamination process is a wet process. Any suitable aqueous etchant, solvent, and / or combination thereof can be used for the wet decontamination process. In one example, a KMnO4 solution can be used as the etchant. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process can be a plasma decontamination process performed using an O2 / CF4 gas mixture. In other embodiments, the decontamination process is a combination of wet and dry processes.

[0126] In operation 1508 and Figure 16D, an optional adhesive layer 1640 and / or seed layer 1642 are formed on the insulating layer 1018. In some embodiments, the adhesive layer 1640 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In some embodiments, the adhesive layer 1640 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the adhesive layer 1640 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesive layer 1640 can be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, or the like.

[0127] The seed layer 1642 may be formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In some embodiments, the seed layer 1642 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the seed layer 1642 has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In some embodiments, the seed layer 1642 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesive layer 1640, the seed layer 1642 may be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, or the like. In some embodiments, a molybdenum adhesive layer 1640 and a copper seed layer 1642 are formed on the embedded die assembly 1002 to reduce undercutting of conductive interconnects during subsequent seed layer etching processes at operation 1520.

[0128] At operations 1510, 1512, and 1514 (corresponding to Figures 16E, 16F, and 16G, respectively), a spin-coated / spray-coated or dry resist film 1650 (such as a photoresist) is applied over the adhesion and / or seed surface of the embedded die assembly 1002, followed by patterning and development. In some embodiments, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 prior to the placement of the resist film 1650. Exposure and development of the resist film 1650 results in the opening of the redistribution interlayer window 1603. Thus, patterning of the resist film 1650 can be performed by selectively exposing multiple portions of the resist film 1650 to UV radiation and subsequently developing the resist film 1650 by a wet process (such as a wet etching process). In some embodiments, the resist film development process is a wet etching process utilizing a buffered etching process that is selective for the desired material. In other embodiments, the resist film development process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the resist film development process.

[0129] At operations 1516 and 1518 (corresponding to Figures 16H and 16I, respectively), a redistribution connector 1644 is formed through the exposed redistribution interface window 1603, and thereafter the resist film 1650 is removed. The redistribution connector 1644 is formed by any suitable method, including electroplating and electrodeposition. In some embodiments, the resist film 1650 is removed via a wet process. As depicted in Figures 16H and 16I, after the removal of the resist film 1650, the redistribution connector 1644 fills the redistribution interface window 1603 and protrudes from the surface of the embedded die assembly 1002. In some embodiments, the redistribution connector 1644 is formed of copper. In other embodiments, the redistribution connector 1644 may be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, or the like.

[0130] In operation 1520 and Figure 16J, the embedded die assembly 1002 having the redistribution connector 1644 formed thereon is exposed to a seed layer etching process generally similar to the seed layer etching process of operation 1370. In some embodiments, the seed layer etching is a wet etching process, which includes rinsing and drying the embedded die assembly 1002. In some embodiments, the seed layer etching process is a wet etching process utilizing a buffered etching process selectively applied to the desired material of the seed layer 1642. In other embodiments, the etching process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the seed layer etching process.

[0131] At operation 1522, as depicted in Figures 16K and 16L, one or more finished packages 1602 are singled from the embedded die assembly 1002. However, prior to operation 1522, additional redistribution layers may be formed on the embedded die assembly 1002 using the sequence and processes described above, as depicted in Figure 16L (Figure 16K depicts a finished package 1602 with an additional redistribution layer 1658). For example, one or more additional redistribution layers 1660 may be formed on the side or surface (e.g., main surface 1007) of the embedded die assembly 1002 opposite to the first additional redistribution layer 1658. Alternatively, one or more additional redistribution layers 1660 may be formed on the same side or surface (e.g., main surface 1005) as the first additional redistribution layer 1658 (not shown). After all the required redistribution layers have been formed, the finished package 1602 may then be singled from the embedded die assembly 1002.

[0132] Figure 17 illustrates a flowchart of an alternative method 1700 for placing and laminating an insulating layer onto the embedded die assembly 1002 during the formation of the redistribution layer. Figures 18A to 18C schematically illustrate cross-sectional views of the embedded die assembly 1002 at different stages of method 1700. Therefore, for clarity, Figures 17 and 18A to 18C are described together herein. Note that after performing operations 1702 to 1706 of method 1700, operations 1508 to 1522 of method 1500 may be performed to complete the formation of the redistribution layer, such as depositing an adhesive and / or seed layer, electroplating redistribution connectors, etc.

[0133] Method 1700 is generally similar to one or more of the methods described above. Typically, method 1700 begins with operation 1702 and Figure 18A, where a pre-constructed insulating film 1816 is aligned and placed on the embedded die assembly 1002. Similar to the insulating films 1616 and 1016 described above, insulating film 1816 may comprise one or more layers formed of a polymer-based flowable dielectric material. For example, in some embodiments, insulating film 1816 includes a flowable layer 1818 and one or more support layers 1822. In some embodiments, insulating film 1816 includes an epoxy resin flowable layer 1818 containing ceramic filler and one or more support layers 1822. In another example, insulating film 1816 includes a light-definable polyimide flowable layer 1818 and one or more support layers 1822. However, any suitable combination of layers and insulating materials is contemplated for use in insulating film 1816, such as those described above with reference to insulating films 1616 and 1016. For example, in some embodiments, flowable layer 1818 may be formed of non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and / or silicon nitride. Examples of suitable materials for one or more support layers 1822 include PET, PP, polyethylene (PE) polycarbonate, polystyrene, and the like.

[0134] In some instances, the flowable layer 1818 is formed of a polymer-based flowable dielectric material different from that of flowable layers 1018a and 1018b. For example, flowable layers 1018a and 1018b may include an epoxy resin layer containing ceramic fillers, while flowable layer 1818 may include a photodefinable polyimide layer, or vice versa. In another instance, the flowable layer 1818 is formed of an inorganic dielectric material different from that of flowable layers 1018a and 1018b. For example, flowable layers 1018a and 1018b may include an epoxy resin layer containing ceramic fillers, and flowable layer 1818 may include a silicon dioxide layer, or vice versa.

[0135] The flowable layer 1818 typically has a thickness of less than about 120 μm, such as between about 10 μm and about 100 μm. For example, the flowable layer 1818 has a thickness between about 20 μm and about 80 μm. In some embodiments, the entire insulating film 1816 has a thickness of less than about 200 μm, such as less than about 160 μm.

[0136] However, unlike previous examples of insulating films, the insulating film 1816 is pre-constructed, i.e., constructed before being placed and laminated onto the embedded die assembly 1002. For example, the insulating film 1816 has one or more interlayer windows 1803 formed therein for subsequent electroplating of the redistribution connectors, wherein the sidewalls of the interlayer windows 1803 are selectively cured. The pre-construction of the insulating film 1816 is described in more detail with reference to Figures 19, 20A-20C, and 21A-21B. Therefore, during the placement of the insulating film 1816 onto the embedded die assembly 1002, the insulating film 1816 is aligned with the embedded die assembly 1002 such that the pre-constructed interlayer windows 1803 are aligned with the contact points or pads of the interconnect 1444, thereby enabling the connection of the interconnect 1444 to the subsequently formed redistribution connectors. In some embodiments, the insulating film 1816 has one or more reference marks formed thereon to facilitate alignment with the embedded die assembly 1002, which may have one or more corresponding reference marks (e.g., etched areas or deposited material areas) formed on its mating surface. However, any suitable alignment method is contemplated.

[0137] In operation 1704 and Figure 18B, after the pre-constructed insulating film 1816 is placed, the embedded die assembly 1002 is exposed to a lamination process generally similar to the lamination process described above. The embedded die assembly 1002 is thus exposed to high temperatures to soften the flowable layer 1818, which is then bonded to the insulating layer 1018 already formed on the embedded die assembly 1002. Therefore, in some embodiments, the flowable layer 1818 becomes integrated with the insulating layer 1018 and forms an extension thereto. The integration of the flowable layer 1818 with the insulating layer 1018 results in an extended and integrated insulating layer 1018 covering the previously exposed interconnect 1444. Therefore, the bonded flowable layer 1818 and the insulating layer 1018 will be collectively described herein as the insulating layer 1018. However, in other embodiments, the lamination of the flowable layer 1818 forms a second insulating layer (not shown) on the insulating layer 1018. In some instances, the second insulating layer is formed of a different material than insulating layer 1018. In some embodiments, the second insulating layer may have material properties related to structure, electricity, or composition that are different from those of insulating layer 1018. In other embodiments, the second insulating layer comprises the same material as insulating layer 1018 but has different structural properties (e.g., thickness).

[0138] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a cycle between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10 psig and about 100 psig while simultaneously applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1616 for a cycle between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 30 psig and about 80 psig and a temperature between about 100°C and about 120°C for a cycle between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 5 minutes. In another instance, lamination processes were performed at pressures between approximately 30 psig and approximately 70 psig, such as approximately 50 psig.

[0139] In operation 1706 and Figure 18C, the support layer 1822 is removed from the flowable layer 1818 laminated onto the embedded die assembly 1002 by a mechanical process. After removing the support layer 1822, in some embodiments, the embedded die assembly 1002 is exposed to a curing process to allow the newly extended insulating layer 1018 to fully cure. In some embodiments, the curing process is generally similar to the curing processes described above with reference to operations 918 and 1150. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a cycle between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a cycle between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a cycle of about 30 minutes. In another embodiment, the curing process at operation 1504 is performed under or near ambient pressure conditions.

[0140] Subsequently, as described above, operations 1508 to 1522 of method 1500 can be performed to complete the formation of the redistribution layer, such as depositing an adhesive and / or seed layer, electroplating redistribution connectors, etc.

[0141] Figure 19 illustrates a flowchart of a method 1900 for pre-constructing an insulating film before placement on, for example, an in-die assembly or other semiconductor device package structure, according to embodiments described herein. Figures 20A through 20C schematically illustrate cross-sectional views of the insulating film at different stages of the pre-construction method 1900 depicted in Figure 19. Therefore, for clarity, Figures 19 and 20A through 20C are described together herein.

[0142] Method 1900 begins with operation 1902 and the corresponding figure 20A, wherein an insulating film (e.g., insulating film 1816) is patterned via laser ablation to form one or more features, such as interlayer windows 1803, in its flowable layer. However, in some embodiments, the insulating film is patterned to form one or more features therein by lithography and development processes or mechanical stamping processes. Unless otherwise noted, the embodiments and examples described herein can be performed on any insulating sheet or film comprising a 10-100 μm thick flowable layer sandwiched between two or more support or cover / protective layers. In the examples shown in figures 20A through 20C, the insulating film 1816 includes a flowable layer 1818 attached to the support layer 1822 as described above, except for a cover layer 1824 adhered to the flowable layer 1818 on the side of the insulating film 1816 opposite to the support layer 1822. In some embodiments, the cover layer 1824 is made of a material similar to that of the support layer 1822. For example, the cover layer 1824 may be formed of a lightweight plastic material, such as PET, PP, PE, etc. The cover layer 1824 may be removed after the insulating film 1816 has been pre-constructed and before the insulating film 1816 is placed on, for example, an in-die assembly or other semiconductor device package structure.

[0143] Furthermore, the embodiments and examples described herein can be performed on a bulk or previously monolithized insulating film. For example, a pre-construction can be performed on a roll of insulating film, which can then be monolithized (e.g., at operation 1906) for batch or individual component placement and lamination.

[0144] As described above, the patterning of the insulating film 1816 can be achieved using a laser ablation system with any suitable type of laser source 2007. In some instances, the laser source 2007 is an infrared (IR) laser. In some embodiments, the laser source 2007 is a UV laser, such as a 355 nm UV laser or a 248 nm excimer UV laser. For example, the laser source 2007 may be a picosecond or femtosecond UV laser. In some embodiments, the laser source 2007 is a femtosecond green laser. In other embodiments, the laser source 2007 is a CO2 laser. The laser source 2007 can generate a continuous or pulsed laser beam 2010 for patterning the insulating film 1816. For example, in some embodiments, the laser source 2007 can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam with wavelengths between about 100 nm and about 2000 nm, pulse durations between about 10E-4 ns and about 10E-2 ns, and pulse energies between about 10 μJ and about 300 μJ.

[0145] Laser beam 2007 is configured to form any desired pattern and / or feature in insulating film 1816, including a permeable window 1803, which can be used for electroplating of electrical connections through flowable layer 1818. For example, laser source 2007 can be used to form permeable window 1803 having a diameter between about 5 μm and about 60 μm, such as a diameter between about 10 μm and about 50 μm, such as a diameter between about 20 μm and about 45 μm. Permeable window 1803 can be positioned through insulating film 1816 in any desired arrangement / location to achieve contact / coupling between the electrical connections subsequently electroplated in permeable window 1803 and interconnects and / or redistribution connections in, for example, in-die components or other semiconductor device package structures, after which insulating film 1816 is laminated.

[0146] Following patterning, the insulating film 1816 is exposed to a selective curing process at operation 1904 and in Figure 20B to selectively cure the sidewalls of any patterned features, thereby enabling the patterned features to maintain their morphology during subsequent operations. For example, the curing process at operation 1904 can be used to harden the sidewalls of the interphase window 1803 (shown as 2020 in Figure 20B) so that the interphase window 1803 maintains its morphology and structural integrity during the placement and lamination of the insulating film 1816 onto, for example, an in-die assembly 1002 (as described with reference to method 1700). Thus, the selective curing process prevents any patterned features in the insulating film 1816 from collapsing during, for example, placement and lamination.

[0147] Typically, the curing process can be performed at high temperatures, such as between about 140°C and about 220°C, between about 160°C and about 200°C, or about 180°C. In some embodiments, the curing process is a plasma curing process, wherein the patterned insulating film 1816 is exposed to a plasma comprising N₂, CH₄, H₂, CF₄, and / or O₂. In some other embodiments, the curing process is a UV curing process. The insulating film 1816 may be exposed to the curing process for cycles of about 1 second to about 60 seconds, such as a cycle of about 2 seconds to about 30 seconds, such as a cycle of about 5 seconds to about 20 seconds, or such as a cycle of about 10 seconds.

[0148] In operation 1906 and Figure 20C, the patterned and cured insulating film 1816 is individually standardized as appropriate for placement and lamination onto a semiconductor device package. However, in some embodiments, the insulating film 1816 is placed and laminated onto a batch or bulk semiconductor device package structure, and as described above, the insulating film 1816 can be individually standardized along with the semiconductor device package structure into individual packages (after further processing). In another embodiment, the insulating film 1816 is standardized prior to pre-construction.

[0149] In some embodiments where pre-construction is performed on a bulk insulating film, a roll-to-roll pre-construction apparatus is used to perform method 1900. Figures 21A and 21B schematically illustrate an exemplary roll-to-roll pre-construction apparatus 2100 for use during method 1900. Apparatus 2100 may include an unwinding module 2104, a winding module 2106, and one or more processing stations disposed therebetween. In the example of Figure 21A, apparatus 2100 is shown having three processing stations 2110, 2120, and 2130, each of which can be used to perform a separate operation of method 1900. For example, processing station 2110 may be a laser ablation system for performing operation 1902, as shown in Figure 21B; processing station 2120 may be a curing system (such as a processing chamber or oven) for performing operation 1904; and optionally, processing station 2130 may be a single station for performing operation 1906.

[0150] According to some embodiments, the unwinding module 2104 and the winding module 2106 (each of which may include one or more rolls) operate in series to facilitate the feeding (e.g., winding) of the insulating film 1816 via each of the processing stations 2110, 2120, and 2130. The insulating film 1816 may pass sequentially through each processing station such that the desired area of ​​the insulating film 1816 is sequentially patterned, cured, and homogenized during pre-construction.

[0151] In addition to forming a redistribution layer, the pre-constructed insulating film 1816 can also be used to form several insulating layers of an embedded die assembly or other semiconductor device package structure, encapsulating a substrate / frame and any semiconductor die. For example, by using two pre-constructed insulating films 1816, an insulating layer 2318 substantially similar to insulating layer 1018 can be formed on a substrate / frame (e.g., substrate 302 described above). Figure 22 illustrates a flowchart of a method 2200 for forming this insulating layer according to the embodiments described herein. Figures 23A to 23G schematically illustrate cross-sectional views of substrate 302 at different stages of the method 2200 depicted in Figure 22. Therefore, for clarity, Figures 22 and 23A to 23G are described together herein.

[0152] Typically, method 2200 begins with operation 2202 and Figure 23A, in which a substrate 302 (already patterned and having the desired features formed therein) is aligned (e.g., via reference points) and placed on a first pre-constructed insulating film 1816. In some embodiments, the insulating film 1816 is pre-constructed (i.e., constructed before being placed on the substrate 302) to include one or more interlayer windows 1803 laterally aligned with interlayer windows 303 formed in the substrate 302, such that when the flowable layer 1818 of the insulating film 1816 is laminated to the substrate 302, interconnects (e.g., interconnects 1444) can subsequently be electroplated via the interlayer windows 303 and 1803.

[0153] In some embodiments, after the substrate 302 is placed on the insulating film 1816, and specifically on its flowable layer 1818, the substrate 302 and the insulating film 1816 may be placed on a carrier 1024 for providing mechanical support during subsequent processing operations, as described above with reference to similar methods.

[0154] At operation 2204 and depicted in Figure 23B, one or more semiconductor dies 1026 are placed within cavities 305 formed in substrate 302, such that semiconductor dies 1026 are now surrounded on one side by an insulating film 1816 and on (e.g.) on all four sides by substrate 302 (a single semiconductor die 1026 is depicted in Figure 23B). In some embodiments, die 1026 is a multi-purpose die having integrated circuitry formed on its active surface 1028. Dies 1026 are placed within cavities 305 and positioned on the surface of insulating film 1816 exposed via cavities 305. In some embodiments, die 1026 is placed on an adhesive layer (not shown) disposed on or formed on insulating film 1816.

[0155] In operation 2206 and Figure 23C, substrate 302 is exposed to the lamination process. This substrate 302 is now placed on insulating film 1816 and further has grains 1026 disposed therein. During the lamination process, substrate 302 is exposed to high temperatures, causing the flowable layer 1818 of insulating film 1816 to soften and flow into the gap 1051 between the inner wall of cavity 305 and the grains 1026. Simultaneously, the interlayer window 303 of substrate 302 remains unfilled due to the prior curing of the sidewalls 2020 of the interlayer window 1803. As described above, the selective curing of the sidewalls 2020 of the interlayer window 1803 maintains its structural integrity and thus prevents the dielectric material of the flowable layer 1818 from flowing into the interlayer window 303 after lamination (e.g., preventing the flowable layer 1818 from clogging the interlayer window 3030). Therefore, the semiconductor die 1026 is at least partially embedded within the materials of the insulating film 1816 and the substrate 302, as depicted in Figure 23C. Additionally, the substrate 302 is fixed to the flowable layer 1818.

[0156] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a cycle between about 5 seconds and about 1.5 minutes, such as between about 30 seconds and about 1 minute. In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 50 psig while simultaneously applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1016a for a cycle between about 5 seconds and about 1.5 minutes. For example, the lamination process is performed at a pressure between about 5 psig and about 40 psig and a temperature between about 100°C and about 120°C for a cycle between about 10 seconds and about 1 minute. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 20 seconds.

[0157] In some embodiments, a protective film (e.g., protective film 1060) is placed over the exposed layer (e.g., side 1077) of substrate 302 prior to lamination, as shown in Figure 23C. In some embodiments, protective film 1060 is formed of a material similar to that of support layer 1022a. For example, protective film 1060 is formed of PET, such as biaxial PET. However, protective film 1060 can be formed of any suitable protective material. Protective film 1060 is removed after lamination and before operation 2208 discussed below.

[0158] In operation 2208 and Figure 23D, a second pre-constructed insulating film 1816 is aligned (e.g., via a reference point) and placed on the opposite side (e.g., side 1077) of the substrate 302. In some embodiments, the second insulating film 1816 is positioned such that its flowable layer 1818 contacts and covers the active surface 1028 of the die 1026 within the cavity 305. The second insulating film 1816 may be pre-constructed to include one or more interlayer windows 1803 laterally aligned with interlayer windows 303 formed in the substrate 302, and one or more interlayer windows 1803 laterally aligned with contacts 1030 formed on the active surface 1028 of each embedded die 1026. Thus, interconnects (e.g., interconnects 1444) can then be electroplated via the interlayer windows 303 and 1803, and these interconnects can be further routed to the contacts 1030 for connecting the embedded die 1026 to other components.

[0159] In operation 2210 and Figure 23E, substrate 302 is exposed to the second lamination process. The substrate 302 now has a first insulating film 1816 fixed on a first side 1075 and a second insulating film 1816 placed on a second side 1077. Similar to the lamination process in operation 2206, substrate 302 is exposed to high temperatures, causing the flowable layer 1818 of the second insulating film 1816 to soften and flow into the remaining gap 1051 between the inner wall of cavity 305 and the die 1026, thereby integrating itself with the insulating material of the flowable layer 1818 of the first insulating film 1816. Therefore, cavity 305 becomes filled (e.g., packaged, sealed), and semiconductor die 1026 becomes completely embedded within the insulating material of the flowable layer 1818, while interlayer windows 303 and 1803 remain open.

[0160] In some embodiments, the second lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C for a cycle between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10 psig and about 150 psig while simultaneously applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1016b for a cycle between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 20 psig and about 100 psig and a temperature between about 100°C and about 120°C for a cycle between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 5 minutes.

[0161] In operation 2212 and Figure 23F, the laminated embedded die assembly 1002 is detached from any carrier and / or protective film, the support layer 1822 is removed, and the embedded die assembly 1002 is exposed to a curing process. Typically, the support layer 1822 and any carrier and / or protective film are removed from the embedded die assembly 1002 by any suitable mechanical process, such as peeling. Subsequently, the embedded die assembly 1002 is exposed to a curing process to allow the insulating dielectric material of the flowable layer 1818 to be fully cured (i.e., through chemical reaction and cross-linking), thereby forming a cured insulating layer 2318. The insulating layer 2318 generally surrounds the substrate 302 and the semiconductor die 1026 embedded therein, except for the sidewalls of the interlayer window 303. For example, the insulating layer 2318 contacts or encapsulates at least sides 1075, 1077 of the substrate 302 (including surfaces 606, 608) and at least six sides or surfaces of each semiconductor die 1026, thereby exposing the sidewalls of the interlayer window 303.

[0162] In some embodiments, a curing process is performed at a high temperature to fully cure the embedded die component 1002. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a cycle between about 15 minutes and about 45 minutes, such as at a temperature between about 160°C and about 200°C for a cycle between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180°C for a cycle of about 30 minutes. In another embodiment, the curing process at operation 2212 is performed under or near ambient (e.g., atmospheric) pressure conditions.

[0163] After curing, the embedded die assembly 1002 is ready for forming interconnect paths therein (as described above with reference to Figures 13 and 14A to 14H) and for unification to form a completed package. For reference, an exemplary package 2302 is depicted in Figure 23G. Using the above method, interconnects 1444 can be formed via the interposer windows 303 and 1803 of the embedded die assembly 1002 for interconnecting one or more components and / or other package structures (including die 1026). However, unlike the previously described example, interconnects 1444 and / or adhesive layers 1440 and / or seed layers 1442 can be formed directly on the sidewalls of the interposer window 303 (rather than within the through-component interposer window formed in the interposer window 303) because no insulating material flows into the interposer window 303 during the lamination process of method 2200. Therefore, since the sidewalls of the mesowindow 303 may have an oxide layer formed thereon (as described with reference to Figures 2 and 3D), the interconnect 1444 may be formed on the oxide layer inside the mesowindow 303.

[0164] Although the above describes a separate lamination process for each of the two pre-constructed insulating films 1816, in some embodiments, method 2200 includes only a single lamination process for both films, thus reducing the amount of operation in method 2200. For example, in some embodiments, after placing the die 1026 in cavity 305 at operation 2204, operation 2208 can be performed, in which the second insulating film 1816 is placed on substrate 302. Therefore, thereafter, at operation 2210, both insulating films 1816 can be laminated simultaneously according to the lamination parameters described above.

[0165] Note that in some embodiments, method 2200 may be performed on a pre-metallized substrate 302. For example, substrate 302 may include one or more interlayer windows 302 having electroplated interconnects 1444 (and / or adhesive layers 1440 and / or seed layers 1442) formed therein. Thus, after lamination and curing on the pre-constructed insulating film 1816, the pre-metallized interconnects may be extended through the interlayer windows 1803 by any suitable technique discussed herein.

[0166] Compared to more traditional insulation and / or stacking methods, the use of pre-constructed insulating films (as described above with reference to Figures 17, 18A-18C, 19, 20A-20C, 21A-21B, 22, and 23A-23G) offers several advantages. For example, using a short-wavelength laser (e.g., an excimer laser) without damaging the dielectric material of the pre-constructed insulating film, it is possible to form redistribution dielectric windows with a significantly reduced size, such as a diameter of about 5 μm or less. Because the laser ablation of the insulating film occurs before the removal of the supports and / or capping layers to which it is attached, the supports and / or capping layers will absorb any heat accumulated on the surface of the flowable layer during construction and can be removed thereafter. Furthermore, because the construction of the insulating film is performed separately from the substrate, any ablation, etching, undercutting, and / or carbonization of the previously metallized contact pads on the substrate / frame can be avoided, and destructive etching or decontamination processes to remove debris or copper overhangs from the previously metallized layers are unnecessary. Additionally, the total number of operations required to form a semiconductor device package can be reduced because several operations (e.g., re-drilling through the substrate / frame's interlayer windows after lamination, decontamination, etching, etc.) can be avoided, thereby making the manufacturing of semiconductor device packages more efficient.

[0167] The package structures formed by the above methods (e.g., packages 1602 and 2302) can be used in any suitable packaging application and in any suitable configuration. In an exemplary embodiment depicted in Figure 24A, four packages 1602 are used to form a stacked DRAM structure 2400. Thus, each package 1602 includes a memory die 2426 (i.e., a memory chip) embedded within a substrate 302 and encapsulated by an insulating layer 1018 (e.g., a portion of each side is in contact with the insulating layer 1018). One or more interconnects 1444 are formed to extend through the entire thickness of each package 1602 and are in direct contact with one or more solder bumps 2446 disposed between the main surfaces 1005 and 1007 of adjacent (i.e., stacked above or below) packages 1602. For example, as depicted in the stacked DRAM structure 2400, four or more solder bumps 2446 are disposed between adjacent packages 1602 to bridge (e.g., connect, couple) the interconnects 1444 of each package 1602 with the interconnects 1444 of the adjacent packages 1602.

[0168] In some embodiments, encapsulation material 2448 is used to fill the voids between adjacent packages 1602 connected by solder bumps 2446 to enhance the reliability of the solder bumps 2446. Encapsulation material 2448 can be any suitable type of encapsulant or underfill. In one example, encapsulation material 2448 includes pre-assembled underfill materials, such as no-flow underfill (NUF), nonconductive paste (NCP), and nonconductive film (NCF). In one example, encapsulation material 2448 includes post-assembled underfill materials, such as capillary underfill (CUF) and molded underfill (MUF). In some embodiments, the encapsulating material 2448 comprises a resin containing low-expansion fillers, such as epoxy resins filled with (e.g., containing) SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O16, ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O12, MgO, TiO2, ZnO and the like.

[0169] In some embodiments, solder bump 2446 is formed of one or more intermetallic compounds, such as tin (Sn) combined with lead (Pb), silver (Ag), Cu, or any other suitable metal therein. For example, solder bump 2446 is formed of solder alloys, such as Sn-Pb, Sn-Ag, Sn-Cu, or any other suitable material or combination thereof. In some embodiments, solder bump 2446 includes C4 (controlled collapse die connection) bumps. In some embodiments, solder bump 2446 includes C2 (die connection, such as a Cu pillar with a solder cap) bump. The use of C2 solder bumps enables smaller spacing between contact pads and improved thermal and / or electrical properties of the stacked DRAM structure 2400. In some embodiments, solder bump 2446 has a diameter between about 10 μm and about 150 μm, such as a diameter between about 50 μm and about 100 μm. Solder bumps 2446 can be further formed by any suitable wafer flip-chip bonding process, including but not limited to electrochemical deposition (ECD) and electroplating.

[0170] In another exemplary embodiment depicted in Figure 24B, a stacked DRAM structure 2401 is formed by stacking four packages 1602 and directly bonding one or more interconnects 1444 of each package 1602 to the interconnects 1444 of one or more adjacent packages 1602. As depicted, the packages 1602 can be bonded by hybrid bonding, wherein the principal surfaces 1005 and 1007 of adjacent packages are planarized and in full contact with each other. Therefore, one or more interconnects 1444 of each package 1602 are formed to extend through the entire thickness of each package 1602 and to be in direct contact with one or more interconnects 1444 of at least another adjacent package 1602.

[0171] The stacked DRAM structures 2400 and 2401 offer several advantages over conventional DRAM structures. These benefits include a thinner form factor and a high die-to-package volume ratio, enabling greater I / O scalability to meet the increasing bandwidth and power efficiency demands of artificial intelligence (AI) and high-performance computing (HPC). The constructed silicon framework provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability in 3D integrated circuit (3D IC) architectures. Furthermore, compared to conventional TSV technology, the fabrication method described herein for through-device and inter-window inter-window structures offers high performance and flexibility for 3D integration at a relatively low manufacturing cost.

[0172] The embodiments described herein advantageously provide an improved substrate construction and die assembly method for manufacturing advanced integrated circuit packages. By utilizing the above method, high aspect ratio features can be formed on glass and / or silicon substrates, thereby enabling the cost-effective formation of thinner and narrower semiconductor device packages. The thin and small-form-factor packages manufactured using the above method not only offer the benefits of high I / O density and improved bandwidth and power but also provide greater reliability benefits, due to the reduced weight / inertia and low stress of the package architecture allowing for flexible solder ball distribution. Other advantages of the above method include cost-effective manufacturing with double-sided metallization capabilities and high yields by eliminating flip-chip attachment and overmolding steps (which are prone to feature damage in the mass production of conventional and advanced packages).

[0173] Although the foregoing describes an embodiment of this disclosure, other and additional embodiments of this disclosure may be designed without departing from the basic scope of this disclosure, and the scope of this disclosure is determined by the following claims.

[0174] 100: Method 110: Operation 114: Metal cladding 120: Operation 130: Operation 140: Operation 200: Method 210: Operation 220: Operation 230: Operation 240: Operation 302:Substrate 303: Mesoscopic Window 305: Cavity 307: Laser source 309: Powder / Particles 310: Laser Beam 314: Oxide film 316: Metal cladding 404: layer 406: Optional carrier plate 408: Adhesive layer 409: Adhesive layer 412: Mask 606: Surface 608: Surface 706: Stent 801: Column 802: Column 807: Minimum Spacing 900: Method 902: Operation 904: Operation 906: Operation 908: Operation 910: Operation 912: Operation 914: Operation 916: Operation 918: Operation 920: Operation 922: Operation 1002: Component 1003: Through-component interlayer window 1005: Main surface 1007: Main Surface 1016: Insulating film 1018: Insulation layer 1024: Optional carrier 1025: Second Carrier 1026: Semiconductor die 1028: Active Surface 1029: Surface 1030: Contact element 1032: Contact hole 1050: Hole 1051: Gap 1060: Protective film 1060: First protective film 1062: Protective film 1064: Protective film 1075: First side 1077: Second side 1100: Method 1110: Operation 1120: Operation 1130: Operation 1140: Operation 1150: Operation 1160: Operation 1170: Operation 1300: Method 1310: Operation 1320: Operation 1330: Operation 1340: Operation 1350: Operation 1360: Operation 1370: Operation 1440: Adhesive layer 1442: Seed layer 1444: Interconnector 1450: Membrane 1500: Method 1502: Operation 1504: Operation 1506: Operation 1508: Operation 1510: Operation 1512: Operation 1514: Operation 1516: Operation 1518: Operation 1520: Operation 1522: Operation 1602: Package 1602: Adjacent Package 1603: Redistribution Interlayer Window 1616: Insulating film 1618: Flowable layer 1622: (Multiple) support layers 1622: Support layer 1624: Carrier 1640: Adhesive layer 1642: Seed Crystal Layer 1644: Copper Seed Layer 1644: Redistribution connector 1650: Membrane 1658: Redistribution Layer 1660: Additional redistribution layer 1700: Alternative Methods 1702: Operation 1704: Operation 1706: Operation 1803: Mesoscopic Window 1816: Insulating film 1816: Patterned insulating film 1818: Flowable layer 1822: Support layer 1824: Floor 1900: Method 1902: Operation 1904: Operation 1906: Operation 2007: Laser Source 2010: Laser Beam 2020: Sidewall 2100: Roll-to-roll pre-construction device 2104: Unwinding Module 2106: Module 2110: Processing Station 2120: Processing Station 2130: Processing Station 2200: Method 2202: Operation 2204: Operation 2206: Operation 2208: Operation 2210: Operation 2212: Operation 2302: Package 2302: Indicative Package 2318: Insulation layer 2400: DRAM structure 2401: DRAM Structure 2426: Memory chip 2446: Solder bump 2448: Packaging Material 3030: Mesoscopic Window

[0175] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device package, comprising the steps of: placing a pre-constructed insulating film on a patterned substrate, the pre-constructed insulating film comprising a flowable, polymer-based dielectric material, wherein the patterned substrate comprises one or more features formed in a silicon substrate, the one or more features including a first dielectric window and a cavity, wherein a semiconductor die is placed in the cavity before the pre-constructed insulating film is placed on the patterned substrate, and the pre-constructed insulating film further comprises a second dielectric window formed therein, wherein after the pre-constructed insulating film is placed, the second dielectric window is aligned with the first dielectric window; laminating the pre-constructed insulating film onto the patterned substrate; curing the pre-constructed insulating film; and forming a conductive layer extending through the first dielectric window and the second dielectric window.

2. The method as described in claim 1 further includes the step of forming the first interlayer window in the patterned substrate via a laser ablation process.

3. The method as described in claim 1, further comprising the steps of: constructing an insulating film to form the pre-constructed insulating film, the construction step comprising the steps of: patterning one or more features into the insulating film by laser ablation, the one or more features including the second interlayer window; and selectively curing the sidewalls of the features patterned into the insulating film to harden the sidewalls.

4. The method as described in claim 1, wherein the pre-constructed insulating film comprises an epoxy resin.

5. The method as described in claim 4, wherein the epoxy resin comprises ceramic particles.

6. The method as claimed in claim 1, wherein the pre-constructed insulating film is laminated onto the patterned substrate, causing the flowable, polymer-based dielectric material to fill the gap between the surface of the semiconductor die and the surface of the cavity.

7. A method of forming a semiconductor device package, comprising the steps of: patterning one or more features in a silicon substrate, the one or more features including at least a first dielectric window and a cavity; placing the silicon substrate on a first pre-constructed insulating film, the first pre-constructed insulating film including a second dielectric window, the second dielectric window being aligned with the first dielectric window after the silicon substrate is placed; placing a second pre-constructed insulating film on the silicon substrate, the second pre-constructed insulating film including a third dielectric window, the third dielectric window being aligned with the first dielectric window after the second pre-constructed insulating film is placed; laminating the first pre-constructed insulating film and the second pre-constructed insulating film onto the silicon substrate; curing the first pre-constructed insulating film and the second pre-constructed insulating film; and forming a conductive layer extending through at least the first dielectric window, the second dielectric window, and the third dielectric window. A semiconductor die is placed in the cavity before the first pre-constructed insulating film and the second pre-constructed insulating film are placed on the silicon substrate.

8. The method as described in claim 7, wherein the silicon substrate is patterned by laser ablation.

9. The method as claimed in claim 7, further comprising the steps of: constructing an insulating film to form the first pre-constructed insulating film, the construction step comprising the steps of: patterning one or more features into the insulating film via laser ablation, the one or more features including the second interlayer window; and selectively curing the sidewalls of the features patterned into the insulating film to harden the sidewalls.

10. The method as described in claim 7, wherein the first pre-constructed insulating film or the second pre-constructed insulating film comprises an epoxy resin.

11. The method as described in claim 10, wherein the epoxy resin comprises ceramic particles.

12. The method as claimed in claim 7, wherein the first pre-constructed insulating film and the second pre-constructed insulating film are laminated onto the silicon substrate to cause a flowable polymer-based dielectric material to fill the gap between the surface of the semiconductor die and the surface of the cavity.

13. A method of forming a semiconductor device package, comprising the steps of: patterning one or more features in a silicon substrate, the one or more features including at least one first interposer window; placing the silicon substrate on a first pre-constructed insulating film, the first pre-constructed insulating film including a second interposer window, the second interposer window being aligned with the first interposer window after the silicon substrate is placed; exposing the first pre-constructed insulating film and the silicon substrate to a first lamination process; placing a second pre-constructed insulating film on the silicon substrate, the second pre-constructed insulating film including a third interposer window, the third interposer window being aligned with the first interposer window after the second pre-constructed insulating film is placed; and exposing the first pre-constructed insulating film, the substrate, and the second pre-constructed insulating film to a second lamination process. The first pre-constructed insulating film and the second pre-constructed insulating film are cured; and a conductive layer is formed extending through at least one of the first, second, and third dielectric windows.

14. The method of claim 13 further includes the steps of: constructing an insulating film to form the first pre-constructed insulating film, the construction step including the steps of: patterning one or more features into the insulating film by laser ablation, the one or more features including the second interlayer window; and selectively curing the sidewalls of the features patterned into the insulating film to harden the sidewalls.

15. The method as described in claim 13, wherein the first pre-constructed insulating film or the second pre-constructed insulating film comprises an epoxy resin.

16. The method as described in claim 15, wherein the epoxy resin comprises ceramic particles.

17. The method of claim 13, wherein the one or more features patterned into the silicon substrate further include a cavity, and wherein a semiconductor die is placed in the cavity before the first pre-constructed insulating film and the second pre-constructed insulating film are placed on the silicon substrate.

18. The method of claim 17, wherein the first pre-constructed insulating film and the second pre-constructed insulating film are laminated onto the substrate to cause a flowable, polymer-based dielectric material to fill the gap between the surface of the semiconductor die and the surface of the cavity.

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