Memory device and operating method of the memory device

Abstract

This invention relates to a memory device and a method of operating a memory device. A memory device may include: control circuitry adapted to execute a program loop comprising programming operations and verification operations, the programming operations including a program voltage application operation on a selected word line and a bit line setting operation on a plurality of bit lines, and the verification operation applying (N-1) first verification voltages to the selected word line in a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic adapted to control the control circuitry to repeatedly execute the program loop until programming for the selected word line is completed, and to control the control circuitry to apply any of N types of column voltages to each of the plurality of bit lines in a bit line setting operation included in a second program loop.

Description

[Technical Field]

[0001] Various embodiments of the present invention relate generally to electronic devices, and more specifically to memory devices and methods of operating memory devices. [Previous Technology]

[0002] Memory systems are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory systems are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices in which the data stored is lost when the power supply is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices in which the data stored is retained even when the power supply is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly divided into NOR type memory and NAND type memory.

[0003] Cross-reference to related applications: This application claims priority to Korean Patent Application No. 10-2021-0128051, filed on September 28, 2021, the entire contents of which are incorporated herein by reference. [Summary of the Invention]

[0004] According to an embodiment, the memory device may include: a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; control circuitry adapted to execute a program loop including a program operation and a verification operation, the program operation including a program voltage application operation on a selected word line among the plurality of word lines and a bit line setting operation on the plurality of bit lines, the verification operation applying (N-1) first verification voltages to the selected word line in a predetermined order to check N types of first program states for each of the plurality of memory cells included in the selected word line; and control logic adapted to control the control circuitry to repeatedly execute the program loop until the program for the selected word line is completed, and to control the control circuitry to apply any one of N types of column voltages to each of the plurality of bit lines in a bit line setting operation included in a second program loop according to the result of the verification operation included in the first program loop, wherein "N" is a natural number equal to or greater than 4.

[0005] According to an embodiment, a method of operating a memory device may include: executing a program loop including a programming operation and a verification operation, the programming operation including a programming voltage application operation on a selected word line among a plurality of word lines and a bit line setting operation on a plurality of bit lines, the verification operation applying (N-1) first verification voltages to the selected word line in a predetermined order to check N types of first programming states for each of a plurality of memory cells included in the selected word line; and repeatedly executing the program loop until programming for the selected word line is completed, and applying any one of N types of column voltages to each of the plurality of bit lines in a bit line setting operation included in a second program loop according to the result of the verification operation included in the first program loop, wherein "N" is a natural number equal to or greater than 4.

[0006] According to an embodiment, a method for programming a memory device, the memory device executing multiple program loops until programming for a selected word line among multiple word lines is completed, wherein each program loop may include: generating any one of N types of column voltages based on the value of an M-bit setting code of N types input to a page buffer, and applying the generated column voltage to each of the multiple word lines in a bit line setting operation; applying a program voltage to the selected word line in a program voltage application operation; applying (N-1) first verification voltages to the selected word line in a predetermined order in a verification operation to check a first program state of N types for each of the multiple memory cells included in the selected word line; and determining the value of an M-bit setting code of N types to be input to the page buffer in a subsequent program loop bit line setting operation based on the result of applying (N-1) first verification voltages to the selected word line in a predetermined order, wherein "N" is a natural number equal to or greater than 4, and "M" is a natural number equal to or greater than 2.

Implementation Method

[0008] Various embodiments of the present invention are described below with reference to the drawings. However, the elements and features of the present invention may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0009] In this invention, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of the invention, but may or may not necessarily be combined in the same embodiment.

[0010] In this invention, the terms “comprising,” “including,” “containing,” and “included in” are open-ended. As used in the appended claims, these terms specify the presence of the mentioned element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.) in the device.

[0011] In this invention, various units, circuits, or other components may be described or claimed as being “configured to” perform one or more tasks. In this context, “configured to” is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component may be referred to as being configured to perform a task even when the specified block / unit / circuit / component is not currently in operation (e.g., not turned on or not started). Blocks / units / circuits / components used with the “configured to” language include hardware, such as circuits, memory storing program instructions executable to perform the operation, etc. Additionally, “configured to” may include general structures (e.g., general circuits) manipulated by software and / or firmware (e.g., FPGAs or general-purpose processors executing the software) to operate in a manner capable of performing the task in question. “Configured to” may also include means (e.g., integrated circuits) for adapting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means for implementing or performing one or more tasks.

[0012] As used in this invention, the term "circuit" or "logic" refers to all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and / or digital circuits only), and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) portions of processor / software (including digital signal processors), software, and memory that work together to enable a device (such as a mobile phone or server) to perform various functions, and (iii) circuitry such as a microprocessor or a portion of a microprocessor that requires software or firmware (even if the software or firmware is not physically present) to function. The definition of "circuit" or "logic" applies to all uses of the term in this invention (including in any claim scope). As another example, as used in this invention, the term "circuit" or "logic" also covers implementations of processors (or processors) only, or portions of processors and their accompanying software and / or firmware. The term "circuit" or "logic" also covers, for example, and if applicable to a particular claim scope element, integrated circuitry for a storage device.

[0013] As used herein, the terms “first,” “second,” “third,” etc., are used as labels for the nouns following these terms and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must be written before the second value. Furthermore, although these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that has the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0014] Furthermore, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude additional factors that may influence the determination. That is, a determination may be based solely on those factors or at least partially on those factors. For example, the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such usage does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0015] In this document, a data item, data entry, or data term can be a sequence of bits. For example, a data item may include the content of a file, a portion of a file, a page in memory, an object in an object-oriented program, digital information, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to an embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a transmission packet between two different components.

[0016] Various embodiments of the present invention relate to memory devices and methods of operating the same with improved program operation performance.

[0017] Each of the plurality of page buffers may include: an NMOS transistor adapted to couple a bit line to a sensing node in response to a voltage application signal having a predetermined level and any one of (M-K+1) types of selection levels; and a coupling control unit adapted to couple a ground voltage terminal and any one of K types of power supply voltage terminals having a sequential level lower than the predetermined level to the sensing node in response to each of N types of M bit setting codes input to M latches, wherein “K” is a natural number equal to or greater than “M”.

[0018] During the bit line setting operation, the control logic can control the control circuit to generate a voltage application signal having a predetermined level and any one of (M-K+1) types of selection levels, and input the voltage application signal to an NMOS transistor included in each of the plurality of page buffers, and control the control circuit to input each of the plurality of M bit setting codes to M latches included in each of the plurality of page buffers, and couple the sensing node to a ground voltage terminal and any one of the K types of power supply voltage terminals through the coupling control unit.

[0019] The technical problems that can be obtained from the present invention are not limited to those described herein, and those skilled in the art to which this invention pertains will clearly understand other technical problems not described herein based on the following description.

[0020] Figure 1 is a diagram illustrating a memory system according to an embodiment.

[0021] Referring to FIG1, the data processing system 100 may include a host 102 that is coupled to or operatively coupled to the memory system 110.

[0022] The host 102 may include any of the following: portable electronic devices such as mobile phones, MP3 players, and laptops, as well as electronic devices such as desktop computers, game consoles, televisions (TVs), and projectors.

[0023] Host 102 also includes at least one operating system (OS) that can comprehensively manage and control the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is coupled to memory system 110, and users using memory system 110. The OS can support functions and operations corresponding to user requests. By way of example, and not limitation, OS can be classified into general-purpose operating systems and mobile operating systems based on the mobility of host 102. Depending on system requirements or user environment, general-purpose operating systems can be divided into personal operating systems and enterprise operating systems. Personal operating systems, including Windows and Chrome, can be used for general-purpose support services. However, enterprise operating systems can be specifically designed for protection and support of high performance, including Windows servers, Linux, Unix, etc. Furthermore, mobile operating systems can include Android, iOS, Windows Mobile, etc. Mobile operating systems can be used for mobility support services or functions (e.g., power-saving functions). Host 102 can include multiple operating systems. Host 102 can run multiple operating systems interlocked with memory system 110 corresponding to user requests. The host 102 can send multiple commands corresponding to user requests to the memory system 110, thereby executing the operations corresponding to the commands within the memory system 110.

[0024] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data to be accessed by the host 102. The controller 130 may control the operation of storing data in the memory device 150.

[0025] The controller 130 and memory device 150 included in the memory system 110 may be integrated into a single semiconductor device, which may be included in any of the various types of memory systems discussed above in the examples.

[0026] By way of example and not limitation, the controller 130 and memory device 150 can be implemented using an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be significantly increased compared to the operating speed of the host 102 implemented using a hard disk. Furthermore, the controller 130 and memory device 150 can be integrated into a single semiconductor device to form storage cards such as PC cards (PCMCIA), compact flash memory cards (CF), storage cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MCmicro), SD cards (SD, mini SD, micro SD, SDHC), general-purpose flash memory, etc.

[0027] The memory system 110 may be configured as, for example, a computer, a super mobile PC (UMPC), a workstation, a mini laptop, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital video recorder, a digital video player, a digital video recorder, a digital video player, a storage device for configuring a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices for configuring a home network, one of various electronic devices for configuring a computer network, one of various electronic devices for configuring a remote information processing network, a radio frequency identification (RFID) device, or one of various components for configuring a computing system.

[0028] The memory device 150 may be a non-volatile memory device, and the data stored therein may be retained even when no power is supplied. The memory device 150 may store data provided by the host 102 through write operations, and provide the data stored therein to the host 102 through read operations.

[0029] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, each page may be a unit for storing data in the memory device 150 or retrieving data stored in the memory device 150.

[0030] A memory block can be a unit for erasing data. In embodiments, the memory device 150 may take the form of various alternatives such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory device, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). In this specification, for ease of description, the memory device 150 will be described under the assumption that it is NAND flash memory.

[0031] The memory device 150 can receive commands and addresses from the controller 130 and can access a region of the memory cell array selected by the address. That is, the memory device 150 can perform operations instructed by commands on the region selected by the address. For example, the memory device 150 can perform write operations (i.e., programming operations), read operations, and erase operations. During a programming operation, the memory device 150 can program data to the region selected by the address. During a read operation, the memory device 150 can read data from the region selected by the address. During an erase operation, the memory device 150 can erase data stored in the region selected by the address.

[0032] Controller 130 controls the overall operation of memory system 110.

[0033] When power is supplied to the memory system 110, the controller 130 may run firmware (FW). When the memory device 150 is a flash memory device, the controller 130 may run firmware such as a flash memory transition layer (FTL) to control communication between the host 102 and the memory device 150.

[0034] In this embodiment, the controller 130 may receive data and logical block addresses (LBAs) from the host 102, and may translate the logical block addresses into physical block addresses (PBAs), which indicate the addresses of memory cells included in the memory device 150 and in which data is to be stored. In this specification, logical block addresses (LBAs) and logical addresses may be used with the same meaning. In this specification, physical block addresses (PBAs) and physical addresses may be used with the same meaning.

[0035] The controller 130 may control the memory device 150 in response to a request received from the host 102 to perform program operations, read operations, or erase operations. During program operations, the controller 130 may provide the memory device 150 with program commands, physical block addresses, and data.

[0036] During a read operation, the controller 130 may provide a read command and a physical block address to the memory device 150. During an erase operation, the controller 130 may provide an erase command and a physical block address to the memory device 150.

[0037] In this embodiment, the controller 130 may generate commands, addresses, and data autonomously, independent of requests from the host 102, and may send the commands, addresses, and data to the memory device 150. For example, the controller 130 may provide commands, addresses, and data to the memory device 150 to perform background operations such as programming operations for wear leveling and programming operations for waste collection.

[0038] In this embodiment, the controller 130 may control two or more memory devices 100. In this case, the controller 130 may control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme may be an operation mode in which the operation periods of at least two memory devices 100 overlap with each other.

[0039] The host 102 can communicate with the memory system 110 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Non-Volatile Memory Communication Protocol (NVMe), Universal Flash Memory (UFS), Secure Digital Card (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Register DIMM (RDIMM), and Reduced Load DIMM (LRDIMM).

[0040] Figure 2 is a detailed diagram illustrating the memory device shown in Figure 1.

[0041] Referring to FIG2, the memory device 150 may include a memory cell array 151 and a control circuit 152.

[0042] The memory cell array 151 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz may be connected to the address decoder 155 via row lines RL. The multiple memory blocks BLK1 to BLKz may be connected to the page buffer group 156 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In an embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include multiple pages.

[0043] The row line RL may include at least one source select line, multiple character lines and at least one drain select line.

[0044] The memory cells included in the memory cell array 151 can be configured as single-layer cells (SLCs) that each store 1 bit of data, multi-layer cells (MLCs) that each store 2 bits of data, three-layer cells (TLCs) that each store 3 bits of data, or four-layer cells (QLCs) that each store 4 bits of data.

[0045] The control circuit 152 can be configured to perform programming, reading, or erasing operations on selected regions of the memory cell array 151. The control circuit 152 can drive the memory cell array 151. For example, the control circuit 152 can apply various operating voltages to the row lines RL and bit lines BL1 to BLm, or discharge the applied voltages.

[0046] The control circuit 152 may include an address decoder 155, a voltage generator 154, a page buffer group 156, a data input / output circuit (data I / O circuit) 157, a sensing circuit 158, and control logic 153.

[0047] The control circuit 152 can drive the memory cell array 151. For example, the control circuit 152 can drive the memory cell array 151 to perform program operations, read operations, and erase operations.

[0048] The address decoder 155 can be connected to the memory cell array 151 via row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and common source lines.

[0049] Address decoder 155 can be configured to operate in response to control of control logic 153. Address decoder 155 can receive address RADD from control logic 153.

[0050] Address decoder 155 can be configured to decode block addresses in the received address RADD. Address decoder 155 can select at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 155 can be configured to decode row addresses in the received address RADD. Address decoder 155 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 155 can apply an operating voltage Vop supplied from voltage generator 154 to the selected word line.

[0051] During program operation, address decoder 155 may apply a program voltage to the selected word line and apply a pass voltage with a lower level than the program voltage to the unselected word line. During program verification operation, address decoder 155 may apply a verification voltage to the selected word line and apply a verification pass voltage with a higher level than the verification voltage to the unselected word line.

[0052] During a read operation, the address decoder 155 may apply a read voltage to the selected character line and apply a read pass voltage with a higher level than the read voltage to the unselected character line.

[0053] In this embodiment, the erase operation of the memory device 150 can be performed on a block-by-block basis. The address ADDR input to the memory device 150 during the erase operation may include a block address. The address decoder 155 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 155 may apply a ground voltage to the word lines of the selected memory block.

[0054] Voltage generator 154 can be configured to generate multiple operating voltages Vop by using an external power supply voltage supplied to memory device 150. Voltage generator 154 can operate in response to control of control logic 153.

[0055] In this embodiment, the voltage generator 154 can adjust the external power supply voltage and generate an internal power supply voltage. The internal power supply voltage generated by the voltage generator 154 can be used as the operating voltage of the memory device 150.

[0056] In this embodiment, voltage generator 154 can generate multiple operating voltages Vop by using an external power supply voltage or an internal power supply voltage. Voltage generator 154 can be configured to generate various voltages required by memory device 150. For example, voltage generator 154 can generate multiple erase voltages, multiple program voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0057] The voltage generator 154 may include a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of operating voltages Vop with various voltage levels, and selectively activate the plurality of pumping capacitors in response to control of the control logic 153 to generate the plurality of operating voltages Vop.

[0058] The generated operating voltage Vop can be supplied to the memory cell array 151 by the address decoder 155.

[0059] Page buffer group 156 may include multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm may be connected to memory cell array 151 via multiple bit lines BL1 to BLm respectively. The multiple page buffers PB1 to PBm may operate in response to the control of control logic 153.

[0060] Multiple page buffers PB1 to PBm can communicate data DATA with the data input / output circuit 157. During program operation, multiple page buffers PB1 to PBm can receive data DATA to be stored through the data input / output circuit 157 and the data line DL.

[0061] During program operation, when a program voltage is applied to the selected word line, multiple page buffers PB1 to PBm can send data DATA received through the data input / output circuit 157 to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page can be programmed based on the sent data DATA. Memory cells connected to bit lines to which a program enable voltage (e.g., ground voltage) is applied can have an elevated threshold voltage. The threshold voltage of memory cells connected to bit lines to which a program disable voltage (e.g., power supply voltage) is applied can be maintained. During program verification operation, multiple page buffers PB1 to PBm can read data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0062] During a read operation, the page buffer group 156 can read data DATA from the memory cell of the selected page through bit lines BLs and store the read data DATA in multiple page buffers PB1 to PBm.

[0063] During the erase operation, the page buffer group 156 can float the bit lines BLs. In an embodiment, the page buffer group 156 may include column select circuitry.

[0064] The data input / output circuit 157 can be connected to multiple page buffers PB1 to PBm via data lines DL. The data input / output circuit 157 can operate in response to the control logic 153.

[0065] The data input / output circuit 157 may include multiple input / output buffers (not shown) for receiving data DATA input to it. During program operation, the data input / output circuit 157 may receive data DATA to be stored from the controller 130 (see Figure 1). During read operation, the data input / output circuit 157 may output data DATA sent from multiple page buffers PB1 to PBm included in the page buffer group 156 to the controller 130 (see Figure 1).

[0066] During a read operation or a verification operation, the sensing circuit 158 ​​may generate a reference current in response to the enable bit VRYBIT generated by the control logic 153, and output a pass signal PASS or a failure signal FAIL to the control logic 153 by comparing the sensed voltage VPB received from the page buffer group 156 with a reference voltage attributable to the reference current.

[0067] Control logic 153 can be connected to address decoder 155, voltage generator 154, page buffer group 156, data input / output circuit 157, and sensing circuit 158. Control logic 153 can be configured to control the overall operation of memory device 150. Control logic 153 can operate in response to command CMD sent from an external device.

[0068] Control logic 153 can generate various signals in response to command CMD and address ADDR, and control other components 154 to 158 included in control circuit 152. For example, control logic 153 can generate operation signal OPSIG, address RADD, read / write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 153 can output operation signal OPSIG to voltage generator 154, output address RADD to address decoder 155, output read / write circuit control signal PBSIGNALS to page buffer group 156, and output enable bit VRYBIT to sensing circuit 158. In addition, control logic 153 can determine whether the verification operation is successful or unsuccessful in response to pass signal PASS or failure signal FAIL output by sensing circuit 158.

[0069] Figure 3 is a detailed diagram illustrating the memory block shown in Figure 2.

[0070] Referring to Figure 3, multiple character lines arranged in parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line SSL, and the second select line can be a drain select line DSL. More specifically, the memory block BLKi can include multiple memory cell strings ST connected between bit lines BL1 to BLm and a common source line CSL. Bit lines BL1 to BLm can be connected to memory cell strings ST respectively, and the common source line CSL can be connected together to memory cell strings ST. Since memory cell strings ST can have the same configuration, the memory cell string ST connected to the first bit line BL1 is described in detail representatively.

[0071] The memory cell string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST connected in series between the common source line CSL and the first cell line BL1. At least one drain select transistor DST may be included in a memory cell string ST, and more source select transistors SST and memory cells MC1 to MC16 may be included than shown in the figure.

[0072] The source of the source select transistor SST can be connected to the common source line CSL, and the drain of the drain select transistor DST can be connected to the first word line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different memory cell strings ST can be connected to the source select line SSL, the gates of the drain select transistors DST included in different memory cell strings ST can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16 respectively. A group of memory cells connected to the same word line among the memory cells included in different memory cell strings ST can be called a physical page PG. Therefore, the memory block BLKi can include as many physical pages PG as word lines WL1 to WL16.

[0073] A memory cell can store 1 bit of data. This is usually called a single-level cell (SLC). In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0074] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPG) of data.

[0075] FIG4 is a detailed view illustrating the memory device 150 shown in FIG2 according to an embodiment.

[0076] Referring to FIG4, the memory device 150 may include a memory cell array 151, a programming and verification circuit 41, a voltage generation unit 42, and a programming operation control unit 43.

[0077] The control circuit 152 described with reference to FIG2 may include a programming and verification circuit 41. The programming and verification circuit 41 may include the address decoder 155 and page buffer group 156 shown in FIG2. The control logic 153 described with reference to FIG2 may include a program operation control unit 43. The voltage generator 154 described with reference to FIG2 may include a voltage generation unit 42. That is, the operation of the programming and verification circuit 41 described below may be the operation of the control circuit 152, and the operation of the program operation control unit 43 may be the operation of the control logic 153.

[0078] The memory cell array 151 may include multiple memory cells. The memory cell array 151 may be coupled to the program and verification circuit 41 via word lines WLs coupled to the multiple memory cells. The memory cell array 151 may be coupled to the program and verification circuit 41 via bit lines BLs coupled to the multiple memory cells. The word lines WLs and bit lines BLs may be cross-coupled as described in FIG3.

[0079] The voltage generation unit 42 can generate an operating voltage Vop required to operate the memory cell in response to the voltage generation signal V_Gen. In the operating voltage Vop, the voltage applied to the word line can be the word line voltage. The voltage generation unit 42 can provide the generated operating voltage Vop to the programming and verification circuit 41.

[0080] The programming and verification circuit 41 can receive the operating voltage Vop from the voltage generation unit 42. The programming and verification circuit 41 can generate N types of column voltages to be applied to the bit lines BLs of the memory cells coupled to the selected word lines during the bit line setting operation. "N" can be a natural number equal to or greater than 4. According to an embodiment, assuming "N" is 4, the programming and verification circuit 41 can generate 4 types of column voltages to be applied to the bit lines BLs of the memory cells coupled to the selected word lines during the bit line setting operation. The programming and verification circuit 41 can execute a program loop including programming and verification operations according to the bit line control signal BL_Con and the word line control signal WL_Con.

[0081] Specifically, the program operation included in the program loop may be an operation that raises the threshold voltage of the memory cell to a threshold voltage corresponding to the target program state based on the data to be stored in the memory cell. The verification operation included in the program loop may be an operation that verifies whether the program operation has been properly performed on the memory cell. That is, the verification operation may be an operation that checks whether the threshold voltage of the memory cell that has been program-operated has reached the threshold voltage corresponding to the target program state of the program operation.

[0082] The program and verification circuit 41 can repeatedly execute the program loop until the program for the selected character line is completed. That is, the program and verification circuit 41 can repeatedly execute the program operation and verification operation until the program for the selected character line is completed.

[0083] The program and verification circuit 41 can selectively apply N types of column voltages to each bit line BLs coupled to the memory cell according to the bit line control signal BL_Con. The program and verification circuit 41 can selectively apply the operating voltage Vop to each word line WLs coupled to the memory cell according to the word line control signal WL_Con.

[0084] The program and verification circuit 41 can perform a verification operation on the memory cell using N-1 verification voltages according to the word line control signal WL_Con, so as to verify a target program state of the selected word line selected as the program target. In this document, "N" can be a natural number equal to or greater than 4. Therefore, the program and verification circuit 41 can perform a verification operation on the memory cell using L*(N-1) verification voltages according to the word line control signal WL_Con, so as to verify L target program states of the selected word line selected as the program target. In this document, "L" can be a natural number equal to or greater than 1.

[0085] According to an embodiment, assuming "L" is 2, the program and verification circuit 41 can sequentially apply N-1 first verification voltages to the selected character line during the verification operation to check N types of first program states for each of the plurality of memory cells included in the selected character line. Furthermore, the program and verification circuit 41 can sequentially apply N-1 second verification voltages to the selected character line during the verification operation to check N types of second program states for each of the plurality of memory cells included in the selected character line. At this time, assuming that the level corresponding to the first program state as the first target program state is lower than the level corresponding to the second program state as the second target program state, the maximum level of the N-1 second verification voltages can be higher than the maximum level of the N-1 first verification voltages.

[0086] According to the embodiment, assuming "N" is 4 and "L" is 1, the program and verification circuit 41 can perform verification operations to verify four types of program states by using three verification voltages, so as to check a target program state for each of the multiple memory units included in the selected character line.

[0087] According to the embodiment, assuming "N" is 4 and "L" is 2, the program and verification circuit 41 can perform the following program operations: verifying four types of first program states by using three first verification voltages to check the first program state of the first target program state of each of the plurality of memory units included in the selected character lines, and verifying four types of second program states by using three second verification voltages to check the second program state of the second target program state of each of the plurality of memory units included in the selected character lines.

[0088] In this manner, a program loop that includes a verification operation that verifies a target program state by using three verification voltages to verify four types of program states can be defined as a triple verification PGM (TPGM) operation.

[0089] More specifically, assuming "N" is 4 and "L" is 1, the program and verification circuit 41 can verify four types of program states for each of the plurality of memory cells included in the selected word line by using three verification voltages (i.e., additional verification voltage, pre-verification voltage, and main verification voltage) to check a target program state for the selected word line. The program and verification circuit 41 can apply an additional verification voltage to the selected word line during the additional verification operation according to the word line control signal WL_Con. The program and verification circuit 41 can apply a pre-verification voltage to the selected word line during the pre-verification operation according to the word line control signal WL_Con. The program and verification circuit 41 can apply a main verification voltage to the selected word line during the main verification operation according to the word line control signal WL_Con.

[0090] According to an embodiment, the primary verification voltage may be a verification voltage corresponding to the target program state of the program operation. The pre-verification voltage may be a voltage used to verify the extent to which program operations are performed on the memory cell, and its level is lower than the level of the primary verification voltage. The supplementary verification voltage may be a voltage used to verify the extent to which program operations are performed on the memory cell, and its level is lower than the level of the pre-verification voltage.

[0091] As a result of performing a verification operation on the memory cell of the selected word line, the first cell may be a memory cell having a threshold voltage lower than the additional verification voltage. The second cell may be a memory cell having a threshold voltage higher than the additional verification voltage and lower than the pre-verification voltage. The third cell may be a memory cell having a threshold voltage higher than the pre-verification voltage and lower than the main verification voltage. The program inhibit cell may be a memory cell having a threshold voltage higher than the main verification voltage.

[0092] Programming operations on the first unit, which has a threshold voltage lower than the additional verification voltage, need to be executed quickly. Programming operations on the second unit, which has a threshold voltage higher than the additional verification voltage but lower than the pre-verification voltage, need to be executed more slowly than those on the first unit. Programming operations on the third unit, which has a threshold voltage higher than the pre-verification voltage but lower than the main verification voltage, need to be executed more slowly than those on the second unit. Since the fourth unit (i.e., the program disable unit), which has a threshold voltage higher than the main verification voltage, is in the first program state as the target program state, and programming of the fourth unit has been completed, programming operations on the fourth unit need to be disabled.

[0093] Program operations included in the program loop may include bit line setting operations and program voltage application operations.

[0094] The bit line setting operation can be an operation that sets the potential of the bit line BLs coupled to the memory cell of the selected word line selected as the program target among multiple word lines WLs to the voltage required for the program operation.

[0095] The program voltage application operation can be an operation that applies a program voltage to the selected word line. The program voltage application operation can be performed after the bit line setting operation. Some execution periods of the program voltage application operation can overlap with some execution periods of the bit line setting operation.

[0096] The voltage generation unit 42 can respond to the voltage generation signal V_Gen and generate a program voltage to be applied to the selected character line.

[0097] Based on the result of verifying N types of program states for each of the multiple memory cells included in the selected word lines in the above-described verification operation of the program loop in order to check a target program state, any one of the N types of column voltages can be applied to each of the multiple bit lines BLs in the bit line setting operation included in the subsequent program loop operation. That is, based on the result of verifying N types of program states for each of the multiple memory cells included in the selected word lines in the verification operation of the first program loop executed first, in order to check a target program state, any one of the N types of column voltages can be applied to each of the multiple bit lines BLs in the bit line setting operation included in the program operation of the second program loop to be executed later. According to the embodiment, assuming "N" is 4, based on the result of verifying 4 types of program states for each of the multiple memory cells included in the selected word line in the verification operation of the previously executed first program loop in order to check a target program state, any one of the 4 types of column voltages can be applied to each of the multiple bit lines BLs in the bit line setting operation included in the program operation of the subsequently executed second program loop.

[0098] More specifically, assuming "N" is 4, the four types of column voltages may include a first allowable voltage, a second allowable voltage, a third allowable voltage, and a disable voltage. The first allowable voltage may have a voltage level lower than the second allowable voltage. The second allowable voltage may have a voltage level lower than the third allowable voltage. The third allowable voltage may have a voltage level lower than the disable voltage. The first allowable voltage may have a ground voltage level or a negative voltage level below the ground voltage level. The disable voltage may be a voltage applied to a bit line coupled to a memory cell, preventing the memory cell from being programmed. The disable voltage may have a power supply voltage level.

[0099] According to the bit line control signal BL_Con, the program and verification circuit 41 can apply an inhibit voltage to a bit line coupled to a program inhibit unit among the plurality of memory cells included in the selected word line during the bit line setting operation. According to the bit line control signal BL_Con, the program and verification circuit 41 can apply a first enable voltage to a bit line coupled to a first unit among the plurality of memory cells included in the selected word line that has a threshold voltage lower than the additional verification voltage during the bit line setting operation. According to the bit line control signal BL_Con, the program and verification circuit 41 can apply a second enable voltage to a bit line coupled to a second unit among the plurality of memory cells included in the selected word line that has a threshold voltage higher than the additional verification voltage and lower than the pre-verification voltage during the bit line setting operation. According to the bit line control signal BL_Con, the program and verification circuit 41 can apply a third enable voltage to the bit line coupled to the third cell among the plurality of memory cells included in the selected word line during the bit line setting operation. The third cell has a threshold voltage that is higher than the pre-verification voltage and lower than the main verification voltage.

[0100] The program and verification circuit 41 can apply any of the N types of column voltages to each of the multiple bit lines through the bit line setting operation, and then apply the program voltage to the selected word line through the program voltage application operation according to the word line control signal WL_Con.

[0101] According to an embodiment, the intensity of the program operation on the third unit can be lower than the intensity of the program operation on the second unit. Simultaneously, the intensity of the program operation on the second unit can be lower than the intensity of the program operation on the first unit. The program intensity can be determined based on the duration of the applied program pulse, the number of applied program pulses, and the potential difference between the program pulses. For example, during the period when a program voltage is applied to the selected word lines commonly coupled to the first to third units, a first allowable voltage having a ground voltage level can be applied to the bit lines coupled to the first unit, a second allowable voltage having a level higher than the ground voltage level can be applied to the bit lines coupled to the second unit, and a third allowable voltage having a level higher than the second allowable voltage can be applied to the bit lines coupled to the third unit. In this case, since the potential difference of the program voltage applied to the third unit is less than the potential difference of the program voltage applied to the second unit, the intensity of the program operation on the third unit can be lower than the intensity of the program operation on the second unit. Similarly, since the potential difference of the program voltage applied to the second unit is smaller than the potential difference of the program voltage applied to the first unit, the intensity of the program operation on the second unit can be lower than the intensity of the program operation on the first unit.

[0102] Programming operations of the program disable unit can be restricted. For example, while applying a program voltage to the selected word line coupled to the program disable unit, a disable voltage having a power supply voltage level can be applied to the bit line coupled to the program disable unit. In this case, since the potential difference of the program voltage applied to the program disable unit becomes less than the potential difference for raising the threshold voltage of the memory unit, programming operations for raising the threshold voltage of the program disable unit can be restricted.

[0103] The program operation control unit 43 can provide the voltage generation unit 42 with a voltage generation signal V_Gen for controlling the generation of the operating voltage Vop required for program operation or verification operation. The program operation control unit 43 can provide the program and verification circuit 41 with a word line control signal WL_Con for controlling the selective application of the operating voltage Vop generated by the voltage generation unit 42 to each word line WLs coupled to the memory cell. The program operation control unit 43 can provide the program and verification circuit 41 with a bit line control signal BL_Con for controlling the selective application of the operating voltage Vop generated by the voltage generation unit 42 to each bit line BLs coupled to the memory cell.

[0104] According to an embodiment, the program operation control unit 43 can generate a voltage generation signal V_Gen during the verification operation and provide the voltage generation signal V_Gen to the voltage generation unit 42, thereby controlling the voltage generation unit 42 to generate N-1 verification voltages. The program operation control unit 43 can also generate a character line control signal WL_Con during the verification operation and provide the character line control signal WL_Con to the program and verification circuit 41 to sequentially apply the N-1 verification voltages generated by the voltage generation unit 42 to the selected character line.

[0105] According to an embodiment, during the bit line setting operation, the program operation control unit 43 can generate a voltage generation signal V_Gen and provide the voltage generation signal V_Gen to the voltage generation unit 42, and can generate an M-bit setting code and provide the M-bit setting code to the program and verification circuit 41, thereby controlling the program and verification circuit 41 to generate N types of column voltages. The program operation control unit 43 can generate a bit line control signal BL_Con during the bit line setting operation period and provide the bit line control signal BL_Con to the program and verification circuit 41 to apply any of the N types of column voltages generated by the program and verification circuit 41 to each of the multiple bit lines.

[0106] According to an embodiment, the program operation control unit 43 can generate a voltage generation signal V_Gen during the program voltage application operation and provide the voltage generation signal V_Gen to the voltage generation unit 42, thereby controlling the voltage generation unit 42 to generate a program voltage. The program operation control unit 43 can also generate a character line control signal WL_Con during the program voltage application operation and provide the character line control signal WL_Con to the program and verification circuit 41 to apply the program voltage generated by the voltage generation unit 42 to the selected character line.

[0107] Figure 5 is a diagram illustrating the triple verification PGM (TPGM) operation according to an embodiment.

[0108] Referring to Figure 5, the TPGM operation can be a program loop that includes verifying four program states to verify a target program state after program operation is performed by using three verification voltages, PVT, PVP, and PVM. These three verification voltages can be an additional verification voltage PVT, a pre-verification voltage PVP, and a main verification voltage PVM. The main verification voltage PVM can be a verification voltage corresponding to the target program state of the program operation. Each of the additional verification voltage PVT and the pre-verification voltage PVP can be a voltage used to verify the extent to which program operation is performed on the memory cell, and its level is lower than the level of the main verification voltage PVM.

[0109] In Figure 5, it is assumed that the memory cell is a single-level cell (SLC) that stores one data bit. Therefore, the target program state for program operations on the memory cell can be a program state, namely, PROGRAM.

[0110] The state mode can be determined based on the verification results of the program operation of the memory unit. The state mode may include the first state mode PGM mode, the second state mode TPGM mode, the third state mode DPGM mode, and the inhibit mode.

[0111] Since the threshold voltage of the first memory cell MC1 is lower than the additional verification voltage PVT, the state mode of the first memory cell MC1 can be the first state mode PGM mode. Since the threshold voltage of the second memory cell MC2 is higher than the additional verification voltage PVT and lower than the pre-verification voltage PVP, the state mode of the second memory cell MC2 can be the second state mode TPGM mode. Since the threshold voltage of the third memory cell MC3 is higher than the pre-verification voltage PVP and lower than the main verification voltage PVM, the state mode of the third memory cell MC3 can be the third state mode DPGM mode. Since the threshold voltage of the fourth memory cell MC4 is higher than the main verification voltage PVM, the state mode of the fourth memory cell MC4 can be the Inhibit Mode.

[0112] To reach the program state PROGRAM as the target program state, the program operation on the first memory unit MC1 needs to be executed quickly. To reach the program state PROGRAM as the target program state, the program operation on the second memory unit MC2 needs to be executed more slowly than that on the first memory unit MC1. To reach the program state PROGRAM as the target program state, the program operation on the third memory unit MC3 needs to be executed more slowly than that on the second memory unit MC2. Since the fourth memory unit MC4 has been fully programmed to reach the target program state PROGRAM, it is necessary to disable the program operation on the fourth memory unit MC4.

[0113] Therefore, the intensity of the programming operation on the third memory unit MC3 can be lower than the intensity of the programming operation on the second memory unit MC2. Furthermore, the intensity of the programming operation on the second memory unit MC2 can be lower than the intensity of the programming operation on the first memory unit MC1. The programming intensity can be determined based on the duration of the applied programming pulse, the number of applied programming pulses, and the potential difference between the programming pulses.

[0114] For example, during the period when a program voltage is applied to a word line, a first enable voltage can be applied to the bit line coupled to the first memory cell MC1, and a second enable voltage higher than the first enable voltage can be applied to the bit line coupled to the second memory cell MC2. In this case, since the potential difference between program pulses applied to the second memory cell MC2 is smaller than the potential difference between program pulses applied to the first memory cell MC1, program operation can be performed on the second memory cell MC2 at a lower intensity.

[0115] Similarly, during the period when a program voltage is applied to the word line, a second enable voltage can be applied to the bit line coupled to the second memory cell MC2, and a third enable voltage higher than the second enable voltage can be applied to the bit line coupled to the third memory cell MC3. In this case, since the potential difference between program pulses applied to the third memory cell MC3 is less than the potential difference between program pulses applied to the second memory cell MC2, program operation can be performed on the third memory cell MC3 at a lower intensity.

[0116] Programming operations on the fourth memory cell MC4 can be restricted. For example, while a programming pulse is applied to the word line, an inhibit voltage can be applied to the bit line coupled to the fourth memory cell MC4. In this case, since the potential difference of the programming pulse applied to the fourth memory cell MC4 becomes less than the potential difference used to raise the threshold voltage of the memory cell, programming operations used to raise the threshold voltage of the fourth memory cell MC4 can be restricted.

[0117] According to an embodiment, the first permissible voltage may have a ground voltage VSS level or a negative voltage level lower than the ground voltage VSS level. The second permissible voltage may have a level higher than the ground voltage VSS level, for example, a level of 0.25 V. The third permissible voltage may have a level higher than the second permissible voltage, for example, a level of 0.5 V. The prohibition voltage may have a power supply voltage VCORE level, for example, a level of 1.8 V.

[0118] Figure 6 is a diagram illustrating the state patterns in TPGM operation according to an embodiment.

[0119] Referring to Figure 6, the state mode can be determined based on the verification results of the program operation of the memory unit. The state mode may include a first state mode PGM mode, a second state mode TPGM mode, a third state mode DPGM mode, and an inhibit mode.

[0120] For example, a successful verification indicates that the memory cell is read as a disabled cell by the corresponding verification voltage. A failed verification indicates that the memory cell is read as a powered-on cell by the corresponding verification voltage. In other words, when the threshold voltage of the memory cell is lower than the verification voltage or is on the left, the memory cell is read as a powered-on cell, and when the threshold voltage of the memory cell is higher than the verification voltage or is on the right, the memory cell is read as a disabled cell.

[0121] Referring to Figures 5 and 6, a memory cell having a state mode as a first state mode PGM mode can be read as an ON cell by each of the additional verification voltage PVT, the pre-verification voltage PVP and the main verification voltage PVM.

[0122] A memory cell having a state mode as the second state mode TPGM mode can be read as the off unit OFF by the additional verification voltage PVT, and as the on unit ON by each of the pre-verification voltage PVP and the main verification voltage PVM.

[0123] A memory cell having a state mode as the third state mode DPGM mode can be read as a shutdown unit OFF by each of the additional verification voltage PVT and the pre-verification voltage PVP, and as a conduction unit ON by the main verification voltage PVM.

[0124] A memory cell with a state mode as an Inhibit Mode can be turned off by reading each of the additional verification voltage PVT, the pre-verification voltage PVP, and the main verification voltage PVM.

[0125] Because the additional verification voltage PVT is lower than the pre-verification voltage PVP and the main verification voltage PVM, the memory cell may not be read as an ON cell by the additional verification voltage PVT and as an OFF cell by the pre-verification voltage PVP or the main verification voltage PVM. Furthermore, because the pre-verification voltage PVP is lower than the main verification voltage PVM, the memory cell may not be read as an ON cell by the pre-verification voltage PVP and as an OFF cell by the main verification voltage PVM.

[0126] Figure 7 is a diagram illustrating the incremental step pulse program (ISPP) operation including TPGM operation according to an embodiment.

[0127] Referring to Figures 5 and 7, the ISPP operation may include multiple program loops PL1 to PLn. That is, the memory device 150 executing the ISPP program may repeatedly execute the multiple program loops PL1 to PLn in a predetermined order until the program is completed, thus programming each of the multiple memory cells included in the selected word line such that each of the multiple memory cells has either an erase state ERASE or a program state PROGRAM as the target program state. As used herein, the term "predetermined" (such as predetermined order and predetermined level) means that the value of the parameter is determined before the parameter is used in the process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0128] Each of the multiple program loops PL1 to PLn may include a program operation PGM step and a verification operation Verify Step. The PGM step includes a program voltage application operation that applies a program voltage to the selected word line and a bit line setting operation for the multiple bit lines BLs. The verification step sequentially applies N-1 verification voltages to the selected word line and verifies which of the N types of first program states each of the multiple memory cells included in the selected word line has. In this way, based on the result of verifying the N types of program states for each of the multiple memory cells included in the selected word line in the Verify Step of the previous program loop, any one of the N types of column voltages can be applied to each of the multiple bit lines BLs in the bit line setting operation included in the program operation PGM step of the subsequent program loop. In other words, based on the results of verifying N types of first program states for each of the multiple memory cells included in the selected word lines in the Verify Step of the previously executed first program loop PL1, any of the N types of column voltages can be applied to each of the multiple bit lines BLs in the bit line setting operation included in the program operation PGM step of the subsequently executed second program loop PL2.

[0129] Specifically, assuming "N" is 4, in the Verify Step, a verification operation can be performed on each of the multiple memory cells included in the selected word line using the additional verification voltage PVT, the pre-verification voltage PVP, and the main verification voltage PVM. The main verification voltage PVM can be a verification voltage corresponding to the target program state of the program operation. The pre-verification voltage PVP can be a voltage that verifies the degree of program operation performed on the memory cell, and its level is lower than the level of the main verification voltage PVM. Similarly, the additional verification voltage PVT can be a voltage that verifies the degree of program operation performed on the memory cell, and its level is lower than the level of the pre-verification voltage PVP.

[0130] For example, if the verification passes, the memory cell is read as a turned-off cell by the corresponding verification voltage. If the verification fails, the memory cell is read as a turned-on cell by the corresponding verification voltage.

[0131] For example, when the first program loop PL1 is executed, an additional verification voltage PVT, a pre-verification voltage PVP, and a main verification voltage PVM can be applied in a predetermined order, such that the program state of the multiple memory cells included in the selected word line is verified in the Verify Step operation following the application of the first program voltage Vpgm1. The predetermined order may refer to the order in which the additional verification voltage PVT, the pre-verification voltage PVP, and the main verification voltage PVM are applied to the selected word line in sequence. Conversely, the predetermined order may refer to the order in which the main verification voltage PVM, the pre-verification voltage PVP, and the additional verification voltage PVT are applied to the selected word line in sequence.

[0132] According to an embodiment, a memory cell that is read as having failed verification by the additional verification voltage PVT can be determined as a memory cell having a state mode of the first state mode PGM mode. A memory cell that is read as having passed verification by the additional verification voltage PVT and as having failed verification by the pre-verification voltage PVP can be determined as a memory cell having a state mode of the second state mode TPGM mode. A memory cell that is read as having passed verification by the pre-verification voltage PVP and as having failed verification by the main verification voltage PVM can be determined as a memory cell having a state mode of the third state mode DPGM mode. A memory cell that is read as having passed verification by the main verification voltage PVM can be determined as a memory cell having a state mode of the Inhibit Mode. A memory cell having a state mode of the Inhibit Mode can be disabled in the second program loop PL2, which is executed after the first program loop PL1.

[0133] A second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1 used in the first programming loop PL1, can be applied to program memory cells other than those that are disabled in programming in the second programming loop PL2. Subsequently, the verification operation of the second programming loop PL2 can be performed in the same manner as the verification operation of the first programming loop PL1.

[0134] In the Verify Step operation, it can be determined whether the verification of each of the multiple memory cells included in the selected word line has passed based on the current or voltage flowing through multiple bit lines coupled to each of the multiple memory cells included in the selected word line.

[0135] Figure 8 is a diagram illustrating the operation of TPGM according to another embodiment.

[0136] The TPGM operation according to this embodiment described above with reference to FIGS. 5 to 7 has been described under the assumption that the memory cells are single-layer cells (SLCs) where each cell stores one data bit. Therefore, the TPGM operation according to this embodiment described in FIG. 5 may include a verification operation to check a target program state (i.e., program state PROGRAM) by verifying four types of program states using three verification voltages.

[0137] Referring to Figure 8, the TPGM operation is described under the assumption that the memory cell is a multi-level cell (MLC) that stores two data bits each.

[0138] In this document, it can be assumed that the program for the multi-layer memory cell includes three target program states, namely, the first program state PROGRAM1, the second program state PROGRAM2, and the third program state PROGRAM3. Therefore, multiple program loops PL1 to PLn can be repeatedly executed in a predetermined order by the ISPP operation described in FIG7, such that each of the multiple multi-layer memory cells included in the selected word line can be programmed as any one of the first program states to the third program states PROGRAM1, PROGRAM2, and PROGRAM3, which have the erase state ERASE and are the target program states.

[0139] Since it is assumed that the program for the multi-layer memory cell includes three target program states PROGRAM1, PROGRAM2 and PROGRAM3, one of the multiple program loops PL1 to PLn may include a verification operation. In the verification operation, the operation of verifying the four program states by using three verification voltages PVT1, PVP1 and PVM1 or PVT2, PVP2 and PVM2 or PVT3, PVP3 and PVM3 after the program operation is executed is repeated up to 3 times.

[0140] According to an embodiment, three first verification voltages PVT1, PVP1, and PVM1 (i.e., a first additional verification voltage PVT1, a first pre-verification voltage PVP1, and a first main verification voltage PVM1) can be used to check the first program state PROGRAM1 among the three target program states PROGRAM1, PROGRAM2, and PROGRAM3. In this case, the first main verification voltage PVM1 can be the verification voltage corresponding to the first program state PROGRAM1.

[0141] Three second verification voltages, PVT2, PVP2, and PVM2 (i.e., second additional verification voltage PVT2, second pre-verification voltage PVP2, and second main verification voltage PVM2) can be used to check the second program state PROGRAM2 among the three target program states PROGRAM1, PROGRAM2, and PROGRAM3. In this case, the second main verification voltage PVM2 can be the verification voltage corresponding to the second program state PROGRAM2.

[0142] The three third verification voltages PVT3, PVP3, and PVM3 (i.e., the third additional verification voltage PVT3, the third pre-verification voltage PVP3, and the third main verification voltage PVM3) can be used to check the third program state PROGRAM3 among the three target program states PROGRAM1, PROGRAM2, and PROGRAM3. In this case, the third main verification voltage PVM3 can be the verification voltage corresponding to the third program state PROGRAM3.

[0143] Among the three target program states PROGRAM1, PROGRAM2, and PROGRAM3, the first program state PROGRAM1 may have the lowest level, and the third program state PROGRAM3 may have the highest level. Therefore, the maximum level of the three first verification voltages PVT1, PVP1, and PVM1 used to check the first program state PROGRAM1 (i.e., the level of the first main verification voltage PVM1) may be lower than the maximum level of the three second verification voltages PVT2, PVP2, and PVM2 used to check the second program state PROGRAM2 (i.e., the level of the second main verification voltage PVM2).

[0144] Similarly, the maximum level of the three second verification voltages PVT2, PVP2 and PVM2 used to check the second program state PROGRAM2 (i.e., the level of the second main verification voltage PVM2) can be lower than the maximum level of the three third verification voltages PVT3, PVP3 and PVM3 used to check the third program state PROGRAM3 (i.e., the level of the third main verification voltage PVM3).

[0145] The state mode of each of the three target program states PROGRAM1, PROGRAM2 and PROGRAM3 can be determined based on the verification results of the program operation of the memory unit as described with reference to FIG5.

[0146] That is to say, the state modes of the first program state PROGRAM1 may include the first state mode PGM mode, the second state mode TPGM mode, the third state mode DPGM mode, and the Inhibit Mode. The state modes of the second program state PROGRAM2 may include the first state mode PGM mode, the second state mode TPGM mode, the third state mode DPGM mode, and the Inhibit Mode. The state modes of the third program state PROGRAM3 may include the first state mode PGM mode, the second state mode TPGM mode, the third state mode DPGM mode, and the Inhibit Mode.

[0147] The first to fourth memory units MC1, MC2, MC3 and MC4 can have a first program state PROGRAM1 as the target program state. The fifth to eighth memory units MC5, MC6, MC7 and MC8 can have a second program state PROGRAM2 as the target program state. The ninth to twelfth memory units MC9, MCA, MCB and MCC can have a third program state PROGRAM3 as the target program state.

[0148] Since the threshold voltage of the first memory cell MC1 is lower than the first additional verification voltage PVT1, the threshold voltage of the fifth memory cell MC5 is lower than the second additional verification voltage PVT2, and the threshold voltage of the ninth memory cell MC9 is lower than the third additional verification voltage PVT3, the state mode of the first memory cell MC1, the fifth memory cell MC5 and the ninth memory cell MC9 can be the first state mode PGM mode.

[0149] Since the threshold voltage of the second memory cell MC2 is higher than the first additional verification voltage PVT1 and lower than the first pre-verification voltage PVP1, the threshold voltage of the sixth memory cell MC6 is higher than the second additional verification voltage PVT2 and lower than the second pre-verification voltage PVP2, and the threshold voltage of the tenth memory cell MC10 is higher than the third additional verification voltage PVT3 and lower than the third pre-verification voltage PVP3, the state mode of the second memory cell MC2, the sixth memory cell MC6 and the tenth memory cell MCA can be the second state mode TPGM mode.

[0150] Since the threshold voltage of the third memory cell MC3 is higher than the first pre-verification voltage PVP1 and lower than the first main verification voltage PVM1, the threshold voltage of the seventh memory cell MC7 is higher than the second pre-verification voltage PVP2 and lower than the second main verification voltage PVM2, and the threshold voltage of the eleventh memory cell MCB is higher than the third pre-verification voltage PVP3 and lower than the third main verification voltage PVM3, the state mode of the third memory cell MC3, the seventh memory cell MC7 and the eleventh memory cell MCB can be the third state mode DPGM mode.

[0151] Since the threshold voltage of the fourth memory cell MC4 is higher than the first main verification voltage PVM1, the threshold voltage of the eighth memory cell MC8 is higher than the second main verification voltage PVM2, and the threshold voltage of the twelfth memory cell MCC is higher than the third main verification voltage PVM3, the state mode of the fourth memory cell MC4, the eighth memory cell MC8 and the twelfth memory cell MCC can be the Inhibit Mode.

[0152] It is necessary to quickly execute program operations on the first memory unit MC1, the fifth memory unit MC5 and the ninth memory unit MC9 so that the first memory unit MC1, the fifth memory unit MC5 and the ninth memory unit MC9 can respectively reach the first program state PROGRAM1, the second program state PROGRAM2 and the third program state PROGRAM3 as target program states.

[0153] Programming operations on the second memory unit MC2, the sixth memory unit MC6, and the tenth memory unit MCA need to be executed more slowly than programming operations on the first memory unit MC1, the fifth memory unit MC5, and the ninth memory unit MC9, so that the second memory unit MC2, the sixth memory unit MC6, and the tenth memory unit MCA can respectively reach the first program state PROGRAM1, the second program state PROGRAM2, and the third program state PROGRAM3 as target program states.

[0154] Programming operations on the third memory unit MC3, the seventh memory unit MC7, and the eleventh memory unit MCB need to be executed more slowly than programming operations on the second memory unit MC2, the sixth memory unit MC6, and the tenth memory unit MCA, so that the third memory unit MC3, the seventh memory unit MC7, and the eleventh memory unit MCB can respectively reach the first program state PROGRAM1, the second program state PROGRAM2, and the third program state PROGRAM3 as the target program state.

[0155] Since the programming of the fourth memory unit MC4, the eighth memory unit MC8, and the twelfth memory unit MCC, which respectively have the first program state PROGRAM1, the second program state PROGRAM2, and the third program state PROGRAM3 as target program states, has been completed, it is necessary to prohibit program operations on the fourth memory unit MC4, the eighth memory unit MC8, and the twelfth memory unit MCC.

[0156] Therefore, the intensity of the programming operation on each of the third memory unit MC3, the seventh memory unit MC7, and the eleventh memory unit MCB can be lower than the intensity of the programming operation on each of the second memory unit MC2, the sixth memory unit MC6, and the tenth memory unit MCA. Furthermore, the intensity of the programming operation on each of the second memory unit MC2, the sixth memory unit MC6, and the tenth memory unit MCA can be lower than the intensity of the programming operation on each of the first memory unit MC1, the fifth memory unit MC5, and the ninth memory unit MC9. The programming intensity can be determined based on the duration of the applied programming pulse, the number of applied programming pulses, and the potential difference between the programming pulses.

[0157] For example, during the period when a program voltage is applied to a word line, a first allowable voltage may be applied to a bit line coupled to each of the first memory cell MC1, the fifth memory cell MC5, and the ninth memory cell MC9, and a second allowable voltage higher than the first allowable voltage may be applied to a bit line coupled to each of the second memory cell MC2, the sixth memory cell MC6, and the tenth memory cell MCA. In this case, since the potential difference between the program pulses applied to each of the second memory cell MC2, the sixth memory cell MC6, and the tenth memory cell MCA is less than the potential difference between the program pulses applied to each of the first memory cell MC1, the fifth memory cell MC5, and the ninth memory cell MC9, program operation can be performed on each of the second memory cell MC2, the sixth memory cell MC6, and the tenth memory cell MCA at a lower intensity.

[0158] Similarly, during the period when the program voltage is applied to the word line, a second enable voltage can be applied to the bit line coupled to each of the second memory cell MC2, the sixth memory cell MC6, and the tenth memory cell MCA, and a third enable voltage higher than the second enable voltage can be applied to the bit line coupled to each of the third memory cell MC3, the seventh memory cell MC7, and the eleventh memory cell MCB. In this case, since the potential difference between the program pulses applied to each of the third memory cell MC3, the seventh memory cell MC7, and the eleventh memory cell MCB is smaller than the potential difference between the program pulses applied to each of the second memory cell MC2, the sixth memory cell MC6, and the tenth memory cell MCA, the program operation can be performed on each of the third memory cell MC3, the seventh memory cell MC7, and the eleventh memory cell MCB with a lower intensity.

[0159] Programming operations on each of the fourth memory cell MC4, the eighth memory cell MC8, and the twelfth memory cell MCC can be restricted. For example, while a program pulse is applied to a word line, an inhibit voltage can be applied to a bit line coupled to each of the fourth memory cell MC4, the eighth memory cell MC8, and the twelfth memory cell MCC. In this case, since the potential difference between the program pulses applied to each of the fourth memory cell MC4, the eighth memory cell MC8, and the twelfth memory cell MCC becomes less than the potential difference used to raise the threshold voltage of the memory cell, programming operations used to raise the threshold voltage of each of the fourth memory cell MC4, the eighth memory cell MC8, and the twelfth memory cell MCC can be restricted.

[0160] According to an embodiment, the first permissible voltage may have a ground voltage VSS level or a negative voltage level lower than the ground voltage VSS level. The second permissible voltage may have a level higher than the ground voltage VSS level, for example, a level of 0.25 V. The third permissible voltage may have a level higher than the second permissible voltage, for example, a level of 0.5 V. The prohibition voltage may have a power supply voltage VCORE level, for example, a level of 1.8 V.

[0161] According to an embodiment, in the first program loop PL1 among multiple program loops PL1 to PLn, a verification operation can be performed to verify four program states for checking the first program state PROGRAM1 by using three first verification voltages PVT1, PVP1, and PVM1 after the program operation is executed. In this case, the state mode of the memory cell having the second program state PROGRAM2 and the third program state PROGRAM3 as the target program states can also be classified according to the four types of state modes of the first program state PROGRAM1.

[0162] Subsequently, in the second program loop PL2, after the program operation is executed, verification operations can be performed to verify four program states using three first verification voltages PVT1, PVP1, and PVM1 to check the first program state PROGRAM1, and to verify four program states using three second verification voltages PVT2, PVP2, and PVM2 to check the second program state PROGRAM2. In this case, the memory cell with the first program state PROGRAM1 as the target program state can be classified according to the four types of state modes of the first program state PROGRAM1, and the memory cell with the second program state PROGRAM2 and the third program state PROGRAM3 as target program states can be classified according to the four types of state modes of the second program state PROGRAM2.

[0163] Subsequently, in the third program loop PL3, after executing the program operation, verification operations can be performed to verify four program states using three first verification voltages PVT1, PVP1, and PVM1 to check the first program state PROGRAM1, to verify four program states using three second verification voltages PVT2, PVP2, and PVM2 to check the second program state PROGRAM2, and to verify four program states using three third verification voltages PVT3, PVP3, and PVM3 to check the third program state PROGRAM3. In this case, the memory cell with the first program state PROGRAM1 as the target program state can be classified according to the four types of state modes of the first program state PROGRAM1, the memory cell with the second program state PROGRAM2 as the target program state can be classified according to the four types of state modes of the second program state PROGRAM2, and the memory cell with the third program state PROGRAM3 as the target program state can be classified according to the four types of state modes of the third program state PROGRAM3.

[0164] When all memory cells with the first program state PROGRAM1 as the target program state are checked through the first program loop PL1 to the third program loop PL3, and all memory cells with the first program state PROGRAM1 as the target program state have reached the first program state PROGRAM1, in the subsequent fourth program loop PL4, after the program operation is executed, verification operations can be performed to verify four program states using three second verification voltages PVT2, PVP2, and PVM2 to check the second program state PROGRAM2, and to verify four program states using three third verification voltages PVT3, PVP3, and PVM3 to check the third program state PROGRAM3. In this case, all memory cells with the first program state PROGRAM1 as the target program state can be classified into disabled mode, memory cells with the second program state PROGRAM2 as the target program state can be classified according to the four types of state modes of the second program state PROGRAM2, and memory cells with the third program state PROGRAM3 as the target program state can be classified according to the four types of state modes of the third program state PROGRAM3.

[0165] Figure 9 is a diagram illustrating the configuration of the page buffer circuit according to the first embodiment.

[0166] Referring to Figure 9, the page buffer PBx is a circuit diagram illustrating any one of the multiple page buffers PB1 to PBm described with reference to Figure 2. Each PBx of the multiple page buffers PB1 to PBm may include M latches. In this document, "M" can be a natural number equal to or greater than 2. In the figure, assuming "M" is 2, it can be seen that each PBx of the multiple page buffers PB1 to PBm includes two latches 91 and 92.

[0167] The control circuit 152, described with reference to Figures 2 and 4, can input M bit setting codes of N types into M latches included in each of the multiple page buffers PB1 to PBm during a bit line setting operation, and generate N types of column voltages. Assuming "N" is 4 and "M" is 2, the control circuit 152 can input 2 bit setting codes of four types into two latches 91 and 92 included in each of the multiple page buffers PB1 to PBm during a bit line setting operation, and generate four types of column voltages A, B, C, and D. According to an embodiment, the Mth square root of N can be set to a value of 2 or greater.

[0168] That is, when determining the values ​​of multiple M bit setting codes corresponding to multiple bit lines based on the result of verifying N types of program states for each of the multiple memory cells included in the selected word lines in the verification operation of the first program loop executed first, in order to check a target program state, the control circuit 152 can, during the bit line setting operation of the second program loop executed after the first program loop, input the values ​​of the M bit setting codes determined in the first program loop to M latches included in each of the multiple page buffers PB1 to PBm, and then apply multiple column voltages to each of the multiple page buffers PB1 to PBm. Each of the multiple column voltages can be one of N types of column voltages.

[0169] For reference, an external component of the control circuit 152, such as control logic 153, can check the result of the verification operation of the first program loop, determine the values ​​of the multiple M-bit setting codes based on the check result, and then input the values ​​of the multiple M-bit setting codes to the control circuit 152. Alternatively, the control circuit 152 may determine the values ​​of the multiple M-bit setting codes by directly checking the result of the verification operation of the first program loop. Furthermore, the initial values ​​of the multiple M-bit setting codes (i.e., the multiple M-bit setting values ​​that can be input in the first executed program loop) can be predetermined based on the type or characteristics of the memory device.

[0170] According to an embodiment, assuming "N" is 4 and "M" is 2, when the value of a specific 2-bit setting code corresponding to a bit line coupled to a specific memory cell is determined based on the result of verifying four types of program states of the memory cell in the verification operation of the first program loop, the control circuit 152 can input the value of the 2-bit setting code into two latches included in a page buffer corresponding to the bit line during the bit line setting operation of the second program loop executed after the first program loop, generate a column voltage, and then apply the column voltage to the bit line. The column voltage can be one of four types of column voltages.

[0171] Referring to Figures 2 and 4, the control logic 153 can control the control circuit 152 to input M bit setting codes of N types into M latches included in each of the multiple page buffers PB1 to PBm during a bit line setting operation and generate N types of column voltages. In this case, the N types of column voltages can be included in the bit line control signal BL_Con sent from the control logic 153 to the control circuit 152. Assuming that "N" is 4 and "M" is 2, the control logic 153 can control the control circuit 152 during the bit line setting operation to input four types of 2-bit setting codes into two latches 91 and 92 included in each of the multiple page buffers PB1 to PBm and generate four types of column voltages A, B, C, and D.

[0172] That is, control logic 153 can determine the values ​​of multiple M bit setting codes corresponding to multiple bit lines based on the result of verifying N types of program states for each of the multiple memory units included in the selected word line in the verification operation of the first program loop executed first, in order to check a target program state. Additionally, during the bit line setting operation of the second program loop executed after the first program loop, control logic 153 can control control circuit 152 to input the values ​​of the M bit setting codes determined in the first program loop into M latches included in each of the multiple page buffers PB1 to PBm, generating multiple column voltages, and then applying the multiple column voltages to each of the multiple bit lines. In this case, each of the multiple column voltages can be one of N types of column voltages.

[0173] According to an embodiment, assuming "N" is 8 and "M" is 3, control logic 153 can determine the value of a 3-bit set code corresponding to a bit line coupled to a specific memory cell based on the result of verifying eight types of program states of the memory cell in the verification operation of the first program loop. Furthermore, during the bit line set operation of the second program loop executed after the first program loop, control logic 153 can control control circuit 152 to input the value of the 3-bit set code into three latches included in a page buffer corresponding to a bit line, generating a column voltage, and then applying the column voltage to a bit line. A column voltage can be one of eight types of column voltages.

[0174] Referring to Figure 9, each PBx among the multiple page buffers PB1 to PBm may include M latches 91 and 92, a first NMOS transistor N1, a first PMOS transistor P1, (N / 2)-1 second NMOS transistors N2, (N / 2)-1 second PMOS transistors P2, a third NMOS transistor N3, and a coupling control unit 94. Assuming "N" is 4, each PBx among the multiple page buffers PB1 to PBm may include two latches 91 and 92, one first NMOS transistor N1, one first PMOS transistor P1, one second NMOS transistor N2, one second PMOS transistor P2, one third NMOS transistor N3, and a coupling control unit 94.

[0175] The first NMOS transistor N1 can couple the sensing node SO to the first node ND1 in response to the power supply voltage VCORE applied to its gate.

[0176] The first PMOS transistor P1 can couple the sensing node SO to the second node ND2 in response to the ground voltage VSS applied to its gate.

[0177] (N / 2)-1 second NMOS transistors N2 can each respond to a (N / 2)-1 type of first reference voltage REF1 to couple the sensing node SO to (N / 2)-1 third nodes ND3. Assuming "N" is 4, a second NMOS transistor N2 can respond to a type of first reference voltage REF1 to couple the sensing node SO to a third node ND3.

[0178] (N / 2)-1 second PMOS transistors P2 can each respond to (N / 2)-1 types of second reference voltages REF2 to couple the sensing node SO to (N / 2)-1 fourth nodes ND4. Assuming "N" is 4, a second PMOS transistor P2 can respond to one type of second reference voltage REF2 to couple the sensing node SO to a fourth node ND4.

[0179] The third NMOS transistor N3 can couple the sensing node SO to the bit line BL in response to the voltage applied signal PBSENSE.

[0180] The coupling control unit 94 can couple any one of the first to fourth nodes ND1, ND2, ND3, and ND4 to the power supply voltage VCORE terminal or the ground voltage VSS terminal, depending on the type of the M-bit setting code input to the M latches 91 and 92. Assuming "M" is 2, the coupling control unit 94 can couple at least one of the first to fourth nodes ND1, ND2, ND3, and ND4 to the power supply voltage VCORE terminal or the ground voltage VSS terminal, depending on the type of the 2-bit setting code 00, 01, 10, and 11 input to the two latches 91 and 92.

[0181] Referring to Figures 2, 4, and 9, the control circuit 152 can generate a voltage application signal PBSENSE with a predetermined level higher than the power supply voltage VCORE level during the bit line setup operation, and input the generated voltage application signal PBSENSE to the third NMOS transistor N3 included in each of the plurality of page buffers PB1 to PBm. That is, the control circuit 152 can control each of the plurality of page buffers PB1 to PBm during the bit line setup operation to keep the bit line BL and the sensing node SO in an electrically coupled state. Therefore, the voltage level applied to the sensing node SO during the bit line setup operation can be transmitted to the bit line BL without loss. In addition, the control circuit 152 can input multiple M bit setting codes into the M latches 91 and 92 included in each PBx of multiple page buffers PB1 to PBm during the bit line setting operation, and control the coupling control unit 94 to couple at least one of the first to fourth nodes ND1, ND2, ND3 and ND4 included in each PBx of page buffers PB1 to PBm to the power supply voltage VCORE terminal or the ground voltage VSS terminal.

[0182] Referring to Figures 2, 4, and 9, control logic 153 can control control circuit 152 to generate a voltage application signal PBSENSE with a predetermined level higher than the power supply voltage VCORE level during a bit line setup operation, and input the generated voltage application signal PBSENSE to a third NMOS transistor N3 included in each of the plurality of page buffers PB1 to PBm. That is, control logic 153 can control control circuit 152 to allow each of the plurality of page buffers PB1 to PBm to maintain bit line BL and sensing node SO in an electrically coupled state during a bit line setup operation. Therefore, the voltage level applied to sensing node SO during a bit line setup operation can be transmitted to bit line BL without loss. In addition, control logic 153 can control control circuit 152 to input multiple M bit setting codes into M latches 91 and 92 included in each PBx of multiple page buffers PB1 to PBm during bit line setting operation, and through coupling control unit 94, couple at least one of the first to fourth nodes ND1, ND2, ND3 and ND4 included in each PBx of page buffers PB1 to PBm to the power supply voltage VCORE terminal or the ground voltage VSS terminal.

[0183] More specifically, referring to FIG9, the coupling control unit 94 can respond to the input of a first setting code among N types of M-bit setting codes to M latches 91 and 92 included in each of the multiple page buffers PB1 to PBm, thereby coupling the ground voltage VSS terminal to the first node ND1, thereby controlling the first column voltage A with the ground voltage VSS level to be loaded onto the sensing node SO through the first NMOS transistor N1. According to the embodiment, assuming "N" is 4 and "M" is 2, when the first setting code with the value "00" is applied to the corresponding input terminals QS_N and QM_N of the two latches 91 and 92 and the values ​​of the corresponding output terminals QS and QM of the two latches 91 and 92 are "11", the two NMOS transistors N4 and N5 included in the coupling control unit 94 can be turned on, and the two PMOS transistors P3 and P4 included in the coupling control unit 94 can be turned off, so that the first node ND1 can be coupled to the ground voltage VSS terminal. Since the first NMOS transistor N1, coupled between the first node ND1 and the sensing node SO, turns on in response to the power supply voltage VCORE applied to its gate, the first column voltage A with the ground voltage VSS level can be applied to the sensing node SO.

[0184] The coupling control unit 94 can respond to the input of a second setting code among N types of M-bit setting codes to M latches 91 and 92 included in each of the multiple page buffers PB1 to PBm, thereby coupling the power supply voltage VCORE terminal to the second node ND2, thereby controlling the second column voltage D with the power supply voltage VCORE level to be loaded onto the sensing node SO by the first PMOS transistor P1. According to the embodiment, assuming "N" is 4 and "M" is 2, when the second setting code with the value "11" is applied to the corresponding input terminals QS_N and QM_N of the two latches 91 and 92 and the values ​​of the corresponding output terminals QS and QM of the two latches 91 and 92 are "00", the two NMOS transistors N4 and N5 included in the coupling control unit 94 can be turned off, and the two PMOS transistors P3 and P4 included in the coupling control unit 94 can be turned on, so the second node ND2 can be coupled to the power supply voltage VCORE terminal. Since the first PMOS transistor P1, coupled between the second node ND2 and the sensing node SO, turns on in response to the ground voltage VSS applied to its gate, the second column voltage D with the power supply voltage VCORE level can be applied to the sensing node SO.

[0185] The coupling control unit 94 can respond to each of the (N / 2)-1 types of third setting codes among the N types of M-bit setting codes being input to the M latches 91 and 92 included in each of the multiple page buffers PB1 to PBm to couple the power supply voltage VCORE terminal to the third node ND3, thereby controlling the (N / 2)-1 types of third column voltage B having sequential levels between the power supply voltage VCORE level and the ground voltage VSS level to be loaded onto the sensing node SO through the NMOS clamping method in the second NMOS transistor N2. According to the embodiment, assuming "N" is 4 and "M" is 2, when a third setting code with the value "10" is applied to the corresponding input terminals QS_N and QM_N of the two latches 91 and 92, and the values ​​of the corresponding output terminals QS and QM of the two latches 91 and 92 are "01", a PMOS transistor P3 and an NMOS transistor N5 included in the coupling control unit 94 can be turned on, and a PMOS transistor P4 and an NMOS transistor N4 included in the coupling control unit 94 can be turned off. Therefore, the third node ND3 can be coupled to the power supply voltage VCORE terminal. The second NMOS transistor N2 coupled between the third node ND3 and the sensing node SO can determine the level of the third column voltage B precharged to the sensing node SO through the NMOS clamping method according to the power supply voltage VCORE level in response to the first reference voltage REF1 applied to its gate. At this point, NMOS clamping may occur because the level of the first reference voltage REF1 applied to the gate of the second NMOS transistor N2 is not a higher threshold voltage level than the level of the supply voltage VCORE coupled to its drain. The level of the third column voltage B can be obtained by subtracting the threshold voltage level of the second NMOS transistor N2 from the level of the first reference voltage REF1. For example, assuming the level of the supply voltage VCORE is 1.8 V, the level of the first reference voltage REF1 is 1.25 V, and the level of the threshold voltage of the second NMOS transistor N2 is 1 V, then the level of the third column voltage B can be 0.25 V.

[0186] The coupling control unit 94 can respond to each of the (N / 2)-1 types of fourth setting codes of M latches 91 and 92 included in each of the multiple page buffers PB1 to PBm, which do not overlap with the third setting code, and couple the ground voltage VSS terminal to each of the (N / 2)-1 fourth nodes ND4, thereby controlling the (N / 2)-1 types of fourth column voltage C, which has a sequential level between the power supply voltage VCORE level and the ground voltage VSS level and is higher than the third column voltage B, to be loaded onto the sensing node SO through the PMOS clamping method in the second PMOS transistor P2.

[0187] According to an embodiment, assuming "N" is 4 and "M" is 2, when a fourth setting code with the value "01" is applied to the corresponding input terminals QS_N and QM_N of the two latches 91 and 92, and the values ​​of the corresponding output terminals QS and QM of the two latches 91 and 92 are "10", a PMOS transistor P4 and an NMOS transistor N4 included in the coupling control unit 94 can be turned on, and a PMOS transistor P3 and an NMOS transistor N5 included in the coupling control unit 94 can be turned off. Therefore, the fourth node ND4 can be coupled to the ground voltage VSS terminal. The second PMOS transistor P2 coupled between the fourth node ND4 and the sensing node SO can determine the level of the fourth column voltage C discharged in the sensing node SO through the PMOS clamping method according to the ground voltage VSS level in response to the second reference voltage REF2 applied to its gate. At this point, because the level of the second reference voltage REF2 applied to the gate of the second PMOS transistor P2 is not lower than the threshold voltage level of the ground voltage VSS coupled to its drain, PMOS clamping may occur. The level of the fourth column voltage C can be obtained by adding the threshold voltage level of the second PMOS transistor P2 to the level of the second reference voltage REF2. For example, assuming the level of the ground voltage VSS is 0 V, the level of the second reference voltage REF2 is -0.5 V, and the threshold voltage level of the second PMOS transistor P2 is 1 V, then the fourth column voltage C can be 0.5 V.

[0188] FIG10 is a diagram illustrating the operation of the page buffer shown in FIG9 according to the first embodiment.

[0189] Referring to FIG10, the program operations included in the program loop may include bit line setting operations t1 to t3 and program voltage application operations t2 to t4.

[0190] In the bit line setting operation, M bit setting codes of N types can be input into M latches included in each of the multiple page buffers PB1 to PBm, and N types of column voltages A, B, C, and D can be generated. The generated N types of column voltages A, B, C, and D can be selectively applied to each bit line coupled to the memory cell of the selected word line selected as the program target among the multiple word lines.

[0191] According to an embodiment, a second column voltage D, which is the highest voltage among the N types of column voltages A, B, C, and D and has a power supply voltage VCORE level, can be applied as a disable voltage to a bit line coupled to a program disable cell among the plurality of memory cells included in the selected word line. A first column voltage A, which is the lowest voltage among the N types of column voltages A, B, C, and D and has a ground voltage VSS level, can be applied as a first enable voltage to a bit line coupled to a first cell among the plurality of memory cells included in the selected word line that has a threshold voltage lower than the additional verification voltage PVT. A third column voltage B, which is the third highest voltage among the N types of column voltages A, B, C, and D, can be applied as a second enable voltage to a bit line coupled to a second cell among the plurality of memory cells included in the selected word line that has a threshold voltage higher than the additional verification voltage PVT and lower than the pre-verification voltage PVP. The fourth column voltage C, which is the second highest among the N types of column voltages A, B, C, and D, can be applied as the third allowable voltage to a bit line coupled to a third cell among the multiple memory cells included in the selected word line, which has a threshold voltage higher than the pre-verification voltage PVP and lower than the main verification voltage PVM.

[0192] As described above, any one of the N types of column voltages A, B, C, and D can be applied to each of the multiple bit lines through a bit line setting operation, and then a program voltage can be applied to the selected word line through a program voltage application operation. Therefore, in the program voltage application operation, the strength of the program operation on the third unit can be lower than the strength of the program operation on the second unit. At the same time, the strength of the program operation on the second unit can be lower than the strength of the program operation on the first unit. Of course, the program operation on the program disable unit can be restricted.

[0193] FIG11 is a diagram illustrating the configuration of the page buffer circuit according to the second embodiment.

[0194] Referring to Figure 11, the page buffer PBx is a circuit diagram illustrating any one of the multiple page buffers PB1 to PBm described with reference to Figure 2. Each PBx of the multiple page buffers PB1 to PBm may include M latches. In this document, "M" can be a natural number equal to or greater than 2. In the figure, assuming "M" is 3, it can be seen that each PBx of the multiple page buffers PB1 to PBm includes three latches 101, 102, and 103.

[0195] Comparing the configuration of the page buffer circuit according to the first embodiment disclosed in FIG9 and the configuration of the page buffer circuit according to the second embodiment disclosed in FIG11, it can be seen that FIG9 shows the configuration of the page buffer circuit designed under the assumption that “N” is 4 and “M” is 2, while FIG11 illustrates the configuration of the page buffer circuit designed under the assumption that “N” is 8 and “M” is 3.

[0196] Therefore, the operation of the page buffer circuit according to the second embodiment disclosed in FIG11 is almost identical to the operation of the page buffer circuit according to the first embodiment described with reference to FIG9. Hereinafter, the differences between the configuration of the page buffer circuit according to the first embodiment disclosed in FIG9 and the configuration of the page buffer circuit according to the second embodiment disclosed in FIG11 will be described.

[0197] Referring to Figure 11, each PBx in the plurality of page buffers PB1 to PBm may include M latches 101, 102 and 103, a first NMOS transistor N1, a first PMOS transistor P1, (N / 2)-1 second NMOS transistors N2_1, N2_2 and N2_3, (N / 2)-1 second PMOS transistors P2_1, P2_2 and P2_3, a third NMOS transistor N3 and a coupled control unit 104. Assuming "N" is 8 and "M" is 3, each PBx in the multiple page buffers PB1 to PBm may include three latches 101, 102 and 103, a first NMOS transistor N1, a first PMOS transistor P1, three second NMOS transistors N2_1, N2_2 and N2_3, three second PMOS transistors P2_1, P2_2 and P2_3, a third NMOS transistor N3 and a coupled control unit 104.

[0198] The first NMOS transistor N1 can couple the sensing node SO to the first node ND1 in response to the power supply voltage VCORE applied to its gate.

[0199] The first PMOS transistor P1 can couple the sensing node SO to the second node ND2 in response to the ground voltage VSS applied to its gate.

[0200] (N / 2)-1 second NMOS transistors N2_1, N2_2, and N2_3 can respond to (N / 2)-1 types of first reference voltages REF1<1:3> respectively, thereby coupling the sensing node SO to (N / 2)-1 third nodes ND3_1, ND3_2, and ND3_3. Assuming "N" is 8 and "M" is 3, the three second NMOS transistors N2_1, N2_2, and N2_3 can respond to three types of first reference voltages REF1<1:3>, thereby coupling the sensing node SO to the three third nodes ND3_1, ND3_2, and ND3_3.

[0201] (N / 2)-1 second PMOS transistors P2_1, P2_2, and P2_3 can respond to (N / 2)-1 types of second reference voltages REF2<1:3> respectively, thus coupling the sensing node SO to (N / 2)-1 fourth nodes ND4_1, ND4_2, and ND4_3. Assuming "N" is 8 and "M" is 3, the three second PMOS transistors P2_1, P2_2, and P2_3 can respond to three types of second reference voltages REF2<1:3>, thus coupling the sensing node SO to the three fourth nodes ND4_1, ND4_2, and ND4_3.

[0202] The third NMOS transistor N3 can respond to the voltage applied signal PBSENSE and couple the sensing node SO to the bit line BL.

[0203] The coupling control unit 104 can couple any one of the first to fourth nodes ND1, ND2, ND3, and ND4 to the power supply voltage VCORE terminal or the ground voltage VSS terminal according to the type of the M-bit setting code input to the M latches 101, 102, and 103. Assuming "N" is 8 and "M" is 3, the coupling control unit 104 can couple at least one of the first to fourth nodes ND1, ND2, ND3_1, ND3_2, ND3_3, ND4_1, ND4_2, and ND4_3 to the power supply voltage VCORE terminal or the ground voltage VSS terminal according to the type of the 3-bit setting code input to the three latches 101, 102, and 103, 000, 001, 010, 011, 100, 101, 110, and 111.

[0204] More specifically, referring to FIG11, the coupling control unit 104 may respond to the input of a first setting code among the M-bit setting codes of N types to the M latches 101, 102 and 103 included in each of the multiple page buffers PB1 to PBm to couple the ground voltage VSS terminal to the first node ND1, thereby controlling the first column voltage A with the ground voltage VSS level to be loaded onto the sensing node SO through the first NMOS transistor N1. According to the embodiment, assuming "N" is 8 and "M" is 3, when a first setting code with the value "000" is applied to the corresponding input terminals QS_N, QM_N, and QT_N of the three latches 101, 102, and 103, and the values ​​of the corresponding output terminals QS, QM, and QT of the three latches 101, 102, and 103 are "111", the four NMOS transistors N4, N5, N6, and N7 included in the coupling control unit 104 can be turned on, and the four PMOS transistors P3, P4, P5, and P6 included in the coupling control unit 104 can be turned off. Therefore, the first node ND1 can be coupled to the ground voltage VSS terminal. Since the first NMOS transistor N1 coupled between the first node ND1 and the sensing node SO turns on in response to the power supply voltage VCORE applied to its gate, the first column voltage A with the ground voltage VSS level can be applied to the sensing node SO.

[0205] The coupling control unit 104 can respond to the second setting code among the N types of M-bit setting codes being input to the M latches 101, 102 and 103 included in each of the multiple page buffers PB1 to PBm to couple the power supply voltage VCORE terminal to the second node ND2, thereby controlling the second column voltage H with the power supply voltage VCORE level to be loaded onto the sensing node SO through the first PMOS transistor P1. According to the embodiment, assuming "N" is 8 and "M" is 3, when a second setting code with the value "111" is applied to the corresponding input terminals QS_N, QM_N, and QT_N of the three latches 101, 102, and 103, and the values ​​of the corresponding output terminals QS, QM, and QT of the three latches 101, 102, and 103 are "000", the four NMOS transistors N4, N5, N6, and N7 included in the coupling control unit 104 can be turned off, and the four PMOS transistors P3, P4, P5, and P6 included in the coupling control unit 104 can be turned on. Therefore, the second node ND2 can be coupled to the power supply voltage VCORE terminal. Since the first PMOS transistor P1 coupled between the second node ND2 and the sensing node SO turns on in response to the ground voltage VSS applied to its gate, the second column voltage H with the power supply voltage VCORE level can be applied to the sensing node SO.

[0206] The coupling control unit 104 can respond to the input of the (N / 2)-1 type third setting code in the N types of M-bit setting codes to the M latches 101, 102 and 103 included in each of the multiple page buffers PB1 to PBm, thereby coupling the power supply voltage VCORE terminal to the (N / 2)-1 type third node ND3_1, ND3_2 and ND3_3, thereby controlling the (N / 2)-1 type third column voltages B, C and D having sequential levels between the power supply voltage VCORE level and the ground voltage VSS level to be loaded onto the sensing node SO through the NMOS clamping method in the second NMOS transistor N2.

[0207] According to the embodiment, assuming "N" is 8 and "M" is 3, when a third setting code with the value "100" is applied to the corresponding input terminals QS_N, QM_N and QT_N of the three latches 101, 102 and 103 and the values ​​of the corresponding output terminals QS, QM and QT of the three latches 101, 102 and 103 are "011", one PMOS transistor P3 and three NMOS transistors N5, N6 and N7 included in the coupling control unit 104 can be turned on, and three PMOS transistors P4, P5 and P6 and one NMOS transistor N4 included in the coupling control unit 104 can be turned off. Therefore, the first third node ND3_1 can be coupled to the power supply voltage VCORE terminal. The first second NMOS transistor N2_1, coupled between the first third node ND3_1 and the sensing node SO, can determine the level of the first third column voltage B pre-charged from the power supply voltage VCORE level to the sensing node SO via an NMOS clamping method in response to the first first reference voltage REF1<1> applied to its gate. At this time, NMOS clamping may occur because the level of the first first reference voltage REF1<1> applied to the gate of the first second NMOS transistor N2_1 is not a higher threshold voltage level than the level of the power supply voltage VCORE coupled to its drain. The level of the first third column voltage B can be obtained by subtracting the threshold voltage level of the first second NMOS transistor N2_1 from the level of the first first reference voltage REF1<1>. For example, assuming the power supply voltage VCORE level is 1.8 V, the first reference voltage REF1<1> level is 1 V, and the threshold voltage level of the first second NMOS transistor N2_1 is 0.7 V, then the level of the first third column voltage B can be 0.3 V.

[0208] According to the embodiment, assuming "N" is 8 and "M" is 3, when a third setting code with the value "110" is applied to the corresponding input terminals QS_N, QM_N and QT_N of the three latches 101, 102 and 103 and the values ​​of the corresponding output terminals QS, QM and QT of the three latches 101, 102 and 103 are "001", the two PMOS transistors P3 and P4 and the two NMOS transistors N6 and N7 included in the coupling control unit 104 can be turned on, and the two PMOS transistors P5 and P6 and the two NMOS transistors N4 and N5 included in the coupling control unit 104 can be turned off. Therefore, the first third node ND3_1 and the second third node ND3_2 can be coupled to the power supply voltage VCORE terminal. The first second NMOS transistor N2_1 and the second second NMOS transistor N2_2, coupled between the first third node ND3_1 and the second third node ND3_2 and the sensing node SO, can determine the level of the second third column voltage C precharged from the power supply voltage VCORE level to the sensing node SO via an NMOS clamping method in response to the first and second first reference voltages REF1<1:2> applied to their gates. At this time, NMOS clamping may occur because the levels of the first and second first reference voltages REF1<1:2> applied to the gates of the first second NMOS transistor N2_1 and the second second NMOS transistor N2_2 are not higher than the threshold voltage level of the power supply voltage VCORE level coupled to their drains. The level of the second third column voltage C can be the higher of the levels obtained by subtracting the threshold voltage level of the first second NMOS transistor N2_1 from the level of the first first reference voltage REF1<1> and the level obtained by subtracting the threshold voltage level of the second second NMOS transistor N2_2 from the level of the second first reference voltage REF1<2>. For example, assuming the level of the power supply voltage VCORE is 1.8 V, the level of the first first reference voltage REF1<1> is 1 V, the level of the second first reference voltage REF1<2> is 1.1 V, and the threshold voltage level of each of the first second NMOS transistor N2_1 and the second second NMOS transistor N2_2 is 0.7 V, then the level of the second third column voltage C can be 0.4 V, as determined by the second second NMOS transistor N2_2.

[0209] According to the embodiment, assuming "N" is 8 and "M" is 3, when a third setting code with the value "101" is applied to the corresponding input terminals QS_N, QM_N and QT_N of the three latches 101, 102 and 103 and the values ​​of the corresponding output terminals QS, QM and QT of the three latches 101, 102 and 103 are "010", the three PMOS transistors P3, P5 and P6 and one NMOS transistor N5 included in the coupling control unit 104 can be turned on, and the one PMOS transistor P4 and the three NMOS transistors N4, N6 and N7 included in the coupling control unit 104 can be turned off. Therefore, the first third node ND3_1 and the third third node ND3_3 can be coupled to the power supply voltage VCORE terminal. The first second NMOS transistor N2_1 and the third second NMOS transistor N2_3, coupled between the first third node ND3_1 and the third third node ND3_3 and the sensing node SO, can determine the level of the third third column voltage D pre-charged from the power supply voltage VCORE level to the sensing node SO via an NMOS clamping method in response to the first and third first reference voltages REF1<1,3> applied to their gates. At this time, NMOS clamping may occur because the levels of the first and third first reference voltages REF1<1,3> applied to the gates of the first second NMOS transistor N2_1 and the third second NMOS transistor N2_3 are not higher than the threshold voltage level of the power supply voltage VCORE level coupled to their drains. The level of the third column voltage D can be the higher of the levels obtained by subtracting the threshold voltage level of the first second NMOS transistor N2_1 from the level of the first first reference voltage REF1<1> and by subtracting the threshold voltage level of the third second NMOS transistor N2_3 from the level of the third first reference voltage REF1<3>. For example, assuming the level of the power supply voltage VCORE is 1.8 V, the level of the first first reference voltage REF1<1> is 1 V, the level of the third first reference voltage REF1<3> is 1.2 V, and the threshold voltage level of each of the first second NMOS transistor N2_1 and the third second NMOS transistor N2_2 is 0.7 V, then the level of the third column voltage D can be 0.5 V, as determined by the third second NMOS transistor N2_2.

[0210] The coupling control unit 104 can respond to the (N / 2)-1 type of fourth setting code of the M latches 101, 102 and 103 included in each of the multiple page buffers PB1 to PBm, which does not overlap with the third setting code, and couple the ground voltage VSS terminal to the (N / 2)-1 type of fourth nodes ND4_1, ND4_2 and ND4_3, thereby controlling the (N / 2)-1 type of fourth column voltages E, F and G, which have a sequential level between the power supply voltage VCORE level and the ground voltage VSS level and have a level higher than the third column voltages B, C and D, to be loaded onto the sensing node SO through the PMOS clamping method in the second PMOS transistors P2_1, P2_2 and P2_3.

[0211] According to the embodiment, assuming "N" is 8 and "M" is 3, when the fourth setting code with the value "011" is applied to the corresponding input terminals QS_N, QM_N and QT_N of the three latches 101, 102 and 103 and the values ​​of the corresponding output terminals QS, QM and QT of the three latches 101, 102 and 103 are "100", the three PMOS transistors P4, P5 and P6 and one NMOS transistor N4 included in the coupling control unit 104 can be turned on, and one PMOS transistor P3 and three NMOS transistors N5, N6 and N7 in the coupling control unit 104 can be turned off. Therefore, the first fourth node ND4_1 can be coupled to the ground voltage VSS terminal. The first second PMOS transistor P2_1, coupled between the first fourth node ND4_1 and the sensing node SO, can determine the level of the first fourth column voltage E discharged in the sensing node SO via a PMOS clamping method in response to the first second reference voltage REF2<1> applied to its gate. At this time, PMOS clamping may occur because the level of the first second reference voltage REF2<1> applied to the gate of the first second PMOS transistor P2_1 is not lower than the threshold voltage level of the ground voltage VSS coupled to its drain. The level of the first fourth column voltage E can be obtained by adding the threshold voltage level of the first second PMOS transistor P2_1 to the level of the first second reference voltage REF2<1>. For example, assuming the ground voltage VSS level is 0 V, the first second reference voltage REF2<1> is 0.1 V, and the threshold voltage level of the first second PMOS transistor P2_1 is 0.7 V, then the level of the first fourth column voltage E can be 0.8 V.

[0212] According to the embodiment, assuming "N" is 8 and "M" is 3, when the fourth setting code with the value "001" is applied to the corresponding input terminals QS_N, QM_N and QT_N of the three latches 101, 102 and 103 and the values ​​of the corresponding output terminals QS, QM and QT of the three latches 101, 102 and 103 are "110", the two PMOS transistors P5 and P6 and the two NMOS transistors N4 and N5 included in the coupling control unit 104 can be turned on, and the two PMOS transistors P3 and P4 and the two NMOS transistors N6 and N7 included in the coupling control unit 104 can be turned off. Therefore, the first fourth node ND4_1 and the second fourth node ND4_2 can be coupled to the ground voltage VSS terminal. The first second PMOS transistor P2_1 and the second second PMOS transistor P2_2, coupled between the first fourth node ND4_1 and the second fourth node ND4_2 and the sensing node SO, can determine the level of the second fourth column voltage F discharged in the sensing node SO via a PMOS clamping method in response to the first and second second reference voltages REF2<1:2> applied to their gates. At this time, PMOS clamping may occur because the levels of the first and second second reference voltages REF2<1:2> applied to the gates of the first second PMOS transistor P2_1 and the second second PMOS transistor P2_2 are not lower than the threshold voltage level of the ground voltage VSS coupled to their drains. The level of the second fourth column voltage F can be the higher of the level obtained by adding the threshold voltage level of the first second PMOS transistor P2_1 to the level of the first second reference voltage REF2<1> and the level obtained by adding the threshold voltage level of the second second PMOS transistor P2_2 to the level of the second second reference voltage REF2<2>. For example, assuming the level of the ground voltage VSS is 0 V, the first second reference voltage REF2<1> is 0.1 V, the level of the second second reference voltage REF2<2> is 0.2 V, and the threshold voltage level of each of the first second PMOS transistor P2_1 and the second second PMOS transistor P2_2 is 0.7 V, then the level of the second fourth column voltage F can be 0.9 V, as determined in the second second PMOS transistor P2_2.

[0213] According to the embodiment, assuming "N" is 8 and "M" is 3, when a fourth setting code with the value "010" is applied to the corresponding input terminals QS_N, QM_N and QT_N of the three latches 101, 102 and 103 and the values ​​of the corresponding output terminals QS, QM and QT of the three latches 101, 102 and 103 are "101", one PMOS transistor P4 and three NMOS transistors N4, N6 and N7 included in the coupling control unit 104 can be turned on, and three PMOS transistors P3, P5 and P6 and one NMOS transistor N5 included in the coupling control unit 104 can be turned off. Therefore, the first fourth node ND4_1 and the third fourth node ND4_3 can be coupled to the ground voltage VSS terminal. The first second PMOS transistor P2_1 and the third second PMOS transistor P2_3, coupled between the first fourth node ND4_1 and the third fourth node ND4_3 and the sensing node SO, can determine the level of the third fourth column voltage G discharged in the sensing node SO via a PMOS clamping method in response to the first and third second reference voltages REF2<1,3> applied to their gates. At this time, PMOS clamping may occur because the levels of the first and third second reference voltages REF2<1,3> applied to the gates of the first second PMOS transistor P2_1 and the third second PMOS transistor P2_3 are not lower than the threshold voltage level of the ground voltage VSS coupled to their drains. The level of the third fourth column voltage G can be the higher of the level obtained by adding the threshold voltage level of the first second PMOS transistor P2_1 to the level of the first second reference voltage REF2<1> and the level obtained by adding the threshold voltage level of the third second PMOS transistor P2_3 to the level of the third second reference voltage REF2<3>. For example, assuming the level of the ground voltage VSS is 0 V, the first second reference voltage REF2<1> is 0.1 V, the level of the third second reference voltage REF2<3> is 0.3 V, and the threshold voltage level of each of the first second PMOS transistor P2_1 and the third second PMOS transistor P2_3 is 0.7 V, then the level of the third fourth column voltage G can be 1 V determined in the third second PMOS transistor P2_3.

[0214] FIG12 is a diagram illustrating the operation of the page buffer circuit shown in FIG11 according to the second embodiment.

[0215] Referring to FIG12, the program operations included in the program loop may include bit line setting operations t1 to t3 and program voltage application operations t2 to t4.

[0216] In the bit line setting operation, M bit setting codes of N types can be input into M latches included in each of the multiple page buffers PB1 to PBm, and N types of column voltages A, B, C, D, E, F, G, and H can be generated. The generated N types of column voltages A, B, C, D, E, F, G, and H can be selectively applied to each bit line coupled to the memory cell of the selected word line selected as the program target among the multiple word lines.

[0217] According to an embodiment, a second column voltage H, which is the highest voltage among N types of column voltages A, B, C, D, E, F, G, and H and has a power supply voltage VCORE level, can be applied as a disable voltage to a bit line coupled to a program disable cell among the plurality of memory cells included in the selected word line. A first column voltage A, which is the lowest voltage among N types of column voltages A, B, C, D, E, F, G, and H, can be applied as a first enable voltage to a bit line coupled to a first cell among the plurality of memory cells included in the selected word line that has a lowest threshold voltage. A first third column voltage B, which is the second lowest voltage among N types of column voltages A, B, C, D, E, F, G, and H, can be applied as a second enable voltage to a bit line coupled to a second cell among the plurality of memory cells included in the selected word line that has a threshold voltage higher than that of the first cell and lower than that of the third cell. The second third column voltage C, which is the third lowest voltage among the N types of column voltages A, B, C, D, E, F, G, and H, can be applied as a third allowable voltage to a bit line coupled to a third cell among the multiple memory cells included in the selected word line, having a threshold voltage higher than the second cell's threshold voltage and lower than the fourth cell's threshold voltage. The third third column voltage D, which is the fourth lowest voltage among the N types of column voltages A, B, C, D, E, F, G, and H, can be applied as a fourth allowable voltage to a bit line coupled to a fourth cell among the multiple memory cells included in the selected word line, having a threshold voltage higher than the third cell's threshold voltage and lower than the fifth cell's threshold voltage. The first fourth column voltage E, which is the fifth lowest voltage among the N types of column voltages A, B, C, D, E, F, G, and H, can be applied as a fifth allowable voltage to a bit line coupled to a fifth cell among the multiple memory cells included in the selected word line, having a threshold voltage higher than the fourth cell's threshold voltage and lower than the sixth cell's threshold voltage. The second fourth column voltage F, which is the sixth lowest voltage among the N types of column voltages A, B, C, D, E, F, G, and H, can be applied as the sixth enable voltage to a bit line coupled to the sixth unit of the memory cells included in the selected word line, having a threshold voltage higher than the threshold voltage of the fifth unit and lower than the threshold voltage of the seventh unit. The third fourth column voltage G, which is the seventh lowest voltage among the N types of column voltages A, B, C, D, E, F, G, and H, can be applied as the seventh enable voltage to a bit line coupled to the seventh unit of the memory cells included in the selected word line, having a threshold voltage higher than the threshold voltage of the sixth unit and lower than the threshold voltage of the program inhibit unit.

[0218] As described above, any one of N types of column voltages A, B, C, D, E, F, G, and H can be applied to each of the multiple bit lines through a bit line setting operation, and then a program voltage can be applied to the selected word line through a program voltage application operation. Therefore, in the program voltage application operation, the strength of the program operation on the seventh unit can be lower than the strength of the program operation on the sixth unit. Simultaneously, the strength of the program operation on the sixth unit can be lower than the strength of the program operation on the fifth unit. Simultaneously, the strength of the program operation on the fifth unit can be lower than the strength of the program operation on the fourth unit. Simultaneously, the strength of the program operation on the fourth unit can be lower than the strength of the program operation on the third unit. Simultaneously, the strength of the program operation on the third unit can be lower than the strength of the program operation on the second unit. Simultaneously, the strength of the program operation on the second unit can be lower than the strength of the program operation on the first unit. Of course, the program operation on the program disable unit can be restricted.

[0219] FIG13 is a diagram illustrating the configuration of the page buffer circuit according to the third embodiment.

[0220] Referring to Figure 13, the page buffer PBx is a circuit diagram illustrating any one of the multiple page buffers PB1 to PBm described with reference to Figure 2. Each PBx of the multiple page buffers PB1 to PBm may include M latches. In this document, "M" can be a natural number equal to or greater than 2. In the figure, assuming "M" is 2, it can be seen that each PBx of the multiple page buffers PB1 to PBm includes two latches 121 and 122.

[0221] Comparing the configuration of the page buffer circuit according to the first embodiment disclosed in FIG9 and the configuration of the page buffer circuit according to the third embodiment disclosed in FIG13, it can be seen that FIG9 illustrates the configuration of a page buffer circuit operating with a power supply voltage VCORE and a ground voltage VSS applied thereto, while FIG13 illustrates the configuration of a page buffer circuit operating with two power supply voltages VCORE and VCORE2 applied thereto and a ground voltage VSS.

[0222] Therefore, the differences between the configuration of the page buffer circuit according to the first embodiment disclosed in FIG9 and the configuration of the page buffer circuit according to the third embodiment disclosed in FIG13 will be described below.

[0223] Referring to Figure 13, each PBx of the plurality of page buffers PB1 to PBm may include M latches 121 and 122, an NMOS transistor N1, and a coupling control unit 123. In this document, "M" may be a natural number equal to or greater than 2.

[0224] The NMOS transistor N1 can couple bit line BL to sensing node SO in response to a voltage applied signal PBSENSE having a predetermined level and a selection level of type M-K+1.

[0225] The coupling control unit 123 can respond to each of the N types of M-bit setting codes being input to the M latches 121 and 122 to couple the ground voltage VSS terminal and any one of the K types of power supply voltages VCORE and VCORE2 terminals having a sequence level lower than a predetermined level to the sensing node SO. In this document, "K" can be a natural number equal to or greater than "M".

[0226] According to an embodiment, assuming that “K” and “M” are each 2 and “N” is 4, the coupling control unit 123 can couple bit line BL to sensing node SO in response to a voltage application signal PBSENSE having either a selected level or a predetermined level.

[0227] According to the embodiment, assuming that “K” and “M” are each 2 and “N” is 4, the coupling control unit 123 can respond to each of the four types of 2-bit setting codes being input to the M latches 121 and 122 to couple either the ground voltage VSS terminal or either of the two types of power supply voltages VCORE and VCORE2 terminals having a sequence level lower than a predetermined level to the sensing node SO.

[0228] Referring to Figures 2, 4 and 13, the control circuit 152 can generate a voltage application signal PBSENSE having a predetermined level and any one of the M-K+1 types of selection levels during the bit line setting operation, and input the voltage application signal PBSENSE to the NMOS transistor N1 included in each of the multiple page buffers PB1 to PBm.

[0229] Among the multiple page buffers PB1 to PBm, the page buffer having a predetermined voltage application signal PBSENSE, generated by the control circuit 152 and higher than the K types of power supply voltage levels, applied to the internal NMOS transistor N1 can control the bit line BL and the sensing node SO to remain electrically coupled during the bit line setup operation. In this case, the voltage level applied to the sensing node SO can be transmitted to the bit line BL without loss during the bit line setup operation.

[0230] Among the multiple page buffers PB1 to PBm, the page buffer with a voltage application signal PBSENSE of M-K+1 types of selection levels having at least one of the power supply voltage levels of less than K types generated by the control circuit 152 can electrically couple the bit line BL to the sensing node SO during the bit line setting operation period, but the voltage level applied to the sensing node SO can be NMOS clamped by the NMOS transistor N1 and transmitted to the bit line BL.

[0231] In addition, the control circuit 152 can control the coupled control unit 123 to input multiple M bit setting codes into M latches 121 and 122 included in each of the multiple page buffers PB1 to PBm during the bit line setting operation, and to couple the sensing node SO to the ground voltage VSS terminal and any one of the K types of power supply voltages VCORE and VCORE2 terminals.

[0232] Referring to Figures 2, 4 and 13, the control logic 153 can control the control circuit 152 to generate a voltage application signal PBSENSE having a predetermined level and any one of the M-K+1 types of selection levels in the bit line setting operation, and input the voltage application signal PBSENSE to the NMOS transistor N1 included in each of the multiple page buffers PB1 to PBm.

[0233] Under the control of control logic 153, among the multiple page buffers PB1 to PBm, a voltage application signal PBSENSE having a predetermined level higher than the K types of power supply voltage levels generated by control circuit 152 is applied to the page buffer of the internal NMOS transistor N1. This allows the bit line BL and the sensing node SO to be kept electrically coupled during the bit line setup operation period. In this case, the voltage level applied to the sensing node SO can be transmitted to the bit line BL without loss during the bit line setup operation.

[0234] Under the control of control logic 153, among the multiple page buffers PB1 to PBm, a voltage application signal PBSENSE of M-K+1 types of selection levels with at least one of the power supply voltage levels of less than K types generated by control circuit 152 is applied to the page buffer of internal NMOS transistor N1. During the bit line setting operation period, the bit line BL can be electrically coupled to the sensing node SO. However, the voltage level applied to the sensing node SO can be NMOS clamped by NMOS transistor N1 and transmitted to bit line BL.

[0235] In addition, the control logic 153 can control the coupled control unit 123 to input multiple M bit setting codes into M latches 121 and 122 included in each of the multiple page buffers PB1 to PBm during the bit line setting operation, and to couple the sensing node SO to the ground voltage VSS terminal and any one of the K types of power supply voltages VCORE and VCORE2 terminals.

[0236] More specifically, referring to FIG13, the coupling control unit 123 can respond to a first setting code of N types of M-bit setting codes being input to M latches 121 and 122 included in each of the multiple page buffers PB1 to PBm, thereby controlling the ground voltage VSS level to be loaded onto the sensing node SO. According to an embodiment, assuming "N" is 4 and "M" is 2, when a first setting code having the value "00" is applied to the corresponding input terminals QS_N and QM_N of the two latches 121 and 122 and the values ​​of the corresponding output terminals QS and QM of the two latches 121 and 122 are "11", the three NMOS transistors N2, N3 and N5 included in the coupling control unit 123 can be turned on, and one NMOS transistor N7 and one PMOS transistor P1 included in the coupling control unit 123 can be turned off, so that the ground voltage VSS level can be loaded onto the sensing node SO. For reference, the two NMOS transistors N4 and N6 included in the coupling control unit 123 can be controlled to turn on / off in response to operation signals S1 and S2. Since it can be assumed that operation signals S1 and S2 are signals initiated during bit line setting operations, it can be assumed that the two NMOS transistors N4 and N6 are always on during operation of the coupling control unit 123.

[0237] The coupling control unit 123 can respond to the input of a second setting code among N types of M-bit setting codes to M latches 121 and 122 included in each of the multiple page buffers PB1 to PBm, thereby controlling the power supply voltage VCORE level to be loaded onto the sensing node SO. According to an embodiment, assuming "N" is 4 and "M" is 2, when a second setting code with the value "11" is applied to the corresponding input terminals QS_N and QM_N of the two latches 121 and 122 and the values ​​of the corresponding output terminals QS and QM of the two latches 121 and 122 are "00", the three NMOS transistors N2, N3 and N5 included in the coupling control unit 123 can be turned off, and one NMOS transistor N7 and one PMOS transistor P1 included in the coupling control unit 123 can be turned on, so that each of the first power supply voltage VCORE level and the second power supply voltage VCORE2 level can be loaded onto the sensing node SO. At this point, since it can be assumed that the first power supply voltage VCORE level is higher than the second power supply voltage VCORE2 level, the first power supply voltage VCORE level can be applied to the sensing node SO. For example, the first power supply voltage VCORE level can be 1.8 V, and the second power supply voltage VCORE2 level can be 0.3 V. Therefore, the first power supply voltage VCORE level with 1.8 V can be applied to the sensing node SO.

[0238] The coupling control unit 123 can respond to the input of a third setting code among N types of M-bit setting codes to M latches 121 and 122 included in each of the multiple page buffers PB1 to PBm, thereby controlling the first power supply voltage VCORE level to be loaded onto the sensing node SO. According to an embodiment, assuming "N" is 4 and "M" is 2, when a third setting code with a value of "10" is applied to the corresponding input terminals QS_N and QM_N of the two latches 121 and 122 and the values ​​of the corresponding output terminals QS and QM of the two latches 121 and 122 are "01", the two NMOS transistors N3 and N5 and one PMOS transistor P1 included in the coupling control unit 123 can be turned on, and the two NMOS transistors N2 and N7 included in the coupling control unit 123 can be turned off, so that the first power supply voltage VCORE level can be loaded onto the sensing node SO.

[0239] The coupling control unit 123 can respond to the input of a fourth setting code among N types of M-bit setting codes to M latches 121 and 122 included in each of the multiple page buffers PB1 to PBm, thereby controlling the second power supply voltage VCORE2 level to be loaded onto the sensing node SO. According to an embodiment, assuming "N" is 4 and "M" is 2, when a fourth setting code with the value "01" is applied to the corresponding input terminals QS_N and QM_N of the two latches 121 and 122 and the values ​​of the corresponding output terminals QS and QM of the two latches 121 and 122 are "10", the three NMOS transistors N2, N3 and N5 included in the coupling control unit 123 and one PMOS transistor P1 can be turned off, and one NMOS transistor N7 included in the coupling control unit 123 can be turned on, so that the second power supply voltage VCORE2 level can be loaded onto the sensing node SO.

[0240] More specifically, referring to FIG13, when a voltage application signal PBSENSE having a predetermined level higher than the first power supply voltage VCORE level is applied to the NMOS transistor N1 during the bit line setting operation period, the potential level of the sensing node SO determined by the coupling control unit 123 can be transmitted to the bit line BL as is.

[0241] However, when a voltage application signal PBSENSE having a lower selection level than the voltage level applied to the NMOS transistor N1 during the bit line setup operation period, the potential level of the bit line BL can be determined by an NMOS clamping method. According to an embodiment, when a first power supply voltage VCORE level is applied to the sensing node SO and a voltage application signal PBSENSE lower than the first power supply voltage VCORE level is applied to the NMOS transistor N1 during the bit line setup operation period, the level of the bit line BL can be obtained by subtracting the threshold voltage level of the NMOS transistor N1 from the selection level. For example, when the first power supply voltage VCORE level is 1.8 V, the selection level is 1.2 V, and the threshold voltage level of the NMOS transistor N1 is 0.7 V, the level of the bit line BL can be 0.5 V.

[0242] FIG14 is a diagram illustrating the operation of the page buffer circuit shown in FIG13 according to the third embodiment.

[0243] Referring to FIG14, the program operations included in the program loop may include bit line setting operations t1 to t4 and program voltage application operations t3 to t5.

[0244] In the bit line setup operation, M bit setup codes of N types can be input into M latches included in each of the multiple page buffers PB1 to PBm, and N types of column voltages VSS, VCORE2, PBSENSE-Vth, and VCORE can be generated. The generated N types of column voltages VSS, VCORE2, PBSENSE-Vth, and VCORE can be selectively applied to each bit line coupled to the memory cell of the selected word line selected as the program target among the multiple word lines.

[0245] Among the multiple page buffers PB1 to PBm, the page buffer that needs to transmit the first power supply voltage VCORE level applied to the sensing node SO to the bit line BL can continuously receive a voltage application signal PBSENSE with a predetermined level VPB_H higher than the first power supply voltage VCORE level during bit line setup operations t1 to t4. On the other hand, among the multiple page buffers PB1 to PBm, the page buffer that needs to transmit the second power supply voltage VCORE2 level, the ground voltage VSS level, or the clamping voltage PBSENSE-Vth level applied to the sensing node SO to the bit line BL can receive a voltage application signal PBSENSE with a selected level VPB_L lower than the first power supply voltage VCORE level during some time periods t3 to t4 of the bit line setup operations t1 to t4.

[0246] According to an embodiment, the first power supply voltage VCORE, which is the highest voltage among the N types of column voltages VSS, VCORE2, PBSENSE-Vth, and VCORE, can be applied as a disable voltage to a bit line coupled to a program disable cell among the plurality of memory cells included in the selected word line. The ground voltage VSS, which is the lowest voltage among the N types of column voltages VSS, VCORE2, PBSENSE-Vth, and VCORE, can be applied as a first enable voltage to a bit line coupled to a first cell among the plurality of memory cells included in the selected word line that has a threshold voltage lower than the additional verification voltage PVT. The voltage PBSENSE-Vth, which is the third highest voltage among the N types of column voltages VSS, VCORE2, PBSENSE-Vth, and VCORE, can be applied as a second enable voltage to a bit line coupled to a second cell among the plurality of memory cells included in the selected word line that has a threshold voltage higher than the additional verification voltage PVT and lower than the pre-verification voltage PVP. The second power supply voltage VCORE2, which is the second highest voltage among the N types of column voltages VSS, VCORE2, PBSENSE-Vth, and VCORE, can be applied as a third allowable voltage to a bit line coupled to a third cell in the multiple memory cells included in the selected word line, which has a threshold voltage higher than the pre-verification voltage PVP and lower than the main verification voltage PVM.

[0247] As described above, any one of the N types of column voltages VSS, VCORE2, PBSENSE-Vth, and VCORE can be applied to each of the multiple bit lines through a bit line setting operation, and then a program voltage can be applied to the selected word line through a program voltage application operation. Therefore, in the program voltage application operation, the strength of the program operation on the third unit can be lower than the strength of the program operation on the second unit. At the same time, the strength of the program operation on the second unit can be lower than the strength of the program operation on the first unit. Of course, the program operation on the program disable unit can be restricted.

[0248] FIG15 is a diagram illustrating the configuration of the page buffer circuit according to the fourth embodiment.

[0249] Referring to Figure 15, the page buffer PBx is a circuit diagram illustrating any one of the multiple page buffers PB1 to PBm described with reference to Figure 2. Each PBx of the multiple page buffers PB1 to PBm may include M latches. In this document, "M" can be a natural number equal to or greater than 2. In the figure, assuming "M" is 2, it can be seen that each PBx of the multiple page buffers PB1 to PBm includes two latches 141 and 142.

[0250] Comparing the configuration of the page buffer circuit according to the third embodiment disclosed in FIG13 and the configuration of the page buffer circuit according to the fourth embodiment disclosed in FIG15, it can be seen that FIG13 illustrates the configuration of the page buffer circuit operating with two power supply voltages VCORE and VCORE2 applied thereto and a ground voltage VSS level, while FIG15 illustrates the configuration of the page buffer circuit operating with three power supply voltages VCORE, VCORE1 and VCORE2 applied thereto.

[0251] Therefore, the differences between the configuration of the page buffer circuit according to the third embodiment disclosed in FIG13 and the configuration of the page buffer circuit according to the fourth embodiment disclosed in FIG15 will be described below.

[0252] Referring to Figure 15, each of the multiple page buffers PB1 to PBm may include M latches 141 and 142, an NMOS transistor N1, and a coupling control unit 143. In this document, "M" may be a natural number equal to or greater than 2.

[0253] The NMOS transistor N1 can couple bit line BL to sensing node SO in response to a voltage applied signal PBSENSE having a predetermined level and a selection level of type M-K+1.

[0254] The coupling control unit 143 can respond to each of the N types of M-bit setting codes being input to the M latches 141 and 142 to couple the ground voltage VSS terminal and any one of the K types of power supply voltages VCORE, VCORE1, and VCORE2 terminals having a sequence level lower than a predetermined level to the sensing node SO. In this document, "K" can be a natural number equal to or greater than "M".

[0255] According to the embodiment, assuming that “K” is 3 and “M” is 2, since there may be no voltage application signal PBSENSE with a selected level, the coupling control unit 143 can respond to the voltage application signal PBSENSE with a predetermined level by coupling bit line BL to sensing node SO.

[0256] According to the embodiment, assuming "K" is 3 and "M" is 2, the coupling control unit 143 can respond to each of the four types of 2-bit setting codes being input to the two latches 141 and 142 to couple the ground voltage VSS terminal and any one of the three types of power supply voltages VCORE, VCORE1 and VCORE2 terminals having a sequence level lower than a predetermined level to the sensing node SO.

[0257] More specifically, referring to FIG15, the coupling control unit 143 can respond to a first setting code of N types of M-bit setting codes being input to M latches 141 and 142 included in each of the multiple page buffers PB1 to PBm, thereby controlling the ground voltage VSS level to be loaded onto the sensing node SO. According to an embodiment, assuming "N" is 4 and "M" is 2, when a first setting code having the value "00" is applied to the corresponding input terminals QS_N and QM_N of the two latches 141 and 142 and the values ​​of the corresponding output terminals QS and QM of the two latches 141 and 142 are "11", the three NMOS transistors N2, N3 and N7 included in the coupling control unit 143 can be turned on, and the two NMOS transistors N5 and N9 and the two PMOS transistors P1 and P2 included in the coupling control unit 143 can be turned off, so that the ground voltage VSS level can be loaded onto the sensing node SO. For reference, the three NMOS transistors N4, N6, and N8 included in the coupling control unit 143 can be controlled to turn on / off in response to operation signals S1, S2, and S3. Since it can be assumed that operation signals S1, S2, and S3 are signals initiated during bit line setting operations, it can be assumed that the three NMOS transistors N4, N6, and N8 are always on during operation of the coupling control unit 143.

[0258] The coupling control unit 143 can respond to the second setting code among N types of M-bit setting codes being input to M latches 141 and 142 included in each of the multiple page buffers PB1 to PBm, thereby controlling the first power supply voltage VCORE level to be loaded onto the sensing node SO. According to the embodiment, assuming "N" is 4 and "M" is 2, when a second setting code with the value "11" is applied to the corresponding input terminals QS_N and QM_N of the two latches 141 and 142, and the values ​​of the corresponding output terminals QS and QM of the two latches 141 and 142 are "00", the three NMOS transistors N2, N3, and N7 included in the coupling control unit 143 can be turned off, and the two NMOS transistors N5 and N9 and the two PMOS transistors P1 and P2 included in the coupling control unit 143 can be turned on. Therefore, each of the first power supply voltage VCORE level, the second power supply voltage VCORE2 level, and the third power supply voltage VCORE1 level can be applied to the sensing node SO. At this time, since it can be assumed that the first power supply voltage VCORE level is higher than the second power supply voltage VCORE2 level and the third power supply voltage VCORE1 level, the first power supply voltage VCORE level can be applied to the sensing node SO. For example, the first power supply voltage VCORE level can be 1.8 V, the second power supply voltage VCORE2 level can be 0.3 V, and the third power supply voltage VCORE1 level can be 0.5 V. Therefore, the first power supply voltage VCORE level with 1.8 V can be applied to the sensing node SO.

[0259] The coupling control unit 143 can respond to the input of a third setting code among N types of M-bit setting codes to M latches 141 and 142 included in each of the multiple page buffers PB1 to PBm, thereby controlling the third power supply voltage VCORE1 level to be loaded onto the sensing node SO. According to an embodiment, assuming "N" is 4 and "M" is 2, when a third setting code with a value of "10" is applied to the corresponding input terminals QS_N and QM_N of the two latches 141 and 142 and the values ​​of the corresponding output terminals QS and QM of the two latches 141 and 142 are "01", the three NMOS transistors N3, N5 and N7 and one PMOS transistor P1 included in the coupling control unit 143 can be turned on, and the two NMOS transistors N2 and N9 and one PMOS transistor P2 included in the coupling control unit 143 can be turned off, so that the third power supply voltage VCORE1 level can be loaded onto the sensing node SO.

[0260] The coupling control unit 143 can respond to the input of a fourth setting code among N types of M-bit setting codes to M latches 141 and 142 included in each of the multiple page buffers PB1 to PBm, thereby controlling the second power supply voltage VCORE2 level to be loaded onto the sensing node SO. According to an embodiment, assuming "N" is 4 and "M" is 2, when a fourth setting code with a value of "01" is applied to the corresponding input terminals QS_N and QM_N of the two latches 141 and 142 and the values ​​of the corresponding output terminals QS and QM of the two latches 141 and 142 are "10", the three NMOS transistors N3, N5 and N7 and one PMOS transistor P1 included in the coupling control unit 143 can be turned off, and the two NMOS transistors N2 and N9 and one PMOS transistor P2 included in the coupling control unit 143 can be turned on, so that the second power supply voltage VCORE2 level can be loaded onto the sensing node SO.

[0261] FIG16 is a diagram illustrating the operation of the page buffer circuit shown in FIG15 according to the fourth embodiment.

[0262] Referring to FIG16, the program operations included in the program loop may include bit line setting operations t1 to t4 and program voltage application operations t3 to t5.

[0263] In the bit line setting operation, M bit setting codes of N types can be input into M latches included in each of the multiple page buffers PB1 to PBm, and N types of column voltages VSS, VCORE2, VCORE1, and VCORE can be generated. The generated N types of column voltages VSS, VCORE2, VCORE1, and VCORE can be selectively applied to each bit line coupled to the memory cell of the selected word line selected as the program target among the multiple word lines.

[0264] According to an embodiment, the first power supply voltage VCORE, which is the highest voltage among the N types of column voltages VSS, VCORE2, VCORE1, and VCORE, can be applied as a disable voltage to a bit line coupled to a program disable cell among the plurality of memory cells included in the selected word line. The ground voltage VSS, which is the lowest voltage among the N types of column voltages VSS, VCORE2, VCORE1, and VCORE, can be applied as a first enable voltage to a bit line coupled to a first cell among the plurality of memory cells included in the selected word line that has a threshold voltage lower than the additional verification voltage PVT. The third power supply voltage VCORE1, which is the third highest voltage among the N types of column voltages VSS, VCORE2, VCORE1, and VCORE, can be applied as a second enable voltage to a bit line coupled to a second cell among the plurality of memory cells included in the selected word line that has a threshold voltage higher than the additional verification voltage PVT and lower than the pre-verification voltage PVP. The second power supply voltage VCORE2, which is the second highest voltage among the N types of column voltages VSS, VCORE2, VCORE1, and VCORE, can be applied as the third allowable voltage to the bit line coupled to the third cell of the multiple memory cells included in the selected word line, which has a threshold voltage higher than the pre-verification voltage PVP and lower than the main verification voltage PVM.

[0265] As described above, any one of the N types of column voltages VSS, VCORE2, VCORE1, and VCORE can be applied to each of the multiple bit lines through a bit line setting operation, and then a program voltage can be applied to the selected word line through a program voltage application operation. Therefore, in the program voltage application operation, the strength of the program operation on the third unit can be lower than the strength of the program operation on the second unit. At the same time, the strength of the program operation on the second unit can be lower than the strength of the program operation on the first unit. Of course, the program operation on the program disable unit can be restricted.

[0266] According to an embodiment of the present invention, a set threshold voltage level and at least three verification voltages that decrease sequentially from the set threshold voltage level can be used in the verification operation of a plurality of memory cells whose program states are divided based on a set threshold voltage level, so that the program states of the plurality of memory cells can be divided into at least four types of program states.

[0267] Thus, in various embodiments, a programming operation can be performed in which any one of at least four types of column voltages is selected and applied to each of the plurality of bit lines according to at least four types of programming states divided in the verification operation. Therefore, in various embodiments, an improvement in the performance of the programming operation can be expected.

[0268] Although the invention has been illustrated and described with respect to specific embodiments and figures, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that the invention can be implemented in various ways through substitutions, alterations, and modifications, as those skilled in the art will recognize from the teachings of the invention, without departing from the spirit and / or scope of the invention.

[0269] For example, the arrangement and type of logic gates and transistors described in the foregoing embodiments can be implemented differently depending on the polarity of the input signal. [Simplified Explanation of the Diagram]

[0007] FIG1 is a diagram illustrating a memory system according to an embodiment. FIG2 is a detailed diagram illustrating the memory device shown in FIG1. ​​FIG3 is a detailed diagram illustrating the memory block shown in FIG2. FIG4 is a detailed diagram illustrating the memory device shown in FIG2 according to an embodiment. FIG5 is a diagram illustrating the triple verification PGM (TPGM) operation according to an embodiment. FIG6 is a diagram illustrating the state mode in the TPGM operation according to an embodiment. FIG7 is a diagram illustrating the incremental step pulse program operation including TPGM operation according to an embodiment. FIG8 is a diagram illustrating the TPGM operation according to another embodiment. FIG9 is a diagram illustrating the configuration of a page buffer circuit according to a first embodiment. FIG10 is a diagram illustrating the operation of the page buffer circuit shown in FIG9 according to a first embodiment. FIG11 is a diagram illustrating the configuration of a page buffer circuit according to a second embodiment. FIG12 is a diagram illustrating the operation of the page buffer circuit shown in FIG11 according to a second embodiment. FIG13 is a diagram illustrating the configuration of a page buffer circuit according to a third embodiment. FIG14 is a diagram illustrating the operation of the page buffer circuit shown in FIG13 according to a third embodiment. Figure 15 is a diagram illustrating the configuration of the page buffer circuit according to the fourth embodiment. Figure 16 is a diagram illustrating the operation of the page buffer circuit shown in Figure 15 according to the fourth embodiment.

Claims

1. A memory device, the memory device comprising: Multiple memory cells, the multiple memory cells being coupled between multiple word lines and multiple bit lines; Multiple page buffers, each page buffer being coupled to a plurality of memory cells via multiple bit lines, and each including M latches; a control circuit adapted to execute a program loop including program operations and verification operations, the program operations including program voltage application operations on selected word lines among the multiple word lines and bit line setting operations on the multiple bit lines, and the verification operations applying (N-1) first verification voltages to the selected word lines in a predetermined order to check N types of first program states for each of the plurality of memory cells included in the selected word lines; The control logic is adapted to control the control circuit to repeatedly execute the program loop until the program for the selected word line is completed, and to control the control circuit to generate any one of N types of column voltages based on the values ​​of the M types of M bit setting codes input to each of the plurality of page buffers, and to apply the generated column voltages to each of the plurality of bit lines in the bit line setting operation included in the second program loop, and to determine the values ​​of the N types of M bit setting codes input to each of the plurality of page buffers in the bit line setting operation of the second program loop based on the result of executing the verification operation included in the first program loop, where "N" is a natural number equal to or greater than 4 and "M" is a natural number equal to or greater than 2.

2. The memory device as claimed in claim 1, wherein, In the verification operation, the control circuit applies (N-1) second verification voltages to the selected character line in a predetermined order to check N types of second program states for each of the plurality of memory cells included in the selected character line, and the maximum level of the second verification voltage is higher than the maximum level of the first verification voltage.

3. The memory device as claimed in claim 2, wherein, Each of the plurality of page buffers includes: a first n-channel metal-oxide-semiconductor (NMOS) transistor adapted to couple a sensing node to a first node in response to a power supply voltage applied to the gate of the first NMOS transistor; a first p-channel metal-oxide-semiconductor (PMOS) transistor adapted to couple the sensing node to a second node in response to a ground voltage applied to the gate of the first PMOS transistor; (N / 2)-1 second NMOS transistors adapted to couple the sensing node to (N / 2)-1 third nodes in response to (N / 2)-1 types of first reference voltages; and (N / 2)-1 second PMOS transistors adapted to couple the sensing node to (N / 2)-1 fourth nodes in response to (N / 2)-1 types of second reference voltages. A third NMOS transistor, the third NMOS transistor being adapted to couple the sensing node to a bit line in response to a voltage applied signal; and a coupling control unit, the coupling control unit being adapted to couple any one of the first to the fourth nodes to a power supply voltage terminal or a ground voltage terminal according to the type of the M bit setting code input to the M latches.

4. The memory device as claimed in claim 3, wherein, During the bit line setup operation, the control logic controls the control circuit to generate the voltage application signal having a predetermined level higher than the power supply voltage level and inputs the voltage application signal to the third NMOS transistor included in each of the plurality of page buffers, and controls the control circuit to input each of the plurality of M bit setup codes to the M latches included in each of the plurality of page buffers, and couples at least one of the first to the fourth nodes to the power supply voltage terminal or the ground voltage terminal through the coupling control unit.

5. The memory device as claimed in claim 4, wherein, The coupling control unit, in response to a first setting code among the N types of M-bit setting codes being input to the M latches included in each of the plurality of page buffers, couples the ground voltage terminal to the first node and controls a first column voltage having the ground voltage level to be applied to the sensing node through the first NMOS transistor. The coupling control unit, in response to a second setting code among the N types of M-bit setting codes being input to the M latches included in each of the plurality of page buffers, couples the power supply voltage terminal to the second node and controls a second column voltage having the power supply voltage level to be applied to the sensing node through the first PMOS transistor. The coupling control unit responds to the input of a third setting code of type (N / 2)-1 among the N types of M-bit setting codes to the M latches included in each of the plurality of page buffers, thereby coupling the power supply voltage terminal to the (N / 2)-1 third nodes respectively, and controls the loading of a third column voltage of type (N / 2)-1 having a sequential level between the power supply voltage level and the ground voltage level onto the sensing node through the NMOS clamping method in the second NMOS transistor, and the coupling control unit responds to the input of the third column voltage of type (N / 2)-1. A fourth setting code of type (N / 2)-1 that does not overlap with the third setting code among the N types of M-bit setting codes is input to the M latches included in each of the plurality of page buffers to couple the ground voltage terminal to the (N / 2)-1 fourth nodes respectively, and controls the fourth column voltage of type (N / 2)-1 that has a sequential level between the power supply voltage level and the ground voltage level and is higher than the third column voltage to be loaded onto the sensing node through the PMOS clamping method in the second PMOS transistor.

6. A method of operating a memory device, the method comprising the following steps: A program loop is executed, comprising programming operations and verification operations. The programming operations include applying programming voltages to selected word lines among a plurality of word lines and setting bit lines on a plurality of bit lines. The verification operations apply (N-1) first verification voltages to the selected word lines in a predetermined order to check N types of first programming states for each of a plurality of memory cells included in the selected word lines. The program loop is repeatedly executed until programming for the selected word lines is completed. Based on the result of the verification operations included in the first program loop, the values ​​of M bit setting codes of N types are determined for each of M latches included in a plurality of page buffers in the bit line setting operations of a second program loop. Any one of N types of column voltages is generated based on the values ​​of the M bit setting codes of N types input to the M latches, and the generated column voltage is applied to each of the plurality of bit lines in the bit line setting operations included in the second program loop. Wherein, "N" is a natural number equal to or greater than 4, and "M" is a natural number equal to or greater than 2.

7. The operating method as described in claim 6, wherein, The steps of executing the program loop include: in the verification operation, applying (N-1) second verification voltages to the selected word line in the predetermined order to check N types of second program states for each of the plurality of memory cells included in the selected word line, and the maximum level of the second verification voltage is higher than the maximum level of the first verification voltage.

8. A method for programming a memory device, wherein the memory device executes multiple program loops until programming for a selected character line among multiple character lines is completed, wherein... Each of the program loops includes: generating any one of N types of column voltages based on the value of an M-bit setting code of N types input to the page buffer in a bit line setting operation, and applying the generated column voltage to each of the plurality of bit lines; applying a program voltage to the selected word line in a program voltage application operation; applying (N-1) first verification voltages to the selected word line in a predetermined order in a verification operation to check a first program state of N types for each of the plurality of memory cells included in the selected word line; and determining the value of the M-bit setting code of the N types to be input to the page buffer in the bit line setting operation of a subsequent program loop based on the result of applying the (N-1) first verification voltages to the selected word line in the predetermined order, wherein "N" is a natural number equal to or greater than 4, and "M" is a natural number equal to or greater than 2.

9. The program operation method as described in claim 8, wherein, Applying the (N-1) first verification voltages to the selected character line according to the predetermined sequence includes: in the verification operation, applying (N-1) second verification voltages to the selected character line according to the predetermined sequence to check N types of second program states for each of the plurality of memory cells included in the selected character line, and the maximum level of the second verification voltage is higher than the maximum level of the first verification voltage.

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