Plasma processing apparatus and plasma processing method

Abstract

This invention relates to a plasma processing apparatus and a plasma processing method, improving the controllability of the tilt angle of the edge region of a substrate during plasma processing, and at least one of the abnormal discharges between the substrate and the edge ring. The apparatus for performing plasma processing on a substrate includes: a processing chamber; a substrate support disposed within the processing chamber, the substrate support including a base, an electrostatic chuck on the base, and an edge ring disposed surrounding a substrate mounted on the electrostatic chuck; a radio frequency power supply supplying radio frequency power for generating plasma from gas inside the processing chamber; a DC power supply applying a negative DC voltage to the edge ring; a waveform control element controlling the waveform of the DC voltage; and a control unit adjusting a constant of the waveform control element to control the time for the DC voltage to reach a desired value.

Description

Technical Field

[0001] This invention relates to a plasma treatment apparatus and a plasma treatment method. Prior Technology

[0002] Patent Document 1 discloses a plasma processing apparatus for performing plasma processing on wafers. The apparatus includes a stage for mounting a wafer disposed in a processing chamber and an edge ring disposed on the stage to surround the wafer. In this plasma processing apparatus, the distortion of the sheath layer is resolved by applying a negative DC voltage to the edge ring consumed by plasma, thereby achieving perpendicular ion incidence across the entire surface of the wafer. [Known Technical Literature] [Patent Literature]

[0003] Patent Document 1: Japanese Patent Application Publication No. 2008-227063 Summary of the Invention

[0004] [The problem that this invention aims to solve]

[0005] The technology disclosed in this invention improves at least one of the controllability of the tilt angle of the edge region of the substrate during plasma processing and abnormal discharge between the substrate and the edge ring. [Technical means to solve the problem]

[0006] One aspect of the present invention is an apparatus for performing plasma treatment on a substrate, comprising: a processing chamber; a substrate support disposed in the processing chamber, the substrate support including a base, an electrostatic chuck on the base, and an edge ring disposed to surround a substrate mounted on the electrostatic chuck; an radio frequency power supply for supplying radio frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; a waveform control element for controlling the waveform of the DC voltage; and a control unit for adjusting a constant of the waveform control element to control the time for the DC voltage to reach a desired value. [Effects of the Invention]

[0007] According to the present invention, the controllability of the tilt angle of the edge region of the substrate during plasma processing and at least one of abnormal discharge between the substrate and the edge ring can be improved. Simple Explanation of the Diagram

[0008] Figure 1 is a schematic longitudinal sectional view showing the configuration of the plasma processing apparatus of this embodiment. Figure 2 is an explanatory diagram of the power supply system of the plasma processing device in this embodiment. Figure 3A is an explanatory diagram showing an example of the internal structure of the second radio frequency filter. Figure 3B is an explanatory diagram showing an example of the internal structure of the second radio frequency filter. Figure 3C is an illustrative diagram showing an example of the internal structure of the second radio frequency filter. Figure 3D is an explanatory diagram showing an example of the internal structure of the second radio frequency filter. Figures 4(a) and (b) are illustrations showing the changes in the shape of the sheath caused by the consumption of the edge ring and the occurrence of the tilting of the incident direction of ions. Figures 5(a) and (b) are explanatory diagrams showing the changes in the shape of the sheath and the occurrence of the tilting of the incident direction of ions. Figure 6 is an explanatory diagram showing the relationship between the DC voltage from the DC power supply, the impedance of the second RF filter, and the tilt correction angle. Figure 7 is an explanatory diagram showing the time-varying changes in radio frequency power and DC voltage in this embodiment. Figure 8 is an explanatory diagram of the power supply system of another embodiment of the plasma processing device. Figure 9 is an explanatory diagram of the power supply system of another embodiment of the plasma processing device. Figure 10 is an explanatory diagram of the power supply system of another embodiment of the plasma processing device. Figure 11 is an explanatory diagram showing the time-varying changes of radio frequency power and DC voltage in another embodiment. Figure 12 is an explanatory diagram showing the time-varying changes in radio frequency power and DC voltage in another embodiment. Implementation

[0009] In the manufacturing process of semiconductor devices, plasma processing is performed on semiconductor wafers (hereinafter referred to as "wafers"). In plasma processing, plasma is generated by exciting processing gases, and the wafer is processed by the plasma.

[0010] Plasma processing is performed in a plasma processing apparatus. A plasma processing apparatus generally includes a processing chamber, a platform, and a radio frequency (RF) power supply. In one example, the RF power supply includes a first RF power supply and a second RF power supply. The first RF power supply provides first RF power to generate plasma in the gas within the processing chamber. The second RF power supply provides second RF power for biasing the lower electrode to guide ions into the wafer. Plasma is generated within the processing chamber. A platform is disposed within the processing chamber. The platform includes a lower electrode and an electrostatic chuck. In one example, an edge ring is disposed on the electrostatic chuck in a manner that surrounds the wafer placed on the electrostatic chuck. The edge ring is provided to improve the uniformity of plasma processing on the wafer.

[0011] As the plasma processing continues, the edge ring wears down, causing a reduction in its thickness. This reduction in edge ring thickness alters the shape of the sheath layer above the edge ring and the wafer's edge region. This change in sheath shape causes the incident direction of ions in the wafer's edge region to tilt towards the vertical. Consequently, the recesses formed in the wafer's edge region become tilted towards the wafer's thickness direction.

[0012] In order to form a recess extending along the thickness direction of the wafer in the edge region, it is necessary to control the shape of the edge ring and the sheath layer above the edge region of the wafer, and adjust the tilt of the incident direction of ions toward the edge region of the wafer. Therefore, in order to control the shape of the edge ring and the sheath layer above the edge region of the wafer, for example, Patent Document 1 proposes a plasma processing apparatus configured to apply a negative DC voltage to the edge ring from a DC power supply.

[0013] In conventional plasma processing apparatuses, one or both of the first and second radio frequency (RF) powers are supplied in a pulsed manner. In such plasma processing, there is a concern that discharge may occur due to the potential difference between the wafer and the edge ring. Therefore, plasma processing apparatuses may apply a DC voltage to the edge ring in sync with the pulsed RF power supply.

[0014] However, when supplying RF power in a pulsed manner, the bias voltage cannot be activated immediately due to the reflection of the RF power (reflected power). Therefore, even if a DC voltage is applied to the edge ring synchronously with the RF power, a potential difference still exists between the wafer and the edge ring, which cannot sufficiently reduce the risk of discharge. As a result, the wafer may be damaged.

[0015] The technology disclosed in this invention suppresses discharge between the substrate and the edge ring. Hereinafter, with reference to the drawings, the plasma processing apparatus and plasma processing method of this embodiment will be described. Furthermore, in this specification and drawings, elements having substantially the same functional configuration are given the same reference numerals to avoid redundant descriptions.

[0016] <Plasma Treatment Device> First, the plasma processing apparatus of this embodiment will be described. Figure 1 is a schematic longitudinal sectional view showing the configuration of the plasma processing apparatus 1. Figure 2 is an explanatory diagram of the power supply system for applying DC voltage to the edge ring 14. The plasma processing apparatus 1 is a capacitively coupled type plasma processing apparatus. In the plasma processing apparatus 1, plasma processing is performed on the wafer W, which serves as a substrate. The plasma processing is not particularly limited, and for example, etching, film formation, diffusion, etc., are performed.

[0017] As shown in Figure 1, the plasma processing apparatus 1 has a slightly cylindrical processing chamber 10. The processing chamber 10 has a centrally defined processing space S for generating plasma. The processing chamber 10 is, for example, made of aluminum. The processing chamber 10 is connected to ground potential.

[0018] Inside the processing chamber 10, a platform 11 serving as a substrate support for the wafer W is housed. The platform 11 includes a lower electrode 12, an electrostatic chuck 13, and an edge ring 14. The lower electrode is an example of a base plate. Alternatively, an electrode plate (not shown) made of aluminum may be provided on the bottom surface of the lower electrode 12.

[0019] The lower electrode 12 is made of a conductive material, such as aluminum or other metals, and has a slightly rounded plate shape.

[0020] Alternatively, platform 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 13, edge ring 14, and wafer W to a desired temperature. The temperature control module may also include a heater, a flow path, or a combination thereof, allowing temperature-regulating media such as refrigerant or heat transfer gas to flow through the flow path.

[0021] In one example, a flow path 15a is formed inside the lower electrode 12. A temperature-regulating medium is supplied to the flow path 15a from a quench unit (not shown) located outside the processing chamber 10 via an inlet pipe 15b. The temperature-regulating medium supplied to the flow path 15a returns to the quench unit via an outlet flow path 15c. Within the flow path 15a, by circulating a temperature-regulating medium, such as cooling water, the electrostatic chuck 13, the edge ring 14, and the wafer W can be cooled to the desired temperature.

[0022] An electrostatic chuck 13 is disposed on the lower electrode 12. In one example, the electrostatic chuck 13 is configured to hold both the wafer W and the edge ring 14 by electrostatic attraction. The top surface of the central portion of the electrostatic chuck 13 is formed to be higher than the top surface of the edge portion. The top surface of the central portion of the electrostatic chuck 13 becomes the wafer mounting surface for placing the wafer W; in one example, the top surface of the edge portion of the electrostatic chuck 13 becomes the edge ring mounting surface for placing the edge ring 14.

[0023] In one example, a first electrode 16a for adsorbing and holding the wafer W is provided at the center of the electrostatic chuck 13. A second electrode 16b for adsorbing and holding the edge ring 14 is provided at the edge of the electrostatic chuck 13. The electrostatic chuck 13 has a configuration that clamps the electrodes 16a and 16b between insulating materials made of insulating material.

[0024] A DC voltage from a DC power supply (not shown) is applied to the first electrode 16a. The resulting electrostatic force adsorbs and holds the wafer W on the top surface of the center portion of the electrostatic chuck 13. Similarly, a DC voltage from a DC power supply (not shown) is applied to the second electrode 16b. In one example, the resulting electrostatic force adsorbs and holds the edge ring 14 on the top surface of the edge portion of the electrostatic chuck 13.

[0025] In this embodiment, the central portion of the electrostatic chuck 13 where the first electrode 16a is disposed is integrated with the edge portion where the second electrode 16b is disposed; however, the central portion and the edge portion can also be separate components. Furthermore, both the first electrode 16a and the second electrode 16b can be unipolar or bipolar.

[0026] Furthermore, in this embodiment, the edge ring 14 is electrostatically attracted to the electrostatic chuck 13 by applying a DC voltage to the second electrode 16b, but the method of holding the edge ring 14 is not limited to this one. For example, the edge ring 14 can also be attracted and held by an adsorption sheet, or the edge ring 14 can also be clamped and held. Alternatively, the edge ring 14 can also be held by its own weight.

[0027] Edge ring 14 is a ring-shaped component configured to surround the wafer W mounted on the top surface of the central portion of electrostatic chuck 13. Edge ring 14 is provided to improve the uniformity of plasma processing. Therefore, edge ring 14 is made of a material suitable for plasma processing and has electrical conductivity, for example, it can be made of Si or SiC.

[0028] The platform 11, constructed as described above, is fastened to a slightly cylindrical support member 17 located at the bottom of the processing chamber 10. The support member 17 is made of an insulator, such as ceramic or quartz.

[0029] A spray head 20 is disposed above the platform 11, facing the platform 11. The spray head 20 includes an electrode plate 21 disposed facing the processing space S, and an electrode support 22 disposed above the electrode plate 21. The electrode plate 21 functions as an upper electrode paired with the lower electrode 12. The spray head 20 is connected to ground potential when the first radio frequency power supply 50 is electrically coupled to the lower electrode 12 as described later. Furthermore, the spray head 20 is supported on the upper part (ceiling surface) of the processing chamber 10 via an insulating shielding member 23.

[0030] On the electrode plate 21, a plurality of gas outlets 21a are formed for supplying the processing gas delivered from the gas diffusion chamber 22a (described later) to the processing space S. The electrode plate 21 is, for example, made of a conductor or semiconductor with low resistivity that generates little Joule heat.

[0031] The electrode support 22 supports the electrode plate 21 in a detachable manner. The electrode support 22 may have, for example, a plasma-resistant film formed on the surface of a conductive material such as aluminum. This film may be formed by anodizing or a ceramic film such as yttrium oxide. A gas diffusion chamber 22a is formed inside the electrode support 22. From the gas diffusion chamber 22a, a plurality of gas flow holes 22b communicating with the gas outlet 21a are formed. Furthermore, a gas inlet hole 22c connected to the gas supply pipe 33 (described later) is formed in the gas diffusion chamber 22a.

[0032] In addition, the gas supply source group 30 that supplies the processing gas to the gas diffusion chamber 22a is connected to the electrode support 22 via the flow control machine group 31, the valve group 32, the gas supply pipe 33, and the gas inlet port 22c.

[0033] The gas supply source group 30 includes multiple gas supply sources required for etching. The flow control machine group 31 includes multiple flow controllers, and the valve group 32 includes multiple valves. Each of the multiple flow controllers in the flow control machine group 31 is a mass flow controller or a pressure-controlled flow controller. In the plasma processing apparatus 1, the processing gas selected from one or more gas supply sources from the gas supply source group 30 is supplied to the gas diffusion chamber 22a via the flow control machine group 31, the valve group 32, the gas supply pipe 33, and the gas inlet port 22c. Then, the processing gas supplied to the gas diffusion chamber 22a is dispersed in a spray-like manner into the processing space S via the gas flow port 22b and the gas outlet 21a.

[0034] A baffle 40 is provided at the bottom of the processing chamber 10, between the inner wall of the processing chamber 10 and the support member 17. The baffle 40 is constructed, for example, by coating aluminum with a ceramic such as yttrium oxide. A plurality of through holes are formed in the baffle 40. The processing space S is connected to the exhaust port 41 via the baffle 40. For example, an exhaust device 42 such as a vacuum pump is connected to the exhaust port 41, so that the pressure inside the processing space S can be reduced by means of the exhaust device 42.

[0035] In addition, a wafer W loading port 43 is formed on the side wall of the processing chamber 10, which can be opened and closed by a gate valve 44.

[0036] The plasma processing apparatus 1 further includes a first radio frequency power supply 50, a second radio frequency power supply 51, and a matching unit 52. The first radio frequency power supply 50 and the second radio frequency power supply 51 are coupled to the lower electrode 12 via the matching unit 52. Furthermore, the first radio frequency power supply 50 and the second radio frequency power supply 51 constitute the radio frequency power supply disclosed in this invention.

[0037] The first radio frequency (RF) power supply 50 generates RF power HF for plasma generation and supplies this RF power HF to the lower electrode 12. The RF power HF can be a frequency in the range of 27MHz to 100MHz, and in one example, 40MHz. The first RF power supply 50 is coupled to the lower electrode 12 via the first matching circuit 53 of the matching circuit 52. The first matching circuit 53 is a circuit used to match the output impedance of the first RF power supply 50 with the input impedance of the load side (lower electrode 12 side). Alternatively, the first RF power supply 50 may not be electrically coupled to the lower electrode 12, or it may be coupled to the upper electrode, i.e., the spray head 20, via the first matching circuit 53. Furthermore, instead of the first RF power supply 50, a pulse power supply configured to apply a pulse voltage other than RF power to the lower electrode 12 may be used. This pulse power supply is the same as the pulse power supply used later to replace the second RF power supply 51.

[0038] The second RF power supply 51 generates RF power (RF bias power) LF for introducing ions into the wafer W, and supplies this RF power LF to the lower electrode 12. The RF power LF can be a frequency in the range of 400kHz to 13.56MHz, and in one example, it is 400kHz. The second RF power supply 51 is coupled to the lower electrode 12 via the second matching circuit 54 of the matching circuit 52. The second matching circuit 54 is a circuit used to match the output impedance of the second RF power supply 51 with the input impedance of the load side (lower electrode 12 side). Alternatively, instead of the second RF power supply 51, a pulsed power supply configured to apply a pulsed voltage other than RF power to the lower electrode 12 can be used. Here, the pulsed voltage is a pulsed voltage whose magnitude changes periodically. The pulsed power supply can also be a DC power supply. The pulsed power supply can be configured to apply a pulsed voltage itself, or it can be configured to have a device for pulsed voltage on the downstream side. In one example, a pulsed voltage is applied to the lower electrode 12 to generate a negative potential in the wafer W. The pulsed voltage can be a rectangular wave, a triangular wave, a pulse wave, or other waveforms. The frequency of the pulsed voltage (pulse frequency) can be in the range of 100kHz to 2MHz. The aforementioned radio frequency power LF or pulsed voltage (hereinafter referred to as "bias power") can also be supplied or applied to the bias electrode disposed inside the electrostatic chuck 13. Furthermore, the pulsed power supply is not limited to a power-controlled power supply; there are also cases where a constant voltage controlled power supply is used. In this case, the radio frequency power RF and the radio frequency voltage of the constant voltage controlled power supply are synonymous. The bias electrode can also include a first bias electrode disposed in the region corresponding to the wafer mounting surface (the first region) and a second bias electrode disposed in the region corresponding to the edge ring mounting surface (the second region). In this case, the bias power applied or supplied to the first bias electrode (first bias power) and the bias power applied or supplied to the second bias electrode (second bias power) can also be controlled independently.

[0039] Furthermore, in the following description, the state in which one or both of the radio frequency power HF from the first radio frequency power source 50 and the radio frequency power LF from the second radio frequency power source 51 are supplied to the lower electrode 12 is referred to as "RF on (RF on)". In addition, the state in which neither the radio frequency power HF nor the radio frequency power LF is supplied to the lower electrode 12 is referred to as "RF off (RF off)". Furthermore, the radio frequency power HF and the radio frequency power LF are collectively referred to as "radio frequency power RF".

[0040] As shown in Figures 1 and 2, the plasma processing apparatus 1 further includes a direct current (DC) power supply 60, a switching unit 61, a first radio frequency (RF) filter 62, and a second RF filter 63. The DC power supply 60 is electrically connected to the edge ring 14 via a path 64. Along the path 64, the switching unit 61, the second RF filter 63, and the first RF filter 62 are sequentially arranged from the DC power supply 60 side. In this embodiment, two RF filters 62 and 63 are provided for the DC power supply 60, but the number of RF filters is not limited to this configuration; for example, it could be one.

[0041] Furthermore, in this embodiment, the DC power supply 60 is connected to the edge ring 14 via the switching unit 61, the first RF filter 62, and the second RF filter 63. However, the power supply system that applies DC voltage to the edge ring 14 is not limited to this embodiment. For example, the DC power supply 60 may also be directly electrically connected to the edge ring 14 via the switching unit 61, the second RF filter 63, the first RF filter 62, and the lower electrode 12.

[0042] The DC power supply 60 generates a negative DC voltage (DC) applied to the edge ring 14. Furthermore, the DC power supply 60 is a variable DC power supply, and the level of the DC voltage (DC) can be adjusted. Inside the DC power supply 60, a pulse generating unit 65 is provided to generate pulses of the DC voltage (DC). The pulse generating unit 65 applies the DC voltage (DC) in a pulsed manner based on a pulse signal from the pulse signal source 80 (described later). Alternatively, the pulse generating unit 65 can also be configured as a device independent of the DC power supply 60, located downstream of the DC power supply 60.

[0043] The switching unit 61 is configured to stop the application of DC voltage from the DC power supply 60 to the edge ring 14. Specifically, the switching unit 61 switches the connection between the edge ring 14 and the DC power supply circuit 66 or the power stripping circuit 67. Furthermore, in cases where the DC power supply 60 has two or more DC voltage outputs, a built-in power stripping circuit may be included. For example, if the output of the first DC voltage is greater than the output of the second DC voltage, in order to change the output from the first DC voltage to the second DC voltage, after outputting the first DC voltage, it is de-charged to remove the charge until it is equal to the second DC voltage before outputting the second DC voltage. Therefore, depending on the number of power outputs, a power stripping circuit may be built into the DC power supply 60, either internally or externally, to eliminate the potential difference when switching between the two DC voltage outputs. This power stripping circuit can also be used as the power stripping circuit 67.

[0044] The DC power supply circuit 66 is a circuit connected to a DC power supply 60 for applying a DC voltage (DC) to the edge ring 14 from the DC power supply 60. In one example, the DC power supply circuit 66 includes a switching element 66a and a damping element 66b. For example, a field-effect transistor (FET) is used for the switching element 66a. However, in addition to an FET, an insulated-gate bipolar transistor (IGBT) or a relay can also be used for the switching element 66a. When the switching element 66a is closed (on state), the edge ring 14 is connected to the DC power supply 60, and a DC voltage (DC) is applied to the edge ring 14. On the other hand, when the switching element 66a is open (off state), no DC voltage (DC) is applied to the edge ring 14. Additionally, in the following description, the state in which the switching element 66a is turned on is referred to as "DC on" and the state in which the switching element 66a is turned off is referred to as "DC off". Furthermore, the damping element 66b, such as a resistor or a coil, can have its value and position arbitrarily determined by the designer.

[0045] The power-removing circuit 67 is a circuit used to remove charge from the edge ring 14. In one example, the power-removing circuit 67 includes a switching element 67a and a damping element 67b. For example, a field-effect transistor (FET) is used for the switching element 67a. However, in addition to FET, an insulated-gate bipolar transistor (IGBT) or a relay can also be used for the switching element 67a. When the switching element 67a is in the closed state (conducting state), the edge ring 14 is connected to the power-removing circuit 67, and the charge of the edge ring 14 flows to the power-removing circuit 67, thereby removing charge from the edge ring 14. On the other hand, when the switching element 67a is in the open state (off state), the edge ring 14 is not removed from the charge. In the following description, the state in which the switching element 67a is in the conducting state is referred to as "power-removing conduction," and the state in which the switching element 67a is in the off state is referred to as "power-removing off." Furthermore, the damping element 67b, such as a resistor or coil, can have its value and location determined arbitrarily by the designer.

[0046] The first RF filter 62 and the second RF filter 63 each attenuate the radio frequency (RF) power, which is provided to protect the DC power supply 60. The first RF filter 62, for example, attenuates 40MHz of RF power from the first RF power supply 50. The second RF filter 63, for example, attenuates 400kHz of RF power from the second RF power supply 51.

[0047] The second radio frequency filter 63 includes a waveform control element 70 and a non-waveform control element 71. The waveform control element 70 controls the waveform of the DC voltage (DC). The non-waveform control element 71 is a component with functions other than controlling the waveform of the DC voltage (DC), such as a variable element used to make the impedance of the second radio frequency filter 63 variable, as described later. Alternatively, the non-waveform control element 71 may be, for example, a capacitive element, an inductive element, a resistive element, all elements with equivalent functions, an electromagnetic energy converter, a transmission line, or any combination of one or more of these, or all of them. Furthermore, in the example of Figure 2, although the waveform control element 70 and the non-waveform control element 71 are arranged sequentially from the DC power supply 60 side, their arrangement order can be reversed. Those skilled in the art can appropriately design the arrangement order of these waveform control elements 70 and non-waveform control elements 71.

[0048] Figures 3A-3D are explanatory diagrams showing an example of the internal structure of the second RF filter 63. As shown in Figure 3A, a high-potential side path 72 and a low-potential side path 73 are provided inside the second RF filter 63. The high-potential side path 72 is, for example, a path 64 connecting the DC power supply 60 to the edge ring 14. The low-potential side path 73 is, for example, a path connecting to a grounded housing or shielding wire, a grounding wire, etc.

[0049] The waveform control element 70 can be any one of a capacitive element (waveform control element 70b), an inductive element (waveform control element 70a), a resistive element (waveform control element 70b), a collection of elements with equivalent functions, an electromagnetic energy converter, or a transmission line. Furthermore, the waveform control element 70 can also be a combination of multiple types of capacitive, inductive, resistive, electromagnetic energy converters, and transmission lines, or it can be composed of all of them. Further, as shown in FIG3B, the waveform control element 70 can also be connected in series with the non-waveform control element 71 in the high-potential side path 72, for example; or as shown in FIG3C, it can be connected in parallel with the non-waveform control element 71 in the high-potential side path 72. In this way, those skilled in the art can appropriately design the number and configuration of the waveform control elements 70.

[0050] The constant of the waveform control element 70 becomes variable. In this case, the waveform control element 70 can be, for example, either a coil (inductor) or a capacitor (capacitor). Furthermore, it is not limited to coils or capacitors; any element whose constant can be changed by voltage or current (such as a diode) can achieve the same function. By making the constant of the waveform control element 70 variable, as described later, the waveform of the DC voltage can be controlled by adjusting the constant of the waveform control element 70. Alternatively, it is not necessary for the constant of the waveform control element 70 itself to be variable; as shown in FIG. 3D, the constant of the waveform control element 70 can be adjusted by switching a combination of waveform control elements 70 with fixed constant values ​​using the switching circuit 74. In this case, a plurality of waveform control elements 70 with different constants are provided inside the second RF filter 63.

[0051] The second RF filter 63 can also be configured with variable impedance. That is, the impedance can be made variable by making the non-waveform control element 71 of the second RF filter 63 a variable element. The non-waveform control element 71 can be, for example, either a coil (inductor) or a capacitor (capacitor). Furthermore, it is not limited to coils or capacitors; any variable impedance element, such as a diode, can achieve the same function regardless of its configuration if it is a variable impedance element that can be made constant by voltage or current. Those skilled in the art can also appropriately design the number and position of the non-waveform control element 71. Furthermore, it is not necessary for the element itself to be variable; for example, it is also possible to have a plurality of elements with fixed impedance values, and make the impedance variable by switching the combination of elements with fixed impedance values ​​using a switching circuit. In addition, those skilled in the art can appropriately design the circuit configurations of the second RF filter 63 and the first RF filter 62 described above.

[0052] Furthermore, in this embodiment, a waveform control element 70 is newly added to the existing configuration of the second RF filter 63. In this case, the design freedom of the waveform control element 70 is high. Alternatively, the constants of an existing non-waveform control element 71 can be changed within the second RF filter 63 to make it function as a waveform control element 70. In this case, the waveform control element 70 has functions other than controlling the waveform of the DC voltage. For example, the waveform control element 70 has the function of attenuating the RF power and adjusting the tilt angle (described later) using impedance control. Furthermore, it is preferable to make these functions independent. This requires a design where adjusting the circuit constant has an effect on waveform control but not on impedance adjustment. Those skilled in the art can freely design the degree of influence of these functions and the separation and independence of functions. This reduces the equipment cost compared to not adding the waveform control element 70.

[0053] Furthermore, although the waveform control element 70 is provided inside the second RF filter 63 in this embodiment, the waveform control element 70 may also be provided inside the first RF filter 62. Alternatively, when multiple waveform control elements 70 are provided, waveform control elements 70 may be provided in both the second RF filter 63 and the first RF filter 62.

[0054] As shown in Figure 1, the plasma processing apparatus 1 further includes a pulse signal source 80. The pulse signal source 80 sends pulse signals, i.e., signals controlling the pulse timing, to the first RF power supply 50, the second RF power supply 51, and the DC power supply 60 (pulse generation unit 65). The first RF power supply 50 and the second RF power supply 51 each supply RF power HF and RF power LF in a pulsed manner according to the pulse signal. Furthermore, the DC power supply 60 applies a DC voltage DC in a pulsed manner according to the pulse signal. The pulse signal source 80 can control the synchronization timing of the RF power HF and RF power LF with the DC voltage DC. Alternatively, this pulse signal source can also be built into the first RF power supply 50, the second RF power supply 51, and the DC power supply 60.

[0055] The plasma processing apparatus 1 further includes a measuring device (not shown) for measuring the self-bias voltage of the edge ring 14 (or the self-bias voltage of the lower electrode 12 or the wafer W). Furthermore, those skilled in the art can appropriately design the configuration of the measuring device.

[0056] A control unit 100 is provided in the aforementioned plasma processing apparatus 1. The control unit 100, for example, is a computer equipped with a CPU (Central Processing Unit) and memory, and has a program storage unit (not shown). The program storage unit stores the program for controlling the plasma processing of the plasma processing apparatus 1. Alternatively, the program can be recorded on a computer-readable recording medium and installed onto the control unit 100.

[0057] <Plasma Treatment Methods> Next, the plasma treatment performed using the plasma treatment apparatus 1 configured as described above will be explained.

[0058] First, wafer W is moved into the processing chamber 10 and placed on an electrostatic chuck 13. Then, by applying a DC voltage to the first electrode 16a of the electrostatic chuck 13, wafer W is electrostatically attracted to the chuck 13 by Coulomb force and held in place. Furthermore, after wafer W is moved in, the vacuum level inside the processing chamber 10 is reduced to the desired vacuum level using an exhaust device 42.

[0059] Next, processing gas is supplied from the gas supply source group 30 to the processing space S via the spray head 20. Furthermore, radio frequency power HF for plasma generation is supplied to the lower electrode 12 by the first radio frequency power supply 50 to excite the processing gas and generate plasma. At this time, radio frequency power LF for iontophoresis can also be supplied by the second radio frequency power supply 51. Then, plasma processing is performed on the wafer W by the action of the generated plasma.

[0060] At the end of the plasma processing, firstly, the supply of radio frequency power HF from the first radio frequency power source 50 and the supply of processing gas from the gas supply source group 30 are stopped. Furthermore, if radio frequency power LF is supplied during the plasma processing, the supply of radio frequency power LF is also stopped. Next, the supply of heat transfer gas to the back side of the wafer W is stopped, and the adsorption and holding of the wafer W by the electrostatic chuck 13 is stopped.

[0061] Subsequently, wafer W is removed from processing chamber 10, ending a series of plasma processes on wafer W.

[0062] In addition, in plasma processing, there are also cases where the RF power HF from the first RF power source 50 is not used, but only the RF power LF from the second RF power source 51 is used to generate plasma.

[0063] <Tilt Angle Control Method> Next, the method for controlling the tilt angle in the aforementioned plasma processing will be explained. The tilt angle is the degree of tilt (angle) of the recess formed by the plasma processing in the edge region of wafer W relative to the thickness direction of wafer W. The tilt angle is approximately the same as the angle of tilt of the direction of ion incidence toward the edge region of wafer W relative to the vertical direction. Furthermore, in the following explanation, for the thickness direction of wafer W, the direction on the inner side (center side) is referred to as the inner side; and for the thickness direction of wafer W, the direction on the outer side is referred to as the outer side.

[0064] Figure 4 is an explanatory diagram showing the changes in the shape of the sheath and the tilting of the ion incident direction caused by the consumption of the edge ring. In Figure 4(a), the edge ring 14 shown as a solid line represents the edge ring 14 in the state without consumption. The edge ring 14 shown as a dotted line represents the edge ring 14 whose thickness has decreased due to consumption. Furthermore, the sheath SH shown as a solid line in Figure 4(a) shows the shape of the sheath SH in the state where the edge ring 14 is not consumed. The sheath SH shown as a dotted line shows the shape of the sheath SH in the state after the edge ring 14 is consumed. Further, in Figure 4(a), the arrows indicate the ion incident direction in the state after the edge ring 14 is consumed.

[0065] As shown in Figure 4(a), in one example where the edge ring 14 is not consumed, the shape of the sheath SH remains flat above the wafer W and the edge ring 14. Therefore, ions are incident on the entire surface of the wafer W in a slightly perpendicular direction (vertical direction). Thus, the tilt angle becomes 0 (zero) degrees.

[0066] On the other hand, once the edge ring 14 is consumed and its thickness decreases, the thickness of the sheath layer SH in the edge region of wafer W and above the edge ring 14 becomes smaller, and the shape of the sheath layer SH changes to a downward convex shape. As a result, the incident direction of ions relative to the edge region of wafer W is tilted relative to the vertical direction. In the following description, the phenomenon that the indentation formed by plasma processing tilts inward by an angle θ1 relative to the vertical direction when the incident direction of ions is tilted inward by an angle θ1 as shown in FIG. 4(b) is called inner tilt. The cause of inner tilt is not limited to the consumption of the edge ring 14. For example, if the voltage generated by the edge ring 14 is lower than the voltage on the wafer W side, it will be inner tilt in the initial state. In addition, for example, there are cases where the edge ring 14 is intentionally adjusted to be inner tilt in the initial state, and the tilt angle is corrected by adjusting the DC power supply 60 described later.

[0067] Alternatively, as shown in Figure 5, the thickness of the sheath layer SH may increase relative to the central region of wafer W, in the edge region of wafer W and above the edge ring 14, causing the shape of the sheath layer SH to bulge upwards. For example, when the voltage generated by the edge ring 14 is high, the shape of the sheath layer SH may bulge upwards. In Figure 5(a), the arrows indicate the incident direction of the ions. In the following description, when the incident direction of the ions is tilted outwards by an angle θ2 relative to the vertical direction as shown in Figure 5(b), the phenomenon that the concave portion formed by the plasma treatment tilts outwards by an angle θ2 is called outward tilt.

[0068] The plasma processing apparatus 1 of this embodiment controls the tilt angle. Specifically, the tilt angle is controlled by adjusting the DC voltage DC from the DC power supply 60 and the impedance of the second radio frequency filter 63 to control the ion incident angle. In this case, the waveform control element 70, which controls the waveform of the DC voltage DC, and the non-waveform control element 71, which makes the impedance variable, are independent or functionally separated. The waveform control element 70 and the non-waveform control element 71 do not necessarily have to be separate elements, but their functions must be separated; those skilled in the art can design circuit configurations based on this principle.

[0069] [DC Voltage Adjustment] First, the adjustment of the DC voltage DC from the DC power supply 60 will be explained. In the DC power supply 60, the DC voltage DC applied to the edge ring 14 is set to the negative polarity of the sum of the absolute value of the self-bias voltage Vdc (hereinafter referred to as "bias voltage Vdc") and a set value ΔV, that is, it is set to -(|Vdc|+ΔV). The bias voltage Vdc is the self-bias voltage of the wafer W, supplying RF power to one or both sides, and is the self-bias voltage of the lower electrode 12 when the DC voltage DC from the DC power supply 60 is not applied to the lower electrode 12. The set value ΔV is provided by the control unit 100.

[0070] The control unit 100 specifies a set value ΔV by using a predetermined function or table, based on the consumption of the edge ring 14 (the reduction in thickness calculated from the initial value of the edge ring 14) and the plasma processing conditions (e.g., processing time). That is, the control unit 100 determines the set value ΔV by inputting the consumption of the edge ring 14 and the bias voltage into the aforementioned function, or by using the consumption of the edge ring 14 and the bias voltage and referring to the aforementioned table.

[0071] In determining the setpoint ΔV, the control unit 100 may use the difference between the initial thickness of the edge ring 14 and the thickness of the edge ring 14 measured by a measuring instrument such as a laser measuring instrument or a camera as the consumption of the edge ring 14. Alternatively, the consumption of the edge ring 14 may be estimated from the change in the mass of the edge ring 14 measured by a measuring instrument such as a mass meter. Alternatively, the control unit 100 may use a pre-determined function or table to estimate the consumption of the edge ring 14 from specific parameters in order to determine the setpoint ΔV. These specific parameters may be any of the following: bias voltage Vdc, the peak value Vpp of the RF power HF or RF power LF, load impedance, or the electrical characteristics of the edge ring 14 or its periphery. The electrical characteristics of the edge ring 14 or its periphery may be any of the following: voltage, current, or resistance value including the edge ring 14 at any point on or around the edge ring 14. The additional function or table is predetermined in a way that determines the relationship between specific parameters and the consumption of edge ring 14. In order to estimate the consumption of edge ring 14, before the actual plasma treatment is performed or during maintenance of plasma treatment device 1, the plasma treatment device 1 is operated under the setting of the measurement conditions used to estimate the consumption, namely, radio frequency power HF, radio frequency power LF, pressure in the treatment space S, and flow rate of the treatment gas supplied to the treatment space S. Then, the aforementioned specific parameters are obtained, and the consumption of edge ring 14 is indicated by inputting these specific parameters into the aforementioned additional function, or by using the specific parameters and referring to the aforementioned table.

[0072] In the plasma processing apparatus 1, during plasma processing, that is, during the supply of radio frequency power (RF) of one or both of the radio frequency power (HF) and radio frequency power (LF), a DC voltage (DC) is applied to the edge ring 14 from the DC power supply 60. This controls the shape of the sheath layer above the edge ring 14 and the edge region of the wafer W, reduces the tilt of ions toward the edge region of the wafer W, and controls the tilt angle. As a result, a recess is formed covering the entire area of ​​the wafer W, slightly parallel to the thickness direction of the wafer W.

[0073] More specifically, during plasma processing, the bias voltage Vdc is measured using a measuring instrument (not shown). Furthermore, a DC voltage DC is applied to the edge ring 14 from the DC power supply 60. The value of the DC voltage DC applied to the edge ring 14 is, as described above, -(|Vdc|+ΔV). |Vdc| is the absolute value of the bias voltage Vdc measured immediately preceding it by the measuring instrument; ΔV is a set value determined by the control unit 100. Thus, the DC voltage DC applied to the edge ring 14 is determined from the bias voltage Vdc measured during etching. In this way, even if the bias voltage Vdc changes, the DC voltage DC generated by the DC power supply 60 is corrected, appropriately correcting the tilt angle.

[0074] [Impedance Adjustment] Next, the adjustment of the impedance of the second RF filter 63 will be explained.

[0075] Figure 6 is an explanatory diagram showing the relationship between the DC voltage DC from the DC power supply 60, the impedance of the second RF filter 63, and the tilt correction angle (hereinafter referred to as the "tilt correction angle"). The vertical axis of Figure 6 shows the tilt correction angle, and the horizontal axis shows the DC voltage DC from the DC power supply 60. As shown in Figure 6, if the absolute value of the DC voltage DC from the DC power supply 60 is increased, the tilt correction angle becomes larger. In addition, by adjusting the impedance of the second RF filter 63, the tilt correction angle also becomes larger. That is, by adjusting the impedance in this way, the correlation between the DC voltage DC and the tilt correction angle can be shifted towards the side where the tilt correction angle increases.

[0076] As shown in Figure 4, for example, once the edge ring 14 is consumed, the incident angle of the ions tilts inward relative to the vertical direction, becoming an inward tilt. Therefore, if the absolute value of the DC voltage DC from the DC power supply 60 is increased as shown in Figure 6, the tilt correction angle becomes larger, changing the inward tilt angle outward, and the tilt angle can be corrected to 0 (zero) degrees. However, if the absolute value of the DC voltage DC becomes too high, a discharge occurs between the wafer W and the edge ring 14. Therefore, the DC voltage DC that can be applied to the edge ring 14 is limited, and even if the tilt angle is to be controlled solely by adjusting the DC voltage DC, the control range is still limited.

[0077] Therefore, as shown in Figure 6, adjusting the impedance of the second RF filter 63 shifts the correlation between the DC voltage (DC) and the tilt correction angle towards a larger tilt correction angle. This further increases the absolute value of the DC voltage (DC) from the DC power supply 60, adjusting the tilt correction angle to the target angle θ3, thus correcting the tilt angle (back to 0). Therefore, according to this embodiment, by adjusting the impedance, the control range of the tilt angle can be increased without changing the adjustment range of the DC voltage (DC).

[0078] In this embodiment, although the tilt angle is controlled by adjusting the DC voltage DC from the DC power supply 60 and the impedance of the second RF filter 63, the tilt angle can also be controlled solely by the DC voltage DC.

[0079] <DC Voltage Waveform Control Methods> Here, in order to control the tilt angle as described above, the DC voltage DC applied from the DC power supply 60 to the edge ring 14 is adjusted, and a potential difference, i.e., a set value ΔV, is set between the wafer W and the edge ring 14. At this time, for example, if the timing of the DC voltage application is biased and an unexpected potential difference occurs, there is a concern that discharge may occur between the wafer W and the edge ring 14. As a result, the wafer W may be damaged.

[0080] Therefore, in this embodiment, by adjusting the constant of the waveform control element 70, the waveform of the DC voltage DC is controlled, and the time for the DC voltage DC to reach the desired value is controlled, that is, the time for the sum of the absolute value of the bias voltage Vdc and the set value ΔV to be the negative polarity of its absolute value (=-(|Vdc|+ΔV)), so as to enable it to track the potential changes of the wafer W in the edge ring 14.

[0081] Figure 7 is an explanatory diagram showing the changes in radio frequency power (RF) and DC voltage over time. In the upper graph of Figure 7, the vertical axis represents the RF power, and the horizontal axis represents time t. In the lower graph of Figure 7, the vertical axis represents the DC voltage, and the horizontal axis represents time t. In the lower graph of Figure 7, the solid line "BiasVoltage" shows the bias voltage generated by the RF power. The dotted line "Controlled Waveform" shows the DC voltage after waveform control is performed by adjusting the constant of the waveform control element 70 in this embodiment. The dotted chain line "Non-Controlled Waveform" shows the DC voltage in the conventional embodiment without waveform control, as a comparative example of this embodiment.

[0082] (Step S1) Step S1 is the step of removing charge from the edge ring 14. In step S1, the switching element 66a of the DC power supply circuit 66 is turned off (DC off), and the switching element 67a of the charge removal circuit 67 is turned off (charge removal on). In this way, the edge ring 14 is connected to the charge removal circuit 67, and the charge on the edge ring 14 is removed by the charge removal circuit 67. In this step S1, the supply of radio frequency power RF to the lower electrode 12 is stopped (RF off). Alternatively, the charge removal process of the edge ring 14 in step S1 may be omitted.

[0083] (Step S2) Step S2 involves supplying radio frequency power RF to the lower electrode 12 (RF on) and applying a DC voltage DC to the edge ring 14 (DC on), causing the DC voltage DC to rise to the desired value, i.e., to -(|Vdc|+ΔV). In step S2, the switching element 66a of the DC power supply circuit 66 is closed (DC on), and the switching element 67a of the power removal circuit 67 is open (power removal off).

[0084] In step S2, if RF is turned on, the RF power is reflected, causing the RF power supplied to the lower electrode 12 to rise slowly. Therefore, as shown by the solid line "Bias Voltage," the bias voltage generated by the RF power, i.e., the potential generated on wafer W, also rises slowly relative to the RF turn-on sequence. In contrast, as shown by the dotted chain line "Non-Controlled Waveform," the DC power supply 60 typically starts up quickly, and the DC voltage DC rises rapidly. As a result, the potential of the edge ring 14 tracks the potential of the DC power supply 60 and rises rapidly. Therefore, a larger potential difference than intended is generated between wafer W and edge ring 14, raising concerns about discharge between wafer W and edge ring 14.

[0085] Therefore, in this embodiment, the waveform of the DC voltage is controlled by adjusting the constant of the waveform control element 70. Specifically, when the DC voltage DC is applied (DC is turned on), the constant of the waveform control element 70 is adjusted so that the rise rate of the DC voltage DC, as shown by the dotted chain "Non-Controlled Waveform", is the same as the rise rate of the solid line "Bias Voltage". The rise rate is the degree of tilt of the graph in Figure 7. This suppresses the potential difference between the bias voltage (the potential of wafer W) and the DC voltage DC (the potential of edge ring 14). By converging this potential difference within a predetermined threshold, discharge between wafer W and edge ring 14 can be suppressed.

[0086] Furthermore, in this embodiment, the constant of the waveform control element 70 is adjusted so that the DC voltage DC reaches a stable state of -(|Vdc|+ΔV), maximizing the application time of this DC voltage DC on the edge ring 14. The maximum application time is the same as the time for supplying radio frequency power RF (RF turn-on). This maximizes the execution time of the plasma processing in step S3 described later, allowing for efficient and effective plasma processing.

[0087] (Step S3) Step S3 involves supplying radio frequency power RF (RF on) to the lower electrode 12 and applying a DC voltage DC (DC on, power off) to the edge ring 14 to perform plasma treatment on the wafer W. At this time, the DC voltage DC is maintained at a stable state of -(|Vdc|+ΔV).

[0088] (Step S4) Step S4 involves stopping the supply of radio frequency power (RF) to the lower electrode 12 (RF shutdown) and stopping the application of DC voltage (DC) to the edge ring 14 (DC shutdown), causing the DC voltage (DC) to drop to the desired value. At this time, the edge ring 14 is de-energized (de-energization on). In step S4, the switching element 66a of the DC power supply circuit 66 is opened, and the switching element 67a of the de-energization circuit 67 is closed (de-energization on).

[0089] In step S4, if the RF is turned off, the voltage is slowly removed using the time constant of the hardware (device) and plasma. Therefore, as shown by the solid line "Bias Voltage," the bias voltage, i.e., the potential of wafer W, decreases slowly. In contrast, as shown by the dotted chain line "Non-Controlled Waveform," the DC voltage DC decreases sharply, and the potential of edge ring 14 also decreases sharply. Therefore, a larger potential difference than expected is generated between wafer W and edge ring 14, raising concerns about discharge occurring between wafer W and edge ring 14.

[0090] Therefore, in this embodiment, the waveform of the DC voltage is controlled by adjusting the constant of the waveform control element 70. Specifically, when the switching element 67a of the power removal circuit 67 is closed (power removal is on), the constant of the waveform control element 70 is adjusted so that the potential difference between the bias voltage and the DC voltage is close. Alternatively, the bias voltage can be measured in advance, or it can be determined by a calculated time constant, etc. In this case, the potential difference between the bias voltage (the potential of the wafer W) and the DC voltage (the potential of the edge ring 14) can be suppressed. Then, by bringing this potential difference within a predetermined threshold, the discharge between the wafer W and the edge ring 14 can be suppressed.

[0091] Furthermore, when the switching unit 61 does not have a power-removing circuit 67, and the switching unit 61 is either open-circuited or the application of DC voltage is stopped (DC off), the plasma potential can be tracked to suppress the potential difference between the bias voltage (the potential of wafer W) and the DC voltage (the potential of edge ring 14). In addition, as another example, when the DC power supply 60 is a power supply with two or more DC voltages output, and it is switching to a second DC voltage different from the first DC voltage applied when DC is on, the speed of switching to the second DC voltage is controlled.

[0092] According to this embodiment, in either RF on or RF off, the waveform of DC voltage can be controlled by adjusting the constant of waveform control element 70, thereby suppressing the potential difference between wafer W and edge ring 14.

[0093] Here, the conditions for optimizing the waveform control element 70 are explained. The constant of the waveform control element 70 can also be adjusted in advance before the process to determine the optimal constant.

[0094] Specifically, the waveform control element 70 can be optimized by satisfying all five of the following conditions, or by satisfying any one or more of the five conditions according to the specifications. (1) The first condition is to make the rise rate of the DC voltage DC the same as the rise rate of the bias voltage, as described above, and to maximize the application time of the DC voltage DC. In order to achieve this condition, the constant of the waveform control element 70 and the configuration of the waveform control element 70 used are optimized. (2) The second condition is that when a discharge (arc discharge) is generated due to the potential difference between the wafer W and the edge ring 14 caused by the addition of a new waveform control element 70, the scale of the arc discharge does not increase. In order to achieve this condition, the constant of the waveform control element 70 is optimized, a specific waveform control element 70 is adopted, or a combination of specific waveform control elements 70 is adopted. (3) The third condition is that the power consumption of the DC power supply 60 does not increase. In order to achieve this condition, the constant of the waveform control element 70 is optimized, or only a specific waveform control element 70 is used. (4) The fourth condition is compatibility with existing components. For example, in this embodiment, if there is an existing non-waveform control element 71 inside the second RF filter 63, the constant of the waveform control element 70 is optimized after considering the constant of the non-waveform control element 71. (5) The fifth condition is to suppress the influence of radio frequency power (RF). For example, if a waveform control element 70 is provided inside the second radio frequency filter 63 as in this embodiment, the constant of the waveform control element 70 and the configuration of the waveform control element 70 are optimized within the range that the function of the second radio frequency filter 63 in attenuating the radio frequency power (RF) is not destroyed.

[0095] Furthermore, by making the constant of the waveform control element 70 variable as in this embodiment, the constant of the waveform control element 70 can be optimized for each pulse frequency of the radio frequency power RF and the DC voltage DC. In this case, the constant of the waveform control element 70 can also be changed at any timing.

[0096] Furthermore, the constant of the waveform control element 70 can be controlled by feedback. For example, when the constant of the waveform control element 70 changes with each pulse frequency of the radio frequency power RF and the DC voltage, the pulse frequency of the radio frequency power RF and the DC voltage can be measured, and the constant of the waveform control element 70 can be adjusted based on the measurement result. Additionally, for example, a voltage and current measuring device (not shown) for monitoring the waveform of the DC voltage can be installed together with the waveform control element 70, and the constant of the waveform control element 70 can be adjusted based on the measurement result of the measuring device, so that the DC voltage becomes an arbitrary waveform shape or value. Furthermore, for example, the waveform of the DC voltage can be measured using the monitoring function of the DC power supply 60, and the constant of the waveform control element 70 can be adjusted based on the result. Further, for example, a sensor for measuring the waveform shape can be installed on the second radio frequency filter 63, and the constant of the waveform control element 70 can be adjusted based on the measurement result (waveform shape) of the sensor.

[0097] <Another implementation of the waveform control element> Although the waveform control element 70 is provided inside the second RF filter 63 in the above embodiment, the placement of the waveform control element 70 is not limited to this embodiment. Those skilled in the art can design it appropriately between the DC power supply 60 and the edge ring 14. Hereinafter, another embodiment of the waveform control element 70 will be described.

[0098] As shown in Figure 8, the waveform control element 70 can also be disposed inside the DC power supply 60. The waveform control element 70 is disposed closer to the edge ring 14 than the pulse generation unit 65. Furthermore, for example, if the switching unit 61 is omitted, and a switching circuit (not shown) equivalent to the switching unit 61 is disposed inside the DC power supply 60, the waveform control element 70 is disposed closer to the edge ring 14 than the switching circuit. In this case, as shown in Figures 3A-3D, those skilled in the art can appropriately design the number and arrangement of the waveform control elements 70. Furthermore, the waveform control element 70 can be a newly added element to existing elements inside the DC power supply 60, or the constants of existing elements can be changed to make them function as the waveform control element 70.

[0099] As shown in Figure 9, the waveform control element 70 can also be disposed inside the switching unit 61. In this case, as shown in Figures 3A-3D, those skilled in the art can appropriately design the number and configuration of the waveform control element 70. Furthermore, the waveform control element 70 can be a new element added to the existing elements of the switching unit 61, namely the damping elements 66b and 67b. Alternatively, the existing damping elements 66b and 67b can be modified to function as the waveform control element 70. Furthermore, a new damping element can be added to the switching unit 61, and the constant of the added damping element can be modified to function as the waveform control element 70.

[0100] As shown in Figure 10, the waveform control element 70 can be located in path 64, which electrically connects the DC power supply 60 to the edge ring 14. However, considering the influence of radio frequency power (RF), the waveform control element 70 should preferably be located in path 64, which connects the DC power supply 60 to the second RF filter 63, or in path 64, which connects the second RF filter 63 to the first RF filter 62.

[0101] <Another Implementation of DC Voltage Waveform Control Method> In the above implementation, the waveform control element 70 is adjusted to control the waveform of the DC voltage when the RF is on and off. However, in addition to this waveform control, the function of delaying the pulse timing on the DC power supply 60 side can also be used. In this case, by setting the delay time, a floating potential state is formed at the output of the DC power supply 60, thereby enabling it to track the potential changes of the wafer W in the edge ring 14.

[0102] Furthermore, the delay time function generally provided by the switching unit 61 is to delay the switching of one circuit when switching between the DC power supply circuit 66 and the power removal circuit 67, so that the two circuits do not become conductive at the same time. If the two circuits are conductive at the same time, a short circuit will occur, hence this delay time function is provided. When supplying radio frequency power RF in a pulsed manner, a pulse signal is sent from the pulse signal source 80 and used as a synchronization signal in the first radio frequency power supply 50, the second radio frequency power supply 51, and the DC power supply 60. The aforementioned delay time function sets a delay time for these pulse signals. During these delay times, the DC power supply 60 is neither in a conductive state nor a conductive state, but in an indeterminate state. In the following description, the general delay time is sometimes referred to as "delay time Do", and the delay time of this embodiment is sometimes referred to as "delay time Dt".

[0103] Figure 11 is an explanatory diagram showing the time-varying changes in radio frequency power (RF) and DC voltage (DC). Figure 11 is the same graph as Figure 7. In the lower graph of Figure 11, the solid line "Bias Voltage" shows the bias voltage generated by the radio frequency power (RF). The dotted line "Controlled Waveform" shows the DC voltage after waveform control is performed by adjusting the constant of the waveform control element 70 in this embodiment. The dotted chain line "Non-Controlled Waveform" shows the DC voltage in the conventional embodiment without waveform control, as a comparative example of this embodiment.

[0104] (Step T1) Step T1 is the step of removing the static charge from the edge ring 14. The static charge removal process in step T1 is the same as that in step S1 described above. In addition, there are cases where the static charge removal process of the edge ring 14 in step T1 is omitted.

[0105] (Step T2) Step T2 refers to the period between supplying radio frequency power RF to the lower electrode 12 (RF on) and applying a DC voltage DC to the edge ring 14 (DC on), which is the first delay time Dt1. In step T2, the switching element 66a of the DC power supply circuit 66 is kept open (DC off), and the switching element 67a of the power removal circuit 67 is made open (power removal off). That is, the edge ring 14 is in a state where it is not connected to both the DC power supply circuit 66 and the power removal circuit 67.

[0106] Here, in the case of the delay time Do of the general switching unit 61, the DC power supply 60 is in an uncertain state, neither on nor off, so the delay time Do should be shortened as much as possible. In contrast, during the first delay time Dt1 in step T2, by first opening the switching element 66a of the DC power supply circuit 66 and the switching element 67a of the power stripping circuit 67, the output of the DC power supply 60 becomes a floating potential during the uncertain state. That is, by first setting the DC power supply circuit 66 and the power stripping circuit 67 to be in an idle state, the output of the DC power supply 60 becomes a floating potential during the first delay time Dt1. In this floating potential state, the potential of the edge ring 14 slowly rises, tracking the potential of the wafer W. Therefore, after the first delay time Dt1, the potential difference between the wafer W and the edge ring 14 decreases.

[0107] (Step T3) Step T3 involves applying a DC voltage (DC on) to the edge ring 14 while the lower electrode 12 is supplied with radio frequency power (RF on), causing the DC voltage to rise to the desired value, i.e., to -(|Vdc|+ΔV). In step T3, the switching element 66a of the DC power supply circuit 66 is closed (DC on), and the switching element 67a of the power removal circuit 67 is open (power removal off).

[0108] In step T3, the potential of the edge ring 14 can be made equal to the potential of the wafer W (the potential of the plasma and sheath), that is, it becomes the bias voltage Vdc based on the radio frequency power RF (which removes the generated reflections).

[0109] Furthermore, during DC conduction in step T3, the constant of the waveform control element 70 is adjusted in the same manner as in the above embodiment to control the waveform of the DC voltage DC. Specifically, at the start of DC voltage DC application (DC conduction), the constant of the waveform control element 70 is adjusted so that the rise rate of the DC voltage DC, as shown by the dotted chain "Non-Controlled Waveform," is the same as the rise rate of the solid line "Bias Voltage." This suppresses the potential difference between the bias voltage (the potential of wafer W) and the DC voltage DC (the potential of edge ring 14). Then, by bringing this potential difference within a predetermined threshold, discharge between wafer W and edge ring 14 can be suppressed.

[0110] (Step T4) Step T4 involves supplying radio frequency power RF (RF on) to the lower electrode 12 and applying a DC voltage DC (DC on, power off) to the edge ring 14 to perform plasma processing on the wafer W. At this time, the DC voltage DC is maintained at a stable state of -(|Vdc|+ΔV).

[0111] (Step T5) Step T5 refers to the period between the cessation of RF power supply to the lower electrode 12 (RF shutdown) and the cessation of DC voltage application to the edge ring 14 (DC shutdown), which is the second delay time Dt2. In step T5, the switching element 67a of the power-removing circuit 67 is kept open (power-removing shutdown), and the switching element 66a of the DC power supply circuit 66 is also made open (DC shutdown). That is, the edge ring 14 is made to be in a state where it is not connected to either the DC power supply circuit 66 or the power-removing circuit 67.

[0112] During the second delay time Dt2 of step T5, by first opening the switching element 66a of the DC power supply circuit 66 and the switching element 67a of the power stripping circuit 67, the output of the DC power supply 60 becomes a floating potential in the indeterminate state. That is, by first setting the DC power supply circuit 66 and the power stripping circuit 67 to be in an idle state, the output of the DC power supply 60 becomes a floating potential during the second delay time Dt2. When the DC power supply 60 is in a floating potential state, the potential of the edge ring 14 gradually decreases, tracking the potential of the wafer W. Therefore, after the second delay time Dt2 has elapsed, the potential difference between the wafer W and the edge ring 14 becomes smaller.

[0113] (Step T6) Step T6 involves stopping the supply of radio frequency power RF to the lower electrode 12 (RF off), stopping the application of DC voltage DC to the edge ring 14 (DC off), and causing the DC voltage DC to drop to a desired value. In step T6, the switching element 66a of the DC power supply circuit 66 is opened, and the switching element 67a of the power removal circuit 67 is closed (power removal on).

[0114] During the DC shutdown in step T6, the constant of the waveform control element 70 is adjusted in the same manner as in the above embodiment to control the waveform of the DC voltage. Specifically, when the switching element 67a of the power removal circuit 67 is closed (power removal is on), the constant of the waveform control element 70 is adjusted so that the potential difference between the bias voltage and the DC voltage is close. In this case, the potential difference between the bias voltage (the potential of wafer W) and the DC voltage (the potential of edge ring 14) can be suppressed. Then, by bringing this potential difference within a predetermined threshold, the discharge between wafer W and edge ring 14 can be suppressed.

[0115] Furthermore, in this embodiment, the common constraint on delay times Dt1 and Dt2 is the ratio of delay times Dt1 and Dt2 to the time when a DC voltage (DC turn-on time) is applied to the edge ring 14. Delay times Dt1 and Dt2 represent the time when no DC voltage (DC) is applied; therefore, if delay times Dt1 and Dt2 become longer, there is a deviation from the state of applying a DC voltage synchronized with the RF power supply. Therefore, delay times Dt1 and Dt2 are determined based on the DC turn-on time. Additionally, the minimum ratio of delay times Dt1 and Dt2 is determined by the process evaluation results of the plasma treatment.

[0116] The specific method for determining the first delay time Dt1 when RF is turned on is as follows. That is, the reflection time from the start of RF power supply is measured in advance, and the time above this reflection time is determined as the first delay time Dt1. Alternatively, the potential of the edge ring 14 can be measured, and the first delay time Dt1 can be determined based on the potential of the RF power and the edge ring 14.

[0117] The specific method for determining the second delay time Dt2 during RF shutdown is as follows. That is, the second delay time Dt2 is determined by measuring the potential of the edge ring 14 and de-energizing the edge ring 14 after the potential of the edge ring 14 has sufficiently decreased. Alternatively, the RF power RF can be measured, and the second delay time Dt2 can be determined solely based on the RF power RF.

[0118] In this embodiment, in addition to controlling the waveform of the DC voltage DC with the waveform control element 70 when the RF is on, a first delay time Dt1 is set between the RF on and DC on, thus further suppressing the potential difference between the wafer W and the edge ring 14. Similarly, when the RF is off, in addition to controlling the waveform of the DC voltage DC with the waveform control element 70, a second delay time Dt2 is set between the RF off and DC off, thus further suppressing the potential difference between the wafer W and the edge ring 14.

[0119] Here, when setting the functions of steps T2 and T5 in this embodiment based on existing functions, two types of pulse timing signals are generally used. A timing signal capable of determining three states—DC on, DC off, and floating potential—is required. Therefore, the device configuration becomes very complex.

[0120] Regarding this point, in this embodiment, by utilizing delay times Dt1 and Dt2, the timing of the edge ring 14's potential tracking relative to the wafer W's potential can be determined regardless of the DC power supply. Furthermore, since the timing of the floating potential is established on the DC power supply 60 side, the same pulse timing signal as the radio frequency power (RF) can be used. In other words, an existing pulse signal source 80 can be used, eliminating the need to recreate the pulse signal source 80.

[0121] Furthermore, the method for controlling the DC voltage when the RF is on and off is not limited to the above-described embodiments. For example, when the RF is on, step T2 can be omitted, and only the waveform control of the DC voltage in step T3 can be performed; when the RF is off, the DC voltage control in step T5 with the second delay time Dt2 and the waveform control of the DC voltage in step T6 can be performed. Alternatively, for example, when the RF is on, the DC voltage control in step T2 with the first delay time Dt1 and the waveform control of the DC voltage in step T3 can be performed; when the RF is off, step T5 can be omitted, and only the waveform control of the DC voltage in step T6 can be performed.

[0122] <Another implementation form>

[0123] The above embodiments can also be applied to power supplies where the DC power supply 60 has two or more DC voltages as outputs. Figure 12 is an explanatory diagram showing the time-varying changes in radio frequency power RF and DC voltage. Figure 12 is the same graph as Figures 7 and 11, and detailed descriptions are omitted. In Figure 12, the first bias voltage 1 represents the bias voltage generated by the first radio frequency power RF1. There is a first potential difference 1 between the first bias voltage 1 and the first DC voltage DC1. The second bias voltage 2 represents the bias voltage generated by the second radio frequency power RF2. There is a second potential difference 2 between the second bias voltage 2 and the second DC voltage DC2. The potential of the wafer W and the first potential difference 1 and the second potential difference 2 can be the same or different values.

[0124] In this situation, where the output of the first DC voltage DC1 is greater than the output of the second DC voltage DC2, in order to change the output of the first DC voltage DC1 to the second DC voltage DC2, after outputting the first DC voltage DC1, it is de-charged to remove the charge until it is equal to the second DC voltage DC2 before outputting the second DC voltage DC2. Therefore, depending on the number of power supply outputs, a de-charge circuit can be built inside or outside the DC power supply 60 to eliminate the potential difference when switching the outputs of the two DC voltages. This de-charge circuit can also be used as a de-charge circuit 67. In this embodiment, the above-mentioned waveform control effect can also be obtained for the switching between the first DC voltage DC1 and the second DC voltage DC2.

[0125] Although the plasma treatment apparatus 1 described above is a capacitively coupled plasma treatment apparatus, the plasma treatment apparatus used in this invention is not limited to this form. For example, the plasma treatment apparatus can also be an inductively coupled plasma treatment apparatus.

[0126] Furthermore, for example, the present invention includes the following embodiments.

[0127] (Note 1) A plasma processing apparatus for performing plasma processing on a substrate, the plasma processing apparatus comprising: Processing room; A substrate support is disposed in the processing chamber. The substrate support includes a base, an electrostatic chuck on the base, and an edge ring configured to surround the substrate placed on the electrostatic chuck. Radio frequency power supply, providing radio frequency power for generating plasma from the gas inside the processing chamber; A DC power supply applies a negative DC voltage to the edge ring; Waveform control element, controlling the waveform of the DC voltage; and The control unit adjusts the constant of the waveform control element to control the time when the DC voltage reaches the desired value.

[0128] (Note 2) As described in Note 1, the plasma treatment apparatus, wherein, Includes an RF filter, which is electrically connected to the edge ring; The waveform control element is configured within the radio frequency filter.

[0129] (Note 3) As described in Note 1, the plasma treatment apparatus, wherein, The waveform control element is located within the DC power supply.

[0130] (Note 4) As described in Note 3, the plasma treatment apparatus, wherein, The DC power supply includes a pulse generating unit that generates pulses of the DC voltage; The waveform control element is positioned closer to the edge ring side than the pulse generating section.

[0131] (Note 5) As described in Note 1, the plasma treatment apparatus, wherein, It also includes: a DC power supply circuit for applying the DC voltage to the edge ring; A voltage-removing circuit is used to remove voltage from the edge ring; and The switching unit switches the connection between the edge ring and the DC power supply circuit or the power elimination circuit; The waveform control element is configured within the switching unit.

[0132] (Note 6) As described in Note 1, the plasma treatment apparatus, wherein, The waveform control element is positioned in the path between the DC power supply and the RF filter.

[0133] (Note 7) As described in any of Notes 1 to 6, the plasma processing apparatus, wherein, It has a high-potential side path connecting the DC power supply to the edge ring and a low-potential side path connecting the edge ring to ground; The waveform control element includes any one or more of the following: a capacitive element, an inductive element, a resistive element, an electromagnetic energy converter, and a transmission line, disposed on the high-potential side path or disposed between the high-potential side path and the low-potential side path.

[0134] (Note 8) As described in any of Notes 1 to 7, the plasma processing apparatus, wherein, It also includes non-waveform control elements, which have functions other than controlling the waveform of the DC voltage; The other functions include at least one function selected from the group consisting of capacitive elements, inductive elements, resistive elements, electromagnetic energy converters and transmission lines.

[0135] (Note 9) As described in any of Notes 1 to 8, the plasma processing apparatus, wherein, This waveform control element has functions other than controlling the waveform of the DC voltage; The other functions include at least one function selected from the group consisting of capacitive elements, inductive elements, resistive elements, electromagnetic energy converters and transmission lines.

[0136] (Note 10) As described in Note 2, the plasma treatment apparatus, wherein, The non-waveform control element includes a variable element for making the impedance of the RF filter variable.

[0137] (Note 11) As described in any of Notes 1 to 9, the plasma processing apparatus, wherein, The constant of this waveform control element can be changed.

[0138] (Note 12) As described in any of Notes 1 to 9, the plasma processing apparatus, wherein, The constant of this waveform control element is a fixed value; It includes a plurality of waveform control elements with different constants; It also includes a switching circuit for switching the plurality of waveform control elements.

[0139] (Note 13) As described in any of Notes 1 to 12, the plasma processing apparatus, wherein, The control unit adjusts the constant of the waveform control element to control the waveform of the DC voltage so that the DC voltage is close to the bias voltage.

[0140] (Note 14) As described in any of Notes 1 to 12, the plasma processing apparatus, wherein, The control unit controls the plasma processing device to perform a process including the following steps: (a) Initiating the supply of radio frequency power, and after a predetermined delay time, initiating the application of DC voltage; and (b) Adjust the constant of the waveform control element to control the waveform of the DC voltage and control the time for the DC voltage to reach the desired value.

[0141] (Note 15) As described in Note 14, the plasma processing apparatus, wherein, The control unit controls the plasma processing device to perform a process including the following steps: (c) Stop the supply of radio frequency power, and after a predetermined delay, begin de-energizing the edge ring; and (b) Adjust the constant of the waveform control element to control the waveform of the DC voltage and control the time for the DC voltage to reach the desired value.

[0142] (Note 16) As described in Note 14 or 15, in which, The control unit determines the delay time based on the ratio of the delay time to the application time of the DC voltage.

[0143] (Note 17) As described in Note 16, the plasma treatment apparatus, wherein, The control unit measures the reflection time from the start of the supply of the radio frequency power, and determines the time exceeding the reflection time as the delay time.

[0144] (Note 18) As described in Note 16 or 17, in which, The control unit measures the potential of the edge ring and determines the delay time based on the potential of the edge ring.

[0145] (Note 19) A plasma treatment method involves applying plasma treatment to a substrate using a plasma treatment apparatus. The plasma processing device includes: Processing room; A substrate support is disposed in the processing chamber. The substrate support includes a base, an electrostatic chuck on the base, and an edge ring configured to surround the substrate placed on the electrostatic chuck. Radio frequency power supply, providing radio frequency power for generating plasma from the gas inside the processing chamber; A DC power supply applies a negative DC voltage to the edge ring; An RF filter, electrically connected to the edge ring; and A waveform control element controls the waveform of the DC voltage; In this plasma processing method, the constant of the waveform control element is adjusted to control the time when the DC voltage reaches the desired value.

[0146] The embodiments disclosed herein are for illustrative purposes only and are not intended to limit the invention. The aforementioned embodiments may also be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended patent application.

[0147] 1: Plasma treatment device 10: Processing Room 11: Platform 12: Lower electrode 13: Electrostatic chuck 14: Edge ring 15a:Flow path 15b:Inlet piping 15c:Exit flow path 16a: First electrode 16b: Second electrode 17: Supporting components 20: Spray head 21: Electrode plate 21a: Gas ejection outlet 22: Electrode support 22a: Gas diffusion chamber 22b: Gas flow hole 22c: Gas inlet port 23: Insulating shielding components 30: Gas supply source group 31: Flow control machine group 32: Valve Group 33: Gas supply pipe 40: baffle 41: Exhaust port 42: Exhaust device 43:Move out entrance 44: Gate valve 50: First RF power supply 51: Second RF power supply 52: Matcher 53: First Matching Circuit 54: Second Matching Circuit 60: DC power supply 61: Switching Unit 62: First RF Filter 63: Second RF Filter 64: Path 65: Pulse Generation Unit 66: DC power supply circuit 66a, 67a: Switching elements 66b, 67b: Damping elements 67: Electrostatic discharge circuit 70: Waveform control element 71: Non-waveform control element 72: High-potential side path 73: Low-potential side path 74: Switching Circuit 80: Pulse signal source 100: Control Department W: Wafer DC: Direct current voltage DC1: First DC voltage DC2: Second DC voltage RF: Radio Frequency Power RF1: First Radio Frequency Power RF2: Second Radio Frequency Power S: Processing space SH: Sheath θ1, θ2, θ3: Inclination angles

Claims

1. A plasma processing apparatus for performing plasma processing on a substrate, comprising: a processing chamber; a substrate support disposed within the processing chamber, the substrate support including a base, an electrostatic chuck on the base, and an edge ring disposed surrounding a substrate mounted on the electrostatic chuck; an radio frequency power supply for supplying radio frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; a waveform control element for controlling the waveform of the DC voltage; and a control unit for adjusting a constant of the waveform control element and controlling the time from the start of applying the DC voltage until the DC voltage reaches a desired value, so that the potential difference between the bias voltage generated on the substrate by the radio frequency power and the DC voltage converges within a predetermined threshold.

2. The plasma treatment apparatus as claimed in claim 1, wherein, It further includes an RF filter electrically connected to the edge ring; and a waveform control element disposed within the RF filter.

3. The plasma treatment apparatus as claimed in claim 1, wherein, The waveform control element is located within the DC power supply.

4. The plasma treatment apparatus as described in claim 3, wherein, The DC power supply includes a pulse generating section that generates pulses of the DC voltage; the waveform control element is disposed closer to the edge ring side than the pulse generating section.

5. The plasma treatment apparatus as claimed in claim 1, wherein, It further includes: a DC power supply circuit for applying the DC voltage to the edge ring; a power removal circuit for removing power from the edge ring; and a switching unit for switching the connection of the edge ring to the DC power supply circuit or the power removal circuit; and a waveform control element disposed within the switching unit.

6. The plasma treatment apparatus as claimed in claim 1, wherein, The waveform control element is positioned in the path between the DC power supply and the RF filter.

7. The plasma treatment apparatus as claimed in claim 1, wherein, The device includes a high-potential side path connecting the DC power supply to the edge ring and a low-potential side path connecting the edge ring to ground; the waveform control element includes any one or more of the following: a capacitive element, an inductive element, a resistive element, an electromagnetic energy converter, and a transmission line disposed on the high-potential side path or disposed between the high-potential side path and the low-potential side path.

8. The plasma treatment apparatus as claimed in claim 1, wherein, It further includes non-waveform control elements that have functions other than controlling the waveform of the DC voltage; the other functions include at least one function selected from the group consisting of capacitive elements, inductive elements, resistive elements, electromagnetic energy converters and transmission lines.

9. The plasma treatment apparatus as claimed in claim 1, wherein, The waveform control element has functions other than controlling the waveform of the DC voltage; the other functions include at least one function selected from the group consisting of capacitive elements, inductive elements, resistive elements, electromagnetic energy converters and transmission lines.

10. The plasma treatment apparatus as claimed in claim 8, wherein, The non-waveform control element includes a variable element for making the impedance of the RF filter variable.

11. The plasma treatment apparatus as claimed in claim 1, wherein, The constant of this waveform control element can be changed.

12. The plasma treatment apparatus as claimed in claim 1, wherein, The constant of the waveform control element is a fixed value; it includes a plurality of waveform control elements with different constants; and it further includes a switching circuit for switching the plurality of waveform control elements.

13. The plasma treatment apparatus as claimed in claim 1, wherein, The control unit adjusts the constant of the waveform control element to control the waveform of the DC voltage so that the DC voltage is close to the bias voltage.

14. The plasma processing apparatus as claimed in claim 1, wherein, The control unit controls the plasma processing device to perform a process comprising the following steps: (a) starting the supply of radio frequency power, and after a predetermined delay time, starting the application of DC voltage; and (b) adjusting the constant of the waveform control element to control the waveform of the DC voltage and controlling the time for the DC voltage to reach the desired value.

15. The plasma treatment apparatus as claimed in claim 14, wherein, The control unit controls the plasma processing device to perform a process comprising the following steps: (c) stopping the supply of radio frequency power and, after a predetermined delay time, starting to de-energize the edge ring; and (b) adjusting the constant of the waveform control element to control the waveform of the DC voltage and controlling the time for the DC voltage to reach the desired value.

16. The plasma processing apparatus as claimed in claim 14 or 15, wherein, The control unit determines the delay time based on the ratio of the delay time to the application time of the DC voltage.

17. The plasma processing apparatus as claimed in claim 16, wherein, The control unit measures the reflection time from the start of the supply of the radio frequency power, and determines the time exceeding the reflection time as the delay time.

18. The plasma processing apparatus as claimed in claim 16, wherein, The control unit measures the potential of the edge ring and determines the delay time based on the potential of the edge ring.

19. A plasma processing method for performing plasma processing on a substrate using a plasma processing apparatus, the plasma processing apparatus comprising: a processing chamber; a substrate support disposed within the processing chamber, the substrate support including a base, an electrostatic chuck on the base, and an edge ring disposed surrounding a substrate mounted on the electrostatic chuck; an RF power supply for supplying RF power to generate plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; an RF filter electrically connected to the edge ring; and a waveform control element for controlling the waveform of the DC voltage; in the plasma processing method, adjusting a constant of the waveform control element to control the time from the start of applying the DC voltage until the DC voltage reaches a desired value, such that the potential difference between the bias voltage generated on the substrate by the RF power and the DC voltage converges within a predetermined threshold.

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