Digital-to-analog converter and apparatus for transmitting and receiving radio frequency signal

Abstract

This invention provides an apparatus configured to transmit and receive radio frequency (RF) signals. The apparatus includes: a digital-to-analog converter (DAC) configured to convert digital signals into analog signals; a power amplifier configured to amplify the analog signals; and an antenna configured to output the amplified analog signals as RF signals to an external location. The DAC includes: a current element matrix containing a plurality of current elements configured to generate analog signals; a plurality of normal paths configured to control the multiple current elements to be switched on or off based on the digital signals; and a plurality of alternative paths configured to selectively consume power based on the mode of the digital signals.

Description

Technical Field

[0001] The present invention generally relates to a digital-to-analog converter (DAC), and more particularly, to a DAC that converts a digital signal into an analog signal and a device including the DAC. Cross-reference to related applications

[0002] This application is based on and claims the priority of Korean Patent Application No. 10-2021-0117944, filed on September 3, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Background Art

[0003] The output of a DAC included in a device or a transmitter can be up-converted to a higher frequency band using a radio frequency (RF) generator and a mixer, and then transmitted to the outside as an RF signal via a power amplifier and an antenna. Recently, a direct RF synthesis architecture without an RF generator and a mixer has been used. In order to cover RF signals corresponding to a high frequency band, a DAC using a direct RF synthesis architecture is required to maintain high linearity at a high operating frequency during operation.

Summary of the Invention

[0004] Provided is a digital-to-analog converter (DAC) and a device including the digital-to-analog converter for ensuring high linearity while operating at a high frequency to generate a radio frequency (RF) signal.

[0005] Additional aspects will be set forth in part in the following description and in part will be apparent from the description, or may be learned by practice of the presented embodiments.

[0006] According to an aspect of the present disclosure, a device configured to transmit and receive RF signals may include: a DAC configured to convert a digital signal into an analog signal; a power amplifier configured to amplify the analog signal; and an antenna configured to output the amplified analog signal as an RF signal to the outside. The DAC includes: a current cell matrix including a plurality of current cells configured to generate an analog signal; a plurality of normal paths configured to control the plurality of current cells to be turned on or off based on a digital signal; and a plurality of alternative paths configured to selectively consume power based on a pattern of the digital signal.

[0007] According to an aspect of the present disclosure, a DAC configured to convert a digital signal including a plurality of digital data segments into an analog signal may include: a data decoder configured to decode an n-bit digital data into a plurality of digital data segments based on a thermometer code, where n is an integer of at least 2; a current cell matrix including a plurality of current cells configured to generate an analog signal; a first alternative path including a first latch circuit configured to generate a bistable trigger in a first dummy data; a first normal path including a second latch circuit configured to control turning on or off a first current cell among the plurality of current cells; and a first path selector configured to control at least one of the first alternative path and the first normal path based on a pattern of a first digital data among the plurality of digital data segments.

[0008] According to an aspect of the present disclosure, a DAC configured to convert a digital signal including a plurality of digital data segments into an analog signal may include: a current cell matrix including a plurality of current cells configured to generate an analog signal; a plurality of normal paths connected to the plurality of current cells and configured to control turning on or off the plurality of current cells based on the plurality of digital data segments; and a plurality of alternative paths configured to selectively perform internal bistable triggering on a plurality of dummy data segments based on a pattern of the plurality of digital data segments.

Embodiments

[0010] FIG. 1 is a diagram of a device 5 according to an embodiment.

[0011] The following description is given based on the fact that the device 5 in FIG. 1 is a communication device, which can support fifth-generation (5G) communication, long-term evolution (LTE) communication, code division multiple access (CDMA) communication, global system for mobile communication (GSM) communication, wireless local area network (WLAN) communication, or next-generation communication. However, this is only an example, and the embodiments are not limited thereto. For example, the device 5 may include at least one selected from the following: smart phone, tablet personal computer (PC), mobile phone, video phone, e-book reader, desktop PC, laptop PC, mini notebook computer, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, mobile medical device, camera, and wearable device (e.g., head-mounted device (HMD), such as electronic glasses, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smart watch).

[0012] According to some embodiments, the device 5 may correspond to a smart home appliance having an image display function. For example, the smart home appliance may include at least one selected from the following: television (TV), digital video disc (DVD) player, audio player, refrigerator, air conditioner, vacuum cleaner, oven, microwave oven, washing machine, air cleaner, set-top box, TV box (e.g., Samsung HomeSyncTM, Apple TVTM, or Google TVTM), game console, electronic dictionary, electronic key, camcorder, and electronic photo frame.

[0013] According to some embodiments, device 5 may include at least one selected from the following: various medical devices (e.g., magnetic resonance angiography (MRA) devices, magnetic resonance imaging (MRI) devices, computed tomography (CT) scanners, imaging machines, and spectrometers), navigation devices, global positioning system (GPS) receivers, event data recorders (EDRs), flight data recorders (FDRs), automotive infotainment devices, electronic equipment for ships (e.g., navigation equipment for ships and gyrocompasses), avionics, safety equipment, automotive head units, industrial robots, domestic robots, automatic teller's machines (ATMs), and point-of-sale (POS) systems.

[0014] According to some embodiments, device 5 may include at least one of the following: furniture having an image display function, a part of a building or structure having an image display function, an electronic board, an electronic signature receiving device, a projector, and various measuring instruments (e.g., water meters, electricity meters, gas meters, and radio wave measuring devices).

[0015] Referring to FIG. 1, device 5 may include a transmitter 10, a receiver 20, and a processor 30. The transmitter 10 may transmit a radio frequency (RF) signal to a base station or another device via a transmission channel 7. The receiver 20 may receive an RF signal from a base station or another device via a reception channel 8.

[0016] The processor 30 may generally control various operations of device 5 and process data required for the operations. The processor 30 may include a baseband processor. For example, the processor 30 may provide a digital signal to the transmitter 10 or receive a digital signal from the receiver 20.

[0017] In an example embodiment, the transmitter 10 may include a digital-to-analog converter (DAC) 12 that converts a digital signal received from the processor 30 into an analog signal. In an example embodiment, the transmitter 10 may have a mixerless direct RF synthesis architecture, and thus, the DAC 12 may generate an analog signal corresponding to the band of the RF signal output from the transmitter 10. In other words, the DAC 12 may generate a broadband analog signal from a low frequency band to a high frequency band (e.g., a millimeter wave band). However, this is only an example, and the embodiment may also be applied to an up-conversion architecture and an intermediate frequency architecture.

[0018] In an example embodiment, the DAC 12 may include a plurality of alternative paths 14. The alternative paths 14 may selectively perform internal bistate triggering during the digital-to-analog conversion operation of the DAC 12, such that the power consumption is uniform during the operation of the DAC 12. The DAC 12 may further include a current cell matrix and a plurality of normal paths, the current cell matrix including a plurality of current cells for generating an analog signal, the plurality of normal paths being connected to the current cells and configured to control the current cells to be turned on or off based on a plurality of digital data segments. The digital signal received by the DAC 12 from the processor 30 may include digital data segments.

[0019] In an example embodiment, the alternative paths 14 may selectively perform internal bistate triggering on a plurality of dummy data segments generated in the alternative paths 14 based on the pattern of each of the digital data segments. The pattern of the digital data may refer to the level change of the digital data. A detailed description thereof is given below.

[0020] In an example embodiment, the activation of the alternative paths 14 may be started or canceled according to the operation mode of the device 5. For example, the alternative paths 14 may be activated when the device 5 is operating in a low power mode and deactivated when the device 5 is operating in a normal mode. The operation mode of the device 5 may be interpreted as the operation mode of the DAC 12. In some embodiments, the activation of the alternative paths 14 may be started or canceled according to the communication state of the device 5. For example, when the communication state of the device 5 is greater than or equal to a threshold value and thus good, the activation of the alternative paths 14 may be canceled to reduce power consumption instead of ensuring the high linearity of the DAC 12. When the communication state is less than the threshold value and thus poor, the alternative paths 14 may be activated to ensure the high linearity of the DAC 12 instead of the low power consumption of the DAC 12.

[0021] The transmitter 10 and the receiver 20 may be implemented in an RF integrated circuit and may include amplifiers, oscillators, filters, frequency dividers, or the like that may be required to transmit or receive RF signals.

[0022] According to an example embodiment, the DAC 12 may consume power evenly via an alternative path 14 that selectively performs internal bistatic triggering during a conversion operation. Thus, enhanced linearity is ensured, and accordingly, the performance of the DAC 12 can be improved.

[0023] FIG. 2A and FIG. 2B are diagrams of a DAC according to an embodiment.

[0024] Referring to FIG. 2A, the DAC 100a may include a data decoder 110a, a path array 120a, and a current cell matrix 130a. In an example embodiment, the data decoder 110a may convert n-bit digital data received from the processor 30 (FIG. 1) (where "n" is an integer of at least 2) into some digital data that can be processed by the DAC 100a. For example, the data decoder 110a may convert the n-bit digital data into digital data based on a thermometer code. In some embodiments, the data decoder 110a may be included in the processor 30 (FIG. 1) and omitted from the DAC 100a. The data decoder 110a may provide a plurality of decoded digital data segments to the path array 120a.

[0025] In an example embodiment, the path array 120a may include a first path group 120_1a to an nth path group 120_na. Hereinafter, a description of the configuration of the first path group 120_1a is mainly given, and the description may also be applied to other path groups, that is, the second path group 120_2a to the nth path group 120_na. The current cell matrix 130a may include a plurality of current cells, and the plurality of current cells are controlled to be turned on or off to generate an analog signal. Among the current cells, the first current cell 131a may receive a cell control signal CCS from the first path group 120_1a, and includes a switch SW, a current source CS, and an output node ND. The first current cell 131a may output a current corresponding to the current source CS via the output node ND in response to the cell control signal CCS. The configuration of the first current cell 131a may also be applied to other current cells of the current cell matrix 130a, and each of the other current cells may receive a cell control signal from a corresponding one of the other path groups (that is, the second path group 120_2a to the nth path group 120_na).

[0026] In an exemplary embodiment, the first path group 120_1a may include a first normal path 120_11a, a first alternative path 120_21a, and a first path selector 120_31a. The first alternative path 120_21a may include a first latch circuit that generates a bistable trigger in the first dummy data. The first normal path 120_11a may include a second latch circuit that receives and outputs normal data corresponding to the cell control signal CCS of the first current unit 131a. The latch circuit included in the alternative path may be defined as the first latch circuit, and the latch circuit included in the normal path may be defined as the second latch circuit. In addition, the normal data sent to the second latch circuit may correspond to the digital data provided by the data decoder 110a. In an exemplary embodiment, the first latch circuit included in the first alternative path 120_21a may include a floating output terminal, and the second latch circuit included in the first normal path 120_11a may include an output terminal that outputs the cell control signal to the first current unit 131a. The normal path may refer to a circuit that generates a cell control signal provided to the current unit, and the alternative path may refer to a circuit that selectively performs an internal bistable trigger corresponding to the operation of the normal path.

[0027] In an exemplary embodiment, the first path selector 120_31a may control at least one of the first normal path 120_11a and the first alternative path 120_21a based on the pattern of the first digital data provided by the data decoder 110a. The level of the normal data of the second latch circuit included in the first normal path 120_11a may be maintained or changed according to the level of the first digital data provided by the data decoder 110a. The level of a data or signal may mean the value of the data or signal, and may be used interchangeably with the value of the data or signal.

[0028] Among the multiple normal data segments of the respective second latches of the normal paths 120_11a to 120_1na sent to the path array 120a, the number of normal data segments with a changed level may vary with the multiple digital data segments provided by the data decoder 110a, and thus, the power consumed by the normal paths 120_11a to 120_1na may depend on the digital data segments. The irregular change in the power consumption of the normal paths 120_11a to 120_1na may cause degradation of the linearity of the DAC 100a and parasitic resistance between the power supply and the ground of the DAC 100a. According to an exemplary embodiment, to eliminate this factor, the multiple alternative paths 120_21a to 120_2na may selectively perform an internal bistable trigger in response to the change in the power consumption of the normal paths 120_11a to 120_1na, thereby allowing the power consumption of the path array 120a to be uniform.

[0029] In an exemplary embodiment, when the current level of the first digital data is the same as the previous level of the first digital data, the first path selector 120_31a can control the first alternative path 120_21a such that the dummy data sent to the first latch circuit toggles. For example, when the current level of the first digital data is different from the previous level of the first digital data, the first path selector 120_31a can control the first normal path 120_11a such that the normal data sent to the second latch circuit toggles.

[0030] In an exemplary embodiment, the first path selector 120_31a can control the power consumption of the first path group 120_1a to be uniform by allowing the dummy data of the first latch circuit sent to the first alternative path 120_21a to toggle when the normal data of the second latch circuit sent to the first normal path 120_11a does not toggle. The operations of the first path selector 120_31a described above can also be applied to other path selectors 120_32a to 120_32n. In some embodiments, the path selector can be referred to as a path controller.

[0031] In an exemplary embodiment, the first path selector 120_31a can activate or deactivate the first alternative path 120_21a according to the operation mode of the DAC 100a. For example, when the DAC 100a operates in a low power mode, the first path selector 120_31a can deactivate the first alternative path 120_21a to reduce the power consumption of the first alternative path 120_21a. In an exemplary embodiment, the first path selector 120_31a can activate or deactivate the first alternative path 120_21a according to the communication state of the device including the DAC 100a. For example, when the communication state (e.g., channel state) is greater than or equal to a threshold value, the first path selector 120_31a can deactivate the first alternative path 120_21a to reduce the power consumption of the first alternative path 120_21a.

[0032] In an exemplary embodiment, the first alternative path 120_21a can include circuits copied from the first normal path 120_11a such that the first alternative path 120_21a has a power consumption as similar as possible to that of the first normal path 120_11a during internal toggling. Specifically, the first alternative path 120_21a can include a buffer circuit and a first latch circuit, the buffer circuit being copied from the buffer circuit of the first normal path 120_11a, and the first latch circuit being copied from the second latch circuit of the first normal path 120_11a. The copied circuits can have characteristics similar to or the same as those of the original circuits, such as the degree of delay or amplification.

[0033] Although, in FIG. 2A, the components of each of the first path group 120_1a to the nth path group 120_na of the path array 120a are shown adjacent to each other, this is merely an example. The normal paths 120_11a to 120_1na may be adjacent to each other, the alternative paths 120_21a to 120_2na may be adjacent to each other, and the path selectors 120_31a to 120_3na may be adjacent to each other.

[0034] In an exemplary embodiment, the data decoder 110a and the path array 120a may be implemented as digital logic, and the current cell matrix 130a may be implemented as analog logic. In some embodiments, the data decoder 110a and the path array 120a may be implemented as analog logic or a combination of digital logic and analog logic.

[0035] Referring to FIG. 2B, unlike the path array 120a in FIG. 2A, the path array 120b may include a first path group 120_1b to an mth path group 120_mb (where "m" is an integer of at least 2) and a (m + 1)th normal path 120_41b to a (m + k)th normal path 120_4kb (where "k" is an integer of at least 2). In other words, the number of normal paths 120_11b to 120_1mb and normal paths 120_41b to 120_4kb included in the path array 120b may be greater than the number of alternative paths 120_21b to 120_2mb.

[0036] According to an exemplary embodiment, the path array 120b may minimize the power consumption of the alternative paths by including a minimum number of alternative paths 120_21b to 120_2mb for ensuring linearity greater than or equal to a threshold value.

[0037] FIG. 3 is a diagram of a DAC 200 according to an embodiment. Although the normal path 210, the alternative path 220, the path selector 230, and the current cell 240 are shown in FIG. 3, the DAC 200 may include additional normal paths, alternative paths, path selectors, and current paths. The following embodiments may be applied to the DAC 200.

[0038] Referring to FIG. 3, the DAC 200 may include a normal path 210, an alternative path 220, a path selector 230, and a current unit 240. The normal path 210 may receive a first clock signal CLK and a current digital data D_c. The alternative path 220 may receive the first clock signal CLK. The alternative path 220 may include a data bistable trigger circuit 222 for internal bistable triggering. The path selector 230 may receive the current digital data D_c, the previous digital data D_p, and a second clock signal CLK_E. The second clock signal CLK_E may be a clock signal leading the first clock signal CLK by a certain phase angle. In other words, the path selector 230 may operate based on the second clock signal CLK_E, and thus control at least one selected from the normal path 210 and the alternative path 220 before generating a unit control signal CCS based on the current digital data D_c. The current digital data D_c and the previous digital data D_p may respectively correspond to the current and previous levels of the digital data.

[0039] In an exemplary embodiment, the path selector 230 may compare the current digital data D_c with the previous digital data D_p based on the second clock signal CLK_E, and generate a first path selection signal PSS1 and a second path selection signal PSS2 based on the comparison result. The path selector 230 may provide the first path selection signal PSS1 to the normal path 210 and provide the second path selection signal PSS2 to the alternative path 220.

[0040] Specifically, when the current digital data D_c is different from the previous digital data D_p, the path selector 230 may generate the first path selection signal PSS1 and provide it to the normal path 210, so that the current digital data D_c is sent to the second latch circuit of the normal path 210, and generate the second path selection signal PSS2 and provide it to the alternative path 220, so that the dummy data of the first latch circuit of the alternative path 220 is not bistable triggered.

[0041] When the current digital data D_c is the same as the previous digital data D_p, the path selector 230 may generate the first path selection signal PSS1 and provide it to the normal path 210, so that the first clock signal CLK is not sent to the second latch circuit of the normal path 210, and generate the second path selection signal PSS2 and provide it to the alternative path 220, so that the dummy data of the first latch circuit of the alternative path 220 is bistable triggered. For example, the data bistable trigger circuit 222 may provide the dummy data bistable triggered based on the second path selection signal PSS2 to the first latch circuit, and the first latch circuit may output the bistable triggered dummy data in response to the first clock signal CLK, thereby performing internal bistable triggering.

[0042] Through the control operation of the path selector 230, the period of the normal data bistable trigger of the second latch circuit of the normal path 210 can be different from the period of the dummy data bistable trigger of the first latch circuit of the alternative path 220. In other words, the alternative path 220 can perform internal bistable triggering during the period when the normal data of the second latch circuit of the normal path 210 does not bistable trigger. The normal path 210 can provide the cell control signal CCS having a value corresponding to the normal data sent to the second latch circuit to the current cell 240.

[0043] FIG. 4 is a flowchart of the operation of the DAC according to an embodiment. For a clear understanding, FIG. 4 is described with reference to FIG. 3.

[0044] Referring to FIG. 4, in operation S100, the path selector 230 can compare the current digital data D_c with the previous digital data D_p. In operation S110, the path selector 230 can determine whether the current digital data D_c is different from the previous digital data D_p. When the response in operation S110 is "yes", in operation S120, the path selector 230 can not select the alternative path 220 and can only control the normal path 210 to perform the operation. In addition, when the response in operation S110 is "no", in operation S130, the path selector 230 can select and control the alternative path 220 to perform internal bistable triggering.

[0045] FIG. 5 is a diagram of the operations of the normal path 210 and the alternative path 220 in FIG. 3 according to an embodiment.

[0046] Referring to FIG. 5, when the DAC 200 receives the digital data DD, the normal path 210 and the alternative path 220 can output the cell control signal CCS and the dummy cell control signal CCS', respectively, in response to the digital data DD. For example, the digital data DD can transition from the low level to the high level at "t11", remain at the high level from "t11" to "t41", and transition from the high level to the low level at "t41". In response to the digital data DD, the normal path 210 can generate the cell control signal CCS, which transitions from the low level to the high level at "t12", remains at the high level from "t12" to "t42", and transitions from the high level to the low level at "t42". The alternative path 220 can generate the dummy cell control signal CCS' that is bistable triggered during the period from "t22" to "t32", where the cell control signal CCS is not bistable triggered. The output terminal of the output dummy cell control signal CCS' of the alternative path 220 can float.

[0047] FIG. 6 is a block diagram of the normal path 210 according to an embodiment.

[0048] Referring to FIG. 6, the normal path 210 may include a data output circuit 212, a clock output circuit 214, and a latch circuit 216. The latch circuit 216 may be referred to as a second latch circuit. The data output circuit 212 may receive digital data DD and a first clock signal CLK, and output a second output data DBB to the latch circuit 216. In an exemplary embodiment, the second output data DBB may be generated by buffering the digital data DD and have a different phase or magnitude from the digital data DD.

[0049] The clock output circuit 214 may receive a first path selection signal PSS1 and a first clock signal CLK, generate a second output clock signal CLKBB from the first clock signal CLK based on the first path selection signal PSS1, and output the second output clock signal CLKBB to the latch circuit 216. In an exemplary embodiment, the second output clock signal CLKBB may be generated by buffering the first clock signal CLK and have a different phase or magnitude from the first clock signal CLK. For example, when the current level of the digital data DD is different from the previous level of the digital data DD, the first path selection signal PSS1 may have a first level (or a first value), and the clock output circuit 214 may generate and output the second output clock signal CLKBB to the latch circuit 216 in response to the first path selection signal PSS1 having the first level. Additionally, when the current level of the digital data DD is the same as the previous level of the digital data DD, the first path selection signal PSS1 may have a second level (or a second value), and the clock output circuit 214 may not output the second output clock signal CLKBB in response to the first path selection signal PSS1 having the second level. In an exemplary embodiment, the clock output circuit 214 may output a signal held at a certain level instead of the second output clock signal CLKBB.

[0050] The normal path 210 of FIG. 6 may include a clock output circuit 214 that selectively provides a second output clock signal CLKBB to the latch circuit 216 based on the first path selection signal PSS1. However, this is merely an example, and the embodiments are not limited thereto. The clock output circuit 214 may be configured to continuously provide the second output clock signal CLKBB to the latch circuit 216 without receiving the first path selection signal PSS1.

[0051] In some embodiments, the data output circuit 212 may provide output data (e.g., the first output data DB in FIG. 9) having a phase opposite to that of the second output data DBB to the latch circuit 216, and the clock output circuit 214 may output an output clock signal (e.g., the first output clock signal CLKB in FIG. 9) having a phase opposite to that of the second output clock signal CLKBB to the latch circuit 216.

[0052] FIG. 7 is a diagram of an alternative path 220 according to an embodiment.

[0053] Referring to FIG. 7, the alternative path 220 may include a data bistable trigger circuit 222, a clock output circuit 224, and a latch circuit 226. The latch circuit 226 may be referred to as a first latch circuit. The data bistable trigger circuit 222 may receive a first clock signal CLK and a second path selection signal PSS2 and output a second output dummy data DBB_A based on the second path selection signal PSS2, and the second output dummy data DBB_A is bistable triggered in response to the first clock signal CLK. For example, when the current level (FIG. 6) of the digital data DD is the same as the previous level of the digital data DD, the second path selection signal PSS2 may have a third level (or third value), and the data bistable trigger circuit 222 may output the second output dummy data DBB_A that is bistable triggered according to the first clock signal CLK in response to the second path selection signal PSS2 having the third level. In addition, when the current level of the digital data DD is different from the previous level of the digital data DD, the second path selection signal PSS2 may have a fourth level (or fourth value), and the data bistable trigger circuit 222 may output the second output dummy data DBB_A maintained at a certain level in response to the second path selection signal PSS2 having the fourth level.

[0054] The clock output circuit 224 may receive the second path selection signal PSS2 and the first clock signal CLK, generate a second dummy clock signal CLKBB_A from the first clock signal CLK based on the second path selection signal PSS2, and output the second dummy clock signal CLKBB_A to the latch circuit 226. In an exemplary embodiment, the second dummy clock signal CLKBB_A may be generated by buffering the first clock signal CLK and have a different phase or magnitude from the first clock signal CLK. For example, when the second path selection signal PSS2 has a third level (or third value), the clock output circuit 224 may generate the second dummy clock signal CLKBB_A in response to the second path selection signal PSS2 and output the second dummy clock signal CLKBB_A to the latch circuit 226. When the second path selection signal PSS2 has a fourth level (or fourth value), the clock output circuit 224 may not output the second dummy clock signal CLKBB_A in response to the second path selection signal PSS2. In some embodiments, the clock output circuit 224 may output a signal maintained at a certain level instead of the second dummy clock signal CLKBB_A.

[0055] As shown in FIG. 7, the data bistable trigger circuit 222 and the clock output circuit 224 of the alternative path 220 can receive the second path selection signal PSS2, and selectively output the second output dummy data DBB_A and the second dummy clock signal CLKBB_A to the latch circuit 226 respectively. However, this is only an example, and the embodiments are not limited thereto. Only one of the data bistable trigger circuit 222 and the clock output circuit 224 can receive the second path selection signal PSS2 and perform a selective output operation based on the second path selection signal PSS2.

[0056] In some embodiments, the data bistable trigger circuit 222 can provide output dummy data (e.g., the first output dummy data DB_A in FIG. 9) having a phase opposite to that of the second output dummy data DBB_A to the latch circuit 226, and the clock output circuit 224 can output a dummy clock signal (e.g., the first dummy clock signal CLKB_A in FIG. 9) having a phase opposite to that of the second dummy clock signal CLKBB_A to the latch circuit 226.

[0057] FIG. 8 is a diagram of a path selector 230 according to an embodiment.

[0058] Referring to FIG. 8, the path selector 230 may include a comparison circuit 232 and a path selection signal generation circuit 234. The comparison circuit 232 can receive the current digital data D_c and the previous digital data D_p, compare the current digital data D_c with the previous digital data D_p, and generate a comparison result signal RS. In other words, the comparison circuit 232 can be used to continuously monitor whether there is a level transition of the digital data. The path selection signal generation circuit 234 can receive the comparison result signal RS and the second clock signal CLK_E. As described above, the phase of the second clock signal CLK_E can lead the phase of the first clock signal CLK (FIGS. 7 and 8), and the path selection signal generation circuit 234 can generate the first path selection signal PSS1 and the second path selection signal PSS2 in response to the second clock signal CLK_E having a leading phase. In an exemplary embodiment, the path selection signal generation circuit 234 can receive an enable / disable control signal EN corresponding to the operation mode of the DAC, and can be enabled or disabled in response to the enable / disable control signal EN. Specifically, when the DAC is in the low power mode, the path selection signal generation circuit 234 can be disabled, and the alternative path can also be disabled so that internal bistable triggering can be avoided. When the communication state of the device including the DAC is greater than or equal to a threshold value, the path selection signal generation circuit 234 can be disabled, and the alternative path can also be disabled.

[0059] FIG. 9 is a diagram of a DAC 300 according to an embodiment.

[0060] Referring to FIG. 9, the DAC 300 may include a normal path 310, an alternative path 320, and a path selector 330. The normal path 310 may include a data output circuit 312, a clock output circuit 314, and a latch circuit 316. The alternative path 320 may include a data bistable trigger circuit 322, a clock output circuit 324, and a latch circuit 326.

[0061] In an exemplary embodiment, the data output circuit 312 may include a first inverter IV1 to a sixth inverter IV6 and a first flip-flop FF1. The first flip-flop FF1 may receive a first clock signal CLK and digital data DD that have passed through the first inverter IV1 and the second inverter IV2. The first flip-flop FF1 may output the digital data DD to the third inverter IV3 at the rising edge of the first clock signal CLK that has passed through the first inverter IV1 and the second inverter IV2. In other words, the first flip-flop FF1 may provide the digital data DD as the current digital data D_c before output to the third inverter IV3 and the digital data DD as the previous digital data D_p to the third inverter IV3 for the path selector 330. The first output data DB generated from the previous digital data D_p that has passed through the third inverter IV3 to the fifth inverter IV5 and the second output data DBB generated from the previous digital data D_p that has passed through the third inverter IV3 to the sixth inverter IV6 may be provided to the latch circuit 316.

[0062] In an exemplary embodiment, the clock output circuit 314 may include a first NAND gate NAND1, a seventh inverter IV7, and an eighth inverter IV8. The first NAND gate NAND1 may receive the first clock signal CLK and a first path selection signal PSS1. The first path selection signal PSS1 may be provided from the path selector 330. The first NAND gate NAND1 may perform a NAND operation on the first path selection signal PSS1 and the first clock signal CLK and output the operation result to the seventh inverter IV7. For example, the first NAND gate NAND1 may output the first clock signal CLK or a signal with a constant level according to the value of the first path selection signal PSS1. The first output clock signal CLKB generated from the operation result of the first NAND gate NAND1 that has passed through the seventh inverter IV7 and the second output clock signal CLKBB generated from the operation result of the first NAND gate NAND1 that has passed through the seventh inverter IV7 and the eighth inverter IV8 may be provided to the latch circuit 316. The latch circuit 316 may generate a cell control signal by changing or maintaining the value of the normal data in response to the first output data DB, the second output data DBB, the first output clock signal CLKB, and the second output clock signal CLKBB.

[0063] In an exemplary embodiment, the data bistable trigger circuit 322 may include a second NAND gate NAND2, a second flip-flop FF2, and ninth to thirteenth inverters IV9 to IV13. The second NAND gate NAND2 may receive a first clock signal CLK and a second path selection signal PSS2. The second path selection signal PSS2 may be provided from a path selector 330. The second NAND gate NAND2 may perform a NAND operation on the second path selection signal PSS2 and the first clock signal CLK and output the operation result to the ninth inverter IV9. For example, the second NAND gate NAND2 may output the first clock signal CLK or a signal with a constant level according to the value of the second path selection signal PSS2. A third clock signal CLK_V generated from the operation result of the second NAND gate NAND2 that has passed through the ninth inverter IV9 may be provided to the second flip-flop FF2. The second flip-flop FF2 may output some data that is bistable triggered in response to the third clock signal CLK_V to the tenth inverter IV10. Some data may pass through the tenth inverter IV10 and the eleventh inverter IV11, and then be provided as dummy data D_A to the twelfth inverter IV12. The twelfth inverter IV12 and the thirteenth inverter IV13 may provide a first output dummy data DBB_A and a second output dummy data DBB_A to the latch circuit 326, respectively.

[0064] In an exemplary embodiment, the clock output circuit 324 may include a third NAND gate NAND3, and fourteenth and fifteenth inverters IV14 and IV15. The third NAND gate NAND3 may receive a first clock signal CLK and a second path selection signal PSS2. The third NAND gate NAND3 may perform a NAND operation on the second path selection signal PSS2 and the first clock signal CLK and output the operation result to the fourteenth inverter IV14. For example, the third NAND gate NAND3 may output the first clock signal CLK or a signal with a constant level according to the value of the second path selection signal PSS2. A first dummy clock signal CLKB_A generated from the operation result of the third NAND gate NAND3 that has passed through the fourteenth inverter IV14 and a second dummy clock signal CLKBB_A generated from the operation result of the third NAND gate NAND3 that has passed through the fourteenth inverter IV14 and the fifteenth inverter IV15 may be provided to the latch circuit 326.

[0065] The latch circuit 326 may generate a dummy cell control signal by changing or maintaining the value of normal data in response to the first output dummy data DBB_A and the second output dummy data DBB_A, and the first dummy clock signal CLKB_A and the second dummy clock signal CLKBB_A.

[0066] In an exemplary embodiment, the path selector 330 may include an XOR gate XOR and a third flip-flop FF3. The XOR gate XOR may receive a current digital data D_c and a previous digital data D_p and perform an XOR operation thereon. The XOR gate XOR may provide an XOR operation result signal (i.e., a comparison result signal RS) to the third flip-flop FF3. The third flip-flop FF3 may receive a second clock signal CLK_E, the phase of the second clock signal CLK_E leading the phase of the first clock signal CLK, and output a first path selection signal PSS1 and a second path selection signal PSS2 in response to a rising edge of the second clock signal CLK_E. For example, the first path selection signal PSS1 may have a phase opposite to that of the second path selection signal PSS2.

[0067] In an exemplary embodiment, when the current digital data D_c is different from the previous digital data D_p, the path selector 330 may output a first path selection signal PSS1 at a high level and a second path selection signal PSS2 at a low level. The clock output circuit 314 of the normal path 310 may provide a first output clock signal CLKB and a second output clock signal CLKBB generated from the first clock signal CLK to the latch circuit 316 in response to the first path selection signal PSS1 at a high level. The clock output circuit 324 of the alternative path 320 may provide a first dummy clock signal CLKB_A and a second dummy clock signal CLKBB_A each having a constant level to the latch circuit 326 in response to the second path selection signal PSS2 at a low level. The data bistable trigger circuit 322 of the alternative path 320 may provide a first output dummy data DB_A and a second output dummy data DBB_A each having a constant level to the latch circuit 326 in response to the second path selection signal PSS2 at a low level. In other words, the alternative path 320 may not perform an internal bistable trigger in response to the second path selection signal PSS2 at a low level.

[0068] In an exemplary embodiment, when the current digital data D_c is the same as the previous digital data D_p, the path selector 330 may output a first path selection signal PSS1 at a low level and a second path selection signal PSS2 at a high level. The clock output circuit 314 of the normal path 310 may provide a first output clock signal CLKB and a second output clock signal CLKBB, each having a constant level, to the latch circuit 316 in response to the first path selection signal PSS1 at a high level. The clock output circuit 324 of the alternative path 320 may provide a first dummy clock signal CLKB_A and a second dummy clock signal CLKBB_A generated from the first clock signal CLK to the latch circuit 326 in response to the second path selection signal PSS2 at a high level. The data bistable trigger circuit 322 of the alternative path 320 may provide a first output dummy data DB_A and a second output dummy data DBB_A that are bistable triggered according to the third clock signal CLK_V to the latch circuit 326 in response to the second path selection signal PSS2 at a high level. In other words, the alternative path 320 may perform internal bistable triggering in response to the second path selection signal PSS2 at a high level.

[0069] In an exemplary embodiment, the alternative path 320 may include a circuit replicated from the normal path 310. For example, the data bistable trigger circuit 322 of the alternative path 320 may be replicated from the data output circuit 312 of the normal path 310. Specifically, the path through which the first clock signal CLK is provided to the second flip-flop FF2 in the data bistable trigger circuit 322 may be the same as or similar to the path through which the first clock signal CLK is provided to the first flip-flop FF1 in the data output circuit 312. In other words, the characteristics (e.g., phase delay) of the second NAND gate NAND2 and the ninth inverter IV9 with respect to the first clock signal CLK may be the same as or similar to the characteristics (e.g., phase delay) of the first inverter IV1 and the second inverter IV2 with respect to the first clock signal CLK. The configuration of the tenth inverter IV10 to the thirteenth inverter IV13 of the data bistable trigger circuit 322 may be the same as or similar to the configuration of the third inverter IV3 to the sixth inverter IV6 of the data output circuit 312. In other words, the phase delay characteristics of the third inverter IV3 to the sixth inverter IV6 may be the same as or similar to the phase delay characteristics of the tenth inverter IV10 to the thirteenth inverter IV13. The first inverter IV1 to the sixth inverter IV6 of the data output circuit 312 may be referred to as the first buffer circuit of the data output circuit 312. The second NAND gate NAND2 and the ninth inverter IV9 to the thirteenth inverter IV13 of the data bistable trigger circuit 322 may be referred to as the second buffer circuit of the data bistable trigger circuit 322. The second buffer circuit may be replicated from the first buffer circuit.

[0070] For example, the clock output circuit 324 that replaces the path 320 can be replicated from the clock output circuit 314 of the normal path 310. Specifically, the path through which the first clock signal CLK is provided to the latch circuit 326 in the clock output circuit 324 of the alternative path 320 can be the same as or similar to the path through which the first clock signal CLK is provided to the latch circuit 316 in the clock output circuit 310 of the normal path 310. In other words, the characteristics (e.g., phase delay) of the third NAND gate NAND3, the fourteenth inverter IV14, and the fifteenth inverter IV15 with respect to the first clock signal CLK can be the same as or similar to the characteristics (e.g., phase delay) of the first NAND gate NAND1, the seventh inverter IV7, and the eighth inverter IV8 with respect to the first clock signal CLK.

[0071] The DAC 300 in FIG. 9 is an example, and the embodiments are not limited thereto. Various structures that allow the alternative path 320 to be selectively internally bistable triggered according to the pattern of the digital data DD can be applied to the DAC 300.

[0072] Although in FIG. 9 it is shown that the latch circuit 316 of the normal path 310 receives the first output data DB, the second output data DBB, the first output clock signal CLKB, and the second output clock signal CLKBB, the latch circuit 316 can receive one of the first output data DB and the second output data DBB and one of the first output clock signal CLKB and the second output clock signal CLKBB.

[0073] Although in FIG. 9 it is shown that the latch circuit 326 of the alternative path 320 receives the first output dummy data DB_A, the second output dummy data DBB_A, the first dummy clock signal CLKB_A, and the second dummy clock signal CLKBB_A, the latch circuit 326 can receive one of the first output dummy data DB_A and the second output dummy data DBB_A and one of the first dummy clock signal CLKB_A and the second dummy clock signal CLKBB_A.

[0074] FIG. 10A is a diagram of a DAC 400 according to an embodiment. FIG. 10B is a diagram of the DAC 400 of FIG. 10A according to an embodiment.

[0075] Referring to FIG. 10A, the DAC 400 may include a normal path 410, an alternative path 420, and a path selector 430. The normal path 410 may receive a first clock signal CLK and current digital data D_c. The alternative path 420 may receive the first clock signal CLK. The alternative path 420 may include a data bistable trigger circuit 422 for internal bistable triggering. The path selector 430 may receive current digital data D_c, previous digital data D_p, and a second clock signal CLK_E.

[0076] In an exemplary embodiment, the path selector 430 may compare the current digital data D_c with the previous digital data D_p based on the second clock signal CLK_E, and generate a bistable trigger control signal CS_DTC based on the comparison result. The path selector 430 may provide the bistable trigger control signal CS_DTC only to the alternative path 420. The path selector 430 may use the bistable trigger control signal CS_DTC to control the selective operation of the data bistable trigger circuit 422.

[0077] Further referring to FIG. 10B, the DAC 400 may include a normal path 410, an alternative path 420, and a path selector 430. The following focuses on describing the differences between the DAC 400 and the DAC 300 of FIG. 9. Compared with the DAC 300 of FIG. 9, the clock output circuit 414 of the normal path 410 may not include the first NAND gate NAND1, and the first clock signal CLK may be directly provided to the seventh inverter IV7. Therefore, the clock output circuit 414 may continuously provide a first output clock signal CLKB and a second output clock signal CLKBB generated from the first clock signal CLK to the latch circuit 416. Compared with the DAC 300 of FIG. 9, the clock output circuit 424 may not include the third NAND gate NAND3, and the first clock signal CLK may be directly provided to the fourteenth inverter IV14. Therefore, the clock output circuit 424 may continuously provide a first dummy clock signal CLKB_A and a second dummy clock signal CLKBB_A generated from the first clock signal CLK to the latch circuit 426.

[0078] Compared with the DAC 300 of FIG. 9, the third flip-flop FF3' of the path selector 430 may provide a signal with a phase opposite to that of the comparison result signal RS to the data bistable trigger circuit 422, such as the bistable trigger control signal CS_DTC at the rising edge of the second clock signal CLK_E.

[0079] In summary, in the DAC 400 of FIG. 10B, the clock signal generated from the first clock signal CLK can be continuously provided to the latch circuit 416 and the latch circuit 426, and the internal bistable trigger of the alternative path 420 according to the exemplary embodiment can be controlled using the bistable trigger control signal CS_DTC.

[0080] FIG. 11 is a flowchart of the operation of a DAC according to an embodiment.

[0081] Referring to FIG. 11, in operation S200, the DAC can switch to an operation mode according to the state of the device including the DAC (e.g., battery state or communication state). In operation S210, the DAC can determine whether an operation mode is a low-power mode. When the response in operation S210 is "yes", in operation S220, the DAC can cancel the activation of the alternative path. In addition, when the response in operation S210 is "no", in operation S230, the DAC can activate the alternative path.

[0082] In some embodiments, the DAC can cancel the activation of the alternative path when the communication state of the device is at least a threshold value and thus good, and activate the alternative path when the communication state of the device is less than the threshold value and thus poor. The DAC can comprehensively consider the communication state and operation mode of the device to activate or cancel the activation of the alternative path.

[0083] FIG. 12 is a diagram of a DAC 500 according to an embodiment.

[0084] Referring to FIG. 12, the DAC 500 can include a row decoder 510, a row path array 520, a column decoder 530, a column path array 540, and a current cell matrix 550. The row decoder 510 can receive and decode multiple row digital data DD_col segments based on thermometer codes, and provide the multiple decoded row digital data segments to the row path array 520. The row path array 520 can include multiple alternative paths 522 according to the exemplary embodiments described above with reference to FIGS. 1 to 11. The row path array 520 can provide row cell control signals for controlling the current cells of the current cell matrix 550 to the current cell matrix 550. The column decoder 530 can receive and decode multiple column digital data DD_row segments based on thermometer codes, and provide the multiple decoded column digital data segments to the column path array 540. The column path array 540 can include multiple alternative paths 542 according to the exemplary embodiments described above with reference to FIGS. 1 to 11. The column path array 540 can provide column cell control signals for controlling the current cells of the current cell matrix 550 to the current cell matrix 550. Based on the row cell control signal and the column cell control signal, the current cell matrix 550 can output currents with various magnitudes, and the currents can be used to generate an analog signal.

[0085] FIG. 13 is a diagram of an electronic device 1000 according to an embodiment.

[0086] Referring to FIG. 13, the electronic device 1000 may include an application processor (AP) 1010, a transceiver 1020, a memory 1030, a display 1040, an input / output (I / O) device 1050, and a sensor 1060.

[0087] The electronic device 1000 may communicate with the outside world via the transceiver 1020. For example, the transceiver 1020 may include a WLAN communication interface, such as a local area network (LAN) interface, Bluetooth, Wireless Fidelity (WiFi), or ZigBee, or a modem communication interface that can be connected to a mobile cellular network, such as a power line communication (PLC) network, a third-generation (3G) network, an LTE network, a 5G network, a new radio (NR) network, or a next-generation communication network. The transceiver 1020 may include a DAC according to the embodiments described above.

[0088] The AP 1010 may generally control the operation of the electronic device 1000 and the operation of the components of the electronic device 1000. The AP 1010 may perform various operations. According to some embodiments, the AP 1010 may include a single-core processor or a multi-core processor.

[0089] The display 1040 may display internal status information of the electronic device 1000. The display 1040 may include a touch sensor. The display 1040 may include an input or output function and an exterior for a user interface. The user may control the electronic device 1000 via the touch sensor and the user interface.

[0090] The I / O device 1050 may include an input unit such as a touchpad, a keypad, or an input button, and an output unit such as a display or a speaker. The memory 1030 may store instruction codes, control data, or user data for controlling the electronic device 1000. The memory 1030 may include at least one selected from a volatile memory or a non-volatile memory.

[0091] The sensor 1060 may include an image sensor that senses an image. The sensor 1060 may be connected to the AP 1010, generate image information, and provide it to the AP 1010. The sensor 1060 may include a biometric sensor that senses biometric information. The sensor 1060 may include a lighting sensor, a sound sensor, an acceleration sensor, or the like.

[0092] The electronic device 1000 may have a battery embedded therein for internal power supply or further include a power supply that receives external power. The electronic device 1000 may further include a storage device. The storage device may include non-volatile media such as a hard disk drive (HDD), a solid state disk (SSD), an embedded multimedia card (eMMC), or a universal flash storage (UFS). The storage device may store user information provided via the I / O device 1050 and sensing information collected via the sensor 1060.

[0093] At least some of the components of the electronic device 1000 (e.g., the AP 1010, the transceiver 1020, the memory 1030, the display 1040, the I / O device 1050, and the sensor 1060) may include a DAC for digital-to-analog conversion, and embodiments may be applied to the DAC.

[0094] FIG. 14 is a diagram illustrating a communication device including a DAC according to an embodiment.

[0095] Referring to FIG. 14, the home gadget 2100, the home appliance 2120, the entertainment device 2140, and the access point 2200 may each include a DAC that performs digital-to-analog conversion according to an embodiment. In some embodiments, the home gadget 2100, the home appliance 2120, the entertainment device 2140, and the access point 2200 may constitute an Internet of Thing (IoT) network. The communication device shown in FIG. 14 is only an example, and the DAC according to the example embodiment may also be included in a communication device different from the communication device shown in FIG. 14.

[0096] Although the inventive concept has been specifically illustrated and described with reference to its embodiments, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the following claims.

Brief Description of the Drawings

[0009] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a diagram of an apparatus according to an embodiment. FIGS. 2A and 2B are diagrams of a digital-to-analog converter (DAC) according to an embodiment. FIG. 3 is a diagram of a DAC according to an embodiment. FIG. 4 is a flowchart of the operation of a DAC according to an embodiment. FIG. 5 is a diagram of the operation of a normal path and an alternative path in FIG. 3 according to an embodiment. FIG. 6 is a diagram of a normal path according to an embodiment. FIG. 7 is a diagram of an alternative path according to an embodiment. FIG. 8 is a diagram of a path selector according to an embodiment. FIG. 9 is a diagram of a DAC according to an embodiment. FIG. 10A is a diagram of a DAC according to an embodiment. FIG. 10B is a detailed block diagram of the DAC of FIG. 10A according to an embodiment. FIG. 11 is a flowchart of the operation of a DAC according to an embodiment. FIG. 12 is a diagram of a DAC according to an embodiment. FIG. 13 is a diagram of an electronic device according to an embodiment. FIG. 14 is a diagram showing a communication device including a DAC according to an embodiment.

Claims

1. An apparatus configured to transmit and receive radio frequency (RF) signals, the apparatus comprising: A digital-to-analog converter (DAC) is configured to convert digital signals into analog signals; a power amplifier is configured to amplify the analog signals; The digital-to-analog converter includes: an antenna configured to output the amplified analog signal as the radio frequency signal to the outside; a current unit matrix including a plurality of current units configured to generate the analog signal; a plurality of normal paths configured to control the multiple current units to be turned on or off based on the digital signal; and a plurality of alternative paths configured to selectively consume power based on the mode of the digital signal, wherein the digital signal comprises a plurality of digital data segments; each of the plurality of alternative paths includes: a first latch circuit; and a data dual-state trigger circuit configured to selectively output dummy data to the first latch circuit, the dummy data being dual-state triggered based on a transition or non-transition of a digital data segment corresponding to the dummy data among the plurality of digital data segments; and each of the plurality of alternative paths further includes: a first clock output circuit configured to selectively output a dummy clock signal to the first latch circuit based on the transition or non-transition of the digital data segments. Each of the plurality of normal paths includes: a second latch circuit; and a data output circuit configured to output the digital data segments of the plurality of digital data segments to the second latch circuit, wherein the first latch circuit is copied from the second latch circuit such that each of the plurality of alternative paths has power consumption similar to that of each of the plurality of normal paths during dual-state triggering, and wherein the data dual-state triggering circuit is copied from the data output circuit.

2. The apparatus of claim 1, wherein the dual-state triggering circuit is further configured to: output the dual-state triggered dummy data to the first latch circuit based on the current level of the digital data segment being equal to the previous level of the digital data segment; and output the dummy data at a constant level to the first latch circuit based on the current level of the digital data segment being different from the previous level of the digital data segment.

3. The apparatus of claim 1, wherein at least one output terminal of the first latch circuit is in a floating state.

4. The apparatus as claimed in claim 1, wherein the plurality of normal paths correspond to the plurality of alternative paths respectively.

5. The apparatus as claimed in claim 1, wherein the number of the plurality of normal paths is greater than the number of the plurality of alternative paths.

6. The apparatus as claimed in claim 1, wherein the plurality of alternative paths are further configured to deactivate startup in the low-power mode of the apparatus.

7. The apparatus of claim 1, wherein the apparatus is implemented in a direct radio frequency synthesis architecture, and wherein the digital-to-analog converter is further configured to operate based on a clock signal having a frequency corresponding to the frequency band of the radio frequency signal.

8. The apparatus of claim 1, wherein a first cycle of data dual-state triggering sent to a first latch circuit is different from a second cycle of data dual-state triggering sent to a second latch circuit, wherein the first latch circuit is included in each of the plurality of alternative paths, and wherein the second latch circuit is included in each of the plurality of normal paths.

9. The apparatus of claim 1, wherein the digital-to-analog converter further includes a data decoder configured to decode the initial digital signal into the digital signal in thermometric code format.

10. A digital-to-analog converter (DAC) configured to convert a digital signal comprising multiple digital data segments into an analog signal, the digital-to-analog converter comprising: A data decoder, configured to decode n-ary digital data into a plurality of digital data segments based on thermometer codes, where n is an integer of at least 2; a current unit matrix, comprising a plurality of current units configured to generate the analog signal; a first alternative path, comprising a first latch circuit and a first clock output circuit configured to generate dual-state triggering in the first dummy data, the first clock output circuit being configured to selectively output the dummy clock signal to the first latch circuit based on the transition or non-transition of the plurality of digital data segments; a first normal path, comprising a second latch circuit configured to control the first current unit among the plurality of current units to be turned on or off, and a data output circuit configured to output the digital data segments among the plurality of digital data segments to the second latch circuit. The first latch circuit is copied from the second latch circuit, such that the first alternative path has power consumption similar to the first normal path during dual-state triggering, and the data dual-state triggering circuit is copied from the data output circuit; and a first path selector is configured to control at least one of the first alternative path and the first normal path based on a pattern of the first digital data among the plurality of digital data segments.

11. The digital-to-analog converter of claim 10, wherein the first path selector is further configured to control the first alternative path to allow the first dummy data to be dual-state triggered based on the current level of the first digital data, which is equal to the previous level of the first digital data, the first dummy data having been sent to the first latch circuit, and to control the first normal path to allow normal data to be dual-state triggered based on the current level of the first digital data, which is different from the previous level of the first digital data, the normal data being sent to the second latch circuit and provided to the first current unit as a cell control signal.

12. The digital-to-analog converter as described in claim 10, further comprising: The second alternative path includes a third latch circuit configured to generate a dual-state trigger in the second dummy data; The second normal path includes a fourth latch circuit configured to control the on or off of the second current unit among the plurality of current units. And a second path selector, configured to control at least one of the second alternative path and the second normal path based on a pattern of the second digital data among the plurality of digital data segments.

13. The digital-to-analog converter as claimed in claim 10 further includes a second normal path configured to control the second current unit among the plurality of current units to be turned on or off based on a pattern of the second digital data among the plurality of digital data segments.

14. The digital-to-analog converter as claimed in claim 10, wherein the first path selector comprises: The comparator circuit is configured to compare the current level of the first digital data with the previous level of the first digital data and generate a comparison result signal. And a flip-flop, configured to generate a first path selection signal and a second path selection signal from the comparison result signal, and to provide the first path selection signal to the first alternative path and the second path selection signal to the first normal path.

15. A digital-to-analog converter (DAC) configured to convert a digital signal comprising multiple digital data segments into an analog signal, the digital-to-analog converter comprising: A current element matrix comprising multiple current elements configured to generate the analog signal; Multiple normal paths are connected to the multiple current units and configured to control the on / off switching of the multiple current units based on the multiple digital data segments; and multiple alternative paths are configured to selectively internally trigger multiple dummy data segments based on the pattern of the multiple digital data segments, wherein each of the multiple alternative paths further includes: a first clock output circuit configured to selectively output a dummy clock signal to a first latch circuit based on the transition or non-transition of the digital data segments, wherein each of the multiple normal paths includes: a second latch circuit; and a data output circuit configured to output the digital data segments of the multiple digital data segments to the second latch circuit, wherein the first latch circuit is copied from the second latch circuit such that each of the multiple alternative paths has power consumption similar to that of each of the multiple normal paths during dual-state triggering, and wherein the data dual-state triggering circuit is copied from the data output circuit.

16. The digital-to-analog converter of claim 15, wherein each of the plurality of alternative paths is configured such that a first cycle of dummy data dual-state triggering of each of the plurality of alternative paths is different from a second cycle of normal data dual-state triggering of a normal path, the normal path corresponding to each of the plurality of alternative paths among the plurality of normal paths, and the normal data controls the on or off of the plurality of current units.

17. The digital-to-analog converter of claim 15, wherein each of the plurality of alternative paths is configured to perform the internal dual-state triggering based on the current level of the digital data corresponding to each of the plurality of alternative paths in the plurality of digital data segments being equal to the previous level of the digital data.

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