Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The second semiconductor structure is disposed along a first direction on one side of the first semiconductor structure. The first semiconductor structure includes a first electrode, a second electrode located on one side of the first electrode, and a resistive switching film between the first electrode and the second electrode. The first electrode, the resistive switching film, and the second electrode are disposed along the first direction. The second semiconductor structure includes a first via element and a first metal layer. The first metal layer is disposed along a second direction on the first via element and electrically connected to the first via element. The first direction is perpendicular to the second direction. The upper surfaces of the first electrode, the second electrode, the resistive switching film, and the first metal layer are coplanar.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and in particular to a semiconductor device including a resistance conversion film and a method for forming the same. Prior Art

[0002] Resistive Random Access Memory (RRAM) is a highly anticipated next-generation non-volatile memory. RRAM stores data in a resistive switching film. By applying an appropriate voltage, the film can switch between a high resistance state and a low resistance state, storing digital information. However, the development of RRAM still faces several key challenges, among which is how to reduce the critical dimension of RRAM.

[0003] Therefore, there is a need for an improved semiconductor device including a resistance random access memory (RRAM) having a smaller critical dimension. Summary of the Invention

[0004] According to one embodiment, a semiconductor device is provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The second semiconductor structure is disposed on one side of the first semiconductor structure along a first direction. The first semiconductor structure includes a first electrode, a second electrode located on one side of the first electrode, and a resistance conversion film interposed between the first and second electrodes. The first electrode, the resistance conversion film, and the second electrode are disposed along the first direction. The second semiconductor structure includes a first via element and a first metal layer. The first metal layer is disposed on the first via element along a second direction and is electrically connected to the first via element. The first direction is perpendicular to the second direction. The upper surface of the first electrode, the upper surface of the second electrode, the upper surface of the resistance conversion film, and the upper surface of the first metal layer are coplanar.

[0005] According to one embodiment, a method for forming a semiconductor device is provided. The method includes the following steps: providing a substrate; forming a resistance conversion film on the substrate; and forming a first electrode and a second electrode on opposite sides of the resistance conversion film.

[0006] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. Simple diagram description

[0007] Figure 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention; Figure 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention; Figures 3-9 are exemplary diagrams illustrating a method for forming a semiconductor device according to one embodiment of the present invention; and 10-17 exemplarily illustrate a method for forming a semiconductor device according to another embodiment of the present invention. Implementation Method

[0008] The following examples, along with accompanying figures, provide a detailed description of the semiconductor device and its manufacturing method disclosed herein. However, the present disclosure is not limited thereto. The descriptions in the examples, such as the detailed structures, manufacturing method steps, and material applications, are for illustrative purposes only, and the scope of protection intended by the present disclosure is not limited to the described aspects.

[0009] At the same time, it should be noted that this disclosure does not represent all possible embodiments. Those skilled in the relevant art may, without departing from the spirit and scope of this disclosure, vary and modify the structures and manufacturing methods of the embodiments to meet the needs of actual applications. Therefore, other embodiments not set forth in this disclosure may also be applicable. Furthermore, the figures are simplified to facilitate the clear description of the embodiments, and the dimensional ratios in the figures are not drawn to scale according to the actual products. Therefore, the description and figures are intended only to describe the embodiments and are not intended to limit the scope of protection of this disclosure. Identical or similar reference numerals are used to represent identical or similar elements.

[0010] Furthermore, ordinal numbers such as "first," "second," and "third" used in the specification and patent claims are intended to modify elements and do not imply or represent any previous ordinal number of the element, nor do they represent the order of one element relative to another or the order of manufacturing methods. The use of such ordinal numbers is merely to clearly distinguish one element with a certain name from another element with the same name.

[0011] Please refer to FIG. 1 . FIG. 1 illustrates a cross-sectional view of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 includes a substrate 100 . The substrate 100 may include a first dielectric layer 101 , a second dielectric layer 102 , and a third dielectric layer 103 stacked along a second direction D2 . A portion of the substrate 100 may be defined as a memory region 11 , and another portion of the substrate 100 may be defined as a logic region 12 . The memory region 11 and the logic region 12 may be adjacent to each other. The logic region 12 may be disposed around the memory region 11 . The semiconductor device 10 includes a first semiconductor structure 110 located within the memory region 11 and within the substrate 100 , and a second semiconductor structure 120 located within the logic region 12 and within the substrate 100 . The second semiconductor structure 120 is disposed on one side of the first semiconductor structure 110 along a first direction D1 . The first direction D1 is perpendicular to the second direction D2 .

[0012] The first semiconductor structure 110 includes a first electrode 111, a second electrode 112, and a resistive switching film 113 interposed between the first electrode 111 and the second electrode 112. The second electrode 112 is located on one side of the first electrode 111. In this embodiment, the first electrode 111, the resistive switching film 113, and the second electrode 112 are arranged along a first direction D1. The first electrode 111, the resistive switching film 113, and the second electrode 112 are located within the third dielectric layer 103. In this embodiment, the resistive switching film 113 directly contacts the first electrode 111 and the second electrode 112.

[0013] The second semiconductor structure 120 includes a first metal layer 121, a second metal layer 122, and a first via element 123 interposed between the first metal layer 121 and the second metal layer 122. The second metal layer 122 is in the first dielectric layer 101. The first via element 123 is in the second dielectric layer 102 and the third dielectric layer 103. The second metal layer 122 is below the first via element 123 along the second direction D2. The first metal layer 121 is in the third dielectric layer 103. The first metal layer 121 is above the first via element 123 along the second direction D2. The first metal layer 121, the second metal layer 122, and the first via element 123 are electrically connected to each other.

[0014] The height H1 of the first electrode 111 in the second direction D2 may be equal to the height H2 of the second electrode 112 in the second direction D2. The height H1 of the first electrode 111 in the second direction D2 may be greater than the height H3 of the resistance conversion film 113, but the present disclosure is not limited to this. In other embodiments, the height H1 of the first electrode 111 in the second direction D2 may be equal to the height H3 of the resistance conversion film 113. The upper surface 111U of the first electrode 111, the upper surface 113U of the resistance conversion film 113, the upper surface 112U of the second electrode 112, and the upper surface 121U of the first metal layer 121 may be coplanar. The lower surface 111B of the first electrode 111 and the lower surface 112B of the second electrode 112 may be coplanar. In this embodiment, the lower surface 113B of the resistance conversion film 113 may be higher than the lower surface 111B of the first electrode 111 and / or the lower surface 112B of the second electrode 112, but the present disclosure is not limited to this. In other embodiments, the lower surface 111B of the first electrode 111 may be coplanar with the lower surface 113B of the resistance conversion film 113 .

[0015] In one embodiment, the semiconductor device 10 may further include a fourth dielectric layer 104 on the substrate 100. The first semiconductor structure 110 may further include a second via element 114 and a third via element 115 in the fourth dielectric layer 104. The second via element 114 is on the upper surface 111U of the first electrode 111. The third via element 115 is on the upper surface 112U of the second electrode 112. The second via element 114 may be electrically connected to the first electrode 111. The third via element 115 may be electrically connected to the second electrode 112. The second semiconductor structure 120 may further include a fourth via element 124 in the fourth dielectric layer 104. The fourth via element 124 is on the first metal layer 121. The fourth via element 124 may be electrically connected to the first metal layer 121. The second via element 114, the second semiconductor structure 120, and the third via element 115 are electrically connected to each other. In one embodiment, the first semiconductor structure 100 of the semiconductor device 10 may further include a third metal layer 116 and a fourth metal layer 117 in the first dielectric layer 101 of the substrate 100. The third metal layer 116 may at least partially overlap the first electrode 111 in the second direction D2. The fourth metal layer 117 may at least partially overlap the second electrode 112 in the second direction D2.

[0016] The first electrode 111, the second electrode 112, and the resistance conversion film 113 can form a resistive random access memory (RRAM). By applying an appropriate voltage to the first electrode 111 and the second electrode 112, conductive filaments 130 can be induced to form in the resistance conversion film 113. The conductive filaments 130 can penetrate the resistance conversion film 113. The opposite ends of the conductive filaments 130 can contact the first electrode 111 and the second electrode 112, respectively, and can serve as a conductive path between the first electrode 111 and the second electrode 112. In FIG. 1, arrows indicate the direction of current flow, but the present disclosure is not limited to this. The current can also flow from the second electrode 112 to the first electrode 111. When the conductive filaments 130 are formed, the RRAM is in a low-resistance state. Subsequently, another voltage can be applied to the first electrode 111 and the second electrode 112 to disconnect the conductive filaments 130, switching the RRAM from a low-resistance state to a high-resistance state.

[0017] Please refer to FIG. 2 . FIG. 2 illustrates a cross-sectional view of a semiconductor device 20 according to another embodiment of the present invention. The differences between semiconductor device 20 and semiconductor device 10 are described below. Semiconductor device 20 includes a first semiconductor structure 110A located in the memory region 11 and within substrate 100, and a second semiconductor structure 120A located in the logic region 12 and within substrate 100. The first semiconductor structure 110A shown in FIG. 2 differs from the first semiconductor structure 110 shown in FIG. 1 in that the first semiconductor structure 110A further includes a first barrier film 211, a second barrier film 212, a third barrier film 216, and a fourth barrier film 217. The first barrier film 211 is located on the outer surface of the first electrode 111. The first barrier film 211 may be interposed between the first electrode 111 and the resistance conversion film 113. The first barrier film 211 may be interposed between the first electrode 111 and the third dielectric layer 103. The second barrier film 212 is located on the outer surface of the second electrode 112. The second barrier film 212 may be interposed between the second electrode 112 and the resistance conversion film 113. The second barrier film 212 may be interposed between the second electrode 112 and the third dielectric layer 103. The third barrier film 216 is located on the outer surface of the third metal layer 116. The third barrier film 216 may be interposed between the third metal layer 116 and the first dielectric layer 101. The fourth barrier film 217 is located on the outer surface of the fourth metal layer 117. The fourth barrier film 217 may be interposed between the fourth metal layer 117 and the first dielectric layer 101. In the first semiconductor structure 110A, the opposite ends of the conductive filament 130 may contact the first barrier film 211 and the second barrier film 212, respectively, and may serve as a conductive path between the first electrode 111 and the second electrode 112. The second semiconductor structure 120A shown in FIG. 2 differs from the second semiconductor structure 120 shown in FIG. 1 in that the second semiconductor structure 120A further includes a fifth barrier film 221, a sixth barrier film 222, and a seventh barrier film 223. The fifth barrier film 221 is located on the outer surface of the first metal layer 121. The fifth barrier film 221 may be interposed between the first metal layer 121 and the third dielectric layer 103. The sixth barrier film 222 is located on the outer surface of the second metal layer 122. The sixth barrier film 222 may be interposed between the second metal layer 122 and the first dielectric layer 101. The seventh barrier film 223 is located on the outer surface of the first via element 123. The seventh barrier film 223 may be interposed between the first via element 123 and the third dielectric layer 103. The seventh barrier film 223 may directly contact the second metal layer 122.

[0018] 3-9 exemplarily illustrate a method for forming a semiconductor device according to an embodiment of the present invention.

[0019] Refer to FIG. 3 . A substrate 100 is provided. A second metal layer 122, a third metal layer 116, and a fourth metal layer 117 may be formed in the substrate 100. A mask layer 301 may be formed on the substrate 100. The substrate 100 may include a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 103 stacked along a second direction D2. The substrate 100 may be a semiconductor substrate that has reached a certain stage of manufacturing, such as a semiconductor substrate that has completed the front-end of line (FEOL) and partial back-end of line (BEOL) processes, or other substrate materials on which resistive random access memory (RRAM) can be fabricated on its front or back side. In one embodiment, the second metal layer 122, the third metal layer 116, and the fourth metal layer 117 may be first formed in the first dielectric layer 101. Then, the second dielectric layer 102, the third dielectric layer 103, and the mask layer 301 may be sequentially formed on the first dielectric layer 101 along the second direction D2 to form the structure shown in FIG. 3 . The second metal layer 122, the third metal layer 116, and the fourth metal layer 117 may comprise the same or different materials. The second metal layer 122, the third metal layer 116, and the fourth metal layer 117 may comprise, but are not limited to, conductive materials such as aluminum (Al), copper (Cu), or tungsten (W). The first dielectric layer 101, the second dielectric layer 102, and the third dielectric layer 103 may comprise, but are not limited to, dielectric materials such as silicon oxide (SiO2), undoped silicon glass (USG), fluorine-doped silicon glass (FSG), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN). The mask layer 301 may comprise, but is not limited to, materials such as silicon oxide (SiO2), silicon nitride (SiN), and titanium nitride (TiN). A portion of the substrate 100 may be defined as a memory region 11, and another portion of the substrate 100 may be defined as a logic region 12. The third metal layer 116 and the fourth metal layer 117 may be located in the memory region 11 of the substrate 100. The second metal layer 122 may be located in the logic region 12 of the substrate 100.

[0020] Please refer to FIG. 4 . An opening 401 is formed in the memory region 11 of the substrate 100 . The opening 401 penetrates the mask layer 301 and the third dielectric layer 103 along the second direction D2. The opening 401 exposes the sidewalls of the mask layer 301 and the sidewalls of the third dielectric layer 103. The bottom of the opening 401 exposes the third dielectric layer 103. In one embodiment, the opening 401 can be formed by removing portions of the mask layer 301 and the third dielectric layer 103 using an etching process such as wet etching or dry etching.

[0021] Refer to FIG. 5 . A resistance conversion material film 501A is formed. In one embodiment, the resistance conversion material film 501A can be formed in the opening 401 and on the upper surface 301U of the mask layer 301 by a deposition process such as chemical vapor deposition. The resistance conversion material film 501A can include metal oxides such as hafnium oxide (HfOx), tungsten oxide (WOx), aluminum oxide (AlOx), tantalum oxide (TaOx), nickel oxide (NiOx), titanium oxide (TiOx), and zirconium oxide (ZrOx).

[0022] Refer to FIG. 6 . A resistance conversion material film 501B is formed. In one embodiment, the portion of the resistance conversion material film 501A on the upper surface 301U of the mask layer 301 can be removed by chemical-mechanical planarization (CMP) or another suitable etching process, while retaining the portion of the resistance conversion material film 501A within the opening 401. The portion of the resistance conversion material film 501A within the opening 401 is the resistance conversion material film 501B.

[0023] Refer to Figure 7. A resistance conversion film 113A, a first hole 701, a second hole 702, and a third hole 705 are formed. The third hole 705 and the second hole 702 are located on opposite sides of the first hole 701. The first hole 701 and the second hole 702 are located on opposite sides of the resistance conversion film 113A. The first hole 701 penetrates the mask layer 301 and the third dielectric layer 103 along the second direction D2. The first hole 701 exposes the sidewalls 113S of the resistance conversion film 113A, the sidewalls of the mask layer 301, and the sidewalls of the third dielectric layer 103. The bottom 701B of the first hole 701 exposes the third dielectric layer 103. The second hole 702 penetrates the mask layer 301 and the third dielectric layer 103 along the second direction D2. The second hole 702 exposes the sidewalls 113S of the resistance conversion film 113A, the sidewalls of the mask layer 301, and the sidewalls of the third dielectric layer 103. The bottom 702B of the second hole 702 exposes the third dielectric layer 103. The third hole 705 includes a third hole lower portion 703 and a third hole upper portion 704 above the third hole lower portion 703. The third hole lower portion 703 is connected to the third hole upper portion 704. The third hole lower portion 703 penetrates the third dielectric layer 103 and the second dielectric layer 102 along the second direction D2. The third hole lower portion 703 exposes the sidewalls of the third dielectric layer 103 and the sidewalls of the second dielectric layer 102. The bottom 703B of the third hole lower portion 703 (or the bottom of the third hole 705) exposes the second metal layer 122. In one embodiment, the third hole lower portion 703 may gradually narrow along the second direction D2 from the third dielectric layer 103 toward the upper surface 122U of the second metal layer 122. The third hole upper portion 704 penetrates the mask layer 301 and the third dielectric layer 103 along the second direction D2. The third hole upper portion 704 exposes the sidewalls of the third dielectric layer 103 and the mask layer 301. In one embodiment, a wet or dry etching process may be used to remove portions of the resistance-switching material film 501B, the mask layer 301, and the third dielectric layer 103 to form the first hole 701 and the second hole 702. Furthermore, portions of the mask layer 301, the third dielectric layer 103, and the second dielectric layer 102 may be removed to form the third hole 705. The first hole 701, the second hole 702, and the third hole 705 may be formed in the same etching process. At this point, the portion of the resistance-converting material film 501B that has not been removed (or the portion that remains) becomes the resistance-converting film 113A. In this step, removing a portion of the resistance-converting material film 501B to form the resistance-converting film 113A can help reduce device size, but the present disclosure is not limited to this. In other embodiments, the steps of forming the first hole 701 and the second hole 702 may not involve removing a portion of the resistance-converting material film 501B.

[0024] In FIG. 7 , the height H7 of the first hole 701 and the height H8 of the second hole 702 in the second direction D2 are greater than the height H3 of the resistance conversion film 113A in the second direction D2, but the present disclosure is not limited to this. In other embodiments, the height H7 of the first hole 701 in the second direction D2 may be equal to the height H3 of the resistance conversion film 113A in the second direction D2. In FIG. 7 , the bottom 701B of the first hole 701 and the bottom 702B of the second hole 702 are lower than the lower surface 113B of the resistance conversion film 113A in the second direction D2, but the present disclosure is not limited to this. In other embodiments, the bottom 701B of the first hole 701 and the bottom 702B of the second hole 702 may be flush with the lower surface 113B of the resistance conversion film 113A in the second direction D2.

[0025] Refer to FIG. 8 . A conductive material layer 801 is formed to fill the first hole 701, the second hole 702, and the third hole 705. In one embodiment, the conductive material layer 801 can be formed on the upper surface 301U of the mask layer 301, on the upper surface 113U of the resistance conversion film 113A, and in the first hole 701, the second hole 702, and the third hole 705 by a deposition process such as chemical vapor deposition. The conductive material layer 801 can include, but is not limited to, conductive materials such as aluminum (Al), copper (Cu), or tungsten (W).

[0026] Please refer to FIG. 9 . A first electrode 111 and a second electrode 112 are formed on opposite sides of the resistance conversion film 113. A first via element 123 and the first metal layer 121 are formed on the second metal layer 122. In one embodiment, the portion of the conductive material layer 801 above the upper surface 103U of the third dielectric layer 103 can be removed by chemical mechanical polishing or other suitable etching processes, leaving the portion of the conductive material layer 801 below the upper surface 103U of the third dielectric layer 103. Of the remaining conductive material layer 801, the conductive material layer 801 formed in the first hole 701 serves as the first electrode 111, the conductive material layer 801 formed in the second hole 702 serves as the second electrode 112, the conductive material layer 801 formed in the lower portion 703 of the third hole serves as the first via element 123, and the conductive material layer 801 formed in the upper portion 704 of the third hole serves as the first metal layer 121. During the removal of the portion of the conductive material layer 801 on the upper surface 103U of the third dielectric layer 103, the mask layer 301 and the resistance conversion film 113A on the upper surface 103U of the third dielectric layer 103 are also removed, while the portion of the resistance conversion film 113A below the upper surface 103U of the third dielectric layer 103 remains. The portion of the resistance conversion film 113A below the upper surface 103U of the third dielectric layer 103 constitutes the resistance conversion film 113. In this embodiment, the resistance conversion film 113 can directly contact the first electrode 111 and the second electrode 112. In other embodiments, the step of removing a portion of the conductive material layer 801 to form the first electrode 111, the second electrode 112, the first through-hole element 123, and the first metal layer 121 may not involve removing the mask layer 301 (not shown); that is, the portion of the conductive material layer 801 above the upper surface of the mask layer 301 may be removed, while the portion of the conductive material layer 801 below the upper surface of the mask layer 301 is retained, and the mask layer 301 and the resistance conversion film 113A as shown in FIG. 8 are retained; in this case, the resistance conversion film 113A is the resistance conversion film 113.

[0027] In one embodiment, after forming the first electrode 111, the second electrode 112, the first metal layer 121, and the first via element 123, the fourth dielectric layer 104 may be formed on the upper surface 103U of the third dielectric layer 103 (e.g., by a deposition process such as chemical vapor deposition). Subsequently, the second via element 114, the third via element 115, and the fourth via element 124 may be formed in the fourth dielectric layer 104. The second via element 114, the third via element 115, and the fourth via element 124 may comprise the same or different materials. The second via element 114, the third via element 115, and the fourth via element 124 may comprise, but are not limited to, conductive materials such as aluminum (Al), copper (Cu), or tungsten (W). The fourth dielectric layer 104 may include dielectric materials such as silicon oxide (SiO 2 ), undoped silicon glass (USG), fluorine-doped silicon glass (FSG), silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbon nitride (SiCN), but is not limited thereto.

[0028] In one embodiment, the semiconductor device 10 shown in FIG. 1 can be obtained by performing the steps exemplarily illustrated in FIG. 3-9 .

[0029] 10-17 exemplarily illustrate a method for forming a semiconductor device according to another embodiment of the present invention.

[0030] Refer to FIG. 10 . A substrate 100 is provided. A third barrier film 216, a fourth barrier film 217, a sixth barrier film 222, a second metal layer 122, a third metal layer 116, and a fourth metal layer 117 may be formed on the substrate 100. A mask layer 301 may be formed on the substrate 100. The substrate 100 may be a semiconductor substrate that has reached a certain stage of manufacturing, such as a semiconductor substrate that has completed the front-end of the line (FEOL) and part of the back-end of the line (BEOL) manufacturing process, or other substrate materials on which resistive random access memory (RRAM) can be fabricated on its front or back side. In one embodiment, a third barrier film 216, a fourth barrier film 217, and a sixth barrier film 222 may be formed in the first dielectric layer 101. Then, a third metal layer 116, a fourth metal layer 117, and a second metal layer 122 may be formed on the third barrier film 216, the fourth barrier film 217, and the sixth barrier film 222, respectively. Then, a second dielectric layer 102, a third dielectric layer 103, and a mask layer 301 may be sequentially formed on the first dielectric layer 101 along the second direction D2 to form the structure shown in FIG. The third barrier film 216, the fourth barrier film 217, and the sixth barrier film 222 may comprise the same or different materials. The third barrier film 216, the fourth barrier film 217, and the sixth barrier film 222 may comprise titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but are not limited thereto. A portion of the substrate 100 may be defined as a memory region 11, and another portion of the substrate 100 may be defined as a logic region 12. The third barrier film 216, the fourth barrier film 217, the third metal layer 116, and the fourth metal layer 117 may be located in the memory region 11 of the substrate 100. The sixth barrier film 222 and the second metal layer 122 may be located in the logic region 12 of the substrate 100.

[0031] Please refer to Figures 11-14. The steps shown in Figures 11-14 are similar to those shown in Figures 4-7. You can refer to the instructions for Figures 4-7 and perform the steps shown in Figures 11-14.

[0032] Please refer to FIG. 15 . A barrier material film 1501 is formed on the mask layer 301 and lines the first hole 701, the second hole 702, and the third hole 705. The barrier material film 1501 may directly contact the third dielectric layer 103, the mask layer 301, the resistance conversion film 113A, the second dielectric layer 102, and the second metal layer 122. In one embodiment, the barrier material film 1501 may be formed on the upper surface 301U of the mask layer 301, the upper surface 113U of the resistance conversion film 113A, and the sidewalls of the first hole 701, the second hole 702, and the third hole 705 by a deposition process such as chemical vapor deposition. The barrier material film 1501 may include, but is not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

[0033] Refer to FIG. 16 . A conductive material layer 1601 is formed to fill the remaining spaces in the first hole 701, the second hole 702, and the third hole 705. In one embodiment, the conductive material layer 1601 can be formed on the upper surface 1501U of the barrier material film 1501 and in the first hole 701, the second hole 702, and the third hole 705 by a deposition process such as chemical vapor deposition. The conductive material layer 1601 can include, but is not limited to, a conductive material such as aluminum (Al), copper (Cu), or tungsten (W).

[0034] Please refer to FIG. 17 . A first electrode 111 and a second electrode 112 are formed on opposite sides of the resistance conversion film 113. A first via element 123 and the first metal layer 121 are formed on the second metal layer 122. In the steps shown in FIG. 17 , a first barrier film 211 is formed between the resistance conversion film 113 and the first electrode 111, a second barrier film 212 is formed between the resistance conversion film 113 and the second electrode 112, a fifth barrier film 221 is formed between the first metal layer 121 and the third dielectric layer 103, a portion of the seventh barrier film 223 is formed between the first via element 123 and the third dielectric layer 103, and another portion of the seventh barrier film 223 is formed between the first via element 123 and the second dielectric layer 102. In one embodiment, the portion of the conductive material layer 1601 above the third dielectric layer 103 and the portion of the barrier material film 1501 above the third dielectric layer 103 can be removed by chemical mechanical polishing or other suitable etching processes, while retaining the portion of the conductive material layer 1601 below the third dielectric layer 103 and the portion of the barrier material film 1501 below the third dielectric layer 103. Of the retained barrier material film 1501, the barrier material film 1501 formed in the first hole 701 is the first barrier film 211, the barrier material film 1501 formed in the second hole 702 is the second barrier film 212, the barrier material film 1501 formed in the lower portion 703 of the third hole is the seventh barrier film 223, and the barrier material film 1501 formed in the upper portion 704 of the third hole is the fifth barrier film 221. In the retained conductive material layer 1601, the conductive material layer 1601 formed in the first hole 701 serves as the first electrode 111, the conductive material layer 1601 formed in the second hole 702 serves as the second electrode 112, the conductive material layer 1601 formed in the lower portion 703 of the third hole serves as the first through-hole element 123, and the conductive material layer 1601 formed in the upper portion 704 of the third hole serves as the first metal layer 121. During the removal of the portion of the conductive material layer 1601 above the third dielectric layer 103 and the portion of the barrier material film 1501 above the third dielectric layer 103, the portions of the mask layer 301 and the resistance conversion film 113A above the third dielectric layer 103 are also removed, while the portion of the resistance conversion film 113A within the third dielectric layer 103 remains. The portion of the resistance conversion film 113A within the third dielectric layer 103 serves as the resistance conversion film 113. In this embodiment, the resistance conversion film 113 may directly contact the first barrier film 211 and the second barrier film 212 .In other embodiments, the step of removing a portion of the conductive material layer 1601 to form the first electrode 111, the second electrode 112, the first via element 123, and the first metal layer 121 may not involve removing the mask layer 301 (not shown). Specifically, the portion of the conductive material layer 1601 and the barrier material film 1501 above the upper surface of the mask layer 301 may be removed, while the portion of the conductive material layer 1601 and the barrier material film 1501 below the upper surface of the mask layer 301 remains. The mask layer 301 and the resistance conversion film 113A shown in FIG. 16 remain. In this case, the resistance conversion film 113A is the resistance conversion film 113.

[0035] In one embodiment, after forming the first electrode 111, the second electrode 112, the first metal layer 121, the first barrier film 211, the second barrier film 212, the fifth barrier film 221, and the seventh barrier film 223, the fourth dielectric layer 104 may be formed on the upper surface of the third dielectric layer 103 (e.g., by a deposition process such as chemical vapor deposition). Subsequently, the second via element 114, the third via element 115, and the fourth via element 124 may be formed in the fourth dielectric layer 104. In other embodiments, a barrier film may be included between the second via element 114 and the fourth dielectric layer 104, and / or between the third via element 115 and the fourth dielectric layer 104, and / or between the fourth via element 124 and the fourth dielectric layer 104.

[0036] In one embodiment, the semiconductor device 20 shown in FIG. 2 can be obtained by performing the steps exemplarily illustrated in FIG. 10-17 .

[0037] The semiconductor device and its method of formation according to the present disclosure have at least the following benefits. The RRAM system in the semiconductor device disclosed herein is a lateral RRAM. Compared to vertical RRAM, this reduces the number of via elements, resulting in a simpler and lower-cost formation method and improved space efficiency within the semiconductor device. The critical dimension (i.e., the height of the resistive switching film in the second direction D2) of the RRAM in the semiconductor device disclosed herein can be freely adjusted as needed without being restricted by the logic region process steps, enabling the formation of a RRAM with a smaller critical dimension and higher speed. Furthermore, the electrodes in the memory region and the conductive connectors in the logic region (e.g., the first via element and the first metal layer) can be formed simultaneously using the same process, eliminating the need for separate materials and processes to form the electrodes in the memory region and the conductive connectors in the logic region. This results in a simple and low-cost formation method.

[0038] It should be noted that the diagrams, structures, and steps described above are intended to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the aforementioned structures and steps. Other embodiments with different structural aspects, such as known components of different internal components, can be applied, and the illustrative structures and steps can be adjusted according to the needs of actual applications. Therefore, the structures in the diagrams are merely illustrative and are not intended to limit the present invention. A person skilled in the art should understand that the relevant structures and steps of the present disclosure, such as the arrangement or configuration of the relevant elements and layers in a semiconductor device, or the details of the manufacturing steps, may be adjusted and varied accordingly depending on the needs of the actual application.

[0039] In summary, although the present invention has been disclosed above through the use of embodiments, this is not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and alterations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0040] 10,20:Semiconductor devices 11: Memory area 12:Logical area 100:Substrate 101,102,103,104: Dielectric layer 110, 110A, 120, 120A: semiconductor structure 111,112: Electrode 111B, 112B, 113B: bottom surface 113,113A:Resistive switching film 113S: Sidewall 116,117,121,122: Metal layer 111U, 112U, 113U, 121U, 122U, 301U, 1501U: Top surface 114,115,123,124:Through-hole components 211,212,216,217,221,222,223: Barrier film 130: Conductive filament 301: Mask layer 401: Opening 501A, 501B: resistance conversion material film 701,702,705: holes 701B, 702B, 703B: bottom 703: Lower part of the third hole 704: Upper part of the third hole 801,1601: conductive material layer 1501: Barrier material film D1, D2: direction H1,H2,H3,H7,H8:Height

Claims

1. A semiconductor device comprising: a first semiconductor structure and a second semiconductor structure, the second semiconductor structure being disposed on one side of the first semiconductor structure along a first direction, wherein the first semiconductor structure comprises: a first electrode; a second electrode located on one side of the first electrode; and a resistive switching film disposed between the first electrode and the second electrode, wherein the first electrode, the resistive switching film, and the second electrode are disposed along the first direction, the second semiconductor structure comprising: a first via element; a first metal layer disposed on the first via element along a second direction and electrically connected to the first via element, the first direction being perpendicular to the second direction; and a second metal layer disposed below the first via element and electrically connected to the first via element, wherein an upper surface of the first electrode, an upper surface of the resistive switching film, an upper surface of the second electrode, and an upper surface of the first metal layer are coplanar.

2. The semiconductor device as claimed in claim 1, wherein the first semiconductor structure includes a second via element and a third via element, the second via element being on the upper surface of the first electrode and the third via element being on the upper surface of the second electrode, wherein the second via element, the second semiconductor structure and the third via element are electrically connected to each other.

3. The semiconductor device as claimed in claim 1, wherein the first semiconductor structure is located in a memory region and the second semiconductor structure is located in a logic region.

4. The semiconductor device as claimed in claim 1, wherein the resistive switching film is in direct contact with the first electrode and the second electrode.

5. The semiconductor device as claimed in claim 1, wherein the first semiconductor structure includes a first barrier film between the first electrode and the resistive switching film, and a second barrier film between the second electrode and the resistive switching film.

6. The semiconductor device as claimed in claim 1, wherein a lower surface of the first electrode is coplanar with a lower surface of the resistive conversion film.

7. The semiconductor device as claimed in claim 1, wherein a height of the first electrode is greater than a height of the resistive switching film.

8. A method for forming a semiconductor device, comprising: providing a substrate; forming a resistive conversion film in the substrate; and forming a first electrode and a second electrode on opposite sides of the resistive conversion film.

9. The method as described in claim 8, wherein the first electrode and the second electrode are formed after the resistive conversion film is formed.

10. The method as described in claim 8 further comprises: forming a first barrier film between the resistive switching film and the first electrode; and forming a second barrier film between the resistive switching film and the second electrode.

11. The method as claimed in claim 8 further comprises: forming a resistivity conversion material film in a substrate; removing a portion of the resistivity conversion material film to form the resistivity conversion film; and removing a portion of the substrate and a portion of the resistivity conversion material film to form a first hole and a second hole, the first hole and the second hole being on opposite sides of the resistivity conversion film.

12. The method as described in claim 11, wherein the first hole and the second hole expose a plurality of sidewalls of the resistive conversion film.

13. The method as described in claim 11, wherein a height of the first hole is equal to a height of the resistive conversion film.

14. The method as described in claim 11, wherein a bottom of the first hole is lower than a bottom of the resistive conversion film.

15. The method as claimed in claim 11 further comprises: forming the first electrode and the second electrode in the first hole and the second hole respectively, wherein the resistive switching film is in direct contact with the first electrode and the second electrode.

16. The method of claim 11 further comprises: forming a third hole in the substrate, wherein the third hole and the second hole are located on opposite sides of the first hole, and the first hole, the second hole and the third hole are formed in an etching process.

17. The method as described in claim 16 further comprises: filling the first hole, the second hole, and the third hole with a conductive material layer; removing a portion of the conductive material layer to form the first electrode in the first hole, the second electrode in the second hole, and a first through-hole element and a first metal layer on the first through-hole element in the third hole.

18. The method as described in claim 17, wherein an upper surface of the first electrode, an upper surface of the resistive conversion film, and an upper surface of the first metal layer are coplanar.

19. The method as described in claim 16, wherein a bottom of the first hole exposes a dielectric layer in the substrate, and a bottom of the third hole exposes a second metal layer in the substrate.

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