Semiconductor devices

Abstract

The purpose of this disclosure is to further improve driving capability without relying on miniaturization of fin structure. The semiconductor device disclosed herein includes: a channel layer extending from a main surface of a substrate in a normal direction to the main surface; a gate electrode disposed across the channel layer in one in-plane direction of the main surface; and a gate insulating film disposed between the channel layer and the gate electrode; and the channel layer having: at least one pair of convex structures protruding from two sides in the aforementioned direction at an angle in a cross-section in the aforementioned direction; and a pair of concave structures disposed between the pair of convex structures and the substrate.

Description

Semiconductor devices This disclosure relates to a semiconductor device. In recent years, FinFETs (Fin Field-Effect Transistors), with their three-dimensional structure, have been put into practical use, offering improved driving capabilities compared to planar MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). FinFETs enhance gate control over the channel by having the gate three-dimensionally surround two or more sides of the channel, thereby increasing current drive capability. For example, Patent Document 1 below discloses a FinFET in which a gate surrounds five sides of a channel having a hexagonal cross-sectional shape. [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 2005-203798 [The problem the invention aims to solve] This type of FinFET can achieve higher driving capability by further narrowing the width of the channel, i.e., the fin structure. However, further miniaturization of the fin structure increases the difficulty and cost of FinFET manufacturing processes. Therefore, this disclosure proposes a novel and improved semiconductor device that can improve driving capability without relying on miniaturization of the fin structure. [Technical Means for Solving the Problem] According to this disclosure, a semiconductor device is provided, comprising: a channel layer extending from a main surface of a substrate in a normal direction of the main surface; a gate electrode disposed across the channel layer in one in-plane direction of the main surface; and a gate insulating film disposed between the channel layer and the gate electrode; wherein the channel layer has: at least one pair of convex structures protruding from two sides in the one direction at an angle in a cross-section in the one direction; and a pair of concave structures disposed between the pair of convex structures and the substrate. The preferred embodiments disclosed herein will be described in detail below with reference to the accompanying drawings. Furthermore, in this specification and drawings, constituent elements having substantially the same functional configuration are omitted from repeated description by using the same symbols. Additionally, the explanation should be presented in the following order: 1. Example of composition; 2. Effects and functions; 3. Example of variation. <1. Configuration Example> First, referring to Figures 1 and 2, a configuration example of a semiconductor device according to one embodiment of the present disclosure will be described. Figure 1 is a perspective view showing the overall configuration of the semiconductor device 100 of the present embodiment. Figure 2 is a longitudinal sectional view showing the cross-sectional configuration of the semiconductor device 100 shown in Figure 1. Furthermore, the cross-section shown in Figure 2 is a cross-section of the semiconductor device 100 cut along the channel width (or fin width) direction. As shown in FIG1, the semiconductor device 100 includes, for example, a substrate 110, a channel layer 120, a gate electrode 140, a gate insulating film 130, a source layer 150S, and a drain layer 150D. The substrate 110 serves as a support for the semiconductor device 100. The substrate 110 may, for example, be a substrate made of Si, SiGe, SiC, or a III-V compound semiconductor. Furthermore, as shown in FIG2, a component separation layer 111 made of an insulating material is provided on the substrate 110. The component separation layer 111 is formed by embedding an insulating material in a portion of the substrate 110, and can electrically separate the semiconductor device 100 from other components. The channel layer 120 is made of a semiconductor material and extends from the main surface of the substrate 110 in the normal direction of the main surface. The channel layer 120 may also be made of, for example, Si, SiGe, SiC, or III-V compound semiconductors with introduced conductive impurities. To reduce lattice defects, the channel layer 120 is preferably made of a semiconductor material with a lattice constant close to that of the semiconductor material constituting the substrate 110. For example, the channel layer 120 may also be made of the same semiconductor material as the semiconductor material constituting the substrate 110. As shown in FIG2, in the semiconductor device 100 of this embodiment, the channel layer 120 has at least a pair of protruding structures 121 that protrude at an angle from both sides of the channel width direction. The protruding structures 121 are provided to protrude from the side of the channel layer 120 in such a way as to form a concave structure 122 between themselves and the substrate 110, and have ridges on two sides that are inclined in the normal direction of the main surface of the substrate 110. That is, the shape of the cross-section of the convex structure 121 in the width direction of the channel (the cross-sectional shape shown in Figure 2) is a triangular shape with an acute, right, or obtuse angle at the apex protruding from the side of the channel layer 120. Furthermore, the shape of the channel length direction orthogonal to the width direction of the convex structure 121 is a triangular prism shape with the aforementioned triangular shape as its base. In this configuration, an electric field is applied to the channel layer 120 from the gate electrode 140 by means of the two inclined surfaces forming the convex structure 121. Accordingly, because the electric fields from the two inclined surfaces are applied to the channel layer 120 simultaneously in the convex structure 121, a stronger electric field can be applied to the channel layer 120 even with the same gate voltage. Therefore, since the semiconductor device 100 can improve its gate control over the channel layer 120, its current driving capability can be improved. The apex angle of the triangular shape in the channel width direction of the convex structure 121 is preferably an angle of 60 degrees to 150 degrees, and more preferably an angle of 60 degrees to 90 degrees. In this case, as detailed in the section on effects later, the semiconductor device 100 can apply a stronger electric field to the channel layer 120 even with the same gate voltage, thereby improving the current driving capability. Furthermore, a pair of protrusions 121 may also coincide in the normal direction of the main surface of the substrate 110, and be provided in multiple protrusions from both sides of the channel layer 120. In this case, the cross-sectional shape of the channel layer 120 in the channel width direction becomes a Z-shape (i.e., a sawtooth shape) due to the multiple protrusions 121. Accordingly, since the semiconductor device 100 can apply a stronger electric field to each of the multiple pairs of protrusions 121 in the channel layer 120, the driving capability can be increased proportionally to the number of protrusions 121 formed. Alternatively, a pair of protrusions 121 may also protrude from both sides of the channel layer 120 at the same height. In this case, since the semiconductor device 100 can form a pair of protrusions 121 on both sides of the channel layer 120 in the same step, it is easier to form a channel layer 120 with a pair of protrusions 121. This channel layer 120 can also be formed by epitaxial growth of the aforementioned semiconductor material as a single crystal. Specifically, the channel layer 120 can also be formed by controlling the crystal growth by forming two sides of the convex structure 121 as the crystal surfaces of the semiconductor material, thereby epitaxial growth of the aforementioned semiconductor material. For example, the convex structure 121 can also be formed by epitaxially growing semiconductor material with the lower surface of the convex structure 121 as the crystallization surface, and then changing the process conditions to epitaxially grow semiconductor material with the upper surface of the convex structure 121 as the crystallization surface. Furthermore, the plurality of pairs of convex structures 121 shown in Figure 2 can also be formed by planarizing the upper end of the channel layer 120 after forming a pair of convex structures 121 using CMP (Chemical Mechanical Polishing) or similar methods, and then repeating the above-mentioned epitaxial growth process. However, the aforementioned channel layer 120 can also be formed by methods other than epitaxial growth using crystal plane orientation. For example, the channel layer 120 can also be formed using various microfabrication processes such as lithography, CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition), as well as etching. The gate electrode 140 is made of a conductive material and is disposed across the channel layer 120 in the channel width direction (i.e., the direction in which the protrusion 121 of the channel layer 120 protrudes). The gate electrode 140 may also be made of a conductive material comprising monomers or compounds such as Si, poly-Si, Al, Cu, Au, W, Ta, Ti, Mo, or Ru. The gate electrode 140 can be connected to the channel layer 120 by a gate insulating film 130 at the two sides of the protrusion 121 of the channel layer 120, through which an electric field is applied to the protrusion 121 of the channel layer 120 from both the upper and lower surfaces. The gate insulating film 130 is made of an insulating material and is disposed between the channel layer 120 and the gate electrode 140. Specifically, the gate insulating film 130 may also be disposed such that it covers the surface of the channel layer 120 in the channel width direction. For example, the gate insulating film 130 may also be made of SiO2. x It can be composed of SiN or SiON, or HfO x HfAlON, Y 2O 3. ZrO x Al 2O 3. or NbO x It is composed of high dielectric materials (High-k materials). As another example, the gate insulating film 130 may also be composed of an oxide of the semiconductor material constituting the channel layer 120. In this case, since the gate insulating film 130 can be easily formed on the surface of the channel layer 120 by oxidation of the semiconductor device 100, the manufacturing process can be further simplified. The source layer 150S and drain layer 150D are respectively disposed on both sides of the channel layer 120 along the channel length direction (i.e., the direction orthogonal to the channel width direction). Furthermore, the source layer 150S and drain layer 150D are electrically insulated from the gate electrode 140 by interposing a gap or insulating layer therebetween. For example, the source layer 150S and drain layer 150D may also be composed of semiconductor materials such as Si, SiGe, or Ge, which incorporate impurities of a different conductivity type than that of the channel layer 120 and epitaxially grow them. <2. Effects> Next, referring to Figures 3 to 7, the effects of the semiconductor device 100 in this embodiment will be explained in more detail. First, referring to Figures 3 and 4, the electric field applied to the convex structure 121 of the channel layer 120 will be explained. Figure 3 is a schematic diagram illustrating the regions defined by the convex structure 121 of the channel layer 120. Figure 4 is a schematic diagram illustrating the method of deriving the formulas representing the electric fields of each region shown in Figure 3. As shown in Figure 3, the electric field applied to the convex structure 121 protruding from the side of the channel layer 120 can be considered to be divided into three regions: region A, region B, and region C. Region C is the region where the a electrode forming the upper surface of the convex structure 121 extends vertically, and the region where the b electrode forming the lower surface of the convex structure 121 extends vertically. Region A is the region after subtracting region C from the region where the a electrode forming the upper surface of the convex structure 121 extends vertically. Region B is the region after subtracting region C from the region where the b electrode forming the lower surface of the convex structure 121 extends vertically. Here, in the FinFET, because the concentration of conductive impurities in the channel layer 120 is low, the electric field generated by the charge of the conductive impurities in the channel layer 120 can be approximately ignored. Therefore, the electric field generated from the gate electrode 140 can be regarded as a depth-specific electric field generated by a parallel plate electrode. If the coordinates and variables are set as shown in Figure 4, the electric field generated from electrode a can be expressed by the following equation 1. Where L is the gate length, Q is the charge imparted to the gate electrode at 140°, and ε is the dielectric constant. [Number 1] (Number 1) Therefore, the electric field intensity Ea' of the equipotential surface of the electric field generated at electrode a can be approximately represented by the following equation 2. [Number 2] (Number 2) Therefore, in the combined region of region A and region C (Y<X*tan(θ / 2), Y>-X / tan(θ / 2)), the electric field intensity (Eax, Eay) generated by electrode a is represented by the following equation 3. [Number 3] (Number 3) Furthermore, in region B (Y>-X*tan(θ / 2), Y<-X / tan(θ / 2)), the electric field intensity (Eax, Eay) generated by electrode a is represented by the following equation 4 (where d=√(x^2+y^2)). [Number 4] (Number 4) The electric field intensity generated by electrode b can also be considered in the same way. Therefore, as |Ea|=|Eb|=E0, if the electric field intensity generated by electrodes a and b is synthesized, then in region A (Y<X*tan(θ / 2),Y>X / tan(θ / 2)), the total electric field intensity (Ex,Ey) generated by electrodes a and b is expressed by the following equation 5 (where d=√(x^2+y^2)). [Number 5] (Number 5) Furthermore, in region B (Y>-X*tan(θ / 2), Y<-X / tan(θ / 2)), the total electric field intensity (Ex, Ey) generated by electrode a and electrode b is represented by the following formula 6 (where d=√(x^2+y^2)). [Number 6] (Number 6) Furthermore, in region C (Y < X / tan(θ / 2), Y > -X / tan(θ / 2)), the total electric field intensity (Ex, Ey) generated by electrode a and electrode b is expressed by the following formula 7 (where d = (X * tan(θ / 2) - Y) / cos(θ / 2)). [Number 7] (Number 7) Figure 5 shows the relationship between the electric field strength applied to the convex structure 121, calculated based on equations 5-7 above, and the angle of the apex angle of the convex structure 121 protruding from the side of the channel layer 120. Figure 5 is a graph showing the correspondence between the electric field strength applied to the convex structure 121 and the angle of the apex angle of the convex structure 121. Furthermore, the electric field strength on the vertical axis of Figure 5 is expressed as a relative value where the electric field strength at an angle of 180° (i.e., without the convex structure 121) is set to 1. Furthermore, since the convex structure 121 functions as a channel within an angle range exceeding 0° but below 90°, the electric field strength acting on the channel is the electric field strength of region C, as represented by Equation 7. On the other hand, since the outermost surface of the convex structure 121 functions as a channel within an angle range exceeding 90° but below 180°, the electric field strength acting on the channel is the sum of the electric field strength of region A, as represented by Equation 5, and the electric field strength of region B, as represented by Equation 6. As shown in Figure 5, the electric field strength acting on the convex structure 121 is higher in the range of 60° to 150° at the apex angle of the convex structure 121 than in the case of an angle of 180° (the case where the convex structure 121 is not formed). Therefore, the semiconductor device 100 can further improve the gate control force in the range of 60° to 150° at the apex angle of the convex structure 121. In particular, since the semiconductor device 100 can use the convex structure 121 as a channel in the range of 60° to 90° at the apex angle of the convex structure 121, the on-resistance of the channel layer 120 can be further reduced. Furthermore, if the state of the electric field applied to the shape-dependent channel layer 120 is represented as the shape factor α, then the current I flowing in the conducting state of the semiconductor device 100 can be modeled as shown in the following equation 8. Here, μ represents charge mobility, C represents gate capacitance, W represents gate width, and L represents gate length. Vg represents gate voltage, Vth represents threshold voltage, and Vd represents drain voltage. [Number 8] (Number 8) According to Equation 8 above, in the semiconductor device 100, the mutual conductance gm, which represents the change in drain current relative to gate voltage, is expressed as a coefficient of (Vg - Vth - Vd / 2) as gm = μCW / L * α * Vd. On the other hand, the mutual conductance gm of a typical FinFET (i.e., when the apex angle of the convex structure is 180°) 0 series gm 0 = μCW / L * Vd. Therefore, the mutual conductance gm of the semiconductor device 100 uses the typical mutual conductance gm of a FinFET. 0 is represented as gm=gm 0*α. That is, the relationship between the shape factor α, which represents the electric field strength dependent on the shape of the channel layer 120, and the angle of the apex angle of the aforementioned convex structure 121 is shown in the graph of Figure 6. Figure 6 is a graph showing the relationship between the shape factor α, which represents the electric field strength dependent on the shape of the channel layer 120, and the angle of the apex angle of the convex structure 121. As shown in Figure 6, the shape factor α (gm / gm) can be determined. 0) Within the range of 60° to 150° at the apex of the convex structure 121, the current conductance is higher than that of a typical FinFET with an angle of 180° (without the convex structure 121). Therefore, within the range of 60° to 150° at the apex of the convex structure 121, the semiconductor device 100 can achieve higher mutual conductance than a typical FinFET, thus obtaining a higher current drive capability than a typical FinFET. As described above, the semiconductor device 100 of this embodiment can form a convex structure 121 even without miniaturizing the width of the channel layer 120, thereby improving the current driving capability. For example, the semiconductor device 100 of this embodiment can drive pixels at a higher speed by means of the amplifier transistors used in pixels in solid-state imaging devices such as CMOS image sensors. <3. Variations> First, referring to Figures 7 to 10, the first to fourth variations of the semiconductor device 100 of this embodiment will be described. (First Variation) Figure 7 is a longitudinal sectional view showing the cross-sectional configuration of the semiconductor device 101 in the channel width direction according to the first variation. As shown in Figure 7, in the semiconductor device 101, the channel layer 120 may also have only one pair of protrusions 121. In this case, since the semiconductor device 101 can also apply a stronger electric field to each of the protrusions 121 on the channel layer 120, the current driving capability can be improved by increasing the gate control force on the channel layer 120. The number of convex structures 121 disposed on one of the channel layers 120 can be appropriately selected based on a balance between the required current driving capability and the cost of the channel layer 120 fabrication process. For example, increasing the number of convex structures 121 disposed on the channel layer 120 increases the gate control over the channel layer 120. On the other hand, the cost increases due to the increased number of steps in the channel layer 120 fabrication process. Therefore, in order to further suppress the cost of the channel layer 120 fabrication process, the number of convex structures 121 may be set to one. On the other hand, in order to further increase the gate control over the channel layer 120, the number of convex structures 121 may be set to three. (Second Variation) Figure 8 is a longitudinal sectional view showing the cross-sectional configuration of the semiconductor device 102 in the channel width direction according to the second variation. As shown in Figure 8, in the semiconductor layer 102, the upper end of the channel layer 120 in the extension direction is not planarized and can also be provided with an angular and protruding ridge portion 123. Specifically, the upper end of the channel layer 120 in the extension direction can also be provided with a ridge portion 123, which includes a ridge line formed by the inclined upper surface of the convex structure 121 protruding from one side and the inclined upper surface of the convex structure 121 protruding from the other side. In this case, the ridge portion 123 contains a ridge line on the two upper surfaces of a pair of convex structures 121 extending in the channel length direction. According to the second variation, the semiconductor device 102 can omit the step of planarizing the upper end of the channel layer 120 with CMP or the like after forming the channel layer 120 having a pair of protrusions 121. Therefore, the semiconductor device 102 can further reduce the cost of the channel layer 120 formation process. (Third Variation) Figure 9 is a longitudinal sectional view showing the cross-sectional configuration of the semiconductor device 103 in the channel width direction according to the third variation. As shown in Figure 9, in the semiconductor device 103, the convex structure 121 can also be configured as a chamfered corner (i.e., rounded corner) protruding from the side of the channel layer 120. For example, the convex structure 121 can also be formed by epitaxial growth of the channel layer 120 using a crystal plane orientation, and then rounded corner by etching or thermal oxidation. According to the third variation, the semiconductor device 103 can suppress excessive electric field concentration at the apex of the convex structure 121 protruding from the side of the channel layer 120. Therefore, the semiconductor device 103 can suppress damage to the gate insulating film 130 caused by excessive electric field concentration, thereby further improving the reliability during operation. (Fourth Variation) Figure 10 is a longitudinal sectional view showing the cross-sectional configuration of the semiconductor device 104 in the channel width direction according to the fourth variation. As shown in Figure 10, in the semiconductor device 104, a pair of convex structures 121 can also protrude from the two sides of the channel layer 120 at different heights. In this case, since the semiconductor device 104 can also apply a stronger electric field to each of the convex structures 121 in the channel layer 120, the current driving capability can be improved. The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings, but the scope of this disclosure is not limited to this example. It should be understood that anyone with general knowledge of the technical field of this disclosure can conceive of various modifications or alterations within the scope of the technical ideas described in the claims, and these should also be understood to fall within the scope of this disclosure. Furthermore, the effects described in this specification are merely illustrative or exemplary and are not limiting. That is, the technology disclosed herein can be used in conjunction with or in place of the aforementioned effects to achieve other effects that will be apparent to those skilled in the art based on the description in this specification. Furthermore, the following configurations also fall within the scope of this disclosure: (1) A semiconductor device comprising: a channel layer extending from a main surface of a substrate in a normal direction to the main surface; a gate electrode disposed across the channel layer in one direction within the main surface; and a gate insulating film disposed between the channel layer and the gate electrode; and the channel layer having: at least one pair of convex structures protruding from two sides in the one direction at an angle in a cross-section in the one direction; and a pair of concave structures disposed between the pair of convex structures and the substrate. (2) The semiconductor device as described in (1) above, wherein the angle of the convex structure is 60° or more and 150° or less. (3) The semiconductor device as described in (2) above, wherein the angle of the convex structure is 60° or more and 90° or less. (4) In any of the above-described semiconductor devices (1) to (3), the gate electrode is connected to the channel layer via the gate insulating film on both sides of the convex structure forming the corner. (5) In any of the above-described semiconductor devices (1) to (4), the corner of the convex structure is chamfered. (6) In any of the above-described semiconductor devices (1) to (5), the pair of convex structures are provided in a plurality in the normal direction. (7) In any of the above-described semiconductor devices (1) to (6), each of the pair of convex structures protrudes from the same height on both sides in the same direction. (8) In any of the above-described semiconductor devices (1) to (6), each of the pair of convex structures protrudes from different heights on both sides in the same direction. (9) In any of the above-described semiconductor devices (1) to (8), the end of the channel layer in the normal direction is flat. (10) The semiconductor device described in any one of (1) to (9) above further comprises: a source layer and a drain layer, wherein the two sides of the channel layer in a direction orthogonal to the aforementioned direction are respectively connected to the channel layer. (11) The semiconductor device described in any one of (1) to (10) above, wherein the channel layer is composed of a single-crystal semiconductor. (12) The semiconductor device described in (11) above, wherein the semiconductor comprises Si, SiGe, SiC, or a III-V compound semiconductor. (13) The semiconductor device described in (11) or (12) above, wherein the two sides of the corner forming the convex structure are the crystal planes of the semiconductor. 100~104: Semiconductor device; 110: Substrate; 111: Component separation layer; 120: Channel layer; 121: Convex structure; 122: Concave structure; 123: Ridge portion; 130: Gate insulating film; 140: Gate electrode; 150D: Drain layer; 150S: Source layer; Ea: Electric field strength gm; Mutual conductance gm 0: Mutual conductance; θ: Angle Figure 1 is a perspective view showing the overall structure of a semiconductor device according to one embodiment of the present disclosure. Figure 2 is a longitudinal sectional view showing the cross-sectional structure of the semiconductor device shown in Figure 1. Figure 3 is a schematic diagram illustrating the regions defined by the convex structure of the channel layer. Figure 4 is a schematic diagram illustrating the method of deriving the formulas representing the electric fields of the regions shown in Figure 3. Figure 5 is a graph showing the relationship between the angle of the apex of the convex structure and the electric field strength applied to the convex structure. Figure 6 is a graph showing the relationship between the form factor α of the electric field strength dependent on the shape of the channel layer and the angle of the apex of the convex structure. Figure 7 is a longitudinal sectional view showing the cross-sectional structure of the semiconductor device in the channel width direction of the first variation example. Figure 8 is a longitudinal sectional view showing the cross-sectional structure of the semiconductor device in the channel width direction of the second variation example. Figure 9 is a longitudinal sectional view showing the cross-sectional structure of the semiconductor device in the channel width direction of the third variation example. Figure 10 is a longitudinal sectional view showing the cross-sectional structure of the semiconductor device in the channel width direction of the fourth variation example. 100: Semiconductor devices 110:Substrate 111: Component Separation Layer 120: Channel Layer 121: Convex Structure 122: Concave structure 130: Gate insulating film 140: Gate electrode

Claims

1. A semiconductor device comprising: a channel layer extending from a main surface of a substrate in a normal direction to the main surface; a gate electrode disposed across the channel layer in one direction in-plane of the main surface; and a gate insulating film disposed between the channel layer and the gate electrode; wherein the channel layer has: at least one pair of convex structures protruding from two sides in one direction at an angle in a cross-section in the one direction; and a pair of concave structures disposed between the pair of convex structures and the substrate, each of the pair of convex structures protruding from two sides in the one direction at different heights.

2. The semiconductor device of claim 1, wherein the size of the angle of the convex structure is 60° or more and 150° or less.

3. The semiconductor device of claim 2, wherein the size of the angle of the convex structure is 60° or more and 90° or less.

4. The semiconductor device of claim 1, wherein the gate electrode is in contact with the channel layer via the gate insulating film on two sides of the convex structure forming the corner.

5. The semiconductor device of claim 1, wherein the aforementioned corner of the aforementioned convex structure is chamfered.

6. The semiconductor device of claim 1, wherein the pair of convex structures are arranged in a plurality of the normal directions.

7. The semiconductor device of claim 1, wherein the end of the channel layer in the normal direction is flat.

8. The semiconductor device of claim 1 further comprises: a source layer and a drain layer, wherein the two sides of the channel layer in a direction orthogonal to the aforementioned direction are respectively connected to the channel layer.

9. The semiconductor device of claim 1, wherein the channel layer is composed of a single-crystal semiconductor.

10. The semiconductor device of claim 9, wherein the semiconductor comprises Si, SiGe, SiC, or a III-V compound semiconductor.

11. The semiconductor device of claim 9, wherein the two faces of the convex structure forming the corner are the crystal faces of the semiconductor.

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