Hybrid patterning-bonding semiconductor tool

Abstract

This apparatus includes a first module configured for wafer shape correction and a second module configured for wafer bonding. The first module includes a measurement module configured to measure wafer shape data of a first wafer and a second wafer, the wafer shape data including the relative z-height values ​​of the first and second wafers. A stress source film deposition module is configured to form a first stress source film on the first wafer. A stress source film modification module is configured to modify the first stress source film based on a first modification pattern, the first modification pattern defining adjustments to the internal stress of the first wafer and generated based on the wafer shape data. The second module includes an alignment module configured to align the first and second wafers, and a bonding module configured to bond the first wafer to the second wafer.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor manufacturing and, more particularly, to wafer overlay control.

[0002] [Priority Claim] This disclosure claims priority to U.S. Provisional Patent Application Nos. 63 / 328,825 and 63 / 328,823, filed on April 8, 2022, and U.S. Non-Provisional Patent Application Nos. 17 / 885,097 and 17 / 885,038, filed on August 10, 2022, each of which is incorporated herein by reference in its entirety. Prior Art

[0003] Semiconductor manufacturing involves many different steps and processes. A well-known and typical manufacturing process is photolithography (also known as lithography). Photolithography uses radiation, such as ultraviolet or visible light, to create fine patterns in semiconductor device designs. Many types of semiconductor devices, such as diodes, transistors, and integrated circuits, can be constructed using semiconductor manufacturing techniques, including photolithography, etching, film deposition, surface cleaning, metallization, and more.

[0004] Exposure systems (also called exposure tools) are used to perform photolithography techniques. These systems typically include an illumination system, a reticle (also called a mask) or spatial light modulator (SLM) for creating circuit patterns, a projection system, and a wafer alignment stage for aligning a semiconductor wafer covered with photosensitive photoresist. The illumination system illuminates an area of ​​the reticle or SLM using a (preferably) rectangular slot illumination field. The projection system projects an image of the illuminated area of ​​the reticle pattern onto the wafer. For accurate projection, it is important that the exposure light pattern be placed on a relatively flat or planar wafer, preferably with a height deviation of less than 10 microns. Summary of the Invention

[0005] The present disclosure relates to an apparatus for bonding wafers together.

[0006] According to a first embodiment of the disclosed content, a device for bonding wafers is provided. The device includes a first module configured for wafer shape correction and a second module configured for wafer bonding. The first module includes a measurement module configured to measure wafer shape data of a first wafer and a second wafer. The wafer shape data includes relative z-height values ​​of the first wafer and the second wafer. A stressor film deposition module is configured to form a first stressor film on the first wafer. A stressor film modification module is configured to modify the first stressor film based on a first modification map, the first modification map defining an adjustment to the internal stress of the first wafer. The first modification map is generated based on the wafer shape data of the first wafer and the second wafer. The second module includes an alignment module configured to align the first wafer with the second wafer, and a bonding module configured to bond the first wafer to the second wafer.

[0007] In some embodiments, the stressor film deposition module is configured to form a first stressor film on a first wafer based on a first modified pattern.

[0008] In some embodiments, the first wafer has a front working surface and a back surface opposite the front working surface. The stressor film deposition module is configured to form a first stressor film on the back side of the first wafer.

[0009] In some embodiments, the stressor film deposition module includes at least one of a spin coating device, a spray coating device, or a vapor deposition device.

[0010] In some embodiments, the stressor film modification module includes a direct write exposure tool configured to expose the first stressor film to a pattern of electromagnetic radiation based on a first modification map.

[0011] In some embodiments, the stressor film modification module includes a developing device configured to develop the photoresist layer of the first stressor film to form a relief pattern.

[0012] In some embodiments, the stressor film modification module includes an etching device configured to etch the shape control layer of the first stressor film using the relief pattern as an etching mask.

[0013] In certain embodiments, the stressor film modification module includes a thermal plate with zoned temperature control.

[0014] In some embodiments, the stressor film modification module includes a heating array having independently temperature controlled heating zones.

[0015] In some embodiments, the heating array includes an array of resistors, each resistor being configured to generate a respective amount of heat based on a respective current flowing therethrough.

[0016] In some embodiments, at least one resistor is integrated into a wafer chuck configured to hold the first wafer.

[0017] In some embodiments, the stressor film modification module includes a laser system configured to heat at least one of a first wafer or a wafer chuck configured to hold the first wafer.

[0018] In some embodiments, the controller is configured to generate a first modification map based on wafer shape data of the first wafer and the second wafer.

[0019] In some embodiments, the controller is configured to receive input from and provide output to at least one module selected from the group consisting of a metrology module, a stressor film deposition module, a stressor film modification module, an alignment module, and a bonding module.

[0020] In some embodiments, the controller is configured to control at least one process selected from the group consisting of: measuring wafer shape data, depositing a first stressor film, modifying the first stressor film, aligning the first wafer with the second wafer, and bonding the first wafer to the second wafer.

[0021] In some embodiments, the controller is configured to generate the first modification map based on historical data in addition to wafer shape data of the first wafer and the second wafer, the historical data including overlap information of the historical wafers.

[0022] In some embodiments, the stressor film deposition module is configured to form a second stressor film on a second wafer. The stressor film modification module is configured to modify the second stressor film based on a second modification map defining an adjustment to stress within the second wafer, the second modification map being generated based on wafer shape data of the first wafer and the second wafer.

[0023] In some embodiments, the alignment module and the bonding module are an integrated module so that there is no wafer transfer between performing alignment and performing bonding.

[0024] According to a second embodiment of the disclosed content, an apparatus for bonding wafers is provided. The apparatus includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a measurement module configured to measure wafer shape data of a first wafer and a second wafer. The wafer shape data includes relative z-height values ​​of the first wafer and the second wafer. A stressor film deposition module is configured to form a first stressor film on a first wafer based on a first modification map, wherein the first modification map defines an adjustment to internal stress in the first wafer. The first modification map is generated based on the wafer shape data of the first wafer and the second wafer. The second set of modules includes an alignment module configured to align the first wafer with the second wafer, without modifying the first stressor film between forming the first stressor film and performing the alignment. The bonding module is configured to bond the first wafer to the second wafer.

[0025] In some embodiments, the first modified image does not include a pattern. The stressor film deposition module is configured to form the first stressor film as a blanket film.

[0026] Please note that this Summary does not specify every embodiment and / or incrementally novel implementation of the present disclosure or claimed invention. Rather, this Summary merely provides an initial discussion of various embodiments and corresponding novel aspects. For additional details and / or potential aspects of the present invention and its embodiments, the reader is directed to the Detailed Description section of the present disclosure and the corresponding figures, discussed further below. Simple diagram description

[0027] The following detailed description is best understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, many features are not drawn to scale. Indeed, the dimensions of many features may be increased or decreased for clarity of discussion.

[0028] 1A is a plan view of a mixing system according to certain embodiments of the present disclosure.

[0029] FIG. 1B is an oblique view of a mixing system according to certain embodiments of the present disclosure.

[0030] FIG. 2A is a diagram illustrating a process for wafer shape correction according to certain embodiments of the present disclosure.

[0031] FIG. 2B is a diagram illustrating a wafer bonding process according to certain embodiments of the present disclosure.

[0032] 3A, 3B, 3C, 3D, 3E, and 3F illustrate cross-sectional views of a wafer at various intermediate steps during fabrication according to certain embodiments of the present disclosure.

[0033] FIG. 4A shows a plan view of a heating array according to one embodiment of the present disclosure.

[0034] FIG. 4B illustrates a heating zone generated by a heating array according to one embodiment of the present disclosure.

[0035] FIG. 4C shows a heating zone generated by a heating array according to another embodiment of the present disclosure.

[0036] FIG. 5 is a flow chart showing a wafer bonding process according to an exemplary embodiment of the present disclosure.

[0037] FIG6A shows an example of low-level wafer deformation.

[0038] FIG6B shows an example of high-order wafer deformation.

[0039] Figure 7 shows an example of warped wafer test results.

[0040] FIG8A shows an example of the raw bonding error.

[0041] FIG8B shows an example of residual bonding error.

[0042] FIG. 8C shows another example of the original bonding error.

[0043] FIG. 8D shows another example of residual bonding error.

[0044] FIG. 9A illustrates a desired bonding alignment according to one embodiment of the present disclosure.

[0045] FIG9B shows an example of a catastrophic joint failure.

[0046] Figure 10 shows experimental data on twisted / warped wafers and bonded overlay error. Implementation Method

[0047] The following disclosure provides numerous different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These examples are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, throughout the present disclosure, reference symbols and / or characters may be repeated throughout various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Furthermore, for ease of description, spatially relative terms such as "top," "bottom," "under," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to other element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0048] For the sake of clarity, the order in which the various steps described herein are discussed has been presented. In general, these steps can be performed in any suitable order. Furthermore, while each of the various features, techniques, configurations, etc. herein may be discussed at various points in this disclosure, it is intended that each of these concepts can be implemented independently of one another or in combination with one another. Thus, the present invention can be implemented and viewed in many different ways.

[0049] A typical semiconductor device can be constructed from numerous layers, for example, over seventy individual layers. Each layer requires multiple process steps, including but not limited to thin film deposition, lithography, and etching, to form the desired structure. Uneven wafer stresses induced by these fundamental operations, caused by thin film patterning and amplified by multiple temperature cycling processes, can fundamentally distort the wafer grid.

[0050] These (wafer shape) distortions can manifest as low-level, global spherical deformations, as depicted in Figure 6A. Higher-level, localized height variations can exist as independent distortions or be embedded within global features. Figure 6B shows an example of higher-level wafer distortion. The data presented is from conventional semiconductor metrology equipment commonly used in the industry. Both low-level and high-level wafer distortions can complicate the W2W (wafer-to-wafer) bonding process and negatively impact yield, for example, resulting in yield loss.

[0051] Wafer (grid) integrity is not only crucial for handling wafers as they move through modules in semiconductor manufacturing equipment, but also significantly impacts yield during the bonding process. With the advent of 3D packaging, the semiconductor industry is reaching a critical juncture where traditional bonding-based alignment correction cannot address nonlinear physical wafer effects induced by processing. Specifically, stresses incurred on the wafer prior to the bonding operation can cause global and localized wafer shape distortions, leading to alignment failures and potentially compromising critical bonding metrics, directly resulting in significant yield losses in advanced packaging processes.

[0052] The purpose of a wafer bonding system is to connect (or bond) two component wafers together in a mechanically stable package. Thus, a W2W bonding platform is comprised of handling mechanisms and process modules for the upper (top) and lower (bottom) wafers. Aside from the fact that alignment tolerances exist when combining the wafers to produce functional devices, the complexity of the bonding platform is not relevant to the present disclosure; functional devices are described in further detail below.

[0053] Wafer shape distortion can affect the most basic operation of a W2W system—wafer handling. If wafer distortion (or wafer warpage) impedes wafer transfer and / or clamping, the effective throughput of the bonding process is reduced to zero. Figure 7 illustrates this failure in an HVM (High Volume Manufacturing) W2W bonding tool. As shown, a wafer with a diameter greater than approximately 370 mm can be Wafers that experience compression-induced strain (or wafer warpage) of 370 m have experienced severe handling failure and require manual recovery from the system. In other words, the wafer in its current warped state cannot be processed at all. Please note that the threshold for wafer warpage that causes handling failure may vary depending on the specific tool. For illustrative purposes, this article uses 370 m as an example.

[0054] On the (same) HVM W2W bonding tool (platform) used in FIG7 , these wafers produced residual bonding errors as shown in FIG8A to 8D . Specifically, FIG8A and 8B show that the wafers with 100 Figures 8C and 8D show the original error and residual error of a wafer with a wafer warpage of 150 m. The original and residual errors for another wafer with wafer warpage of m are shown. Note that the residual errors cannot be corrected by the system configuration (e.g., HVM W2W bonding tool) and represent best-case results even with forward / backward feedback corrections. As those skilled in the art will appreciate, if the magnitude of these residual (overlay) errors is large enough, they can cause severe failures in electrical continuity, rendering the device unmanufacturable. A simplified example can be seen in Figure 9B, where misalignment of the copper interconnects between the top and bottom bonded wafers leads to failure. These residuals are expected to be further exacerbated by complex higher-order wafer deformations, such as that depicted in Figure 6B.

[0055] In FIG9B , misaligned system 900B includes a first wafer 910 (or top wafer) and a second wafer 920 (or bottom wafer) bonded together. First wafer 910 includes a first interconnect structure 913 (e.g., as indicated by 913a, 913b, and 913c), while second wafer 920 includes a second interconnect structure 923 (e.g., as indicated by 923a, 923b, and 923c). First interconnect structure 913 and second interconnect structure 923 are misaligned. Specifically, first interconnect structures 913a, 913b, and 913c are misaligned with second interconnect structures 923a, 923b, and 923c, respectively. Therefore, misaligned system 900B is a defective product.

[0056] FIG9A illustrates an alignment system 900A. Here, a first interconnect structure 913 is aligned with a second interconnect structure 923. Specifically, first interconnect structures 913a, 913b, and 913c are aligned with second interconnect structures 923a, 923b, and 923c, respectively. Although shown as seamless, at least one interface or intermediate layer may exist between first interconnect structure 913 and second interconnect structure 923.

[0057] Consequently, wafer distortion (or stress) leads to overlay errors and yield losses. These yield losses will only worsen as alignment tolerances shrink in next-generation chip designs for advanced-node semiconductor manufacturing. Therefore, it is crucial to have technologies that can advantageously manipulate wafer shape to enable processing of highly warped wafers in W2W bonding tools and provide compensation mechanisms for defects in bonder alignment systems that cannot effectively address wafer grid distortion, especially as the semiconductor industry enters a critical juncture with the advent of 3D packaging and the shrinking alignment tolerances of next-generation device designs. Such novel technologies are described herein.

[0058] Figure 10 shows experimental data further illustrating the relationship between warped / distorted wafers and bonded overlay error. The left side of Figure 10 shows the "Baseline," a standard baseline process. "Global Warp," "High-Order Warp 1," and "High-Order Warp 2" explore the response to global warp and high-order wafer warp. It can be seen that the uncorrected residual component of overlay is significantly worse than the baseline.

[0059] The technology disclosed herein provides the industry with a solution to combat process-induced wafer warpage and enables future packaging solutions. The technology herein includes systems and hardware for manipulating wafer shape via stress control layer(s) (also known as stressor film(s)). The stress control layer(s) can be locally expanded through patterning and / or activation processes to enhance freedom. Wafer shape metrology tools and data known in the semiconductor industry can be used as input to design the correct stress for the control layer(s) and optimize the expansion location, resulting in improved W2W (wafer-to-wafer) bonding performance. The integration of these methods can result in reduced bond overlap, improved bond strength, and reduced voids, providing a corresponding increase in yield. Exemplary embodiments include a combined lithography module for coating, exposure, and development, and a module for bonding wafers. The patterning functionality of such a tool is optimized to manipulate wafer shape via stress control layers integrated onto the wafer using heat and / or electromagnetic radiation. Consequently, a wafer-to-wafer bonding tool is provided with shape correction functionality to increase bonding yield. Please note that in this disclosure, “wafer” and “substrate” are used interchangeably.

[0060] According to certain embodiments of the present disclosure, Figures 1A and 1B are plan and perspective views, respectively, of a hybrid system 100. First, hybrid system 100 includes a first module 150 configured for wafer shape correction and a second module 160 configured for wafer bonding. Hybrid system 100 may also include a plurality of wafer handling components and / or carriers. Carrier block 110 includes a station 111 for receiving a wafer carrier 112. Wafer carrier 112 can hold a plurality of (semiconductor) wafers or substrates. Door 114 can be opened to access the plurality of wafers in wafer carrier 112. A first transfer arm 116 can transfer substrates from wafer carrier 112 to a shelf unit 121 in processing block 120. A second transfer arm 123 can be positioned adjacent to shelf unit 121 and can move forward, backward, and vertically. The third transfer arm 125 may then receive the substrate from the shelf unit 121 or the second transfer arm 123 to move it between modules such as the first module group 150 and the second module group 160 .

[0061] In this example, the first module group 150 (or wafer shape correction module) includes modules 131, 132, 133, 134, 135, 136, 137, 138, and 139. Specifically, modules 131 to 139 may include a measurement module 131, a deposition module 132, a coating module 133, a baking module 134, an imaging module 135, a developing module 136, an etching module 137, a cleaning module 138, and a first inspection module 139.

[0062] Briefly, the metrology module 131 can be configured to measure wafer shape data, such as the warp of a substrate, and generate a warp measurement result that maps z-height deviations on the substrate relative to one or more reference z-height values. The deposition module 132 can be configured to deposit one or more films on the backside surface of the substrate (or on the front working surface of the substrate). The coating module 133 can be configured to coat the backside surface of the substrate (or the front working surface of the substrate) with a radiation-sensitive material, such as a photoresist. The bake module 134 can be configured to bake the radiation-sensitive material. The imaging module 135 can be configured to expose the radiation-sensitive material to a pattern of actinic radiation based on an overlay correction pattern, which will be described later. The development module 136 can be configured to develop the radiation-sensitive material after exposure or imaging. The etching module 137 can be configured to use plasma, vapor etching, or wet etching. The cleaning module 138 can be configured to remove any remaining (or residual) radiation-sensitive material from the substrate after the etching operation. The first inspection module 139 can be configured to inspect for defects after the overlay correction process. Please note that a brief description of modules 131 through 139 is provided herein for illustrative purposes. A detailed description and examples of modules 131 through 139 can be found in Applicant's issued U.S. Patent No. 10,475,657, which is incorporated herein by reference in its entirety.

[0063] Although the example of FIG. 1A shows all modules 131-139 included, first module group 150 may include only one or more of modules 131-139 depending on specific design requirements in other examples. In one embodiment, first module group 150 may include modules 131-138 without first inspection module 139. In another embodiment, first module group 150 may include modules 131-135 without modules 136-138. In yet another embodiment, first module group 150 may include modules 131-132 without modules 133-138. Note that at least one of modules 131-139 may be replaced by an external or external tool. In some examples, wafer metrology is performed in an external metrology tool, eliminating the need for metrology module 131. In some examples, film formation is performed in an external or external deposition tool, eliminating the need for deposition module 132 and / or coating module 133. Furthermore, for a given module among modules 131 to 139, the first set of modules 150 may include any number of the given modules. For example, the first set of modules 150 may include two metrology modules 131 to enable simultaneous characterization of two substrates. In alternative embodiments, a single metrology module 131 may be used to sequentially or simultaneously characterize two substrates.

[0064] In FIG1A , the second module group 160 (or wafer bonding module) includes modules 161 , 162 , 163 , 164 , and 165 . Specifically, modules 161 to 165 may include a surface preparation module 161 , an alignment module 162 , a (pre-)bonding module 163 , a second inspection module 164 , and an annealing module 165 .

[0065] The surface preparation module 161 can be configured to pre-treat one or more substrate surfaces for subsequent bonding. For example, the surface preparation module 161 can include a plasma apparatus configured to generate plasma and perform a plasma activation process on one or more substrates. The plasma activation process typically involves impinging a plasma species on the substrate surface and chemically activating the substrate surface. The surface preparation module 161 can further include a cleaning apparatus configured to rinse the activated substrate surface with deionized water. It should be noted that, depending on the given process performed using the surface preparation module 161, the surface preparation module 161 can also be referred to as a cleaning module, an etching module, an activation module, a pretreatment module, and / or the like.

[0066] The alignment module 162 can be configured to align the two substrates prior to bonding. For example, the two substrates can each include features such as alignment marks, and the alignment module 162 can be configured to align the alignment marks. Alignment modules are well known.

[0067] In this example, the (pre-)bonding module 163 can be configured to pre-bond or bond the two substrates together. For example, the two substrates can be pre-bonded at a relatively low temperature, such as approximately room temperature or 25°C. A second inspection module 164 can optionally be configured to inspect alignment after pre-bonding, for example using infrared (IR) transmission imaging. The annealing module 165 can be configured to anneal the two substrates at a relatively high temperature, such as in the range of 25 to 400°C, to further bond the two substrates. In the example of FIG1A , the alignment module 162 and the (pre-)bonding module 163 are shown as two separate modules. In another example (not shown), the alignment module 162 and the (pre-)bonding module 163 can be an integrated module in which active alignment is performed immediately prior to (pre-)bonding. That is, wafer alignment and (pre-)bonding can be performed sequentially in a single module (e.g., a single tool, a single chamber, etc.), without wafer transfer between alignment and (pre-)bonding.

[0068] Although the example of FIG. 1A shows all modules 161-165 included, the second module group 160 may include one or more of modules 161-165 depending on specific design requirements in other examples. For example, the second module group 160 may include modules 161-163 and 165 without the second inspection module 164. Furthermore, the second module group 160 may include any number of specific modules for a specific module among modules 161-165. For example, the second module group 160 may include two surface preparation modules 161 so that two substrates can be pre-processed simultaneously. In alternative embodiments, one surface preparation module 161 may be used to pre-process two substrates sequentially or simultaneously.

[0069] Furthermore, the second set of modules 160 is configured to bond the two substrates via plasma activated bonding and, accordingly, in some embodiments, includes modules 161 through 165. In other embodiments, the second set of modules 160 may be configured to bond the two substrates via another wafer bonding technique, such as fusion bonding, surface activated bonding, anodic bonding, eutectic bonding, glass adhesive bonding, adhesion bonding, thermocompression bonding, reaction bonding, transient liquid phase diffusion bonding, or the like. Accordingly, the second set of modules 160 may or may not include modules 161 through 165. For example, in the case of surface activated bonding, a surface preparation module (or cleaning module) may be configured to clean the two substrates via rapid atomic bombardment to atomically clean and activate the surfaces of the two substrates. The two substrates may then be aligned in the alignment module 162 and bonded together in the bonding module. Therefore, the second set of modules 160 can be simplified to include three modules (i.e., a surface preparation module, an alignment module 162, and a bonding module), or can further include additional modules, such as an inspection module for checking alignment after bonding. In the case of fusion bonding, the two silicon substrates can be cleaned by a surface preparation module (or etching module) configured to perform a dry or wet etching process on the two silicon substrates to achieve the required cleanliness for pre-bonding. The surface preparation module can further rinse the two silicon substrates with deionized water to render the silicon surfaces hydrophilic. The two silicon substrates can then be aligned in the alignment module 162, pre-bonded in the (pre-)bonding module 163 (optionally inspected using the second inspection module 164), and annealed in the annealing module 165.

[0070] Note that the first module set 150 and the second module set 160 may share one or more modules. For example, the first module set 150 and the second module set 160 may include a shared cleaning module configured to remove residual radiation-sensitive material after etching and to clean both substrates prior to pre-bonding or bonding. In other words, the shared cleaning module is configured to perform the functions of the cleaning module 138 and the surface preparation module 161. Furthermore, while modules 131-139 and modules 161-165 are shown as being arranged in two consecutive rows in FIG. 1A , it should be understood that modules 131-139 and 161-165 may be arranged in any configuration and have any relative positions.

[0071] Note that the deposition module 132 and the coating module 133 may be collectively or individually referred to as a stressor film deposition module. The baking module 134, the imaging module 135, the developing module 136, the etching module 137, the cleaning module 138, and the first inspection module 139 may be collectively or individually referred to as a stressor film modification module. Although modules 131-139 and 161-165 are shown as being located in processing block 120, it should be understood that one or more of modules 131-139 and 161-165 may be located in other processing blocks, such as processing block 130.

[0072] Still referring to FIG. 1A , controller 140 is connected to or included in hybrid system 100 . Controller 140 can be a computer processor located within hybrid system 100 or remotely but in communication with components of hybrid system 100 . Controller 140 can be configured to receive wafer shape data (e.g., warp measurements) and generate a modification map (e.g., an overlay correction pattern) based on the warp measurements. The warp measurements can be received from metrology module 131 or from another system. The overlay correction pattern defines stress adjustments within the substrate (e.g., at specific locations on the substrate) based on the warp measurements. In addition to the warp measurements, the overlay correction pattern can also be based on device parameters of the front working surface of the substrate. For example, relatively deep memory arrays may require more stress modifications than in the early stages of building finFET devices for logic. Overlay correction patterns may be generated or calculated using any of a number of computational methods, such as inter-plane deviation, z-height deviation from a reference plane, multi-order derivative analysis for locations of interest, analysis of Zernike polynomials, pixelated basis function optimization, or spherical Bessel functions.

[0073] In an overlay correction pattern, a first predetermined location on the substrate may have a different defined internal stress adjustment than a second predetermined location on the substrate in the overlay correction pattern. In other words, the stress adjustment to be performed can be specific to a location on the substrate surface. This location can be a point, area, or region of the substrate. For example, the overlay correction pattern can define an internal stress adjustment that produces a flat substrate (no warpage) or a selected warpage that is beneficial for subsequent patterning processes. Such internal stress adjustment can be based on the type and thickness of a film deposited on the rear surface of the substrate or the front working surface of the substrate.

[0074] In certain embodiments, controller 140 can be coupled to various components (e.g., modules) of hybrid system 100 to receive inputs from or provide outputs to the various components. Controller 140 can be configured to control at least one module selected from the group consisting of modules 131 to 139 and 161 to 165. For example, controller 140 can be configured to receive wafer shape data from metrology module 131. Controller 140 can also be configured to adjust knobs and control settings for metrology module 131. Furthermore, it should be understood that one or more functions of controller 140 described herein can be implemented manually. For example, knob adjustments for metrology module 131 can be made manually.

[0075] Furthermore, the components of the hybrid system 100 can be connected to and controlled by a controller 140, which can optionally be connected to a corresponding memory storage unit and a user interface (neither shown). Various module operations can be executed via the user interface, and various processing recipes and operations can be stored in the memory unit. Accordingly, a variety of micromachining techniques can be used to process a given substrate within the hybrid system 100.

[0076] Controller 140 can be implemented in a wide variety of ways. In one example, controller 140 is a computer. In another example, controller 140 includes one or more programmable integrated circuits (ICs) programmed to provide the functionality described herein. For example, one or more processors (e.g., microprocessors, microcontrollers, central processing units, etc.), programmable logic devices (e.g., complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), etc.), and / or other programmable ICs can be programmed using software or other programming instructions to implement the functionality of a specified plasma process recipe. It is further noted that the software or other programming instructions can be stored in one or more non-transitory computer-readable media (e.g., memory storage devices, flash memory, DRAM memory, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), and when executed by the programmable ICs, the software or other programming instructions cause the programmable ICs to perform the processes, functions, and / or capabilities described herein. Other variations are also possible.

[0077] Furthermore, warp measurement herein may include measuring the degree of convexity or concavity, or mapping z-height deviation on the substrate relative to one or more reference z-height values. In other words, z-height deviation may be spatially mapped, for example, using coordinate positions to identify z-height deviation across the substrate surface. Warp and z-height deviation mapping may be performed at various resolutions, depending on the type of metrology equipment used and / or the desired resolution.

[0078] Warp measurements can include raw warp data or be expressed as warp signatures with relative values. Note that in many embodiments, the reference z-height values ​​may all be close to zero, thus representing a nearly flat wafer. For example, a nearly flat or considered flat wafer for overlay improvement purposes herein may be one with an average deviation of less than 10 microns.

[0079] Furthermore, the hybrid system 100 may include one or more processing modules (e.g., the first set of modules 150) having a substrate holder and a substrate processing assembly. The substrate processing assembly is configured to modify internal stress on the substrate at specific locations on the substrate according to an overlay correction pattern, thereby generating a modified warp of the substrate. The substrate having the modified warp has a modified overlay error. The modified overlay error has a reduced overlay error compared to the initial overlay error. In the case where the one or more processing modules are configured to independently modify different locations on the substrate, the first set of modules 150 may be configured to modify the internal stress differently, such that at least a portion of the different locations are modified differently from one another. While global or uniform / symmetrical internal stress correction can be performed, the processing modules herein may be configured to modify stress based on coordinate locations on the substrate.

[0080] The first set of modules 150 can be configured to increase or relax internal stress at a location on the substrate and to modify the internal stress on either the front working surface or the rear surface. The first set of modules 150 can be configured to hold the substrate with the front working surface facing upward (away from the Earth's gravity) when physically modifying the internal stress on the rear surface of the substrate.

[0081] In situations where a first given location on the substrate can have more material added than a second given location, the first set of modules 150 can be configured to modify the internal stress on the substrate by adding material at specific locations on the rear surface of the substrate. For example, the rear deposition system can utilize chemical vapor deposition when a pattern of light or heat is projected onto the rear surface. Because chemical vapor deposition can be temperature-dependent, more or less material can be deposited based on the light or heat pattern projected onto the rear surface. Consequently, different amounts of material are deposited depending on the coordinate location. Once this differential deposition process is complete, the substrate exhibits a modified warpage that corrects or reduces overlay error.

[0082] In other embodiments, where more material may be removed from a first given location on the substrate than from a second given location, the first set of modules 150 may be configured to modify the internal stress in the substrate by removing material at specific locations on the substrate's backside surface. This may include first adding one or more films to the substrate's backside surface and then selectively removing material from the one or more films at the given locations, for example, by etching the backside surface using an etch mask. In other embodiments, where more particles may be implanted at a first given location on the substrate than at a second given location, the processing module may be configured to modify the internal stress in the substrate by implanting particles at specific locations on the substrate's backside surface. For example, an ion implantation tool may implant particles into the working surface or backside surface to increase or decrease tensile / compressive forces, thereby altering the warpage of the substrate. This selective increase or decrease may depend on the type of surface material being processed and the type of particles being implanted. The processing module may be configured to modify the internal stress in the substrate by temperature-modulating specific locations of the cured film. A given cured film may exhibit stronger or weaker bonds depending on the curing temperature. Temperature modulation can be achieved by using heat or light projection during curing, where individual projected pixels can be independently addressed or intensity varied based on an overlay calibration pattern.

[0083] Depending on the type of stress modification performed on the substrate, the process may be performed in one or more modules. Accordingly, multiple modules may be optionally used. While there are numerous mechanisms for modifying stress (e.g., differential deposition, differential curing, ion implantation, selective etching, etc.), for ease of description, this disclosure will provide more exemplary embodiments related to selective etching.

[0084] FIG2A illustrates an example of a wafer shape correction process 200A, in which top and bottom wafers to be bonded undergo wafer metrology to record the warpage characteristics of both wafers. While the depicted process (200A) performs metrology sequentially before the application of the shape control layer(s), data (e.g., bow metrology) can be collected at previous points along the line and fed forward. Depending on the integration situation, the target shape correction can be applied to both wafers or only one. Using the metrology data (e.g., bow metrology), computational methods can be employed to generate a pattern to achieve the desired shape manipulation. This pattern can be recorded in the shape control layer(s) to achieve the optimal shape. With the optimized shape, the two wafers (i.e., top and bottom wafers) then continue the normal integration process via the W2W bonding process, resulting in a sample that is easier to handle / grip in the bonder and produces improved bonding metrics.

[0085] Specifically, in form 201, wafers, such as process warp wafers, are provided. At least one of the wafers may have an initial overlay error resulting from one or more micromachining steps performed to fabricate at least a portion of a semiconductor device on a working surface of the at least one wafer. For example, a transistor gate may be completed or only partially completed.

[0086] Typically, a wafer has a front working surface and a backside surface. The front working surface is the surface on which semiconductor devices, such as transistors, diodes, gates, wiring, etc., are fabricated. The backside surface is typically opposite the front working surface and, in related embodiments, is typically clamped or snapped to a substrate support. Techniques herein include deposition of films on the backside surface to modify or regulate internal stress and alter wafer warpage or first-order curvature.

[0087] Please note that the terms front working surface and backside surface are used herein to refer to opposite sides of a wafer. In certain micromachining processes, a given wafer may have active devices or power delivery structures formed on both sides. In other words, the backside surface can also be a working surface for forming semiconductor devices. For illustrative purposes, this disclosure will use the backside surface of a wafer as an example to demonstrate wafer shape control.

[0088] The wafers provided in form 201 may include two wafers to be bonded together, namely, a first wafer and a second wafer. Form 203 shows an example of the first wafer (the second wafer is omitted for simplicity). Block 210A shows an example of a wafer shape control module (or wafer shape correction module) configured to perform internal stress adjustment on one or both of the two wafers. The internal stress adjustment is configured to produce a flat wafer(s) or a selected warp that is beneficial for subsequent patterning and / or bonding processes. For example, the selected warp may include two warp profiles that cancel each other out when the two wafers are bonded. The two warp profiles may be opposite or symmetrical to each other. The selected warp may also include two warp profiles that are similar or identical to each other so that alignment / overlay errors can be eliminated.

[0089] In state 211, wafer metrology is performed on two wafers to obtain wafer shape data for both wafers, such as warp measurements including relative z-height values. Wafer metrology can be performed, for example, by metrology module 131 or by an external metrology tool. A control unit 212 can be configured to generate a first modification map based on the wafer shape data of the first wafer and the second wafer. The first modification map is configured to define adjustments to stress within the first wafer. The control unit 212 can be implemented by controller 140. In certain embodiments, the control unit 212 can be configured to receive and / or store historical data, such as wafer shape data of historical wafers that have undergone shape correction and bonding, and / or other overlapping information. The historical data can be used alone or in combination with the wafer shape data of the first wafer and the second wafer to generate the first modification map.

[0090] In aspect 213 , a stressor film, including a shape-control layer, may be applied to or deposited on at least one of the two wafers. The stressor film may be deposited by a stressor film deposition module (i.e., deposition module 132 and / or coating module 133 ) or by an external film deposition tool. For example, a first stressor film may be deposited on the backside surface of the first wafer. The first stressor film may be deposited based on a first modification map. Specifically, the first modification map may include information regarding the first stressor film, such as the type(s) of material(s), thickness(es), and so on.

[0091] In form 215, specific location activation is performed, for example, by at least one module selected from the group consisting of the bake module 134, the imaging module 135, the developer module 136, and the etch module 137. Finally, form 205 illustrates an example of a first wafer after shape control or shape correction (the second wafer is omitted for simplicity). Form 205 may exhibit reduced warpage or reduced overlay error compared to form 203.

[0092] In some embodiments, the first stressor film is modified by exposing it to a pattern of electromagnetic radiation based on a first modification pattern. This exposure can be performed by an imaging module 135. The first stressor film can be crosslinked / decrosslinked to induce internal stress modulation due to the exposure. Optionally, the first stressor film can be baked, for example, in a bake module 134. This baking can further promote crosslinking / decrosslinking. Optionally, the photoresist layer of the first stressor film can be developed to form a relief pattern, for example, in a developer module 136. Optionally, the shape-control layer of the first stressor film can be etched using the relief pattern as an etch mask, for example, in an etch module 137. In some embodiments, the first stressor film is modified by a thermal treatment based on the first modification pattern. Optionally, the first stressor film can be developed and / or etched thereafter. In some embodiments, a relatively uniform blanket film (e.g., a spin-on material) can be deposited and selectively activated via UV and / or thermal treatment. No film needs to be removed.

[0093] It should be noted that the first modified map is based on the wafer shape data of the two wafers and can therefore be specific to both wafers. In other words, the first modified map can be varied during the W2W process. Therefore, imaging module 135 can include a programmable direct-write exposure device. Thus, the direct-write exposure device can be configured to expose the first stressor film to a pattern of electromagnetic radiation based on (a variation of) the first modified map. Further details regarding direct-write can be found in applicant's pending U.S. patent application Ser. No. 17 / 703,072, filed on March 24, 2022, which is incorporated herein by reference in its entirety.

[0094] Furthermore, the first stressor film can be any combination of films present on the front and / or backside of the first wafer, such as oxide films, nitride films, and / or spin-on films. The activation process can be the result of any combination of implantation, etching, radiation, and / or temperature. An example of such an embodiment is depicted in Figures 3A to 3F. In this embodiment, a CVD (chemical vapor deposition) SiN film is used as the shape control layer for the first stressor film. The activation process includes applying a photosensitive layer, selectively exposing the photoresist (i.e., the photosensitive layer) using a compatible wavelength, opening the exposed areas using a solvent developer, and selectively removing the SiN using a wet or RIE (reactive ion etching) process to achieve the desired wafer shape. It should be noted that in some cases, activation may not be required at all, and the desired performance can be achieved by using a native blanket control layer(s). For example, in Figures 3A to 3F, the process can end after depositing the SiN (stress control) layer. In this case, the first modified diagram does not include a pattern, resulting in the deposition of the SiN layer and its use as a blanket film.

[0095] Specifically, in FIG3A , a shape-control layer 303 of a first stressor film is deposited on the backside of a first wafer 301. In this example, the shape-control layer 303 is a SiN layer formed by CVD, for example, in a deposition module 132 . In FIG3B , a photoresist layer 305 of the first stressor film is formed on the shape-control layer 303, for example, by spin coating deposition, for example, in a coating module 133 . In FIG3C , the photoresist layer 305 is exposed to a pattern of electromagnetic radiation based on a first modified image, for example, in an imaging module 135 . In FIG3D , the photoresist layer 305 is developed, for example, in a developer module 136 , to form a relief pattern. In FIG3E , the shape-control layer 303 is etched, for example, in an etch module 137 , using the relief pattern as an etch mask. In FIG3F , the photoresist layer 305 is removed, for example, by an etching process in the etching module 137 and optionally by a cleaning process in the cleaning module 138. Although not shown, the photoresist layer 305 may be optionally baked between FIG3B and FIG3C and / or between FIG3C and FIG3D , for example, in the baking module 134. Furthermore, the photoresist layer 305 may be formed based on the first modified pattern.

[0096] As shown in Figures 3A-3F , imaging module 135 can selectively activate the first stressor film via electromagnetic radiation, similar to conventional lithography practices in the industry. Alternatively, such patterning can be performed by locally heating the wafer using a hot plate (or heating plate) with zoned temperature control, or a heating array as shown in Figures 4A-4C . In some embodiments, wafer shape modification / correction can include using both electromagnetic radiation and heat as activation media.

[0097] Figure 4A shows a plan view of a heating array 400A according to one embodiment of the present disclosure. As illustrated, heating array 400A may include individual components, such as those shown by 410a', 410b', 410c', 410p', 410q', and 410r'. The individual components can be configured to generate heat independently of one another, thereby creating heating zones with independent temperature control. The size, location, and temperature of each heating zone are determined by the individual components.

[0098] In certain embodiments, heating array 400A comprises an array of resistors. Each resistor can be configured to generate a specific amount of heat based on a specific current flowing therethrough. At least one resistor can be integrated into a wafer chuck configured to hold a wafer, such as a first wafer. Thus, the at least one resistor can be in direct contact with the wafer. Alternatively, the at least one resistor can be placed close to the wafer so that it can effectively heat the wafer without touching it. For example, the distance between the at least one resistor and the wafer can be between 0 mm (contact) and 5 mm. Of course, heating array 400A can include a combination of both types of resistors. Furthermore, multiple heating arrays 400A can be implemented. For example, a lower heating array for the lower wafer chuck and an upper heating array for the upper wafer chuck can be implemented. The lower and upper heating arrays can each have a configurable height position relative to their respective wafer chucks.

[0099] FIG4B illustrates a first pattern 400B of heating zones generated by a heating array 400A, according to one embodiment of the present disclosure. Here, darker colors represent higher temperatures, while lighter colors represent lower temperatures. For example, zone 410a has a higher temperature than zone 410b, which in turn has a higher temperature than zone 410c. A varying temperature profile can be used to induce varying degrees of internal stress modulation in the stressor film, and thus, the wafer. Specifically, the first pattern 400B of heating zones includes a line pattern 420 in which zones have the same temperature. Zone 410c may represent a background temperature, e.g., where no heat is generated. The resistors of the heating array 400A can locally heat the wafer, thereby selectively activating the stressor film in a location-specific manner.

[0100] FIG4C shows a second pattern 400C of heating zones generated by heating array 400A according to another embodiment of the present disclosure. Similarly, darker colors represent higher temperatures, while lighter colors represent lower temperatures. For example, zone 410p has a higher temperature than zone 410q, which in turn has a higher temperature than zone 410r.

[0101] Note that regions 410a, 410b, 410c, 410p, 410q, and 410r correspond to individual components 410a', 410b', 410c', 410p', 410q', and 410r', respectively. Although the overall shape of heating array 400A in this example resembles a circular wafer, heating array 400A may have any other shape. The individual components of heating array 400A may also have any shape. Each individual component may include multiple resistors. Therefore, the size of the individual components need not be of the same order as the patterning resolution. For example, individual component 410a' may be of the order of 33 mm x 26 mm and may include smaller resistors, such as micro- and / or nano-resistors.

[0102] Furthermore, the heating array 400A can be included in the hybrid system 100 as a separate heating module (not shown), within the bake module 134, or within the deposition module 132. When the heating array 400A is included within the deposition module 132, the deposition module 132 can perform patterning during deposition to form an as-deposited patterned film. This patterned film does not require modification after film formation and prior to future wafer alignment. For example, CVD is temperature-dependent. Independent deposition rate control of the first stressor film can be achieved using the heating zones of the heating array 400A.

[0103] Although not shown, a laser system can also be used to heat the wafer chuck and / or directly heat the wafer. A wavelength that is absorptive at the wafer chuck and / or wafer can be selected to cause heating.

[0104] Referring back to FIG. 2A , the wafer shape correction process 200A is described using a first wafer as an example, while the second wafer is omitted for simplicity. In one embodiment, the second wafer is characterized by wafer metrology in form 211 but does not undergo the processes shown in forms 213 and 215. In other words, internal stress adjustment is performed only on the first wafer. In another embodiment, the second wafer is characterized by wafer metrology in form 211 and undergoes the processes shown in forms 213 and 215. Detailed descriptions have been provided above and will be omitted here for simplicity. In short, internal stress adjustment is performed on both the first and second wafers. A second stressor film can be formed on the second wafer and modified based on a second modification map that defines the adjustment to the internal stress of the second wafer. The second modification map can be generated based on the wafer shape data of the first and second wafers.

[0105] The hardware required to implement the processing necessary to achieve the wafer shape control detailed in this disclosure requires modules not present in any commercially available semiconductor wafer-to-wafer bonding tools. Using the wafer shape correction methods disclosed herein to optimize the wafer bonding process requires offline wafer shape correction before reaching the bonding tool. This is undesirable because inserting another tool into the integrated flow significantly impacts manufacturing yield and introduces redundant wafer handling. The embodiments disclosed herein maintain the core functionality of the bonding tool (e.g., plasma activation, hydrophilization, alignment, bonding, etc.), but also include patterning modules that perform wafer shape control, such as, but not limited to, warp metrology, coating, exposure and development, or other stress activation processes. By creating a hybrid bonding-patterning tool, the yield improvements achieved through wafer shape control can be achieved without the yield reduction caused by offline processing.

[0106] An exemplary embodiment and configuration is depicted in FIG2B . Embodiments include a unified platform or separate tools for wafer-to-wafer bonding to modify the wafer shape of at least one wafer in a wafer pair to be bonded. Such a system includes one or more wafer shape modification modules (e.g., first set of modules 150 ) and one or more bonding modules (e.g., second set of modules 160 ). Exemplary systems (e.g., hybrid system 100 ) may also include conventional wafer handling robots to move wafers between modules and submodules.

[0107] Accordingly, exemplary embodiments include semiconductor tools that maintain the core functionality of conventional W2W bonding platforms while also integrating patterning modules (e.g., coating, exposure, development, etc.) into the bonder to facilitate wafer shape manipulation. Exposure, imaging, or activation modules may include electromagnetic radiation and / or location-specific heating amplification. The semiconductor tool is capable of accessing both the front and back sides of the wafer for processing. The semiconductor tool may include integrated metrology to evaluate incoming wafer shape. The semiconductor tool may also include integrated metrology to evaluate post-bonding alignment metrics.

[0108] While stress control (or wafer shape control) is deposited within the tool in the preferred embodiment, semiconductor tools can accommodate wafers with externally applied films on different platforms. Spin-on stress control films (spin-on stressor films) are preferred for wafer shape correction. CVD film deposition is an alternative film deposition technique that includes patterning of such films.

[0109] As shown in FIG2B , process 200B includes block 210B configured for wafer shape control / correction and block 220 configured for wafer alignment and bonding. Identical components in FIG2A and 2B are labeled identically, such as 201, 203, 205, 211, 212, and 213. Block 210B may comprise an example of block 210A. Specifically, activation of specific locations in block 215 is accomplished by exposing a correction image in block 217 and developing the correction image in block 219. Such a correction image may, for example, be a first modified image. Similarly, internal stress adjustment may be performed on the first wafer but not on the second wafer. Alternatively, internal stress adjustment may be performed on both the first and second wafers.

[0110] In block 220, the first wafer and the second wafer may be (pre-)bonded together. In form 211, a plasma activation process is performed on the first and second wafers, for example, by the surface preparation module 161. In form 223, the first and second wafers are cleaned using deionized water (DIW), for example, by the surface preparation module 161. In form 225, the first and second wafers are aligned, for example, by the alignment module 162, and (pre-)bonded, for example, by the (pre-)bonding module 163. In form 227, the (pre-)bonded wafers are inspected using IR transmission imaging, for example, by the second inspection module 164. In form 207, the (pre-)bonded wafers may be stripped and cleaned, for example, by the cleaning module 138 and / or the surface preparation module 161. The (pre-)bonded wafers may be further bonded, for example, by the annealing module 165. It should be understood that the first wafer and the second wafer may alternatively be bonded by other processes or techniques as described earlier in the second set of modules 160. In some embodiments, block 220 may include form 207.

[0111] FIG5 shows a flow chart of a process 500 for wafer bonding according to certain embodiments of the present disclosure. Process 500 begins at step S510, where a first modification map is generated based on wafer shape data of a first wafer and a second wafer. The first modification map defines an adjustment to internal stress in the first wafer. Process 500 then proceeds to step S510 by modifying the first wafer shape of the first wafer by forming a first stressor film on the first wafer based on the first modification map. In step S530, the first wafer and the second wafer are aligned after step S520. In step S540, the first wafer is bonded to the second wafer.

[0112] In the preceding description, specific details have been set forth, such as the specific geometry of the processing system and descriptions of the various components and processes used in the system. However, it should be understood that the technology herein can be practiced in other embodiments that depart from these specific details, and thus such details are provided for purposes of illustration, not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of illustration, specific symbols, materials, and configurations have been set forth to provide a thorough understanding. Nevertheless, the embodiments may be practiced without such specific details. Components having substantially the same functional structure are designated by the same reference numerals, and any redundant description may be omitted.

[0113] The various techniques have been described as discrete operations to facilitate understanding of the various embodiments. The order of description should not be construed as implying that the operations must be performed in that order. In fact, the operations do not need to be performed in the order presented. The operations may be performed in a different order than the described embodiments. In additional embodiments, additional operations may be performed and / or the operations described may be omitted.

[0114] As used herein, the term "substrate" or "wafer" generally refers to an object processed in accordance with the present invention. A substrate can include any material portion or structure of a device, particularly a semiconductor or other electronic device, and can be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer, such as a thin film, on or overlying a base substrate structure. Thus, a substrate is not limited to any particular base structure, underlying or overlying layer, patterned or unpatterned, but is intended to include any such layer or base structure, as well as any combination of layers and / or base structures. While the description may refer to a specific type of substrate, this is for illustrative purposes only.

[0115] The substrate can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate can include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. Group IV semiconductors can include Si, Ge, or SiGe. The substrate can include a bulk wafer or an epitaxial layer.

[0116] Those skilled in the art will appreciate that many variations of the above-described techniques can be implemented while still achieving the objectives of the present invention. Such variations are intended to be encompassed by the scope of this disclosure. Therefore, the foregoing description of the embodiments of the present invention is not intended to be limiting. Rather, any limitations of the embodiments of the present invention are set forth in the following claims.

[0117] 100: Hybrid system 110: Vehicle Block 111: Platform 112: Wafer carrier 114: Door 116: First transfer arm 120,130: Processing blocks 121: Scaffolding unit 123: Second transfer arm 125: Third transfer arm 131: Measurement module 132:Deposition Module 133: coating module 134: Baking module 135: Imaging module 136: Development module 137: Etching module 138: Cleaning module 139: First inspection module 140:Controller 150: The first set of modules 160: The second set of modules 161: Surface preparation module 162: Alignment module 163: (Pre) bonding module 164: Second inspection module 165: Annealing module 200A, 200B: Wafer shape correction process 201,203,205,207,211,213,215,217,219,221,223,225,227: Morphology 210A, 210B, 220: Block 212: Control unit 301: First wafer 303:Shape Control Layer 305: Photoresist layer 400A: Heating array 400B: First pattern 400C: Second pattern 410a',410b',410c',410p',410q',410r': Components 410a, 410b, 410c, 410p, 410q, 410r: Area 420: Line pattern 500:Process S510, S520, S530, S540: Steps 900A: Alignment System 900B: Misaligned system 910: First Wafer 913a, 913b, 913c: first interconnect structure 920: Second wafer 923a, 923b, 923c: Second interconnect structure

Claims

1. An apparatus for bonding wafers together, the apparatus comprising: a first set of modules configured for wafer shape correction, the first set of modules comprising: a measurement module configured to measure wafer shape data of a first wafer and a second wafer, the first wafer having a front working surface and a rear surface opposite to the front working surface; a stress source film deposition module configured to form a first stress source film on the rear surface of the first wafer; and a stress source film modification module configured to modify the first stress source film based on a first modification pattern, the first modification pattern defining an adjustment for internal stress of the first wafer, the first modification pattern being generated based on the wafer shape data of the first wafer and the second wafer; and a second set of modules configured for bonding the first wafer and the second wafer, the second set of modules comprising: An alignment module is configured to align the first wafer with the second wafer, and a bonding module is configured to bond the front working surface of the first wafer to the second wafer; wherein the stress source film deposition module is configured to form the first stress source film on the rear surface of the first wafer based on the first modification pattern; and wherein the stress source film modification module includes a heating array with independently temperature-controlled heating zones, each of the heating zones including a micrometer or nanometer resistor, each of the micrometer or nanometer resistors being configured to generate a separate amount of heat based on a separate current flowing through it.

2. The apparatus of claim 1, wherein the stress source film deposition module comprises at least one of a spin coating apparatus, a spray coating apparatus, or a vapor deposition apparatus.

3. The apparatus of claim 1, wherein the stress source film modification module includes a write-through exposure device configured to expose the first stress source film to a pattern of electromagnetic radiation based on one of the first modification patterns.

4. The apparatus of claim 3, wherein the stress source film modification module includes a developing apparatus configured to develop a photoresist layer of the first stress source film to form an embossed pattern.

5. The apparatus of claim 4, wherein the stress source film modification module includes an etching apparatus configured to use the relief pattern as an etching mask to etch a shape control layer of the first stress source film.

6. The apparatus of claim 1, wherein the stress source membrane modification module includes a hot plate with zoned temperature control.

7. The apparatus of claim 1, wherein at least one of the micrometer or nanometer resistors is integrated into a wafer chuck configured to hold the first wafer.

8. The apparatus of claim 1, wherein the stress source film modification module includes a laser system configured to heat at least one of the first wafer or a wafer chuck, the wafer chuck being configured to hold the first wafer.

9. The apparatus of claim 1, further comprising a controller configured to generate the first modified pattern based on the wafer shape data of the first wafer and the second wafer.

10. The apparatus of claim 9, wherein the controller is configured to receive input from at least one module and provide output to the at least one module, the at least one module being selected from the group consisting of the measurement module, the stress source film deposition module, the stress source film modification module, the alignment module and the bonding module.

11. The apparatus of claim 10, wherein the controller is configured to control at least one process selected from the group consisting of: measuring the wafer shape data, depositing the first stress source film, modifying the first stress source film, aligning the first wafer with the second wafer, and bonding the first wafer to the second wafer.

12. The apparatus of claim 9, wherein the controller is configured to generate the first modified drawing based on historical data in addition to the wafer shape data of the first wafer and the second wafer, the historical data including overlap information of historical wafers.

13. The apparatus of claim 1, wherein: The stress source film deposition module is configured to form a second stress source film on the second wafer, and the stress source film modification module is configured to modify the second stress source film based on a second modification map, the second modification map defining the adjustment of stress within the second wafer, the second modification map being generated based on wafer shape data of the first wafer and the second wafer.

14. The apparatus of claim 1, wherein the alignment module and the bonding module are an integrated module such that there is no wafer transfer between alignment and bonding.

15. The apparatus of claim 1 further includes an inspection module configured to inspect the first wafer and the second wafer bonded together.

16. The apparatus of claim 15, wherein the inspection module is configured to inspect the first wafer and the second wafer bonded together via infrared light transmission imaging.

17. An apparatus for bonding wafers together, the apparatus comprising: a first module configured for wafer shape correction, the first module comprising: a measurement module configured to measure wafer shape data of a first wafer and a second wafer, the first wafer having a front working surface and a rear surface opposite the front working surface; and a stress source film deposition module configured to form a first stress source film on the rear surface of the first wafer based on a first modification pattern, the first modification pattern defining an adjustment for internal stress in the first wafer, the first modification pattern being generated based on the wafer shape data of the first wafer and the second wafer; and a second module configured for aligning and bonding the first wafer and the second wafer, the second module comprising: An alignment module configured to align the first wafer with the second wafer without modifying the first stress source film between the formation and the alignment; and a bonding module configured to bond the front working surface of the first wafer to the second wafer; wherein the stress source film deposition module is configured to form the first stress source film on the rear surface of the first wafer based on the first modification pattern; and wherein the stress source film modification module includes a heating array with independently temperature-controlled heating zones, each of the heating zones including a micrometer or nanometer resistor, each of the micrometer or nanometer resistors being configured to generate a separate amount of heat based on a separate current flowing through it.

18. The apparatus of claim 17, wherein: The first modified drawing does not include a pattern, nor does it include the configuration of the stress source film deposition module to form the first stress source film as a blanket coating.

Images