Apparatus and method for accessing data in versions of memory pages

Abstract

An apparatus may include at least one memory and at least one processor, the at least one processor being configured to: determine the accessibility of a first version of a page, wherein the first version of the page is available for storage in the at least one memory; and perform access to at least a portion of a second version of the page based on the accessibility of the first version of the page, wherein the second version of the page is available for storage in the at least one memory. The accessibility of the first version of the page may be based on an erase operation of the first version of the page. Access to at least a portion of the second version of the page may include access to a cache column of the second version of the page.

Description

Technical Field

[0001] This disclosure is generally related to memory systems, and more particularly, to systems, methods, and devices for accessing data in a version of a memory page. Background Art

[0002] Memory systems can include different types of memory, such as volatile memory and / or non-volatile memory. Volatile memory can be configured as a memory cache to provide relatively fast access to data and / or store data that can be accessed relatively frequently. The data stored in the cache can also be stored in a main memory, which can be implemented using, for example, non-volatile memory that can retain data throughout a power cycle.

[0003] The above information disclosed in this background art section is only for enhancing the understanding of the background of the principles of the invention, and thus the above information may include information that does not constitute prior art. Summary of the Invention

[0004] A device may include at least one memory and at least one processor, the at least one processor being configured to: determine the accessibility of a first version of a page, wherein the first version of the page is stored in the at least one memory; and perform an access to at least a portion of a second version of the page based on the accessibility of the first version of the page, wherein the second version of the page is stored in the at least one memory. The accessibility of the first version of the page may be based on an erase operation of the first version of the page. The accessibility of the first version of the page may be based on an access amount of the first version of the page. The accessibility of the first version of the page may be further based on an access amount of the second version of the page. The access to at least a portion of the second version of the page may include an access to a cache column of the second version of the page. The access to at least a portion of the second version of the page may be based on a modification status of the first version of the page. The access to at least a portion of the second version of the page may include an access to a portion of the second version of the page, and the modification status of the first version of the page may be based on a modification status of a portion of the first version of the page corresponding to the portion of the second version of the page. The portion of the first version of the page may include a cache column of the first version of the page, and the portion of the second version of the page may include a cache column of the second version of the page corresponding to the cache column of the first version of the page. The at least one processor may be configured to track a modification status of at least a portion of the second version of the page. The access to at least a portion of the second version of the page may include a read operation. The at least one processor may be configured to: store the first version of the page in a first superblock; and store the second version of the page in a second superblock. The method may further include a cache configured to store the first version of the page, wherein the at least one processor may be configured to track a modification status of the first version of the page. The at least one processor may be configured to evict the first version of the page based on the modification status of the first version of the page. The device may include a storage element, and the at least one memory may include at least one storage medium. The storage element may be configured to operate in a coherent memory mode.

[0005] A method may include: determining the accessibility of a first version of a page, where the first version of the page may be stored in at least one memory; and accessing at least a portion of a second version of the page based on the accessibility of the first version of the page, where the second version of the page may be stored in the at least one memory. The method may further include determining the modification status of a portion of the first version of the page, where accessing the at least a portion of the second version of the page may include accessing a portion of the second version of the page corresponding to the portion of the first version of the page.

[0006] A device may include at least one memory and at least one processor configured to: store a first version of a page in at least one memory; store a second version of the page in the at least one memory; and track the modification status of at least a portion of the first version of the page. The modification status of the at least a portion of the first version of the page may include the modification status of a portion of the first version of the page. The portion of the first version of the page may include a cache line. Brief Description of the Drawings

[0007] The figures are not necessarily drawn to scale, and for illustrative purposes, components of similar structure or function in all figures may generally be represented by the same reference numeral or a portion thereof. Each figure is only intended to facilitate the illustration of the various embodiments set forth herein. Each figure does not illustrate every aspect of the teachings disclosed herein and does not limit the scope of the claims. To prevent the figures from becoming cluttered, not all components, connections, and the like may be shown, and not all components may have reference numerals. However, the pattern of component configurations may be apparent from the figures. The accompanying drawings, together with the description, illustrate exemplary embodiments of the disclosure and, together with the description, are used to explain the principles of the disclosure. FIG. 1 shows an embodiment of a memory device according to an exemplary embodiment of the disclosure. FIG. 2 shows an embodiment of a memory access scheme according to an exemplary embodiment of the disclosure. FIG. 3 shows an embodiment of a data cache according to an exemplary embodiment of the disclosure. FIG. 4 shows an embodiment of a buffered page update table according to an exemplary embodiment of the disclosure. FIG. 5 shows an embodiment of an invalid page map table according to an exemplary embodiment of the disclosure. FIG. 6A shows an exemplary embodiment of a memory device in a first state related to a write operation according to an exemplary embodiment of the disclosure. FIG. 6B shows an exemplary embodiment of the memory device shown in FIG. 6A in a second state related to a write operation according to an exemplary embodiment of the present disclosure. FIG. 7 shows an exemplary embodiment of a method for a write operation for memory device operation according to an exemplary embodiment of the present disclosure. FIG. 8A shows an exemplary embodiment of a memory device in a first state related to an evacuation operation according to an exemplary embodiment of the present disclosure. FIG. 8B shows an exemplary embodiment of the memory device shown in FIG. 8A in a second state related to evacuation according to an exemplary embodiment of the present disclosure. FIG. 9 shows an exemplary embodiment of a method for an evacuation operation for memory device operation according to an exemplary embodiment of the present disclosure. FIG. 10A shows an exemplary embodiment of a memory device in a first state related to a read operation according to an exemplary embodiment of the present disclosure. FIG. 10B shows an exemplary embodiment of the memory device shown in FIG. 10A in a second state related to a read operation according to an exemplary embodiment of the present disclosure. FIG. 11 shows an exemplary embodiment of a method for a read operation for memory device operation according to an exemplary embodiment of the present disclosure. FIG. 12A shows an exemplary embodiment of a memory device in a first state related to a garbage collection operation according to an exemplary embodiment of the present disclosure. FIG. 12B shows an exemplary embodiment of the memory device shown in FIG. 12A in a second state related to a garbage collection operation according to an exemplary embodiment of the present disclosure. FIG. 13 shows an exemplary embodiment of a memory device having pages arranged in super blocks according to an exemplary embodiment of the present disclosure. FIG. 14 shows an exemplary embodiment of an element according to an exemplary embodiment of the present disclosure. FIG. 15 shows an embodiment of a method for accessing versions of pages according to an exemplary embodiment of the present disclosure. Embodiments

[0008] A memory system can store multiple versions of data pages. For example, some memory systems can store data that can be accessed (e.g., written or read) in page units in non-volatile memory. However, non-volatile memory can be erased in larger block units that can include multiple pages. To modify a portion of a data page stored in non-volatile memory, the memory system can write an updated data page (which can include both modified and unmodified portions) to a new page in non-volatile memory. The updated data page (and / or the new page in non-volatile memory where the data can be stored) can be referred to as a valid page. The original page of the data (and / or the original page in non-volatile memory where the data can be stored) can be referred to as an invalid page. For example, when the block where the invalid page is located is filled with invalid pages, the invalid pages can be marked for final erasure. Thus, the memory system can store at least temporarily two different versions of a data page: an invalid version (e.g., an original version or an earlier version), which can include at least some invalid data (e.g., data that has been modified in the corresponding updated version of the page); and a valid version (e.g., an updated version or a later version), which can include only valid data (or data that has been most recently updated compared to the invalid version).

[0009] The memory system can retrieve the valid version of a data page by reading the page in memory where the valid version of the data page can be stored. However, in some cases, the valid pages of the memory may not be easily accessible. For example, if the valid pages of the memory are located on a memory die (e.g., an integrated circuit (IC) chip) that is undergoing an erase operation, the memory system can wait until the erase operation is complete before reading the valid pages of the memory. As an alternative, the memory system can pause the erase operation to read the valid pages of the memory. However, pausing the erase operation can still slow down the read operation. As another example, since the valid pages of the memory can be located on a busy memory die or a busy channel that can have a relatively large number of outstanding input and / or output (I / O or IO) operations, the valid pages of the memory may not be easily accessible. Thus, there can still be a relatively long latency for the memory system to read the valid pages of the memory.

[0010] A memory system may receive a read request for only a portion of a data page stored in a memory (e.g., a non-volatile memory). If the data page stored in the memory was previously updated such that there is also an invalid version of the page stored in the memory, the requested portion of the page may still be valid in the invalid version of the page. For example, when the valid version of the page has been updated and / or stored, the requested portion of the data stored in the invalid page may not have been modified in the valid version of the page.

[0011] For example, if the requested portion of the data is valid in the invalid version of the data page, a memory scheme according to an exemplary embodiment of the present disclosure may access the requested portion of the page from the invalid version of the page. Depending on implementation details, for example, if the corresponding valid version of the page is not readily accessible (e.g., if the valid page is stored on a busy or erased memory die), this may reduce the amount of time involved in accessing the requested data. Depending on implementation details, if the target cache line is not modified, the memory request may be quickly serviced by reading the target cache line from the invalid page without interrupting the erase operation.

[0012] In some embodiments, since the invalid data in the invalid version of the page may correspond to portions of the valid version of the page that may have been modified when the valid version of the page was updated and / or stored, even though the actual data in the invalid version of the page may not have changed, the invalid data in the invalid version of the page may be referred to as modified data (e.g., modified cache line). Similarly, in some embodiments, since the valid data in the invalid version of the page may correspond to portions of the valid version of the page that may not have been modified when the valid version of the page was updated and / or stored, the valid data may be referred to as unmodified data (e.g., unmodified cache line).

[0013] Some embodiments may implement one or more schemes for tracking valid data in invalid pages. For example, an invalid page map data structure may map the logical page number of the valid page of the data to the physical page number of the invalid version of the page. The data structure may also use a mapping such as the valid portion of the data in the invalid version of the page to indicate the location of the valid data within the invalid version of the page.

[0014] According to an exemplary embodiment of the present disclosure, a scheme for accessing data in different versions of a data page can be used in combination with a data caching scheme. For example, a valid version of a data page can initially be stored in both a cache memory and a main memory (e.g., a non-volatile memory). In a write-back configuration, modified data can be written to the version of the page in the cache memory, and a cache page tracking data structure can be updated to indicate that one or more portions of the version of the page in the cache memory have been modified compared to the version of the page stored in the main memory (which can be referred to as an invalid page). When a version of a page (which can be referred to as a valid page) in the cache memory is removed from the cache memory (e.g., by eviction), the version can be written to a new page in the main memory. The cache page tracking data structure can be used to update an invalid page mapping data structure to track valid and invalid data in an invalid version of the page in the main memory.

[0015] In a write-through configuration, modified data can be written to a page in the cache memory and can also be written to a new page in the main memory. Thus, a valid version of the page containing the modified data can be stored in both the cache memory and the main memory. If an earlier version of the page exists in the main memory, the invalid page mapping data structure can be updated to indicate that one or more portions of the valid version of the page (in the cache memory and the main memory) have been modified compared to the earlier version of the page (which can be referred to as an invalid page).

[0016] The present disclosure encompasses many inventive principles. The principles disclosed herein can have independent utilities and can be implemented individually, and not every embodiment can utilize every principle. Additionally, the principles can also be implemented in various combinations, some of which can synergistically amplify some of the beneficial effects of the individual principles.

[0017] FIG. 1 illustrates an embodiment of a memory device according to an exemplary embodiment of the present disclosure. The memory device 102 can include a memory 104 and a controller 106. The controller 106 can store multiple versions of a data page in the memory 104. For example, as shown in FIG. 1, the controller 106 can store a first version 110a (referred to as version A) of a data page in the memory 104. Version A can include portions 0, 1, 2, and 3, each of which can include a first version of some portions of the data page, as indicated by single diagonal shading.

[0018] The controller 106 may also store a second version 110b (referred to as version B) of the data page in the memory 104. Version B may include portions 0, 2, and 3, where the data (or relevant portions of the data) may be substantially the same as the data in portions 0, 2, and 3 of version A, respectively. However, portion 1 of version B may include data that is substantially different from the data in portion 1 of version A, as indicated by the diagonal cross shading. For example, version B of the data page may be created by modifying portion 1 of version A.

[0019] The controller 106 may include tracking logic 108 that may track the data in one or more of the data portions in the first version 110a (version A) of the data page and / or the data portions in the second version 110b (version B) of the data page. For example, the tracking logic 108 may use a data structure (e.g., a mapping table) to track which portions of version A of the data page are substantially the same as the corresponding portions of version B and which portions are substantially different.

[0020] The controller 106 may receive a request 112 to access (e.g., read) portion 3 of version B of the data page stored in the memory 104. The tracking logic 108 may determine that the data in portion 3 of version A of the data page is substantially the same as the data in portion 3 of version B of the data page. Accordingly, the controller 106 may service the request 112 by accessing version A of the data page and sending portion 3 of version A (indicated as 110a-3) along with a response 114 to the request 112.

[0021] The embodiments shown in FIG. 1 are not limited to any particular reason for accessing a particular version of the data page. However, in some embodiments, if version B is relatively less accessible than version A (e.g., because version B may be located on a memory die, module, card, server, rack, and / or similar component that may be undergoing an erase operation, experiencing relatively high traffic, experiencing a failure, power outage, and / or similar condition, having a relatively long latency, having a relatively high power consumption, having a relatively low bandwidth, and / or similar condition), then the controller 106 and / or the tracking logic 108 may access version A of the page data.

[0022] The embodiments shown in FIG. 1 are not limited to any particular order, reason, and / or similar elements for storing data pages 110a and 110b. However, in some embodiments, the memory 104 can be implemented using non-volatile memory, which can be accessed (e.g., written to and / or read from) in page units, and the non-volatile memory can be erased in block units that can include multiple pages. Version A can be an earlier version of the data page stored in the memory 104, and version B can be a newer version in which part 1 has been updated with new data. Since the memory 104 can be written in page units, version B can be written to a new page of the memory 104 to update part 1. Thus, version A can still exist (at least temporarily) in the memory 104 until version A is erased, for example, by a garbage collection process.

[0023] The embodiments shown in FIG. 1 and / or the components of the embodiments are not limited to any particular form or configuration. For example, in some embodiments, the memory device 102, the memory 104, and / or the controller 106 can be implemented using at least one or more memory elements (e.g., individual memory dies or stacked memory dies based on any memory technology (e.g., integrated circuit (IC) chips)), and the one or more memory elements include volatile memory (e.g., dynamic random access memory (DRAM) and / or static random access memory (SRAM)), non-volatile memory (including flash memory, persistent memory (e.g., cross-gridded nonvolatile memory), memory with block resistance change, phase change memory (PCM)), and / or similar memory and / or any combination thereof. In some embodiments, any such memory can be located in one or more modules, cards, servers, racks, and / or similar elements or combinations thereof. Although the tracking logic 108 is shown as part of the controller 106, the tracking logic 108 can also be implemented partially or completely as a separate component and / or as part of another component (e.g., the memory 104) or any other component of the memory device 102.

[0024] As another example, in some embodiments, the memory device 102, the memory 104, and / or the controller 106 may be implemented at least in part using storage components, which may include any type of non-volatile storage media based on, for example, solid state media (e.g., solid state drive (SSD)), magnetic media (e.g., hard disk drive (HDD)), optical media, and / or similar media or any combination thereof. In some embodiments, the memory device 102 may be implemented at least in part using an SSD based on not-and (NAND) flash memory, persistent memory, and / or similar memory or any combination thereof. Any such storage component may be implemented in any form factor (e.g., 3.5 inches, 2.5 inches, 1.8 inches, M.2, Enterprise and Data Center SSD Form Factor (EDSFF), NF1, and / or similar form factors) using any connector configuration (e.g., serial advanced technology attachment (SATA), Small Computer Systems Interface (SCSI), Serial Attached SCSI (SAS), U.2, M.2, and / or similar configurations). Any such storage component may be implemented and / or used in conjunction with a server chassis, a server rack, a data room, a data center, an edge data center, a mobile edge data center, and / or any combination thereof, either fully or in part. In some embodiments, the memory device 102 may be implemented at least in part using a memory controller and / or one or more memory elements, modules, and / or similar elements located on a circuit board (e.g., in a host computer, a server computer (e.g., a compute server, a storage server, a network server, and / or similar servers), a node (e.g., a storage node, a compute node, and / or similar nodes), or any combination thereof).

[0025] As yet another example, the memory device 102, the memory 104, and / or the controller 106 may communicate using any type of wired and / or wireless communication media, interfaces, networks, interconnects, protocols, and / or the like, including but not limited to: Peripheral Component Interconnect Express (PCIe), Nonvolatile Memory Express (NVMe), NVMe-over-fabric (NVMe-oF), Compute Express Link (CXL), and / or coherent protocols such as CXL.mem, CXL.cache, CXL.IO, and / or the like, Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerator (CCIX), and / or the like, Advanced Extensible Interface (AXI), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Advanced Message Queuing Protocol (AMQP), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Internet Wide Area RDMA Protocol (iWARP), wireless networks of any generation including 2G, 3G, 4G, 5G, 6G, and / or the like, Wi-Fi of any generation, Bluetooth, near-field communication (NFC), and / or the like, or any combination thereof.

[0026] For illustrative purposes, some exemplary embodiments may be described in the context of some exemplary implementation details, such as a memory device implemented using a storage element capable of operating in a memory mode. However, the inventive principles are not limited to these or any other implementation details.

[0027] FIG. 2 shows an embodiment of a memory access scheme according to an exemplary embodiment of the present disclosure. The scheme shown in FIG. 2 may include a host 216, a memory 220, and a storage element 202. The storage element 202 may be implemented as, for example, an embodiment of the memory device 102 shown in FIG. 1. The host 216 may communicate with the storage element 202 using a communication interface 224, and the communication interface 224 may be implemented using any type of interconnection, network, interface, protocol, and / or similar protocol as described above for the embodiment shown in FIG. 1.

[0028] Although the communication interface 224 is not limited to any specific implementation details, for illustrative purposes of the inventive principles, the communication interface 224 shown in FIG. 2 may be implemented using a CXL interconnect using the CXL.mem protocol. The storage element 202 may be configured to operate at least partially in a memory mode (e.g., a CXL cache coherent memory mode), where some or all of the storage media in the storage element 202 may be accessed by the host 216 as memory (e.g., storage class memory) using the CXL.mem protocol.

[0029] The host 216 may also communicate with the memory 220 using any suitable memory interface 222. For example, if the memory 220 is implemented using DRAM, the memory interface 222 may be implemented using any version (e.g., generation) of the double data rate (DDR) specification, including DDR3, DDR4, DDR5, or any other current or future version.

[0030] The host 216 may include a memory controller 218 that may implement a memory scheme in which the storage media in the memory 220 and the storage element 202 may be tiered, cached, buffered, and / or similar operations.

[0031] The storage element 202 may include a controller 206 and any type and / or any amount of storage media. For illustrative purposes, the storage element 202 may include four NAND flash memory chips 226-0 to 226-3 (designated as chip 0 to chip 3, respectively) arranged in two channels 228-0 and 228-1 (designated as channel 0 and channel 1, respectively), and the controller 206 may be implemented using a flash translation layer (FTL).

[0032] The controller 206 may implement a memory scheme that maps a logical page number (LPN) to a physical page number (PPN). The logical-to-physical mapping enables the controller 206 to perform page-based memory access (e.g., write to and / or read from memory in page units) and block-based erasure (e.g., erase memory in blocks of multiple pages).

[0033] The memory controller 218 at the host 216 may request memory access (e.g., read and / or write) to data in units smaller than a page (e.g., cache lines). Since memory can be written (e.g., programmed) to the memory chips 226-0 to 226-3 in page units, when the controller 206 updates (e.g., modifies) a portion of a page (e.g., a cache line in a page), the controller 206 may write the updated data page including the updated portion (e.g., the modified cache line) to a new page of memory (which may be referred to as a valid page) and invalidate the previous version of the page (which may be referred to as an invalid page).

[0034] Invalid pages may be erased, for example, by a garbage collection process in which a block (e.g., an entire block) containing one or more invalid pages may be erased. If the block contains any valid pages, the valid pages may be moved to a new block before the block is erased.

[0035] The controller 206 may include cache column tracking logic 208, and the cache column tracking logic 208 may track invalid pages and / or potentially valid and / or invalid portions of invalid pages (e.g., cache columns) (e.g., unmodified cache columns and / or modified cache columns). Depending on implementation details, the cache column tracking logic 208 may enable the controller 206 to access valid data in an invalid page. For example, the controller 206 may store a first version 230 of a data page in die 3. If the memory controller 218 at the host 216 sends a write request to the controller 206 to update data stored in a portion stored in the page 230 (e.g., a request to modify a cache column), the controller 206 may store a second version 232 of the data page (including the modified cache column) in die 0. Thus, the second version 232 stored in die 0 of the page may be a valid page, and the first version 230 stored in die 3 of the page may be an invalid page. The cache column tracking logic 208 may track (e.g., using a tracking data structure) which portions (e.g., cache columns) of the first version 230 of the page and / or the second version 232 of the page are valid and / or invalid (e.g., which cache columns are unmodified and / or modified).

[0036] The memory controller 218 at the host 216 may send a read request to the controller 206 to read a portion 234 (e.g., a cache column) of the valid page 232 stored in die 0. If the valid page 232 can be easily accessed, the controller 206 may read the portion 234 of the valid page 232 from die 0 and send the portion 234 to the memory controller 218 along with the response. However, in some cases, the valid page 232 may not be easily accessed. For example, the valid page 232 and / or die 0 may be relatively busy due to I / O requests, or die 0 may be undergoing an erase operation (e.g., as part of a garbage collection operation), as shown in FIG. 2. Thus, before reading the valid page 232 from die 0, the controller 206 may wait for other I / O traffic and / or wait for the erase operation to complete. As an alternative or additionally, the controller 206 may temporarily pause the erase operation to read the valid page 232 from die 0 and resume the erase operation after reading the valid page. However, this may still delay the reading of the valid page and delay other processes that may be based on the erase operation.

[0037] Depending on the implementation details, the cache line tracking logic 208 can determine that a portion 236 of the invalid page 230 (e.g., the first version of the page) may still contain valid data corresponding to the requested portion 234 of the valid page 232 (e.g., the second version of the page). For example, when the controller has stored the updated page 232 in die 0, the requested portion 234 may not have been updated yet (e.g., may not have been modified). Thus, the portion 236 of the invalid page 230 can have the same or substantially the same data as the portion 234 of the valid page 232.

[0038] In some embodiments, the controller 206 and / or the cache line tracking logic 208 can read the portion 236 of the invalid page 230 (e.g., the cache line) in die 3 and send the portion 236 to the memory controller 218 at the host 216 (as shown by the dashed arrow 238), rather than waiting for the valid page 232 stored in die 0 to become more accessible. Depending on the implementation details, this can reduce the latency, power consumption, and / or similar factors associated with responding to a read request.

[0039] The host 216 can be implemented using one or more of any type of device such as: a server, such as a compute server, a storage server, a network server, a cloud server, and / or a similar server; a computer, such as a workstation, a personal computer, a tablet, a smartphone, and / or a similar computer; or a combination of multiple such devices and / or their combinations.

[0040] FIG. 3 illustrates an embodiment of a data cache according to an exemplary embodiment of the present disclosure. The data cache 340 can be used, for example, in combination with the memory scheme shown in FIG. 2 to provide a cache of data that will at least ultimately be stored in the storage medium of the storage element 202 (e.g., non-volatile memory such as flash memory). The data cache 340 can be implemented in the storage element 202 as shown, for example, in FIG. 2.

[0041] Referring to FIG. 3, the data cache 340 can be implemented using, for example, volatile memory (e.g., DRAM), and the volatile memory can be addressed in a granularity that can be smaller than a page (e.g., byte, cache line, and / or a similar granularity). The data stored in the data cache 340 can be organized in logical pages, which can be identified by logical page numbers (e.g., LPN1, LPN2, LPN5, and / or LPN10 shown in FIG. 3). A page can include one or more cache lines indicated by an index in the leftmost row of the page.

[0042] The version of the data contained in the cache column can be indicated by the shading in the rightmost row of the cache column. In the example shown in Figure 3, the single-slash shading can indicate the first version of the data (e.g., the data that may have been present in the cache column when the page was first loaded into the data cache 340). Additionally or alternatively, the first version of the data indicated by the single-slash shading can indicate the data present in the page when the page was last saved to non-volatile memory (e.g., stored in the storage medium of the storage element).

[0043] A modified cache column (e.g., a cache column containing a second version of the data (e.g., a newer version of the data)) can be indicated by cross-hatch shading. For example, if new data has been written to the cache column since the page was first loaded, since the page was last stored in non-volatile memory, and / or since a similar situation, the cache column can be indicated as modified. For example, in the embodiment shown in Figure 3, in the page indicated as LPN2, cache columns 00, 02, and / or 03 may include unmodified data, and cache columns 01 and / or 7F may include modified data.

[0044] The page and cache columns shown in Figure 3 are not limited to any particular implementation details, such as the number and / or size of the pages, cache columns, and / or similar implementation details. However, for illustrative purposes, an exemplary embodiment can be implemented using pages that contain 8192 bytes, which are divided into 128 cache columns (numbered 00 to 7F) that each contain 64 bytes.

[0045] Figure 4 shows an embodiment of a buffered page update table according to an exemplary embodiment of the present disclosure. For example, the buffered page update table 442 can be used to track the cache columns (e.g., the data cache 340 shown in Figure 3) in the pages stored in the data cache that have been updated. The buffered page update table 442 can be implemented in the cache column tracking logic 208 shown, for example, in Figure 2. In some embodiments, the buffered page update table 442 can be used to track the buffered cache columns in the data cache, which is configured for operations using the CXL.mem protocol.

[0046] Referring to FIG. 4, the buffer page update table 442 can be implemented as, for example, a hash table and can include one or more table entries (e.g., horizontal rows) corresponding to one or more pages stored in the data cache. The table entries can include a page identifier (e.g., LPN) of the corresponding page in the data cache and a bitmap for recording which cache columns in the corresponding page have been modified. For example, the top row of the buffer page update table 442 can include the identifier LPN2 in the first row to indicate that the buffer page update table 442 can track the modified cache columns in LPN2 and can include a bitmap in subsequent rows. In the example shown in FIG. 4, logic 1 can indicate an unmodified cache column, and logic 0 can indicate a modified cache column. Although the buffer page update table 442 is not limited to any specific implementation details, in the example shown in FIG. 4, the table entries can include a bitmap having 128 bits (00 to 7F) corresponding to the number of cache columns in the page in the data cache 340 shown in FIG. 3.

[0047] Any type of memory and / or persistence scheme can be used to implement the buffer page update table 442. For example, in some embodiments, the buffer page update table 442 can be implemented in DRAM in a storage component and can be created at runtime. In embodiments where the data cache is saved to non-volatile memory (e.g., in the event of a power outage event), the buffer page update table 442 can also be saved to non-volatile memory.

[0048] For example, when the corresponding page is evicted from the data cache, the table entry can be removed from the buffer page update table 442. As an alternative or in addition, when the number of unmodified cache columns in the bitmap of the table entry drops below a threshold, the table entry can be removed from the buffer page update table 442.

[0049] In some embodiments, the buffer page update table 442 can be used to track the modified and unmodified cache columns of cache pages in a write-back cache scheme, in which only the updated pages can be stored in the main memory (e.g., non-volatile memory) based on one or more specific events (e.g., evicting a page from the cache, a power outage event, and / or a similar event).

[0050] FIG. 5 shows an embodiment of an invalid page mapping table according to an exemplary embodiment of the present disclosure. For example, the invalid page mapping table 544 can be used to track cache columns that are still valid in an invalid version (e.g., most recently invalidated page) of a page that can be stored in a physical page in main memory (e.g., non-volatile memory) and that can correspond to an updated logical page (e.g., valid page) that can also be stored in main memory. The invalid page mapping table 544 can be implemented in the cache column tracking logic 208 shown, for example, in FIG. 2. In some embodiments, the invalid page mapping table 544 can be used to track previously buffered cache columns in a data cache that is configured for operations using the CXL.mem protocol.

[0051] Referring to FIG. 5, the invalid page mapping table 544 can be implemented as, for example, a hash table and can include one or more table entries (e.g., horizontal columns) corresponding to one or more physical pages (e.g., invalid pages) that can be mapped to one or more corresponding logical pages (e.g., corresponding valid pages). Thus, a table entry can include a page identifier (e.g., LPN) of a valid page and a page identifier (e.g., PPN) of the corresponding invalid page. A table entry can also include a bitmap to record which cache columns in the valid page have been modified relative to the invalid page. For example, the top column of the invalid page mapping table 544 can include the identifier LPN2 in the first row and the identifier PPN2 in the second row to indicate that the page at PPN2 can be an invalid version of the page identified as LPN2. Some embodiments can include additional page mapping tables that can map the valid version of the page identified as LPN2 to a valid version stored in another physical page. In the example shown in FIG. 5, in the bitmap row of the table entries in the top column (indicated as 00 to 7F), a logic 1 can indicate that the corresponding cache column in the valid version of the page has not been modified relative to the corresponding cache column in the invalid version of the page, and thus the corresponding cache column in the invalid version of the page is valid. A logic 0 can indicate that the corresponding cache column in the valid version of the page has been modified relative to the corresponding cache column in the invalid version of the page, and thus the corresponding cache column in the invalid version of the page is invalid.

[0052] In some embodiments, the invalid page map table 544 may record the most recently invalidated physical page (e.g., PPN2) that has been mapped to a corresponding logical page (e.g., LPN2). In some embodiments, a least recently used (LRU) policy may be used to maintain the invalid page map table 544, and the LRU policy may remove older entries from the table. Some embodiments may limit the size of the table, for example, by removing entries for logical pages and / or physical pages in which the number of unmodified cache columns is less than a threshold value. Thus, in some embodiments, the invalid page map table 544 may be local, primary, or only for the active region of memory (which may be referred to as the hot region of memory). In some embodiments, entries may be selected based on recency of use, frequency of use, and / or similar factors to include the entries in the invalid page map table 544 and / or remove the entries from the invalid page map table 544. In some embodiments, entries may be selected based on one or more machine learning (ML) algorithms to include the entries in the invalid page map table 544 and / or remove the entries from the invalid page map table 544.

[0053] Although the invalid page map table 544 is not limited to any particular implementation details, in the example shown in FIG. 5, an entry may include a bitmap having 128 bits (00 to 7F) corresponding to the number of cache columns in a page in the data cache shown in FIG. 3. Any type of memory and / or persistence scheme may be used to implement the invalid page map table 544. For example, in some embodiments, the invalid page map table 544 may be implemented in volatile memory (e.g., DRAM) in a storage element and may be created at runtime. In embodiments in which the data cache is saved to non-volatile memory (e.g., in the event of a power-off event), the invalid page map table 544 may also be saved to non-volatile memory.

[0054] FIG. 6A shows an exemplary embodiment of a memory device in a first state related to a write operation according to an exemplary embodiment of the present disclosure. FIG. 6B shows an exemplary embodiment of the memory device shown in FIG. 6A in a second state related to the write operation according to an exemplary embodiment of the present disclosure. FIGS. 6A and 6B together show a write operation according to an exemplary embodiment of the present disclosure and may be collectively and / or individually referred to as FIG. 6. The embodiment shown in FIG. 6 may be implemented, for example, using any of the devices disclosed herein (including the devices shown in FIGS. 1 to 5 above).

[0055] Referring to FIG. 6A, the memory device may include a host 616 and a storage component 602. The host 616 and the storage component 602 may be configured to communicate, for example, using the CXL interface, where the storage component 602 may be configured to operate at least partially in a memory mode (e.g., the CXL cache coherent memory mode), where some or all of the storage media in the storage component 602 may be accessed by the host 616 as memory (e.g., storage class memory) using the CXL.mem protocol.

[0056] The storage component 602 may include a data cache 640, a media translation layer 606, a physical layer (PHY) 646, and one or more memory dies 626-0 to 626-3 (designated as die 0 to die 3) arranged in one or more channels 628-0 and 628-1 (designated as Ch 0 and Ch 1). The data cache 640 may be implemented, for example, using volatile memory (e.g., DRAM) and may be configured to store data pages that may include one or more cache lines. The media translation layer 606 may perform one or more functions related to translating data between the format received from and / or sent to the host and the format suitable for the underlying storage media used for memory channels Ch 0 and Ch 1. For example, if the memory dies 626-0 to 626-3 are implemented using flash memory (e.g., NAND flash memory), the media translation layer 606 may be implemented as a flash translation layer. The media translation layer 606 may include a page map table 650 that may map the LPN of a valid data page to the PPN of the memory, which may store the valid data page using the LPN as an index. The media translation layer 606 may also include a buffered page update table 642 and / or an invalid page map table 644, which may be similar to the components described above with respect to FIGS. 4 and 5.

[0057] The physical layer 646 may implement the physical interface between the media translation layer 606 and the memory dies 626-0 to 626-3.

[0058] For illustrative purposes, a page having six cache lines may be used to illustrate the embodiments shown in FIG. 6, but the inventive principles are not limited to these or any other implementation details. In the embodiments shown herein, cache lines and / or pages shown using the same type of shading (e.g., single diagonal shading, cross hatching, vertical cross hatching, and horizontal cross hatching and / or similar shading) may include the same or similar versions of the data.

[0059] FIG. 6A shows an initial state of the device before a write operation. FIG. 6B shows a state of the device after the write operation. Referring to FIG. 6A, a first version of a data page indicated as LPN2 may be stored in data cache 640. LPN2 may include six cache columns indicated as 0 to 5. The six cache columns may include the first version of the data indicated by single-slash shading. The first version of the data page indicated as LPN2 may also be stored in a physical page indicated as PPN2 in chip 3. Thus, in the initial state before the write operation, page map table 650 may include an entry that maps LPN2 to PPN2. In this example, an invalid version of LPN2 may not be stored in storage element 602, and thus invalid page map table 644 may not have an entry for LPN2.

[0060] Since the data page indicated as LPN2 is stored in data cache 640, buffer page update table 642 may include an entry for LPN2. The version of the data page indicated as LPN2 in data cache 640 may not have been updated since the version was written to the cache or since the version was stored in chip 3, and thus, in the initial state before the write operation, the bitmap for LPN2 in buffer page update table 642 may include all 1s to indicate that no cache column has been modified.

[0061] Additionally, in the initial state before the write operation, host 616 may include cache column 648 having updated data shown by cross-hatch shading, and the host may send the updated data to storage element 602 to modify cache column 1 of LPN2 (which may be referred to as the target cache column).

[0062] The write operation may include any number of the following operations indicated as operations (1) to (6). The operation numbers are provided to identify the operations and do not necessarily indicate the order in which the operations may be performed. Thus, in some embodiments, the order of the operations may be changed, one or more operations may be omitted, and one or more additional operations may be included. Additionally, although one or more of the operations described with respect to FIGS. 6A and 6B may be described as being performed by media translation layer 606, in some embodiments, one or more of the operations may be performed by any other device (such as a storage element controller, communication interface, NVMe controller, and / or similar device).

[0063] (1) The host 616 may send a write request and the updated cache line 1 of LPN2 to the storage element 602. In the example shown in FIG. 6A, the page LPN2 already exists in the data cache 640, which may be referred to as a cache hit. As an alternative, if LPN2 does not exist in the data cache 640 (which may be referred to as a cache miss), the buffered page update table 642 may not include an entry for LPN2. In the case of a cache miss, the media translation layer 606 may search the page map table 650 to find the physical page corresponding to LPN2 (PPN2 in this example). The media translation layer 606 may read the physical page PPN2 from the storage media (wafer 3 in this example), load the page into the data cache 640, and place an entry for LPN2 in the buffered page update table 642.

[0064] (2) The media translation layer 606 may write the data of the updated cache line 1 (shown using cross-hatched shading) into the cache line 1 of LPN2 in the data cache 640, as shown in FIG. 6B.

[0065] (3) The media translation layer 606 may clear the bits corresponding to cache line 1 in the bitmap portion of the entry for LPN2 in the buffered page update table 642 shown in FIG. 6B (e.g., change the bits to logical 0) to indicate that cache line 1 is a modified cache line.

[0066] (4) The media translation layer 606 may write the updated valid page LPN2 including the modified cache line 1 (as indicated by the cross-hatched shading) into a new physical page (e.g., PPN4 in wafer 0 shown in FIG. 6B).

[0067] (5) The media translation layer 606 may search the page map table 650 to determine whether the page map table 650 includes an entry for LPN2, and the entry may indicate that an earlier version of LPN2 is stored in the storage element 602. In this example, the entry that maps LPN2 to PPN2 may indicate that an earlier version of LPN2 is stored in PPN2 in wafer 3. The earlier version of LPN2 stored in PPN2 in wafer 3 may become an invalid page, and thus the media translation layer 606 may place an entry for LPN2 in the invalid page map table 644, as shown in FIG. 6B. The entry for LPN2 may map LPN2 to PPN2 in the second row to indicate that PPN2 in wafer 3 may become an invalid version of LPN2.

[0068] The bitmap portion of the entry for LPN2 in the invalid page map table 644 may include a logical 0 in the position of cache column 1 to indicate that cache column 1 in PPN2 may correspond to a modified cache column 1 in the valid version of LPN2 stored in PPN4 in die 0, and thus the data in cache column 1 in PPN2 in die 3 may be invalid, as shown by X in FIG. 6B. The bitmap portion of the entry for LPN2 in the invalid page map table 644 may include logical 1s in the positions of cache columns 0, 2, 3, 4, and / or 5 to indicate that those cache columns in PPN2 stored in die 3 may correspond to unmodified cache columns in the valid version of LPN2 stored in PPN4 in die 0, and thus the data in cache columns 0, 2, 3, 4, and / or 5 in PPN2 may be valid, as shown by the diagonal hatching in FIG. 6B.

[0069] (6) The media translation layer 606 may update the entry for LPN2 in the page map table 650 to map LPN2 to the valid version of LPN2 stored in PPN4 in die 0, as shown in FIG. 6B.

[0070] Thus, after the write operations shown in FIGS. 6A and 6B, the valid version of LPN2 (including the modified cache column 1) may exist in both the data cache 640 and PPN4 in die 0, the buffered page update table 642 may indicate that cache column 1 of LPN2 has been modified, the page map table 650 may map LPN2 to the valid version of LPN2 stored in PPN4 in die 0, and / or the invalid page map table 644 may indicate that the invalid version of LPN2 stored in PPN2 may include valid data in cache columns 0, 2, 3, 4, and / or 5 corresponding to the unmodified cache columns of the valid version of LPN2. Depending on implementation details, for example, if the valid version of the page with the requested cache column may not be readily accessible, this may enable the media translation layer 606 to quickly determine that the valid version of the requested cache column may be available in an invalid page.

[0071] In some embodiments, if the data cache 640 is configured for write-back operations, after operations (1) through (3) are completed, the entry for LPN2 may be removed from the page map table 650, and the write operation may be considered complete. The device shown in FIG. 6 may not take further action until, for example, LPN2 is evicted from the data cache 640, at which time the media translation layer 606 may perform one or more of operations (4) through (6) to store the evicted page in the storage medium and, if an invalid version of LPN2 is stored in the storage element 602, track the location of the invalid page and / or the presence of valid data in the invalid page.

[0072] FIG. 7 illustrates an exemplary embodiment of a method for a write operation for memory device operation according to an exemplary embodiment of the present disclosure. The embodiment shown in FIG. 7 may be implemented using any of the devices disclosed herein (including the devices shown in FIGS. 1 to 6 above).

[0073] Referring to FIG. 7, the method may begin at operation 751, in which a memory device may receive (e.g., from a host) a request to write an updated cache column to a page in a data cache. At operation 752, the method may determine whether a page with the requested cache column exists in the data cache (e.g., whether there is a cache hit). If there is a cache hit, the method may proceed to operation 756. However, if the page does not exist in the data cache (e.g., there is a cache miss), the method may proceed to operation 753, in which the page with the requested cache column may be read from main memory (e.g., non-volatile memory in a storage element).

[0074] At operation 754, the method may determine whether the data cache is full. If the data cache is not full, the method may proceed to operation 756. However, if the data cache is full at operation 754, the method may proceed to operation 755, in which a page may be evicted from the data cache. In some embodiments, the page to be evicted may be selected based on an LRU policy, the number of unmodified cache columns in the page, and / or similar factors. For example, in some embodiments, if a page has a relatively low number of unmodified cache columns (e.g., the fewest number of unmodified cache columns), the page may be selected for eviction, which may indicate that one or more invalid pages corresponding to the selected page may include a relatively small amount of valid data. The method may proceed to operation 756.

[0075] At operation 756, the method may write the updated cache column to the page in the data cache. At operation 757, the method may update a buffer page update table, e.g., to indicate that the cache column of the page in the data cache has been modified. The method may proceed to operation 758, at which the method may determine whether the data cache is configured for write-through operation or write-back operation. If the data cache is not configured for write-back operation, the method may proceed to operation 761.

[0076] However, if the data cache is configured for write-through operations, the method may proceed to operation 759, in which the updated page in the data cache may be written to a new physical page in the main memory (e.g., non-volatile memory in a storage element). In some embodiments, the page map table may be updated to map the LPN of the updated page to the PPN of the new valid physical page. At operation 760, the invalid page map table may be updated to indicate that the invalid version of the updated page may be stored in the main memory and to indicate that the cache column of the invalid version of the page corresponding to the modified cache column in the valid version of the page may contain invalid data. The method may proceed to operation 761, at which the memory device may send a response (e.g., completion, error, and / or similar response) back to the host.

[0077] FIG. 8A shows an exemplary embodiment of a memory device in a first state related to an eviction operation according to an exemplary embodiment of the present disclosure. FIG. 8B shows an exemplary embodiment of the memory device shown in FIG. 8A in a second state related to the eviction operation according to an exemplary embodiment of the present disclosure. FIGS. 8A and 8B together show an eviction operation according to an exemplary embodiment of the present disclosure and may be collectively and / or individually referred to as FIG. 8. The embodiments shown in FIGS. 8A and 8B may be implemented, for example, using any of the devices disclosed herein (including the devices shown in FIGS. 1 to 6 above).

[0078] In some aspects, the embodiments shown in FIGS. 8A and 8B may be similar to the embodiments shown in FIGS. 6A and 6B, and like components may be identified using reference identifiers ending with the same number. Thus, the embodiments shown in FIGS. 8A and 8B may include a host 816 and a storage element 802, which may include a data cache 840, a media translation layer 806, a physical layer 846, and one or more memory dies 826-0 to 826-3 (designated as die 0 to die 3) arranged in one or more channels 828-0 and 828-1 (designated as Ch 0 and Ch 1). The media translation layer 806 may include a page map table 850, a buffered page update table 842, and / or an invalid page map table 844, which components may be, for example, similar to the components described above with respect to FIGS. 6A and 6B. Additionally, the host 816 and the storage element 802 may be configured to communicate, for example, using a CXL interface, where the storage element 802 may be configured to operate at least partially in a memory mode (e.g., CXL cache coherent memory mode), in which some or all of the storage media in the storage element 802 may be accessed by the host 816 as memory (e.g., storage class memory) using the CLX.mem protocol.

[0079] FIG. 8A shows an initial state of the memory device before a data cache eviction operation. FIG. 8B shows a state of the memory device after the data cache eviction operation. Referring to FIG. 8A, a data page designated as LPN2 may be stored in the data cache 840. The page LPN2 stored in the data cache 840 may include three different data versions: cache column 0 may include the data version indicated by cross-hatching, cache column 1 may include the data versions indicated by vertical cross-hatching and horizontal cross-hatching, and cache columns 2 to 5 may include the data versions indicated by single hatching.

[0080] The page mapping table 850 may map LPN2 to the physical page PPN4 stored in die 0. The physical page PPN4 stored in die 0 may include different versions of the data page in LPN2 stored in the data cache 840. The cache columns in the physical page PPN4 stored in die 0 may include two data versions: cache columns 0 to 1 may include the data versions indicated by vertical cross-hatching and horizontal cross-hatching, and cache columns 2 to 5 may include the data versions indicated by single hatching.

[0081] The buffer page update table 842 may include an entry for LPN2 having a bitmap portion indicating that cache column 0 in LPN2 may be modified (indicated by logic 0) relative to cache column 0 in PPN4 and that cache columns 1 to 5 in LPN2 may not be modified (indicated by logic 1) relative to cache columns 1 to 5 in PPN4. Since PPN4 includes a cache column (cache column 0) that has been modified relative to LPN2, PPN4 may be considered an invalid page. However, since cache columns 1 to 5 in PPN4 may include data that is actually the same as the data in the corresponding unmodified cache columns of LPN2, cache columns 1 to 5 in PPN4 may contain valid data.

[0082] The invalid page mapping table 844 may include an entry that maps the LPN2 to the physical page PPN2 stored in die 2. The physical page PPN2 stored in die 2 may include three different data versions: cache row 0 may include the data version indicated by vertical and horizontal cross-hatching, cache row 1 may include the data version indicated by dots, and cache rows 2 to 5 may include the data version indicated by single-slash shading. Thus, since cache rows 0 to 1 in PPN2 may include data that is actually different from the data in the corresponding modified cache rows 0 to 1 in LPN2, the entry for LPN2 in the invalid page mapping table 844 may include a bitmap portion that indicates that cache rows 0 to 1 in PPN2 may be invalid (indicated by logical 0). Thus, PPN2 in die 2 may be considered an invalid page. Since cache rows 2 to 5 in PPN2 may include data that is actually the same as the data in the corresponding modified cache rows 2 to 5 in LPN2 stored in the data cache 840, the bitmap portion of the entry for LPN2 may also indicate that cache rows 2 to 5 in PPN2 may be valid (indicated by logical 1).

[0083] For example, since the page LPN2 in the data cache 840 may include a cache row (in this example, cache row 0) that has been modified relative to the most recently stored version of the page in PPN4 in die 0, the page LPN2 in the data cache 840 may be considered a dirty page.

[0084] For example, the page LPN2 may be evicted to make room for other data pages in the data cache 840. For example, the page LPN2 may be selected for eviction based on an LRU policy, the number of unmodified cache rows in the page, and / or similar factors. For example, in some embodiments, since LPN2 may have a relatively low number of unmodified cache rows, LPN2 may be selected for eviction.

[0085] The eviction operation may include any number of the following operations indicated as operations (1) to (6). The operation numbers are provided to identify the operations and do not necessarily indicate the order in which the operations may be performed. Thus, in some embodiments, the order of the operations may be changed, one or more operations may be omitted, and one or more additional operations may be included. Additionally, although one or more of the operations described with respect to FIGS. 8A and 8B may be described as being performed by the media translation layer 806, in some embodiments, one or more of the operations may be performed by any other device (such as a storage element controller, a communication interface, an NVMe controller, and / or a similar device).

[0086] (1) The media translation layer 806 may optionally evict the data page indicated as LPN2 stored in the data cache 840.

[0087] (2) The media translation layer 806 may locate the entry for LPN2 in the invalid page map table 844 and update the entry to map LPN2 to the invalid physical page PPN4 in die 0, as shown in FIG. 8B.

[0088] (3) The media translation layer 806 may locate the bitmap portion of the entry for LPN2 in the buffered page update table 842 and use the bitmap portion to update the bitmap portion of the entry for LPN2 in the invalid page map table 844, as shown in FIG. 8B. Since cache column 0 in PPN4 may include data that is actually different from the data in the corresponding modified cache column 0 in LPN2, the updated bitmap portion may indicate that cache column 0 in PPN4 may be invalid (indicated by logical 0), and since cache columns 1 to 5 in PPN4 may include data that is actually the same as the data in the corresponding unmodified cache columns 1 to 5 in LPN2, cache columns 1 to 5 in PPN4 may be valid (indicated by logical 1).

[0089] (4) The media translation layer 806 may evict the dirty page LPN2 from the data cache 840 by writing the dirty page LPN2 to the new physical page PPN5 in die 3 and removing the entry for LPN2 from the buffered page update table 842, as shown in FIG. 8B.

[0090] (5) The media translation layer 806 may update the page map table 850 to map LPN2 in die 3 to PPN5. Thus, LPN2 may no longer be mapped to the physical page PPN2 in die 2, as shown in FIG. 8B.

[0091] (6) The physical page PPN2 in die 2 may be marked for erasure and / or garbage collection.

[0092] Accordingly, after the eviction operations shown in FIGS. 8A and 8B, the data page indicated as LPN2 can be removed from the data cache 840. The page map table 850 can map LPN2 to the valid version of the page stored in the physical page PPN5 in chip 3. The invalid version of the page can be stored in the physical page PPN4 in chip 0, and the invalid page map table 844 can include an entry as follows: The entry maps LPN2 to the invalid page PPN4 and indicates that cache column 0 of PPN4 can contain invalid data corresponding to the modified cache column 0 in PPN5, but cache columns 1 to 5 of PPN4 can include valid data corresponding to the unmodified cache columns 1 to 5 in PPN5.

[0093] FIG. 9 shows an exemplary embodiment of a method for an eviction operation for memory device operations according to an exemplary embodiment of the present disclosure. The embodiment shown in FIG. 9 can be implemented using any one of the devices disclosed herein (including the devices shown in FIGS. 1 to 6 and 8 above).

[0094] Referring to FIG. 9, the method can start at operation 962, in which the memory device can select a page to be evicted from the data cache. For example, if the page has a relatively low number of unmodified cache columns (e.g., the least number of unmodified cache columns), the page can be selected, which can indicate that one or more invalid pages corresponding to the selected page can include a relatively small amount of valid data, and thus, if the corresponding valid page cannot be easily accessed for a read operation, the page is relatively unlikely to be used as an alternative source of valid data.

[0095] At operation 963, the method can write the evicted page to a new physical page in the main memory (e.g., non-volatile memory in a storage component). At operation 964, the method can update the entry of the evicted page in the invalid page map table, for example, to map the LPN of the evicted page to the PPN of the invalid version of the page. The entry of the evicted page can also be updated to indicate one or more cache columns in the invalid page, which can correspond to the unmodified cache columns in the evicted page and thus can include valid data. At operation 965, the method can remove the entry of the evicted page from the buffer page update table.

[0096] FIG. 10A illustrates an exemplary embodiment of a memory device in a first state related to a read operation according to an exemplary embodiment of the present disclosure. FIG. 10B illustrates an exemplary embodiment of the memory device shown in FIG. 10A in a second state related to a read operation according to an exemplary embodiment of the present disclosure. FIGS. 10A and 10B together illustrate a read operation according to an exemplary embodiment of the present disclosure and may be collectively and / or individually referred to as FIG. 10. The embodiment shown in FIG. 10 may be implemented, for example, using any one of the devices disclosed herein (including the devices shown in FIGS. 1 to 6 and / or FIG. 8 above).

[0097] In some aspects, the embodiments shown in FIGS. 10A and 10B may be similar to the embodiments shown in FIGS. 6A and 6B, and reference identifiers ending with the same number may be used to identify similar components. Thus, the embodiments shown in FIGS. 10A and 10B may include a host 1016 and a storage element 1002, and the storage element 1002 may include a data cache 1040, a media translation layer 1006, a physical layer 1046, and one or more memory dies 1026-0 to 1026-3 (designated as die 0 to die 3) arranged in one or more channels 1028-0 and 1028-1 (designated as Ch 0 and Ch 1). The media translation layer 1006 may include a page map table 1050, a buffered page update table 1042, and / or an invalid page map table 1044, and these components may be, for example, similar to the components described above with respect to FIGS. 6A and 6B. Additionally, the host 1016 and the storage element 1002 may be configured to communicate, for example, using a CXL interface, where the storage element 1002 may be configured to operate at least partially in a memory mode (e.g., a CXL cache coherent memory mode), and some or all of the storage media in the storage element 1002 may be accessed by the host 1016 as memory (e.g., storage class memory) using the CLX.mem protocol.

[0098] FIG. 10A shows the initial state of the memory device before a data cache eviction operation. FIG. 10B shows the state of the memory device after a data cache eviction operation. Referring to FIG. 10A, the page map table 1050 may include an entry that maps the logical page LPN2 to a valid version of the page stored in the physical page PPN4 in die 0. The invalid page map table 1044 may include an entry that also maps LPN2 to an invalid version of the page stored in the physical page PPN2 in die 3.

[0099] Since the cache columns 0 and 2 to 5 in PPN2 may include data that is actually the same as the data in the corresponding unmodified cache columns 0 and 2 to 5 in the valid version of the page in PPN4 stored in die 0, the bitmap portion of the entry for LPN2 in the invalid page map table 1044 may indicate that the cache columns 0 and 2 to 5 in PPN2 may include data that may be valid (indicated by a logical 1). Since the cache column 1 in PPN2 may include data that is actually different from the data in the corresponding modified cache column 1 in the valid version of the page in PPN4 stored in die 0, the bitmap portion of the entry for LPN2 in the invalid page map table 1044 may also indicate that the cache column 1 in PPN2 may include data that may be invalid (indicated by a logical 0). This is shown visually in FIG. 8A, where the cache columns 0 and 2 to 5 in both PPN2 and PPN4 are shown as having data versions indicated by diagonal hatching, the cache column 1 in PPN4 is shown as having a data version indicated by cross hatching, and the cache column 1 in PPN2 is shown as invalid (indicated by an X).

[0100] The write may include any number of the following operations indicated as operations (1) to (8). The operation numbers are provided to identify the operations and do not necessarily indicate the order in which the operations may be performed. Thus, in some embodiments, the order of the operations may be changed, one or more operations may be omitted, and one or more additional operations may be included. Additionally, although one or more of the operations described with respect to FIGS. 10A and 10B may be described as being performed by the media translation layer 1006, in some embodiments, one or more of the operations may be performed by any other device (such as a storage element controller, a communication interface, an NVMe controller, and / or a similar device).

[0101] (1) The storage element 1002 may receive a request to read cache column 2 from the logical page LPN2 from the host 1016. (2) If LPN2 is stored in the data cache 1040, the storage element 1002 may read the cache column from LPN2 in the data cache 1040 and send a response including cache column 2 from LPN2 to the host 1016.

[0102] (3) If LPN2 is not stored in the data cache 1040, the media translation layer 1006 may search the page map table 1050 to locate the valid physical page PPN4 in die 0 that may store LPN2.

[0103] (4) For example, since die 0 that can store PPN4 may be busy due to ongoing erase and / or garbage collection operations, relatively heavy I / O traffic, and / or similar reasons, media translation layer 1006 may determine that die 0 may not be easily accessible, as shown by bounding box 1066 in FIG. 10A.

[0104] (5) Media translation layer 1006 may search the invalid page map table 1044 to find the entry for LPN2. The entry for LPN2 may indicate that the invalid version of LPN2 can be stored in physical page PPN2 in die 3. The bitmap portion of the entry for LPN2 in the invalid page map table 1044 may indicate that the invalid version of page LPN2 stored in physical page PPN2 in die 3 may include a valid version of cache column 2 (indicated by a logical 1 in the bitmap). For example, since cache column 2 in PPN2 may correspond to the unmodified cache column 2 in the valid version of LPN2 stored in PPN4 in die 0, cache column 2 in PPN2 may be valid.

[0105] (6) Media translation layer 1006 may determine that die 3 is more accessible than die 0 (e.g., since die 3 may not be undergoing erase and / or garbage collection operations, may not be busy due to relatively heavy I / O operations, and / or similar reasons).

[0106] (7) Since the invalid version of page LPN2 stored in physical page PPN2 in die 3 may include a valid version of the requested cache column 2 and die 3 is more accessible than die 0, media translation layer 1006 may read the invalid version of page LPN2 stored in physical page PPN2 in die 3 and load the invalid version into data cache 1040, as shown in FIG. 10B.

[0107] (8) Storage component 1002 may read the valid data in cache column 2 of LPN2 stored in data cache 1040 and send the valid data to host 1016 in response to the read request, as shown in FIG. 10B.

[0108] Depending on implementation details, opportunistically reading a valid cache column from an invalid version of a data page as described above for FIGS. 10A and 10B can reduce the latency and / or power consumption associated with reading data from a relatively inaccessible page. Additionally, the cache column can be made readable without pausing the erase operation, which can reduce the latency of other processes that can access the die being erased. Further, depending on implementation details, the techniques disclosed herein may have little or no impact on the durability, reliability, lifespan, and / or similar factors of the storage elements in which the techniques may be implemented.

[0109] FIG. 11 illustrates an exemplary embodiment of a method for a read operation for memory device operation in accordance with an exemplary embodiment of the present disclosure. The embodiment shown in FIG. 11 may be implemented using any one of the devices disclosed herein (including the devices shown in FIGS. 1 to 6, 8, and / or 10 above).

[0110] Referring to FIG. 11, the method may begin at operation 1168, in which a memory device may receive a read request for a read cache column of a logical page of data. At operation 1169, the method may locate a valid physical page that can store the requested cache column, for example, using a page map table. At operation 1170, the method may determine whether the valid physical page storing the requested cache column is busy due to, for example, an erase operation, other I / O traffic, and / or similar reasons. If the valid page is on a die that has not been erased and the valid page and / or the die on which the valid page resides is not busy due to relatively high I / O traffic, the method may load the valid page into the data cache at operation 1175 and proceed to operation 1174.

[0111] However, if the method determines at operation 1170 that the die in which the valid physical page is located is being erased or determines that the valid page and / or the die in which the valid page is located is busy due to a relatively high I / O traffic, the method may attempt to avoid subjecting the page to erasure and / or may attempt to perform load balancing by attempting to read the requested cache line from an invalid page that may include a valid version of the requested cache line. Accordingly, the method may proceed to operation 1171, in which the method may determine whether an invalid version of the logical page includes a valid version of the requested cache line. If the method is unable to locate a valid version of the requested cache line in the invalid version of the page at operation 1172, the method may load the valid page into the data cache at operation 1175 and proceed to operation 1174. However, if the method is able to locate a valid version of the requested cache line in the invalid version of the page at operation 1172, the method may load the invalid page into the data cache at operation 1173 and proceed to operation 1174.

[0112] At operation 1174, the method may read the requested cache line from the page in the data cache. The memory device may send a cache line having a response to the read request.

[0113] FIG. 12A illustrates an exemplary embodiment of a memory device in a first state related to a garbage collection operation in accordance with an exemplary embodiment of the present disclosure. FIG. 12B illustrates an exemplary embodiment of the memory device shown in FIG. 12A in a second state related to a garbage collection operation in accordance with an exemplary embodiment of the present disclosure. FIGS. 12A and 12B together illustrate a garbage collection operation in accordance with an exemplary embodiment of the present disclosure and may be collectively and / or individually referred to as FIG. 12. The embodiments shown in FIG. 12 may be implemented using, for example, any one of the devices disclosed herein (including the devices shown in FIGS. 1-6, 8, and / or 10 above).

[0114] In some aspects, the embodiments shown in FIGS. 12A and 12B may be similar to the embodiments shown in FIGS. 6A and 6B, and reference identifiers ending with the same number may be used to identify similar components. Thus, the embodiments shown in FIGS. 12A and 12B may include a host 1216 and a storage element 1202, and the storage element 1202 may include a data cache 1240, a media translation layer 1206, a physical layer 1246, and one or more memory dies 1226-0 to 1226-3 (designated as die 0 to die 3) arranged in one or more channels 1228-0 and 1228-1 (designated as Ch 0 and Ch 1). The media translation layer 1206 may include a page map table 1250, a buffered page update table 1242, and / or an invalid page map table 1244, and these components may be similar to the components described above with respect to FIGS. 6A and 6B, for example. Additionally, the host 1216 and the storage element 1202 may be configured to communicate using, for example, a CXL interface, where the storage element 1202 may be configured to operate at least partially in a memory mode (e.g., a CXL cache coherent memory mode), and some or all of the storage media in the storage element 1202 may be accessed by the host 1216 as memory (e.g., storage class memory) using the CXL.mem protocol.

[0115] FIG. 12A shows an initial state of the memory device before a garbage collection operation. FIG. 12B shows a state of the memory device after the garbage collection operation. Referring to FIG. 12A, the page map table 1250 may include an entry for LPN2 that maps the logical page LPN2 to a valid physical page PPN4 stored in die 1. The invalid page map table 1244 may also map the logical page LPN2 to an invalid physical page PPN2 stored in die 2.

[0116] In some embodiments, if there are any valid pages stored in die 2, the storage element 1202 may initiate a garbage collection operation by moving the valid pages to a different die. After moving any valid pages, the storage element 1202 may initiate an erase operation on die 2, as shown by the bounding box 1266. Thus, as shown in FIG. 12B, the invalid page PPN2 may be erased from die 2. As shown in FIG. 12B, the media translation layer 1206 may remove the entry for PPN2 from the invalid page map table 1244.

[0117] FIG. 13 shows an exemplary embodiment of a memory device having pages arranged in superblocks in accordance with an exemplary embodiment of the present disclosure. In some aspects, the embodiment shown in FIG. 13 may be similar to the embodiment shown in FIG. 8B, and like components may be identified using reference identifiers ending with the same number. However, in the embodiment shown in FIG. 13, the pages in dies 0 through 3 may be arranged in superblocks designated as superblock 0 and superblock 1. The physical page PPN4 stored in die 0 (which may be part of superblock 0) may be the latest version of page LPN2 that was written to the non-volatile memory before LPN2 was evicted from data cache 1340. When LPN2 is evicted from data cache 1340, writing the new valid page to the physical page PPN5 in a different superblock on a different die (e.g., die 3 in superblock 1) rather than the latest invalid page may prevent an ongoing erase operation on the superblock from preventing access to one or more dies belonging to the superblock. Depending on implementation details, this may avoid or eliminate the latency caused by waiting for an erase operation when reading a valid cache line from an invalid page.

[0118] Any of the functionality described herein (including any of host functionality, memory device functionality, and / or similar functionality (such as, for example, controller, tracking logic, cache line tracking, and / or similar functionality)) may be implemented using, for example, hardware, software, firmware, or any combination thereof, including: hardware and / or software combination logic that executes instructions stored in any type of memory, sequential logic, timers, counters, registers, state machines, volatile memory (such as dynamic random access memory (DRAM) and / or static random access memory (SRAM)), non-volatile memory (including flash memory, persistent memory such as cross-point non-volatile memory, memory with chalcogenide resistance change, phase change memory (PCM), and / or similar memory and / or any combination thereof), complex programmable logic device (CPLD), field programmable gate array (FPGA), application specific integrated circuit (ASIC), central processing unit (CPU) (including complex instruction set computer (CISC) processors (such as x86 processors) and / or reduced instruction set computer (RISC) processors (such as RISC-V and / or Advanced RISC Machine (ARM) processors)), graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), and / or similar logic. In some embodiments, one or more components may be implemented as a system-on-chip (SOC).

[0119] FIG. 14 illustrates an exemplary embodiment of an element according to an exemplary embodiment of the present disclosure. For example, the embodiment 1400 shown in FIG. 14 can be used to implement any of the memory devices disclosed herein. The element 1400 may include an element controller 1402, a tracking logic 1408, an element functional circuit 1406, and / or a communication interface 1410. The components shown in FIG. 14 may communicate via one or more element buses 1412. The tracking logic 1408 can be used to implement, for example, any of the invalid page tracking functionality disclosed herein.

[0120] The element functional circuit 1406 may include any hardware for implementing the main function of the element 1400. For example, if the element 1400 is implemented as a storage element, the element functional circuit 1406 may include a storage medium, such as one or more flash memory elements, an FTL, and / or similar elements. As another example, if the element 1400 is implemented as a network interface card (NIC), the element functional circuit 1406 may include one or more modems, network interfaces, a physical layer (PHY), a medium access control layer (MAC), and / or similar elements. As yet another example, if the element 1400 is implemented as an accelerator, the element functional circuit 1406 may include one or more accelerator circuits, memory circuits, and / or similar circuits.

[0121] FIG. 15 illustrates an embodiment of a method for accessing a version of a page according to an exemplary embodiment of the present disclosure. The method may start at operation 1502. At operation 1504, the method may determine the accessibility of a first version of a page, where the first version of the page is stored in at least one memory. The accessibility of the first version of the page may be based on, for example, an erase operation of the first page, an access amount of the first page, an access amount of a second version of the page, and / or similar factors. At operation 1506, the method may access at least a portion of a second version of the page based on the accessibility of the first version of the page, where the second version of the page is stored in the at least one memory. The at least a portion of the second version of the page may include, for example, a cache column. The method may end at operation 1508.

[0122] The embodiments shown in FIG. 15 and all other embodiments described herein are exemplary operations and / or components. In some embodiments, some operations and / or components may be omitted, and / or other operations and / or components may be included. Additionally, in some embodiments, the temporal order and / or spatial order of the operations and / or components may be changed. Although some components and / or operations may be shown as separate components, in some embodiments, some components and / or operations shown separately may be integrated into a single component and / or operation, and / or multiple components and / or operations may be used to implement some components and / or operations shown as a single component and / or operation.

[0123] Some of the embodiments disclosed above have been described in the context of various implementation details, but the principles of this disclosure are not limited to those or any other specific details. For example, some functionality has been described as being implemented by certain components, but in other embodiments, the functionality may be distributed among different systems and components located in different positions and having various user interfaces. Certain embodiments have been described as having specific processes, operations, etc., but these terms also encompass embodiments in which multiple processes, operations, etc. may be used to implement a specific process, operation, etc. or embodiments in which multiple processes, operations, etc. may be integrated into a single process, step, etc. A reference to a component or part may refer only to a part of the component or part. For example, a reference to a block may refer to the entire block or one or more sub-blocks. Unless otherwise apparent from the context, the use of terms such as "first" and "second" in this disclosure and the claims may be for the sole purpose of differentiating the components modified by the terms and may not indicate any spatial or temporal order. In some embodiments, a reference to a component may refer to at least a part of the component, e.g., "based on" may mean "at least partially based on" and / or similar. A reference to a first component may not imply the existence of a second component. The principles disclosed herein have independent utility and can be implemented separately, and not every embodiment can utilize every principle. However, the principles can also be implemented in various combinations, some of which can synergistically amplify the beneficial effects of the individual principles.

[0124] According to the inventive principles disclosed in this patent, the various details and embodiments above can be combined to produce additional embodiments. Since the inventive principles disclosed in this patent can be arranged and modified in details without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the following claims.

[0125] 0, 1, 2, 3 chips / cache columns 00, 02, 03~7F, 4, 5, 648: cache columns 102: Memory device 104, 220: Memory 106, 206: Controller 108, 1408: Tracking logic 110a: First version / version 110a-3, 234, 236: Part 110b: Second version / version 112: Request 114: Response 202, 602, 802, 1002, 1202: Storage element 208: Cache line tracking logic 216, 616, 816, 1016, 1216: Host 218: Memory controller 222: Memory interface 224, 1410: Communication interface 226-0, 226-1, 226-2, 226-3: NAND flash memory chip / memory chip 228-0, 228-1, 628-0, 628-1, 828-0, 828-1, 1028-0, 1028-1, 1228-0, 1228-1, Ch 0, Ch 1: Channel 230: Invalid page / first version / page 232: Valid page / second version / page 238: Dotted arrow 340, 640, 840, 1040, 1240, 1340: Data cache 442, 642, 842, 1042, 1242: Buffer page update table 544, 644, 844, 1044, 1244: Invalid page mapping table 606, 806, 1006, 1206: Media translation layer 626-0, 626-1, 626-2, 626-3, 826-0, 826-1, 826-2, 826-3, 1026-0, 1026-1, 1026-2, 1026-3, 1226-0, 1226-1, 1226-2, 1226-3: Memory chip 646, 846, 1046, 1246: Physical layer (PHY) 650, 850, 1050, 1250: Page mapping table 751, 752, 753, 754, 755, 756, 757, 758, 759, 760, 761, 962, 963, 964, 965, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1502, 1504, 1506, 1508: Operations 1066, 1266: Bounding box 1400: Component / Example 1402: Component controller 1406: Component functional circuit 1412: Component bus LPN1, LPN5, LPN10: Logical page number LPN2: Logical page number / Identifier / Page PPN2, PPN4: Physical page

Claims

1. An apparatus for accessing data in a version of a memory page, the apparatus comprising: At least one memory cell; And at least one processor, configured to: determine the accessibility of a first version of a page, wherein the first version of the page is stored in the at least one memory; Access to at least a portion of a second version of the page is performed based on the accessibility of the first version of the page, wherein the second version of the page is stored in the at least one memory, wherein a portion of the first version of the page is identical to a portion of the second version of the page, and a bitmap data structure is used to determine that the portion of the first version of the page is identical to the portion of the second version of the page, the bitmap data structure indicating the state of one or more cache columns of the second version of the page and one or more cache columns of the first version of the page.

2. The apparatus as claimed in claim 1, wherein the accessibility of the first version of the page is based on an erase operation of the first version of the page.

3. The apparatus of claim 1, wherein the accessibility of the first version of the page is based on the accessibility of the first version of the page.

4. The apparatus as claimed in claim 3, wherein the accessibility of the first version of the page is further based on the accessibility of the second version of the page.

5. The apparatus of claim 1, wherein the access to at least a portion of the second version of the page includes access to a cache column of the second version of the page.

6. The apparatus of claim 1, wherein the access to at least a portion of the second version of the page is based on the modification status of the first version of the page.

7. The apparatus as claimed in claim 6, wherein: The access to at least a portion of the second version of the page includes access to a portion of the second version of the page; and the modification status of the first version of the page is based on the modification status of the portion of the first version of the page corresponding to the portion of the second version of the page.

8. The apparatus as claimed in claim 7, wherein: The portion of the first version of the page includes the cache column of the first version of the page; and the portion of the second version of the page includes the cache column of the second version of the page that corresponds to the cache column of the first version of the page.

9. The apparatus of claim 1, wherein the at least one processor is configured to track the modification status of at least a portion of the second version of the page.

10. The apparatus of claim 1, wherein the access to at least a portion of the second version of the page includes a read operation.

11. The apparatus of claim 1, wherein the at least one processor is configured to: store the first version of the page in a first superblock; and store the second version of the page in a second superblock.

12. The apparatus of claim 1, further comprising a cache configured to store the first version of the page, wherein the at least one processor is configured to track modifications to the first version of the page.

13. The apparatus of claim 12, wherein the at least one processor is configured to evict the first version of the page based on the modification status of the first version of the page.

14. The apparatus as claimed in claim 1, wherein: The device includes a storage element; and the at least one memory includes at least one storage medium.

15. The apparatus of claim 14, wherein the storage element is configured to operate in a coherent memory mode.

16. A method for accessing data in a version of a memory page, the method comprising: Determine the accessibility of a first version of a page, wherein the first version of the page is stored in at least one memory; And accessing at least a portion of a second version of the page based on the accessibility of the first version of the page, wherein the second version of the page is stored in the at least one memory, wherein a portion of the first version of the page is identical to a portion of the second version of the page, and using a bitmap data structure to determine that the portion of the first version of the page is identical to the portion of the second version of the page, the bitmap data structure indicating the state of one or more cache columns of the second version of the page and one or more cache columns of the first version of the page.

17. The method of claim 16, further comprising determining the modification status of a portion of the first version of the page, wherein accessing the at least portion of the second version of the page includes accessing the portion of the second version of the page corresponding to the portion of the first version of the page.

18. An apparatus for accessing data in a version of a memory page, the apparatus comprising: At least one memory cell; and at least one processor, configured to: store a first version of a page in the at least one memory; A second version of the page is stored in at least one memory unit; And tracking the modification status of at least a portion of the first version of the page, wherein a portion of the first version of the page is identical to a portion of the second version of the page, and using a bitmap data structure to determine that the portion of the first version of the page is identical to the portion of the second version of the page, the bitmap data structure indicating the status of one or more cache columns of the second version of the page and one or more cache columns of the first version of the page.

19. The apparatus of claim 18, wherein the modification status of the at least portion of the first version of the page includes the modification status of a portion of the first version of the page.

20. The apparatus of claim 19, wherein the portion of the first version of the page includes a cache column.

Images