Solid state variable impedance device and system

Abstract

The embodiments disclosed herein include an impedance matching network. In one embodiment, the impedance matching network includes: an input; and a first matrix tuning element on a first branch from the input, wherein the first matrix tuning element includes a variable capacitor. In one embodiment, the impedance matching network further includes: a transformer on a second branch from the input, wherein the transformer has at least a first tap, wherein a second matrix tuning element is on the first tap, and wherein the second matrix tuning element includes a variable capacitor. In one embodiment, the impedance matching network further includes: a third matrix tuning element on the second branch after the transformer, wherein the third matrix tuning element includes a variable capacitor. In one embodiment, the impedance matching network further includes: an output on the second branch after the third matrix tuning element.

Description

Solid-state variable impedance devices and systems Embodiments relate to the field of semiconductor manufacturing, and in particular, to solid-state variable impedance matching systems for plasma processing systems. In many semiconductor processing tools, such as plasma processing tools, an RF source is used to couple power into the chamber. The RF power induces the plasma to process the substrate within the chamber. Due to impedance mismatches, some forward power is reflected back toward the RF source. Therefore, many processing tools include an impedance matching network to match the impedance of the load within the chamber. Typically, impedance matching networks rely on electromechanical tuning systems. These systems can include vacuum variable capacitors driven by motors (e.g., servomotors). Electromechanical tuning systems are common in high-power applications due to their excellent voltage and current control properties. However, electromechanical tuning systems are slow. That is, electromechanical tuning can only operate as fast as the motor drive, which is several orders of magnitude slower than the ion transition rate across the plasma sheath. Solid-state impedance matching networks have been proposed as an alternative to electromechanical systems. Compared to electromechanical systems, solid-state solutions offer improved speed. However, existing solid-state impedance matching networks have some drawbacks. For example, solid-state solutions may not offer the same voltage / current control capabilities and resolution as electromechanical systems. Furthermore, solid-state impedance matching systems are significantly more expensive than electromechanical systems. Embodiments disclosed herein include an impedance matching network. In one embodiment, the impedance matching network includes: an input; and a first matrix tuning element on a first branch from the input, wherein the first matrix tuning element includes a first variable capacitor. In one embodiment, the impedance matching network further includes: a transformer on a second branch from the input, wherein the transformer has at least one first tap, wherein a second matrix tuning element is on the first tap, and wherein the second matrix tuning element includes a second variable capacitor. In one embodiment, the impedance matching network further includes: a third matrix tuning element on the second branch after the transformer, wherein the third matrix tuning element includes a third variable capacitor. In one embodiment, the impedance matching network further includes: an output on the second branch after the third matrix tuning element. Embodiments disclosed herein also include a matrix tuning element. In one embodiment, the matrix tuning element includes: one or more units, wherein each unit includes: an array of diodes coupled to a board, wherein the array includes one or more columns of diodes, and wherein each column includes four rows of diodes connected in series. Embodiments disclosed herein also include semiconductor processing tools. In one embodiment, the semiconductor processing tool includes: a chamber; an RF source; an electrode coupled to the RF source for inducing RF power into the chamber; and an impedance matching network coupled between the RF source and the electrode. In one embodiment, the impedance matching network includes: a first matrix tuning element on a first branch, wherein the first matrix tuning element includes a first variable capacitor; a transformer on a second branch, wherein the transformer has at least one first tap, wherein a second matrix tuning element is on the first tap, and wherein the second matrix tuning element includes a second variable capacitor. In one embodiment, the impedance matching network further includes: a third matrix tuning element on the second branch after the transformer, wherein the third matrix tuning element includes a third variable capacitor. The systems described herein include a solid-state variable impedance matching system for a plasma processing system. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that the embodiments can be practiced without these specific details. In other instances, well-known aspects have not been described in detail to avoid unnecessarily obscuring the embodiments. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. As mentioned above, solid-state impedance matching networks have the advantage of being able to tune faster than electromechanical impedance matching networks. For example, the change in capacitance of the solid-state impedance matching network described herein is controlled by varying the DC bias voltage coupled to the circuit. The limitation on the DC bias voltage used to vary the capacitance of the diode cell arrangement is the rise time of the DC power supply. The current consumption for the DC power is also a function of the rise time. The reverse bias of a diode (such as the diode used herein) requires a low current, and the DC power rise time is expected to be less than 10 μs. Such a short rise time is consistent with the RF pulse requirements of plasma processing tools. In addition to improved tuning speed, the embodiments disclosed herein also feature improved resolution. Resolution is improved by arranging diode cells to use a reverse-bias DC voltage to vary capacitance. The DC bias voltage resolution is comparable to that of a radial electromechanical motor drive. Furthermore, voltage and current control capabilities are improved. As used herein, silicon devices are distributed within the cell arrangement to enable higher current applications. The cells can be configured with impedance transformation circuitry to reduce voltage stress. In one embodiment, the complexity of the solid-state impedance matching network disclosed herein is also minimized. Specifically, the DC bias adjustment circuitry is similar to motor drive solutions in electromechanical systems. Furthermore, the cost of the solid-state impedance matching network disclosed herein is reduced compared to existing solid-state solutions. Specifically, common diodes used in impedance matching units are suitable for this application. This narrows the cost gap between electromechanical and solid-state solutions. As will be described in more detail below, the lowest-level building block of a variable capacitor used in a solid-state impedance matching network is a diode. Specifically, a set of four diodes is provided in a column on a board, electrically connected in series. Multiple columns can be provided, electrically connected in parallel, to form an impedance tuning unit (or simply, a unit). In one embodiment, a plurality of units can be coupled together to form a matrix tuning element. As will be appreciated, scaling to multiple columns of diodes and / or multiple units allows for improved resolution and dynamic range of the impedance matching network. In one embodiment, a plurality of variable capacitors can be arranged in a circuit to provide the desired tuning of the impedance matching network. In one embodiment, each variable capacitor can have a variable capacitance. That is, each variable capacitor can have a capacitance range that can be achieved by controlling the variable capacitor (e.g., using a DC bias voltage). In some cases, each variable capacitor can have a different capacitance range, or two or more variable capacitors can have the same capacitance range. Referring now to FIG. 1A , a perspective view of an impedance matching unit 100 according to one embodiment is shown. In one embodiment, the impedance matching unit 100 includes a plurality of diodes 121 coupled to a board 101 (e.g., a printed circuit board (PCB)). The diodes 121 may be arranged in an array. For example, the array may include a plurality of columns 120, each column 120 comprising four rows. As will be described in greater detail below, each of the four rows of columns 120 provides a building block for an impedance matching network. In the illustrated embodiment, eight columns 120 are shown in FIG. 1 . However, it should be understood that one or more columns 120 may be used in some embodiments. Increasing the number of columns 120 increases the resolution achievable by the impedance matching unit 100. In one embodiment, each column 120 can be electrically coupled in parallel to one another. An input can be provided near the top edge of the board 101, and an output can be provided near the bottom edge of the board 101. The input can be coupled to an RF power source, and the output can be coupled to a load, such as a plasma load of a semiconductor processing tool. Additionally, as will be described in more detail below, a first capacitor can be provided between the column 120 and the input, and a second capacitor can be provided between the column 120 and the output. In addition to a single impedance matching unit 100, a plurality of impedance matching units 100 may be coupled together to provide a matrix tuning element. That is, the matrix tuning element may be a structure including two or more impedance matching units 100. For example, the matrix tuning element may include up to five impedance matching units 100. However, it should be understood that even more impedance matching units 100 may be included in the matrix tuning element. Referring now to FIG. 1B , a perspective view of a matrix tuning element 105 is shown, according to one embodiment. Matrix tuning element 105 includes a plurality of impedance matching elements 100 electrically coupled together. This allows impedance tuning to be scaled to larger matrix tuning elements 105, thereby improving the resolution and capacitance range of the system. While four impedance matching elements 100 are shown in FIG. 1B , it should be understood that matrix tuning element 105 may include two or more impedance matching elements 100. Referring now to FIG. 2A , a circuit diagram of a column 220 of an impedance matching unit 100 is shown, according to one embodiment. In one embodiment, column 220 may include a set of four diodes 221A and 221B connected in series between a first capacitor 213 and a second capacitor 215. Input 212 may be coupled to first capacitor 213, and output 214 may be coupled to second capacitor 215. In one embodiment, diodes 221 may be arranged as cathodes 221A or anodes 221B. The arrangement between first capacitor 213 and second capacitor 215 may include a pattern of cathode diode 221A, anode diode 221B, cathode diode 221A, and anode diode 221B. In some embodiments, diodes 221 may be substantially similar to one another. In other embodiments, diodes 221 may have different IV characteristics. In one embodiment, a ground connection 223 may be provided between the first capacitor 213 and the first cathode diode 221A, and between the second anode diode 221B and the second capacitor 215. A resistor 224 may be provided before each ground connection 223. In one embodiment, DC bias inputs 222A and 222B may be provided between the first cathode diode 221A and the first anode diode 221B, and between the second cathode diode 221A and the second anode diode 221B. A resistor 224 may be provided before each DC bias input 222A and 222B. Control of the DC bias voltage at the DC bias input 222 allows the capacitance value of the column 220 to be modulated to provide a desired impedance matching value. In the illustrated embodiment, a resistor 224 is provided before each DC bias input 222A and 222B. However, it should be understood that any high-impedance passive device (or devices) may be provided before the DC bias inputs 222A and 222B. Specifically, the high-impedance passive device prevents RF power from flowing to DC bias voltages 222A and 222B. In one embodiment, the two DC bias inputs 222A and 222B may apply the same DC bias voltage. In other embodiments, the DC bias voltage of the first DC bias input 222 may be different from the DC bias voltage of the second DC bias input 222. In other embodiments, the bias voltage applied to DC bias voltages 222A and 222B may be a differential bias voltage, a pulsed bias voltage, or the like. More specifically, the bias voltages of DC bias voltages 222A and 222B are not limited to any particular waveform. Furthermore, it should be understood that each column 120 in the impedance matching unit 100 may be independently controllable to provide a desired capacitance value for the impedance matching unit 100. Referring now to FIG. 2B , a pair of columns 220 are shown according to one embodiment. 1 and 220 2. As shown, multiple columns 220 can be coupled in parallel between the RF input 212 and the RF output 214. Individual columns 220 1 and 220 2 may be substantially similar to the columns 220 described in more detail above with reference to FIG. 2A. Although two columns 220 are shown, 1 and 220 2, it should be understood that any number of columns 220 may be provided in parallel between the RF input 212 and the RF output 214. Referring now to FIG. 3A , a circuit diagram of an impedance matching network 350 is shown, according to one embodiment. In one embodiment, impedance matching network 350 may be a solid-state impedance matching network 350 . That is, as opposed to an electromechanical solution that uses a motor to drive different capacitors, impedance control is provided by solid-state components (e.g., diodes). The circuit between input 312 and output 314 can be considered tuning circuit 305. In one embodiment, impedance matching network 350 includes an input 312 and an output 314. Input 312 receives power from an RF source (not shown), and output 314 delivers RF power to a load (not shown), such as a plasma load in a semiconductor processing chamber. In one embodiment, the input 312 is divided into a first branch 331 and a second branch 332. The first branch 331 includes a first variable capacitor C 1. Inductor 335, and ground 336. First variable capacitor C 1 can be a matrix tuning element. That is, the first variable capacitor C 1 may comprise a solid-state impedance tuning unit, similar to the impedance tuning unit 100 described in more detail above. Thus, the first variable capacitor C is controlled by a pair of DC bias voltages. The first branch 331 may then continue to an inductor 335 having an output coupled to ground 336 . In one embodiment, the second branch 332 includes a transformer circuit 306. The transformer circuit 306 may include a transformer 337. In one embodiment, the transformer 337 includes a single tap. However, as will be described in more detail below, the transformer 337 may include a plurality of taps. In one embodiment, a first end of the tap includes a third variable capacitor C 3. The third variable capacitor C 3 can be a matrix tuning element. That is, the third variable capacitor C 3 may comprise a solid-state impedance tuning unit, similar to the impedance tuning unit 100 described in more detail above. Thus, the third variable capacitor C is controlled by a pair of DC biases. 3. The third variable capacitor C The output of 3 may be coupled to ground 336. The opposite second end of the tap may be coupled directly to ground 336. In one embodiment, a second variable capacitor C may be provided along the second branch 332 between the transformer 337 and the output 314. 2. Second variable capacitor C 2 can be a matrix tuning element. That is, the second variable capacitor C 2 may comprise a solid-state impedance tuning unit, similar to the impedance tuning unit 100 described in more detail above. Thus, the second variable capacitor C is controlled by a pair of DC biases. 2 capacitors. It should be understood that a plurality of variable capacitors (eg, C 1. C 2 and C 3) can be independently controlled. Thus, various capacitance values ​​can be used to set the desired impedance in the impedance matching network. In some embodiments, all three variable capacitors C 1. C 2 and C 3 is formed by a solid-state impedance tuning unit or a matrix tuning element. In other embodiments, the variable capacitor C 1. C 2 and C 3. One or both of the variable capacitors may include a solid-state impedance tuning unit or a matrix tuning element. Other variable capacitors may include electromechanical variable capacitors. That is, embodiments may include both solid-state variable capacitors and electromechanical variable capacitors. In addition, it should be understood that the variable capacitor C 1. C 2 and C 3 do not need to have the same range of capacitance. That is, C 1 capacitance range can be with C 2 and / or C 3 has different capacitance ranges, C 2 capacitance range can be with C 1 and / or C 3 has different capacitance ranges, and C 3 capacitance range can be with C 1 and / or C The capacitance range of the 2 is different. Referring now to FIG3B , a circuit diagram of transformer circuit 306 according to an additional embodiment is shown. In one embodiment, transformer circuit 306 can be replaced with impedance matching network 350 described above with reference to FIG3A . In one embodiment, transformer circuit 306 can include a plurality of taps. For example, three taps are provided in FIG3B . However, it should be understood that two or more taps may be included in different embodiments. In one embodiment, inductor 337 can be coupled to inductors 341 through 343. Each of inductors 341 through 343 can be a different tap. In one embodiment, each tap includes inductors 341 to 343 and a variable capacitor C 1 to C 3. Variable capacitor C 1 to C Each of the variable capacitors C 3 may be similar to any of the variable capacitors described in more detail above. For example, the variable capacitor C 1 to C 3 may include a matrix tuning element. That is, a variable capacitor C 1 to C 3 may comprise a solid-state impedance tuning unit, similar to the impedance tuning unit 100 described in more detail above. Thus, the variable capacitor C is controlled by a pair of DC biases. 1 to C 3. In one embodiment, each tap may further include a pair of grounds 336 on opposite sides of the inductors 341 to 343. On one side, the output of the inductors 341 to 343 is directly coupled to the ground 336. A variable capacitor C is provided between the inductors 341 to 343 and the ground 336 on the other side of the inductors 341 to 343. 1 to C 3. In one embodiment, the inductors 341 to 343 may have non-uniform inductances. In other embodiments, the inductors 341 to 343 may have the same inductances. Similarly, the variable capacitor C 1 to C 3 can be the same, or a variable capacitor C 1 to C 3 can have different capacitance ranges. Referring now to FIG. 4A , a circuit diagram of an impedance matching network 450 is shown according to an additional embodiment. In one embodiment, impedance matching network 450 may include an input 412 and an output 414. Input 412 may be coupled to an RF source, and output 414 may be coupled to a load, such as a plasma load in a semiconductor processing tool. In one embodiment, impedance matching network 450 may include a first branch 431 and a second branch 432. The first branch 431 may include a first variable capacitor C 1. The transformer 437 can then be coupled to the first variable capacitor C 1. The transformer 437 may have an output coupled to a second variable capacitor C 2. The single tap may have both ends coupled to ground 436. In one embodiment, the first branch 431 may also terminate at ground 436. In one embodiment, the second branch 431 may include a third variable capacitor C 3. The third variable capacitor C 3 and then an inductor 438 is provided. In one embodiment, the variable capacitor C 1 to C Each of 3 can be a capacitance tuning unit or a plurality of units to form a matrix tuning element. In some embodiments, the variable capacitor C 1 to C 3 may include different capacitance ranges. In other embodiments, two or more variable capacitors C 1 to C 3 can have the same capacitance range. Referring now to FIG. 4B , a circuit diagram of an impedance matching network 450 according to an additional embodiment is shown. In one embodiment, impedance matching network 450 may include an input 412 and an output 414. Input 412 may be coupled to an RF source, and output 414 may be coupled to a load, such as a plasma load in a semiconductor processing tool. In one embodiment, impedance matching network 450 may include a first branch 431, a second branch 432, and a third branch 433. The first branch 431 may include a first variable capacitor C 1. Then, the inductor 439 can be coupled to the first variable capacitor C 1. In one embodiment, the first branch 431 may terminate at ground 436. In one embodiment, the second branch 432 may include a transformer 437. The transformer 437 may have a second variable capacitor C coupled to the first branch 431. 2. The single tap may have both ends coupled to ground 436. In one embodiment, the second branch 432 may also terminate at ground 436. In one embodiment, the third branch 433 may include a third variable capacitor C 3. The third variable capacitor C 3 and then an inductor 438 is provided. In one embodiment, the variable capacitor C 1 to C Each of 3 can be a capacitance tuning unit or a plurality of units to form a matrix tuning element. In some embodiments, the variable capacitor C 1 to C 3 may include different capacitance ranges. In other embodiments, two or more variable capacitors C 1 to C 3 can have the same capacitance range. Referring now to Figures 5A and 5B, graphs of capacitance versus mechanical displacement (Figure 5A) and DC bias voltage (Figure 5B) are shown according to one embodiment. Figure 5A is a graph for an electromechanical tuning system, and Figure 5B is a graph for a solid-state tuning system, such as those described herein. As shown in Figure 5A, the resolution of the capacitance is very high. That is, there is a substantially continuous output. This capacitance relationship enables fine tuning of the impedance. In existing solid-state solutions, the output of the capacitance graph is discontinuous, resulting in low resolution. However, in the embodiments disclosed herein, the capacitance graph is continuous. An example of capacitance versus DC bias voltage is shown in FIG5B . As shown, the high resolution enables fine tuning of the impedance, similar to the electromechanical solution plotted in FIG5A . Additionally, the curve in FIG5B is relatively smooth. Thus, the performance of the solid-state solution described herein can substantially match that of the electromechanical solution. However, as described above, the response time of the solid-state solution described herein is several orders of magnitude faster than that of the electromechanical solution. Accordingly, the embodiments disclosed herein include improved resolution and improved response time compared to existing solutions. Referring now to FIG. 6 , a cross-sectional view of a semiconductor processing tool 680 is shown according to one embodiment. In one embodiment, semiconductor processing tool 680 may include a chamber 681. Chamber 681 may be adapted to support a low-pressure environment, such as a near-vacuum pressure. In one embodiment, a pumping and exhaust system (not shown) may be included to achieve the low-pressure environment. In one embodiment, one or more process gases may flow into the chamber. For example, the process gases may flow into chamber 681 through a lid 685. Lid 685 may be a showerhead-type component to more evenly distribute the gases into chamber 681. In one embodiment, chamber 681 may include a pedestal 682. Pedestal 682 may be adapted to support substrate 683. Pedestal 682 may include heating and / or cooling features to control the temperature of substrate 683 during processing. Substrate 683 may be coupled to pedestal 682 using any suitable chuck mechanism. For example, an electrostatic chuck, a vacuum chuck, etc. may be used to secure substrate 683. Substrate 683 may be any substrate processed in semiconductor processing tool 680. For example, substrate 683 may include a semiconductor wafer, such as a silicon wafer. However, other semiconductor materials may also be used. In one embodiment, the wafer has a standard form factor, such as 150 mm, 200 mm, 300 mm, 450 mm, etc. In one embodiment, other substrates (e.g., glass, sapphire, etc.) may also be processed in chamber 681. In one embodiment, an RF source 686 can be coupled to the chamber 681. Specifically, the RF source 686 can be coupled to the lid 685 or other electrode in the chamber 681. The RF source 686 generates RF power that can be coupled to the processing gas within the chamber 681 to form a plasma 684 for processing the substrate 683. To maximize the forward power entering the chamber 681 (with minimal reflected power), an impedance matching network 687 can be provided between the RF source 686 and the lid 685. In one embodiment, impedance matching network 687 may be substantially similar to any impedance matching network described in greater detail herein. Specifically, impedance matching network 687 may be a solid-state impedance matching network 687. For example, impedance matching network 687 may include variable capacitors formed from a diode array. The diode array may be arranged in four rows on a board in any number of parallel columns to form a unit cell. Multiple units may be coupled together to form a matrix tuning element. A DC bias voltage may be used to control the capacitance of the variable capacitor (i.e., the variable capacitance). As described above, the rise time of the DC bias voltage may be approximately 10 μs or less. This enables flexible and precise control of the variable capacitance to control the impedance of impedance matching network 687. In one embodiment, each of the variable capacitors may have a variable capacitance. That is, each variable capacitor may have a capacitance range that can be achieved by controlling the variable capacitor (e.g., using a DC bias voltage). In some cases, each variable capacitor may have a different capacitance range, or two or more variable capacitors may have the same capacitance range. In one embodiment, semiconductor processing tool 680 may also include a second RF source 688. Second RF source 688 may be coupled to susceptor 682 and / or substrate 683. Second RF source 688 may be used in conjunction with RF source 686. In other embodiments, second RF source 688 may be used in place of RF source 686. Second RF source 686 may be coupled to the chamber via a second impedance matching network 689. In one embodiment, the second impedance matching network 689 can be substantially similar to any impedance matching network described in greater detail herein. Specifically, the second impedance matching network 689 can be a solid-state impedance matching network 689. For example, the second impedance matching network 689 can include a variable capacitor formed by a diode array. The diode array can be arranged in four rows on a board in any number of parallel columns to form a unit cell. Multiple units can be coupled together to form a matrix tuning element. A DC bias voltage can be used to control the capacitance of the variable capacitor. As described above, the rise time of the DC bias voltage can be approximately 10 μs or less. This allows for flexible and precise control of the variable capacitor to control the impedance of the second impedance matching network 689. Referring now to FIG7 , a block diagram of an exemplary computer system 700 of a processing tool according to one embodiment is illustrated. In one embodiment, the computer system 700 is coupled to and controls the processing in the processing tool. The computer system 700 can be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The computer system 700 can operate in the capacity of a server or client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 700 can be a personal computer (PC), a tablet computer, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) to specify the actions to be taken by the machine. Further, while a single machine is illustrated with respect to computer system 700, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein. The computer system 700 may include a computer program product, or software 722, a non-transitory machine-readable medium having instructions stored thereon that can be used to program the computer system 700 (or other electronic devices) to perform processes according to embodiments. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer) storage medium (e.g., read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine-readable (e.g., computer) transmission medium (electrical, optical, acoustic, or other form of propagated signals (e.g., infrared light signals, digital signals, etc.)), etc. In one embodiment, the computer system 700 includes a system processor 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 718 (e.g., a data storage device), which communicate with each other via a bus 730. System processor 702 represents one or more general-purpose processing devices, such as a microsystem processor, a central processing unit, or the like. More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor that implements other instruction sets, or a system processor that implements a combination of instruction sets. System processor 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network system processor, or the like. System processor 702 is configured to execute processing logic 726 for performing the operations described herein. The computer system 700 may further include a system network interface device 708 for communicating with other devices or machines. The computer system 700 may also include an image display unit 710 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generating device 716 (e.g., a speaker). Secondary memory 718 may include a machine-accessible storage medium 732 (or, more specifically, a computer-readable storage medium) on which is stored one or more sets of instructions (e.g., software 722) that implement any one or more of the methods or functions described herein. Software 722 may also reside, completely or at least partially, within main memory 704 and / or within system processor 702 during execution by computer system 700, with main memory 704 and system processor 702 also constituting machine-readable storage media. Software 722 may further be transmitted or received over network 720 via system network interface device 708. In one embodiment, network interface device 708 may operate using RF coupling, optical coupling, acoustic coupling, or inductive coupling. Although the machine-accessible storage medium 732 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be construed to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be construed to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methodologies. Accordingly, the term "machine-readable storage medium" should be construed to include, but not be limited to, solid-state memory, and optical and magnetic media. In the foregoing specification, specific exemplary embodiments have been described. It will be apparent that various modifications may be made thereto without departing from the scope of the following claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. 100: Impedance matching unit 101: Plate 105: Matrix tuning element 120: Column 121: Diode 212: Input 213: First capacitor 214: Output 215: Second capacitor 220: Column 220 1: Column 220 2: Column 221: Diode 221A: Cathode Diode 221B: Anode Diode 222: DC Bias Input 222A: DC Bias Input 222B: DC Bias Input 223: Ground Connection 224: Resistor 305: Tuning Circuit 306: Transformer Circuit 312: Input 314: Output 331: First Branch 332: Second Branch 335: Inductor 336: Ground 337: Transformer 341-343: Inductor 350: Impedance Matching Network 412: Input 414: Output 431: First Branch 432: Second Branch 433: Third Branch 436: Ground 437: Transformer 438: Inductor 439: Inductor 450: Impedance matching network 680: Semiconductor processing tool 681: Chamber 682: Base 683: Substrate 684: Plasma 685: Lid 686: RF source 687: Impedance matching network 688: Second RF source 689: Second impedance matching network 700: Computer system 702: System processor 704: Main memory 706: Static memory 708: System network interface device 710: Image display unit 712: Alphanumeric input device 714: Cursor control device 716: Signal generating device 718: Secondary memory 720: Network 722: Software 726: Processing logic 730: Bus 732: Machine-accessible storage medium C 1: First variable capacitor C 2: Second variable capacitor C 3: The third variable capacitor FIG. 1A is a perspective view of a solid-state impedance tuning unit according to an embodiment. 1B is a perspective view of a solid-state matrix tuning element according to one embodiment. FIG. 2A is a circuit diagram of a column of diodes in an impedance tuning unit according to one embodiment. FIG. 2B is a circuit diagram of a matrix tuning element according to an embodiment. 3A is a circuit diagram of a solid-state impedance tuning network having a plurality of variable capacitors, each of which may be a unit cell or matrix tuning element, according to one embodiment. 3B is a circuit diagram of a transformer for a solid-state impedance tuning network including a plurality of taps according to one embodiment. 4A is a circuit diagram of a solid-state impedance tuning network having a plurality of variable capacitors, each of which may be a unit cell or matrix tuning element, according to additional embodiments. 4B is a circuit diagram of a solid-state impedance tuning network having a plurality of variable capacitors, each of which may be a unit cell or matrix tuning element, according to additional embodiments. 5A is a graph of capacitance versus mechanical displacement for an electromechanical impedance matching network according to one embodiment. 5B is a graph of capacitance versus DC voltage for a solid-state impedance matching network, according to one embodiment. 6 is a cross-sectional view of a semiconductor processing tool including one or more solid-state impedance matching networks according to one embodiment. 7 illustrates a block diagram of an exemplary computer system that may be used in conjunction with a processing tool according to one embodiment. Domestic deposit information (please note in the order of deposit organization, date, and number) None Foreign deposit information (please note in the order of deposit country, organization, date, and number) None 100: Impedance matching unit 101: Board 120: Column 121: Diode

Claims

1. An impedance matching network, comprising: One input; A first matrix tuning element on a first branch from the input, wherein the first matrix tuning element includes a first variable capacitor and wherein the first matrix tuning element is connected in series with an inductor; a transformer on a second branch from the input, wherein the transformer has at least a first tap, wherein a second matrix tuning element is on the first tap and wherein the second matrix tuning element includes a second variable capacitor; a third matrix tuning element on the second branch after the transformer, wherein the third matrix tuning element includes a third variable capacitor; and an output on the second branch after the third matrix tuning element.

2. The impedance matching network as described in claim 1, wherein the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element are identical to each other.

3. The impedance matching network as described in claim 1, wherein two or more of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element are different from each other.

4. The impedance matching network as claimed in claim 1, wherein each of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element comprises at least four diodes connected in series with each other.

5. The impedance matching network as described in claim 4, wherein the four diodes comprise: A first cathode diode, a first anode diode, a second cathode diode, and a second anode diode.

6. The impedance matching network as described in claim 5, wherein a ground connection is provided before the first cathode diode and after the second anode diode.

7. The impedance matching network as described in claim 5, wherein a first DC bias is connected between the first cathode diode and the first anode diode, and wherein a second DC bias is connected between the second cathode diode and the second anode diode.

8. The impedance matching network as described in claim 7, wherein the first DC bias and the second DC bias are differential bias or pulse bias.

9. The impedance matching network as described in claim 1, wherein one or more of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element comprises: An impedance tuning unit having two or more columns of diodes, wherein each column comprises four rows of such diodes connected in series.

10. An impedance matching network as described in claim 8, wherein two or more columns of diodes are electrically connected in parallel.

11. The impedance matching network as described in claim 8, wherein each of the matrix tuning elements comprises a plurality of impedance tuning units.

12. The impedance matching network as described in claim 1, wherein the transformer includes three or more taps, and wherein each tap includes a matrix tuning element.

13. The impedance matching network as described in claim 1, wherein the output is coupled to a plasma processing tool and wherein the input is coupled to an RF power source.

14. The impedance matching network as claimed in claim 1, wherein at least one of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element is a solid-state device, and wherein at least one of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element is an electromechanical device.

15. A semiconductor processing tool, comprising: One chamber; An RF source; an electrode coupled to the RF source for sensing RF power entering the chamber; and an impedance matching network coupled between the RF source and the electrode, wherein the impedance matching network includes: a first matrix tuning element on a first branch, wherein the first matrix tuning element includes a first variable capacitor and wherein the first matrix tuning element is connected in series with an inductor; a transformer on a second branch, wherein the transformer has at least one first tap, wherein a second matrix tuning element is on the first tap and wherein the second matrix tuning element includes a second variable capacitor; and a third matrix tuning element on the second branch after the transformer, wherein the third matrix tuning element includes a third variable capacitor.

16. The semiconductor processing tool as claimed in claim 15, wherein each of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element comprises a plurality of units, wherein each unit comprises a plurality of columns of diodes, and wherein each column comprises four rows of diodes coupled together in series.

17. The semiconductor processing tool as claimed in claim 15, wherein the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element have a variable capacitor controlled by a DC bias.

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