Semiconductor structure with metal bonding interface and method for making the same

Abstract

This disclosure relates to semiconductor structures, memory devices, and methods of manufacturing the same. The method includes providing a first structure including a first substrate and a wiring layer disposed above the first substrate. The method includes providing a second structure including a second substrate. The method includes forming a first metal bonding layer on the first substrate and forming a second metal bonding layer on a first surface of the second substrate. The method includes bonding the first metal bonding layer and the second metal bonding layer to form a bonding metal layer. The method includes removing a portion of the second structure and forming a second surface of the second structure. The method includes patterning the second structure to form a plurality of vertical elements. The method includes patterning the bonding metal layer to form a plurality of contact structures for the plurality of vertical elements. In particular, some embodiments of this disclosure relate to semiconductor structures having vertical elements in contact with contact structures, memory cells having vertical elements as selectors, and methods of manufacturing the same.

Description

Semiconductor Structure with Metal Bonding Interface and Method for Manufacturing the Same This disclosure relates to semiconductor structures, memory elements, and methods for manufacturing the same. In particular, some embodiments of this disclosure relate to semiconductor structures having vertical elements in contact with a contact structure, memory cells having a vertical element as a selector, and methods for manufacturing the same. The semiconductor industry continuously needs to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). This improvement in integration density comes from continuously reducing the minimum feature size, such that more components can be integrated within a given wafer area. However, there are physical limitations in the lithography process. On the other hand, as the size of semiconductor components decreases and the integration density increases, the space between these components becomes smaller. This inter-device space becomes more critical for the performance of the components, and when this space is too small, these components may affect each other. Therefore, a compromise is needed to balance the feature size and the inter-device space, and the performance of each component may need to be optimized. When the lateral size of semiconductor components becomes smaller in each technology generation, it faces a bottleneck in further improving the integration density. One means is to integrate components through vertical stacking and interconnection. A method to achieve this means is to use a wafer-to-wafer bonding process to form vertical electrical interconnections between stacked wafers. Specifically, a first metal contact in a first wafer is aligned with a corresponding second metal contact in a second wafer, and a subsequent wafer-to-wafer bonding is performed to bond the first wafer and the second wafer. However, when the feature size of the metal contact is very small, misalignment problems may occur in the wafer-to-wafer bonding process, and the electrical interconnections between the stacked wafers may fail. There is still a need to improve the manufacturing process to achieve higher integration density and better component performance. According to this disclosure, a method for manufacturing a semiconductor structure is provided. The method includes a first structure including a first substrate and a wiring layer located above the first substrate (step (a)). The method includes providing a second structure including a second substrate (step (b)). The method includes forming a first metal bonding layer on the first structure and forming a second metal bonding layer on a first surface of the second substrate (step (c)). The method includes bonding the first metal bonding layer and the second metal bonding layer to form a bonded metal layer (step (d)). The method includes removing a portion of the second structure and forming a second surface of the second substrate (step (e)). The method includes patterning the second structure to form a plurality of vertical elements (step (f)). The method includes patterning the bonded metal layer to form a plurality of contact structures for the plurality of vertical elements (step (g)). According to the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a wiring layer, a first contact structure, a second contact structure, a first vertical element, a second vertical element, and a second dielectric layer. The wiring layer is located in a first dielectric layer. The first contact structure lands on the wiring layer. The second contact structure lands on the wiring layer. The first vertical element is above and in contact with the first contact structure. The second vertical element is above and in contact with the second contact structure. The first vertical element and the second vertical element are at the same level. The second dielectric layer is above the first dielectric layer. The second dielectric layer surrounds each of the first vertical element, the second vertical element, the first contact structure, and the second contact structure. Each of the first contact structure and the second contact structure includes a first metal layer, a second metal layer above the first metal layer, and a metal bonding interface between the first metal layer and the second metal layer. According to the present disclosure, a memory element is provided. The memory element includes a first wiring layer, a first contact structure, a first vertical element, a first memory cell, and a second wiring layer. The first wiring layer is located above a first substrate and is electrically connected to a functional element in the first substrate. The first contact structure lands on the first wiring layer. The first contact structure includes a first metal layer and a second metal layer above the first metal layer and directly bonded to the first metal layer. The first vertical element is above the first contact structure and is in contact with the first contact structure at a first end of the first vertical element. The first memory cell is above the first vertical element and has a first end and a second end. The first vertical element is electrically connected to the second end of the first memory cell by a second end of the first vertical element. The second wiring layer is electrically connected to the first end of the first memory cell. The first metal layer is in contact with the first wiring layer, and the second metal layer is in contact with the first vertical element. Through the present disclosure described herein, multiple vertical components (e.g., the vertical PN diodes 54a, 55a, 56a, and / or 57a shown in FIGS. 1H, 2E, 3E, 4F, 5G, 12E, 13E, and 14, the vertical Schottky diodes 54b and / or 55b shown in FIGS. 6F and 7, and the vertical transistors 54c, 54d, 55c, and / or 55d shown in FIGS. 8F, 9, 10, and 11), metal contact structures (e.g., the metal contact structures 40a, 40b, 40c, and / or 40d shown in the above figures), and wiring layers (e.g., the wiring layer 31 shown in the above figures) can be easily aligned and the metal bonding interfaces therein can be ideal, which can provide better electrical connection between the vertical components and the wiring layer through the corresponding metal contact structures. The conductive features in the wiring layer can be linear (e.g., the first wiring layer 31 shown in FIG. 1F) or island-shaped (e.g., the first wiring layer 31 shown in FIG. 5E) according to the circuit design. Through the present disclosure described herein, since multiple metal contact structures can be formed from an unpatterned bonding metal layer according to alignment marks, the misalignment problem of wafer-to-wafer bonding can be avoided. In some embodiments, as described below, each of the metal contact structures can be formed by patterning a bonding metal layer formed by bonding a first metal bonding layer and a second metal bonding layer. Thus, the second metal layer of the contact structure can be directly bonded to the corresponding first metal layer of the same contact structure, such that a metal bonding interface is formed between the first metal layer and the second metal layer. Through the present disclosure described herein, even when the feature size is small, the connection between metal bonding layers (e.g., the metal bonding layers 41 and / or 42 shown in FIGS. 1B, 2B, 3B, 4B, 5B, 6B, and 8B) can be ensured, and the misalignment problem of wafer-to-wafer bonding can be avoided. For example, referring to FIGS. 1C, 2C, 3C, 4C, 5C, 6C, 8C, and 13D, when both the first metal bonding layer 41 and the second metal bonding layer 42 are unpatterned metal layers, a metal bond with ideal bonding strength can be formed and can be "self-aligned". In some embodiments, at least one of the first metal bonding layer and the second metal bonding layer can be patterned. This can avoid generating thermal mismatch at the metal-dielectric interface, which would reduce the bonding strength and the reliability of the bond. Through the present disclosure described herein, multiple memory units having multiple vertical elements, metal contact structures, and wiring layers can be formed as described above (for example, the memory units 100a and / or 100b shown in FIGS. 1H, 2E, 3E, 4F, 5G, 6F, and 7 may include a phase-change material or a variable resistance material, and the memory units 100a and / or 100b shown in FIGS. 8F, 9, 12E, 13E, and 14 may include a magnetic tunnel junction (MTJ) structure, a phase-change material, or a variable resistance material) to jointly serve as memory elements (for example, the PcRAM element or RRAM element shown in FIGS. 1H, 2E, 3E, 4F, 5G, 6F, 7, 8F, and 9, the STT-MRAM element shown in FIGS. 8F, 9, 12E, and 14, and the SOT-MRAM element shown in FIG. 13E). In some embodiments, a semiconductor structure can serve as a memory element (for example, the surrounding gate transistor nonvolatile memory device shown in FIG. 10 and the ZRAM element shown in FIG. 11) without additional memory units. Through the present disclosure described herein, the second structure for bonding may include a second substrate (for example, a single-crystalline silicon substrate) having an implanted hydrogen layer (for example, the second structure 100B shown in FIG. 1A) or having an embedded etch stop layer (for example, the second structure 300B shown in FIG. 3A). In some embodiments, a silicon-on-insulator (SOI) substrate (for example, the second structure 200B shown in FIG. 2A) or a silicon-etch-stopper-on-insulator (SEOI) substrate (for example, the second structure 400B shown in FIG. 4A) can be used instead of the implanted hydrogen layer to alleviate a large amount of particles and contamination generated when removing a part of the second structure and can provide an additional option for manufacturing vertical elements. Even when used in conjunction with the detailed description of certain specific embodiments in this field, the terms used in the following description are intended to be interpreted in the broadest reasonable manner. Although specific terms may be emphasized hereinafter, any terms intended to be interpreted in any restrictive manner will be defined in this embodiments section. Components or functions of a semiconductor structure or device according to the present disclosure may be depicted in the following figures or embodiments, however, the size and shape of the semiconductor structure or device shown in the figures do not limit the features of the present disclosure. As used in this application, the term "on" may mean directly on top of or indirectly on top of through intervening elements or layers. Spatial relative terms such as, for example, "beneath", "below", "lower", "above", "over", "upper", and the like may be used herein to simplify the description of the relationship of one element or feature depicted in the figures to another element or feature. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figures is turned over, an element described as "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "beneath" can encompass both the orientation of "above" and "beneath". The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative terms used herein may be interpreted accordingly. FIGS. 1A to 1I are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 1A, a first structure 100A is provided (step (a)). The first structure 100A includes a first substrate 10 and a first wiring layer 31. The first substrate 10 may include a layer of semiconductor material. In some embodiments, the first substrate 10 may include single-crystalline semiconductor material, such as made of silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the first substrate 10 may include glass, polysilicon, or ceramic. The first substrate 10 may include a semiconductor device including but not limited to a transistor or a diode. In some embodiments, the first substrate 10 may include a functional element (e.g., the functional element 11 shown in FIG. 1G). The first wiring layer 31 may be located above the first substrate 10. The first wiring layer 31 may include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), other suitable materials, or combinations thereof. The first wiring layer 31 may be fabricated by any suitable process (e.g., photolithography and etching processes, damascene process, dual damascene process, or the like). For example, the first wiring layer 31 may be formed in a first dielectric layer 21 disposed on the first substrate 10 using a damascene process, a dual damascene process, or any suitable method. In some embodiments, the first wiring layer 31 may include a plurality of conductive lines (e.g., a first word line WL1 and a second word line WL2). In some embodiments, the first structure 100A may further include alignment marks 90 located on the first substrate 10. The alignment marks 90 may be fabricated by any suitable method. Fabrication of the first wiring layer 31 and the semiconductor device in the first substrate 10 and subsequent fabrication of semiconductor devices and / or conductive features in and / or above the second substrate 50 may be performed according to the alignment marks 90 (detailed below with reference to FIG. 1E). In one embodiment, the alignment marks 90 may include a plurality of marking layers. For simplicity, only a portion of the alignment marks are shown in the figures herein. As shown in FIG. 1A, a second structure 100B is provided (step (b)). The second structure 100B includes a second substrate 50. The second substrate 50 may include a layer of semiconductor material. In some embodiments, the second substrate 50 may include single-crystalline semiconductor material, such as made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the second substrate 50 includes a first semiconductor material layer 51 and a second semiconductor material layer 52. The second semiconductor material layer 52 may be located above the first semiconductor material layer 51. In some embodiments, the first semiconductor material layer 51 may be doped with a first type of dopant. For example, a p-type dopant such as boron, aluminum, gallium, indium, etc. or a combination thereof, or an n-type dopant such as phosphorus, arsenic, antimony, bismuth, etc. or a combination thereof. In some embodiments, the second semiconductor material layer 52 may be doped with a second type of dopant different from the first type of dopant. For example, the above-mentioned p-type dopant or n-type dopant. In some embodiments, the doping concentration of the first semiconductor material layer 51 and / or the second semiconductor material layer 52 may be between about 1.0×10 14 atoms / cm 3 to about 5.0×10 17 atoms / cm 3 . In one embodiment, the thickness range of the second substrate 50 may be between about 100 nanometers and 1 millimeter. These values are only examples and are not intended to be limiting. As shown in FIG. 1A, the first semiconductor material layer 51 may further include a first heavily doped layer 46. In one embodiment, the first heavily doped layer 46 may be formed by ion implantation or epitaxial growth. In some embodiments, the first heavily doped layer 46 may be doped with the first type of dopant as described above for the first semiconductor material layer 51. In some embodiments, the first heavily doped layer 46 may have a higher doping concentration than the first semiconductor material layer 51. In some embodiments, the doping concentration of the first heavily doped layer 46 may be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 . In one embodiment, the thickness range of the first heavily doped layer 46 may be between about 5 nanometers and about 100 nanometers. These values are only examples and are not intended to be limiting. As shown in FIG. 1A, the second semiconductor material layer 52 may further include a second heavily doped layer 47 extending from the first surface 50a of the second substrate 50. In one embodiment, the second heavily doped layer 47 may be formed by ion implantation or epitaxial growth. In some embodiments, the second heavily doped layer 47 may be doped with a second type of dopant as described above for the second semiconductor material layer 52. In some embodiments, the second heavily doped layer 47 may have a higher doping concentration than the second semiconductor material layer 52. In some embodiments, the doping concentration of the second heavily doped layer 47 may be 1.0×10 18 atoms / cm 3 to 3.0×10 20 atoms / cm 3 . In one embodiment, the thickness range of the second heavily doped layer 47 may be between about 5 nm and about 100 nm. These values are only examples and are not intended to be limiting. In the embodiment shown in FIG. 1A, the second substrate 50 further includes an implanted hydrogen layer 58 in the second substrate 50. The implanted hydrogen layer 58 is implanted to a certain depth in the second substrate before bonding the first structure 100A and the second structure 100B. As long as the implanted hydrogen layer 58 is not damaged by subsequent processes, implantation may be performed before or after the formation of the first semiconductor material layer 51 and / or the second semiconductor material layer 52. For example, if the formation of the first semiconductor material layer 51 and / or the second semiconductor material layer 52 requires high temperature (such as an annealing process), hydrogen generally needs to be implanted after the formation of the first semiconductor material layer 51 and / or the second semiconductor material layer 52. In some embodiments, implantation may be performed after the formation of a metal layer (e.g., the second metal bonding layer 42 as described below in FIG. 1B). In one embodiment, hydrogen ions may be implanted into the second substrate 50 with a dose of 1×10 16 ions / cm 2 to 2×10 17 ions / cm 2 at an implantation energy of 50 keV to 150 keV. A larger dose may be used for a larger substrate. It may be about 4×10 -5 to 8×10 -5An implanted hydrogen layer 58 is formed to a depth of [[ID=]], e.g., from 1 to 2 microns. These values are provided as examples only and are not intended to be limiting. In one embodiment, since the thicknesses of the first semiconductor material layer 51 and the second semiconductor material layer 52 are known, an appropriate implantation voltage can be selected to cause the peak of the implanted hydrogen to occur at a desired depth below the first surface 50a. As shown in FIG. 1B, before bonding the first structure 100A and the second structure 100B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). In some embodiments, the first metal bonding layer 41 can be formed in contact with the wiring layer 31. In some embodiments, the second metal bonding layer 42 can be formed in contact with the first surface 50a of the second substrate 50. In some embodiments, the second metal bonding layer 42 can be formed in contact with the second semiconductor material layer 52. In some embodiments, the second metal bonding layer 42 can be formed in contact with the second heavily doped layer 47 of the second semiconductor material layer 52. In some embodiments, the second heavily doped layer 47 is formed before the second metal bonding layer 42. In some embodiments, each of the first metal bonding layer 41 and the second metal bonding layer 42 can include a suitable metal, a conductive metal compound (e.g., metal silicide, metal nitride), or a metal alloy, such as aluminum (Al), gold (Au), indium (In), palladium (Pd), germanium (Ge), copper (Cu), aluminum-silicon alloy (Al-Si), titanium nitride (TiN), nickel silicide, cobalt silicide, tungsten silicide, chromium silicide, platinum silicide, titanium silicide, molybdenum silicide, palladium silicide, lead-tin alloy (Pb-Sn), aluminum-tin alloy (Al-Sn), gold-tin alloy (Au-Sn), indium-palladium alloy (In-Pd), indium-tin alloy (In-Sn), silver-tin alloy (Ag-Sn), gold-indium alloy (Au-In), copper-tin alloy (Cu-Sn), or a combination thereof. In one embodiment, the thickness of each of the first metal bonding layer 41 and the second metal bonding layer 42 can range from about 5 nanometers to 500 nanometers. These values are provided as examples only and are not intended to be limiting. In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 can be formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 can be formed by sputtering, evaporation, or electroplating. In some embodiments, the first metal bonding layer 41 and the second metal bonding layer 42 may have the same composition; however, in other embodiments, the first metal bonding layer 41 and the second metal bonding layer 42 may have different compositions as long as a successive bonding process can be implemented between the first metal bonding layer 41 and the second metal bonding layer 42. In some embodiments, the first metal bonding layer 41 and the second metal bonding layer 42 may each have a multi-layer structure. The compositions and structures of the first metal bonding layer 41 and the second metal bonding layer 42 can be adjusted according to the desired bonding strength and / or component properties. As shown in FIG. 1C, the first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 100B is flipped and bonded to the first structure 100A through the bonding metal layer 40 to form a bonded structure 100C. The first metal bonding layer 41 and the second metal bonding layer 42 can be bonded through thermal compression bonding, eutectic bonding, or reactive bonding. In some embodiments, the bonding of the first metal bonding layer 41 and the second metal bonding layer 42 can be a direct bonding. For example, the first metal bonding layer 41 and the second metal bonding layer 42 can be bonded through a thermal compression bonding process such as diffusion bonding. In one embodiment, both the first metal bonding layer 41 and the second metal bonding layer 42 can be cleaned through conventional cleaning techniques such as dry etching and plasma surface treatment. The cleaning process removes surface impurities and particles from the surfaces of the metal bonding layers 41 and 42. In one embodiment, an external pressure can be applied to the stacked first structure 100A, first metal bonding layer 41, second metal bonding layer 42, and second structure 100B during the thermal process. In some embodiments, atoms on the surfaces of the first metal bonding layer 41 and the second metal bonding layer 42 can inter-diffuse, such that a metal bond can be formed at the metal bonding interface 43 to form the bonding metal layer 40. In one embodiment, the thickness range of the bonding metal layer 40 can be between 5 nanometers and 1000 nanometers. These values are only examples and are not intended to be limiting. In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 may include a stack including conductive sublayers such as the metals, conductive metal compounds, or metal alloys described above. In some embodiments, the first metal bonding layer 41 may be electrically coupled to a semiconductor element formed in the first substrate 10. In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 may include a diffusion barrier layer (not shown), which may include titanium, tungsten, tantalum, and nitrides thereof. The diffusion barrier layer may contact the second substrate 50 to prevent the diffusion of metal from the metal bonding layer into the second substrate 50. At least one of the first metal bonding layer 41 and the second metal bonding layer 42 is an unpatterned metal layer. As used herein, an unpatterned layer describes a material layer that continuously extends from one point to another point within at least one given region and can be separated by removing a portion of the material layer in a subsequent patterning process. In the embodiment shown in FIG. 1C, both the first metal bonding layer 41 and the second metal bonding layer 42 are unpatterned metal layers, such that the metal bonding interface 43 between the first metal bonding layer 41 and the second metal bonding layer 42 continuously extends from a point overlapping with the first word line WL1 to a point overlapping with the second word line WL2 without a metal-dielectric interface therebetween. However, in some other embodiments, one of the first metal bonding layer and the second metal bonding layer may be patterned. Through the processes described herein, even when the feature size is small, connection between the metal bonding layers can be ensured and the wafer-to-wafer bonding misalignment problem can be avoided. In the case where both the first metal bonding layer 41 and the second metal bonding layer 42 are unpatterned metal layers, a metal bond with ideal bonding strength and that can be "self-aligned" can be formed. This can also avoid the thermal mismatch that occurs at the metal-dielectric interface, which reduces the bonding strength and bonding reliability. Moreover, since the first wiring layer 31 has a larger coefficient of thermal expansion (CTE) than the first dielectric layer 21, when the first metal bonding layer 41 and the second metal bonding layer 42 are bonded, the portion of the metal feature adjacent to the first wiring layer 31 can be subjected to a relatively larger pressure than the portion of the dielectric material adjacent to the first dielectric layer 21, which can provide a larger bonding strength above the metal feature of the first wiring layer 31. Therefore, the portion of the bonded metal layer 40 remaining after the subsequent patterning process may include a metal bonding interface with a larger bonding strength. As shown in FIG. 1D, a portion of the second structure 100B is removed, and a second surface 50b of the second substrate 50 is formed (step (e)). In the embodiment shown in FIG. 1D, a portion of the second substrate 50 is removed from approximately where the hydrogen implantation layer 58 is implanted. The portion of the second substrate 50 can be removed by heating the bonding structure 100C at a first temperature. If there are any semiconductor elements in the semiconductor elements in the first structure 100A and / or the second structure 100B, the first temperature is generally lower than 400 °C to avoid any damage to the semiconductor elements fabricated in the first structure 100A and / or the second structure 100B. In some embodiments, as long as the portion of the second substrate 50 has been sufficiently weakened by prior hydrogen implantation and some subsequent annealing, the portion of the second substrate 50 can be removed by other methods. For example, the bonding structure 100C can be disconnected by applying physical pressure to the second substrate 50 or by soaking in liquid nitrogen and quenching the bonding structure 100C. Depending on the implantation depth of the implanted hydrogen layer 58, the portion of the second substrate 50 remaining on the bonding structure 100C can be less than 3 microns. The thickness of the remaining portion of the second substrate 50 can also depend on the semiconductor manufacturing technology node applied to fabricate various semiconductor elements. After removal, the second surface 50b of the second substrate 50 is formed. The second surface 50b of the second substrate 50 generally has a roughness on the order of a few hundred angstroms. The second surface 50b of the second substrate 50 can be polished by chemical mechanical polishing (CMP) to planarize and minimize non-uniformity. Other methods such as etching can be used for the same purpose. When etching is used to planarize and minimize the non-uniformity of the second surface 50b of the second substrate 50, it may be necessary to deposit an etching stop layer (not shown) in advance. In the embodiment shown in FIG. 1D, after removing a portion of the second structure 100B (e.g., a portion of the second substrate 50), the first heavily doped layer 46 is exposed. In some other embodiments, after a portion of the second structure 100B is removed and the second surface 50b of the second structure 50 is formed (step (e)), the first heavily doped layer 46 extending from the second surface 50b of the second substrate 50 can be formed (step (j2)). In this case, the first heavily doped layer 46 can be formed using materials and methods similar to those described above with reference to FIG. 1A. As shown in FIG. 1E, the second structure 50 is patterned to form a plurality of vertical elements including a first vertical element 54a and a second vertical element 55a (step (f)). In the embodiment shown in FIG. 1E, each of the first vertical element 54a and the second vertical element 55a is a vertical PN diode. The present disclosure is not limited thereto. In some embodiments, the patterning of the second structure 50 to form a plurality of vertical elements (step (f)) may be performed after bonding the first metal bonding layer 41 and the second metal bonding layer 42 (step (d)). The second structure 50 may be patterned by any suitable process (e.g., photolithography and etching processes). In some embodiments, the patterning process of the second structure 50 may be performed according to the alignment marks 90 of the first structure 100A. In some embodiments, the bonding metal layer 40 may serve as an etch stop layer in the etching process of patterning the second structure 50. As shown in FIG. 1E, the bonding metal layer 40 is patterned to form a plurality of contact structures including a first contact structure 40a and a second contact structure 40b for the first vertical element 54a and the second vertical element 55a (step (g)). In some embodiments, the patterning of the bonding metal layer 40 to form a plurality of contact structures (step (g)) may be performed after bonding the first metal bonding layer 41 and the second metal bonding layer 42 (step (d)). The bonding metal layer 40 may be patterned by any suitable process (e.g., photolithography and etching processes). For example, a dry etching process (e.g., reactive-ion etching and inductively coupled plasma) may be used to pattern the bonding metal layer 40. In one embodiment, when the bonding metal layer 40 includes aluminum (e.g., an aluminum alloy), the bonding metal layer 40 may be dry-etched and patterned by using a mixed gas of boron trichloride (BCl 3 ), chlorine gas (Cl 2 ) and ammonia gas (NH 3 ) as the etching gas. In some embodiments, when the bonding metal layer 40 includes titanium nitride (TiN), it may be patterned by using carbon tetrafluoride (CF 4 ), boron trichloride (BCl 3 ) and nitrogen gas (N 2 ), or argon gas (Ar) and chlorine gas (Cl 2Dry-etching and patterning the bonding metal layer 40 using a mixed gas of FIG. 1F is a schematic top view of the semiconductor structure shown in FIG. 1E, and FIG. 1G is another cross-sectional view of the semiconductor structure shown in FIG. 1E. Specifically, FIG. 1E is a cross-sectional view of the semiconductor structure in FIG. 1F along line A-A', and FIG. 1G is a cross-sectional view of the semiconductor structure in FIG. 1F along line B-B'. As shown in FIGS. 1E to 1G, trenches 59 passing through the second substrate 50 and the bonding metal layer 40 can be formed through one or more etching processes as described above, so that the first vertical element 54a is separated from the second vertical element 55a, and the first contact structure 40a is separated from the second contact structure 40b. As shown in FIGS. 1E to 1G, the vertical stack of the first contact structure 40a and the first vertical element 54a is island-shaped, and the vertical stack of the second contact structure 40b and the second vertical element 55a is island-shaped. As shown in FIG. 1G, a third vertical element 55a' similar to the second vertical element 55a and a third contact structure 40b' similar to the second contact structure 40b can also be formed. As shown in FIGS. 1E to 1G, the first substrate 10 may include functional elements 11, and the first wiring layer 31 is electrically connected to the functional elements 11. In some embodiments, the functional elements 11 may be peripheral devices, such as control devices, word line selection devices, and bit line selection devices. The first substrate 10 may include a plurality of functional elements 11. In some embodiments, the first substrate 10 may include an element layer or an element stack, and the element layer or element stack includes a plurality of functional elements 11, where the element layer or element stack may include a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or the like. In some embodiments, the first wiring layer 31 is electrically connected to the functional elements 11 through the first interconnect structure 35. The first interconnect structure 35 may include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, other suitable materials, or a combination of the foregoing, and may be formed in the first dielectric layer 21 using an inlay or dual inlay process or any suitable process before the formation of the first metal bonding layer 41. Through the method disclosed herein, a vertical device including a single-crystalline semiconductor material can be formed and can thus have better performance than vertical devices made of polycrystalline and / or amorphous semiconductor materials. Also, in some embodiments, the semiconductor material layer can be annealed before the formation of the metal contact layer, such that high-temperature processes can be avoided in subsequent stages. Additionally, as discussed previously, through the method disclosed herein, multiple vertical devices, metal contact structures, and wiring layers can be easily aligned and the metal bonding interfaces therein can be ideal, which can enable better electrical connection between the vertical devices and the wiring layer through corresponding metal contact structures. Specifically, since multiple metal contact structures can be formed from an unpatterned bonding metal layer according to alignment marks, wafer-to-wafer bonding misalignment problems can be avoided. As shown in FIGS. 1H and 1I, after patterning of the bonding metal layer 40 (step (g)), a second dielectric layer 22 is formed (step (h)). The second dielectric layer 22 can surround the vertical devices 54a and 55a and the contact structures 40a and 40b. The second dielectric layer 22 can include one or more stacked dielectric layers. The second dielectric layer 22 can include a dielectric material such as silicon oxide, silicon oxynitride, a low-k material, combinations thereof, and / or other suitable materials, and the second dielectric layer 22 can be formed by a deposition process such as CVD, PVD, or ALD, spin coating, or other suitable methods. The second dielectric layer 22 can fill the trenches 59 such that the first vertical device 54a and the second vertical device 55a are laterally isolated by the second dielectric layer 22, and the first contact structure 40a and the second contact structure 40b are laterally isolated by the second dielectric layer 22. In some embodiments, before the formation of the second dielectric layer 22, a conformal diffusion barrier layer (not shown) surrounding the vertical devices and the contact structures can be formed. The conformal diffusion barrier layer can include titanium, tungsten, tantalum, and nitrides thereof. Due to the aforementioned "self-alignment" process with reference to FIGS. 1A to 1G, the sidewalls of the first vertical device 54a and the first contact structure 40a can be vertically aligned without misalignment, and the sidewalls of the second vertical device 55a and the second contact structure 40b can be vertically aligned without misalignment. Thus, a conformal diffusion barrier layer can be formed on the sidewalls of the vertical devices and the contact structures such that the conformal diffusion barrier layer on the sidewalls of the vertical devices and the contact structures can be substantially planar. As shown in FIGS. 1H and 1I, first memory unit 100a and second memory unit 100b can be formed above vertical elements 54a and 55a (step (i)). First memory unit 100a is formed above first vertical element 54a, and second memory unit 100b is formed above second vertical element 55a. First memory unit 100a can have a first end 101a and a second end 102a. In some embodiments, first memory unit 100a extends from the first end 101a of first memory unit 100a to the second end 102a of first memory unit 100a. Second memory unit 100b can have a first end 101b and a second end 102b. In some embodiments, second memory unit 100b extends from the first end 101b of second memory unit 100b to the second end 102b of second memory unit 100b. First memory unit 100a and second memory unit 100b can each include a magnetic tunneling junction (MTJ) structure, a phase change material, or a variable resistance material. In some embodiments, first memory unit 100a and second memory unit 100b can be formed by using suitable materials and processes such as deposition, photolithography, and etching techniques. For example, a stack of memory material layers can be formed above first vertical element 54a and second vertical element 55a by deposition or by a metal bonding process similar to that described above with reference to FIGS. 1A - 1C, and can be defined to form a plurality of memory units. The formation of first memory unit 100a and second memory unit 100b can be performed according to alignment marks 90 located on first substrate 10. As shown in FIG. 1I, a third memory unit 100b' similar to second memory unit 100b can be formed above third vertical element 55a'. Third memory unit 100b' can have a first end 101b' and a second end 102b'. In some embodiments, third memory unit 100b' extends from the first end 101b' of third memory unit 100b' to the second end 102b' of third memory unit 100b'. In the embodiments shown in FIGS. 1H and 1I, memory units 100a and 100b are formed after patterning of second substrate 50. However, in some other embodiments, memory units can be formed by defining a stack of memory material layers on second substrate 50 before patterning of second substrate 50, where the stack of memory material layers can be formed on second substrate 50 by deposition or any suitable process, or the stack of memory material layers can be bonded to second substrate 50 by a metal bonding process similar to that described above with reference to FIGS. 1A - 1C. As shown in FIGS. 1H and 1I, a second wiring layer 32 is formed over the first memory cell 100a and the second memory cell 100b. The second wiring layer 32 may include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), some other suitable materials, or a combination of the foregoing. The second wiring layer 32 can be fabricated through any suitable process (e.g., photolithography and etching processes, damascene process, dual damascene process, or the like). For example, the damascene or dual damascene process or any suitable process can be used to form the second wiring layer 32 in the second dielectric layer 22. Referring to FIGS. 1H and 1I, a semiconductor structure 110 is provided that includes a first wiring layer 31, a first contact structure 40a, a second contact structure 40b, a first vertical element 54a, a second vertical element 55a, and a second dielectric layer 22. The first wiring layer 31 is located over the first substrate 10. In some embodiments, the first wiring layer 31 is located in the first dielectric layer 21. In some embodiments, the first wiring layer 31 is electrically connected to the functional element 11. In some embodiments, the functional element 11 is located in the first substrate 10. In some embodiments, both the first contact structure 40a and the second contact structure 40b are located on the first wiring layer 31. Specifically, the first wiring layer 31 may include conductive features such as vias and conductive lines. In the embodiments shown in FIGS. 1H and 1I, the first contact structure 40a and the second contact structure 40b are respectively located on the first word line WL1 and the second word line WL2. In another embodiment, the first contact structure 40a and the second contact structure 40b may respectively be located on corresponding vias or conductive lines of the first wiring layer 31. The first contact structure 40a includes a first metal layer 41a, a second metal layer 42a, and a metal bonding interface 43a, where the second metal layer 42a is located over the first metal layer 41a, and the metal bonding interface 43a is located between the first metal layer 41a and the second metal layer 42a. The second contact structure 40b includes a first metal layer 41b, a second metal layer 42b, and a metal bonding interface 43b, where the second metal layer 42b is located over the first metal layer 41b, and the metal bonding interface 43b is located between the first metal layer 41b and the second metal layer 42b. In some embodiments, each of the first contact structure 40a and the second contact structure 40b may be formed by patterning the bonding metal layer 40, where the bonding metal layer 40 is formed by bonding a first metal bonding layer 41 and a second metal bonding layer 42, as described previously with reference to FIGS. 1C to 1E. Thus, the second metal layer 42a of the first contact structure 40a may be directly bonded to the first metal layer 41a of the first contact structure 40a, such that a metal bonding interface 43a is formed between the first metal layer 41a and the second metal layer 42a; and the second metal layer 42b of the second contact structure 40b may be directly bonded to the first metal layer 41b of the second contact structure 40b, such that a metal bonding interface 43b is formed between the first metal layer 41b and the second metal layer 42b. As described above, each of the first metal layers 41a and 41b and the second metal layers 42a and 42b may include a multi-layer structure. However, the present disclosure is not limited thereto. The first metal layer 41a of the first contact structure 40a may be in contact with the first wiring layer 31, and the second metal layer 42a of the first contact structure 40a may be in contact with the first vertical element 54a. The first metal layer 41b of the second contact structure 40b may be in contact with the first wiring layer 31, and the second metal layer 42b of the second contact structure 40b may be in contact with the second vertical element 55a. Thus, the first vertical element 54a and the second vertical element 55a may be electrically connected to the first wiring layer 31 through the first contact structure 40a and the second contact structure 40b, respectively. As shown in FIGS. 1H and 1I, in some embodiments, the width W1 of the first metal layer 41a of the first contact structure 40a is substantially equal to the width W2 of the second metal layer 42a of the first contact structure 40a, and the width W1' of the first metal layer 41b of the second contact structure 40b is substantially equal to the width W2' of the second metal layer 42b of the second contact structure 40b. In some embodiments, the metal bonding interface 43a of the first contact structure 40a and the metal bonding interface 43b of the second contact structure 40b are substantially horizontal. In some embodiments, due to the "self-alignment" process described previously with reference to FIGS. 1A to 1G, the first metal layer 41a and the second metal layer 42a of the first contact structure 40a may be vertically aligned without misalignment, and the first metal layer 41b and the second metal layer 42b of the second contact structure 40b may be vertically aligned without misalignment. As shown in FIGS. 1H and 1I, the sidewalls of the first metal layer 41a and the second metal layer 42a of the first contact structure 40a may be substantially aligned, and the sidewalls of the first metal layer 41b and the second metal layer 42b of the second contact structure 40b may be substantially aligned. This may reduce the overall width of the first contact structure 40a and the second contact structure 40b, and thus reduce the size of the memory cell unit made of the semiconductor structure disclosed herein. However, the present disclosure is not limited thereto. As shown in FIGS. 1H and 1I, a first vertical element 54a extends between a first end 54g and a second end 54h of the first vertical element 54a, wherein the first vertical element 54a is located above and in contact with the first contact structure 40a. In some embodiments, the first vertical element 54a contacts the first contact structure 40a at the first end 54g of the first vertical element 54a. In some embodiments, the height H1 of the first vertical element 54a (e.g., the height between the first end 54g and the second end 54h of the first vertical element 54a) can be between about 10 nanometers and about 300 nanometers. In some embodiments, the width W3 of the first vertical element 54a is substantially equal to the width W2 of the second metal layer 42a of the first contact structure 40a. A second vertical element 55a extends between a first end 55g and a second end 55h of the second vertical element 55a, wherein the second vertical element 55a is located above and in contact with the second contact structure 40b. In some embodiments, the second vertical element 55a contacts the second contact structure 40b at the first end 55g of the second vertical element 55a. In some embodiments, the width W3' of the second vertical element 55a is substantially equal to the width W2' of the second metal layer 42b of the second contact structure 40b. In some embodiments, the first vertical element 54a and the second vertical element 55a are at the same level. In other words, the top end (e.g., the second end 54h) of the first vertical element 54a can be substantially horizontal with the top end (e.g., the second end 55h) of the second vertical element 55a, and the bottom end (e.g., the first end 54g) of the first vertical element 54a can be substantially horizontal with the bottom end (e.g., the first end 55g) of the second vertical element 55a. In some embodiments, the height H1 of the first vertical element 54a is substantially equal to the height H2 of the second vertical element 55a (e.g., the height between the first end 55g and the second end 55h of the second vertical element 55a). In some embodiments, each of the first vertical element 54a and the second vertical element 55a can include a single crystal semiconductor material, for example, made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). For simplicity of description, spatial relative terms such as "top" and "bottom" are used herein to describe the relationship of one element or feature shown in the present disclosure to another element or feature. It should be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, the feature described as "top" will then become "bottom", and vice versa. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are correspondingly interpreted. In the embodiments shown in FIGS. 1H and 1I, each of the first vertical element 54a and the second vertical element 55a is a vertical PN diode. The present disclosure is not limited thereto. The first vertical element 54a may be arranged in the same direction as the second vertical element 55a, as shown in FIGS. 1H and 1I, such that the first vertical element 54a allows a first current I1 (e.g., from the first end 54g to the second end 54h of the first vertical element 54a) having the same direction as a second current I2 (e.g., from the first end 55g to the second end 55h of the second vertical element 55a) allowed by the second vertical element 55a under similar conditions. As shown in FIGS. 1H and 1I, the second dielectric layer 22 may be located above the first dielectric layer 21 and surround each of the first vertical element 54a, the second vertical element 55a, the first contact structure 40a, and the second contact structure 40b. In some embodiments, as described above, the second dielectric layer 22 is formed by depositing a dielectric layer on the uppermost surface 21a of the first dielectric layer 21, and the second dielectric layer 22 is formed to surround the first metal layers 41a and 41b and the second metal layers 42a and 42b of the first contact structure 40a and the second contact structure 40b. Thus, the second dielectric layer 22 may continuously extend from the uppermost surface 21a of the first dielectric layer 21 without a bonding interface located between the first contact structure 40a and the second contact structure 40b and at the same level as the metal bonding interfaces 43a of the first contact structure 40a and 43b of the second contact structure 40b. In other words, the bonding interface (such as the metal bonding interface 43a) between the first metal layer 41a and the second metal layer 42a of the first contact structure 40a and the bonding interface (e.g., the metal bonding interface 43b) between the first metal layer 41b and the second metal layer 42b of the second contact structure 40b may be laterally separated by the deposited layer of the second dielectric layer 22, where there is no bonding interface (e.g., dielectric-dielectric bonding interface and / or metal-metal bonding interface) in the second dielectric layer 22. Referring to FIGS. 1H and 1I, a memory element 200 is provided. The memory element 200 includes a first wiring layer 31, a first contact structure 40a, a first vertical element 54a, a first memory cell 100a, and a second wiring layer 32. The first wiring layer 31 may include a plurality of word lines extending in a first direction 103a. In the embodiments shown in FIGS. 1H and 1I, the plurality of word lines include a first word line WL1 and a second word line WL2. The memory element 200 may further include a second contact structure 40b, where the first contact structure 40a may land on the first word line WL1, and the second contact structure 40b may land on the second word line WL2. In some embodiments, both the first contact structure 40a and the third contact structure 40b' (the second contact structure) land on the first word line WL1. In the embodiments shown in FIGS. 1H and 1I, the first vertical element 54a is electrically connected to the second end 102a of the first memory cell 100a by the second end 54h of the first vertical element 54a. In the embodiments shown in FIGS. 1H and 1I, the second vertical element 55a is electrically connected to the second end 102b of the second memory cell 100b by the second end 55h of the second vertical element 55a. The second wiring layer 32 can be electrically connected to the first end 101a of the first memory cell 100a. The second wiring layer 32 can also be electrically connected to the first end 101b of the second memory cell 100b. The second wiring layer 32 can include a plurality of bit lines extending in a second direction 103b different from the first direction 103a. In the embodiments shown in FIGS. 1H and 1I, the plurality of bit lines includes a first bit line BL1 and a second bit line BL2, and the first end 101a of the first memory cell 100a is electrically connected to the first bit line BL1. In the embodiment shown in FIG. 1I, the third vertical element 55a' is electrically connected to the second end 102b' of the third memory cell 100b', and the first end 101b' of the third memory cell 100b' is electrically connected to the second bit line BL2. In some embodiments, the memory element 200 further includes an alignment mark 90 located on the first substrate 10. The relevant details of the features of the memory element 200 have been described above and will not be repeated here. In the illustrated embodiments, the memory element 200 includes memory cells arranged in rows and columns to form a memory array. The memory element 200 can include any suitable number of rows and columns. For example, the memory element 200 includes R rows and C columns, where R is an integer greater than or equal to 1 and C is an integer greater than or equal to 2. Specifically, the memory element 200 shown in FIGS. 1H and 1I can be a RRAM device or a PcRAM device. FIGS. 2A to 2E are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 2A, a first structure 100A is provided (step (a)). The first structure 100A can be substantially similar to the first structure 100A shown in FIG. 1A, where like element symbols indicate like elements. The fabrication and related details of the first structure 100A with reference to FIG. 1A above are applicable here. As shown in FIG. 2A, a second structure 200B is provided (step (b)). The second structure 200B may be substantially similar to the second structure 100B shown in FIG. 1A, where like reference numerals indicate like elements. The second structure 200B including the second substrate 50 further includes a third substrate 60 and a bonding layer 70. The bonding layer 70 may be located between the second substrate 50 and the third substrate 60. In some embodiments, the bonding layer 70 may include an oxide, such as silicon oxide. In one embodiment, the third substrate 60 is a wafer with a diameter of 6, 8, 12, or 18 inches. The third substrate 60 may be a handle wafer. In some embodiments, the third substrate 60 may include glass, polysilicon, or ceramic. In some other embodiments, the third substrate 60 may include a single crystal semiconductor material, for example, made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In one embodiment, the thickness of the third substrate 60 may be between 20 micrometers and 700 micrometers. These values are only examples and are not intended to be limiting. The second substrate 50 in FIG. 2A may be substantially similar to the second substrate 50 in FIG. 1A, where like reference numerals indicate like elements. The foregoing manufacturing and related details of the second substrate 50 with reference to FIG. 1A are applicable herein. In one embodiment, the second structure 200B may be fabricated by bonding the third substrate 60 and a substrate (not shown) with the bonding layer 70 and removing a portion of the substrate after bonding to leave the second substrate 50 in the second structure 200B. As shown in FIG. 2B, before bonding the first structure 100A and the second structure 200B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). The foregoing forming process and related details with reference to FIG. 1B are applicable herein. As shown in FIG. 2C, the first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 200B is flipped and bonded to the first structure 100A through the bonding metal layer 40 to form a bonded structure 200C. The foregoing bonding process and related details with reference to FIG. 1C are applicable herein. As shown in FIG. 2D, a portion of the second structure 200B is removed, and a second surface 50b of the second substrate 50 is formed (step (e)). In the embodiment shown in FIG. 2D, the removed portion of the second structure 200B includes removing the third substrate 60 and the bonding layer 70. The third substrate 60 and the bonding layer 70 can be removed by performing suitable processes such as grinding, chemical mechanical polishing (CMP), and etching processes. In one embodiment, the third substrate 60 is removed by grinding and / or CMP process, and dilute HF (e.g., H 2A first etchant with a weight percentage of O and HF of about 100:1 removes the bonding layer 70. The present disclosure is not limited thereto. After the removal and optional polishing process, a second surface 50b of the second substrate 50 is formed. In the embodiment shown in FIG. 2D, a first heavily doped layer 46 is exposed after removing a portion of the second structure 200B (e.g., the bonding layer 70). The formation process and related details of the first heavily doped layer 46 with reference to FIG. 1D above are applicable herein. As shown in FIG. 2E, a semiconductor structure 110 and a memory element 200 are provided. The processes for fabricating the semiconductor structure 110 and the memory element 200 may be substantially similar to the processes with reference to FIGS. 1E to 1I above, and for the sake of brevity, the related descriptions are omitted herein. FIGS. 3A to 3E are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 3A, a first structure 100A is provided (step (a)). The first structure 100A may be substantially similar to the first structure 100A shown in FIG. 1A, where like element symbols indicate like elements. The fabrication and related details of the first structure 100A with reference to FIG. 1A above are applicable herein. As shown in FIG. 3A, a second structure 300B is provided (step (b)). The second structure 300B may be substantially similar to the second structure 200B shown in FIG. 2A, where like reference numerals indicate like elements. The second structure 300B including the second substrate 50 further includes a third substrate 60 and an etch stop layer 80. The etch stop layer 80 may be located between the second substrate 50 and the third substrate 60. The etch stop layer 80 may have a high etch selectivity relative to the third substrate 60. In other words, under the same etching conditions, the etching rate of the third substrate 60 is substantially faster than the etching rate of the etch stop layer 80. In one embodiment, the etch stop layer 80 may include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination thereof. The doped semiconductor material may be a semiconductor material doped with a p-type dopant or an n-type dopant as described above. The undoped semiconductor material may be amorphous silicon, polycrystalline silicon, silicon germanium, these, or a combination thereof. The metal may be aluminum, gold, copper, tungsten, these, or an alloy thereof. The conductive metal compound may be a metal silicide, metal carbide, metal nitride, these, or a combination thereof, such as: tungsten nitride (WN), tantalum nitride (TaN), tantalum silicide (TaSi), titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium oxide (IrOx), ruthenium oxide (RuOx), or ruthenium titanium nitride (RuTiN). The second substrate 50 and the third substrate 60 in FIG. 3A may be substantially similar to the second substrate 50 and the third substrate 60 in FIG. 2A, where like reference numerals indicate like elements. The manufacturing and related details of the second substrate 50 and the third substrate 60 with reference to FIG. 2A above may be applicable here. As shown in FIG. 3B, before bonding the first structure 100A and the second structure 300B, a first metal bonding layer 41 is formed on the first structure 100A, and is formed on the first surface 50a of the second substrate 50 (step (c)). The formation process and related details with reference to FIG. 1B above may be applicable here. As shown in FIG. 3C, the first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 300B is flipped and bonded to the first structure 100A through the bonding metal layer 40 to form a bonded structure 300C. The bonding process and related details with reference to FIG. 1C above may be applicable here. As shown in FIG. 3D, a portion of the second structure 300B is removed, and a second surface 50b of the second substrate 50 is formed (step (e)). In the embodiment shown in FIG. 3D, the removed portion of the second structure 300B includes removing the etch stop layer 80. The third substrate 60 and the etch stop layer 80 can be removed by performing suitable processes such as polishing, chemical mechanical polishing (CMP), and etching processes. In one embodiment, the third substrate 60 is removed by an etching process under suitable etching conditions. The etch stop layer 80 can be removed by peroxide etching, plasma etching, hydrogen peroxide etching, these or any suitable method. In one embodiment, the etch stop layer 80 including silicon nitride can be removed by applying a second etchant such as hot phosphoric acid. However, the present disclosure is not limited thereto. The second surface 50b of the second substrate 50 can be formed after removing the etch stop layer 80. The introduction of the etch stop layer 80 can ensure the planarity of the formed second surface 50b of the second substrate 50, and the etch stop layer 80 can be used to monitor the etch endpoint. In the embodiment shown in FIG. 3D, after removing a portion of the second structure 300B (e.g., the etch stop layer 80), the first heavily doped layer 46 is exposed. The formation process and related details of the first heavily doped layer 46 with reference to FIG. 1D above are applicable herein. As shown in FIG. 3E, a semiconductor structure 110 and a memory element 200 are provided. The processes for fabricating the semiconductor structure 110 and the memory element 200 can be substantially similar to the processes with reference to FIGS. 1E to 1I above, and for the sake of brevity, the related descriptions are omitted herein. FIGS. 4A to 4F are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 4A, a first structure 100A is provided (step (a)). The first structure 100A can be substantially similar to the first structure 100A shown in FIG. 1A, where like element symbols indicate like elements. The fabrication and related details of the first structure 100A with reference to FIG. 1A above are applicable herein. As shown in FIG. 4A, a second structure 400B is provided (step (b)). The second structure 400B may be substantially similar to the second structure 300B shown in FIG. 3A, where like reference numerals indicate like elements. The second structure 400B including the second substrate 50 further includes a third substrate 60, a bonding layer 70, and an etch stop layer 80. The bonding layer 70 may be located between the second substrate 50 and the third substrate 60, and the etch stop layer 80 may be located between the bonding layer 70 and the second substrate 50. The second substrate 50, the third substrate 60, and the bonding layer 70 in FIG. 4A may be substantially similar to the second substrate 50, the third substrate 60, and the bonding layer 70 in FIG. 2A, where like reference numerals indicate like elements. The etch stop layer 80 may have a high etch selectivity relative to the bonding layer 70. In other words, under the same etching conditions, the etching rate of the bonding layer 70 is substantially faster than the etching rate of the etch stop layer 80. In some embodiments, the etch stop layer 80 may include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination thereof. The doped semiconductor material may be a semiconductor material doped with a p-type dopant or an n-type dopant as described above. The undoped semiconductor material may be amorphous silicon, polysilicon, silicon germanium, these, or a combination thereof. The metal may be aluminum, gold, copper, tungsten, these, or an alloy thereof. The conductive metal compound may be a metal silicide, metal carbide, metal nitride, these, or a combination thereof, such as: tungsten nitride (WN), tantalum nitride (TaN), tantalum silicide (TaSi), titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium oxide (IrOx), ruthenium oxide (RuOx), or ruthenium titanium nitride (RuTiN). The fabrication and related details of the second substrate 50, the third substrate 60, and the bonding layer 70 with reference to FIGS. 2A and 3A above may be applicable here. In one embodiment, the etch stop layer 80 may be formed on a substrate (not shown) by epitaxial growth or a deposition process such as CVD, PVD, or ALD, and then the substrate is bonded to the third substrate 60 through the bonding layer 70. In some embodiments, a portion of the substrate may be removed after bonding, and the second substrate 50 is left in the second structure 400B. A semiconductor substrate including an etch stop layer may be fabricated by bonding two substrates after forming the etch stop layer, as described in application document No. PCT / US23 / 69597, the content of which is incorporated herein by reference. As shown in FIG. 4B, before bonding the first structure 100A and the second structure 400B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). The formation process and related details with reference to FIG. 1B above may be applicable here. As shown in FIG. 4C, the first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 400B is flipped and bonded onto the first structure 100A through the bonding metal layer 40 to form a bonding structure 400C. The bonding process and related details referred to in FIG. 1C above can be applied herein. As shown in FIGS. 4D and 4E, a portion of the second structure 400B is removed, and a second surface 50b of the second substrate 50 is formed (step (e)). In the embodiment shown in FIG. 4D, the removed portion of the second structure 400B includes removing the third substrate 60 and the bonding layer 70 to expose the etch stop layer 80. The third substrate 60 and the bonding layer 70 can be removed by performing suitable processes such as polishing, chemical mechanical polishing (CMP), and etching processes. In one embodiment, the third substrate 60 is removed by a polishing and / or CMP process, and the bonding layer 70 can be removed by applying a first etchant such as dilute HF (e.g., H 2 2O and HF with a weight percentage of about 100:1). The present disclosure is not limited thereto. In the embodiment shown in FIG. 4E, the removed portion of the second structure 400B includes removing the etch stop layer 80. The etch stop layer 80 can be removed by peroxide etching, plasma etching, hydrogen peroxide etching, these or any suitable method. In one embodiment, the etch stop layer 80 including silicon nitride can be removed by applying a second etchant such as hot phosphoric acid. However, the present disclosure is not limited thereto. The second surface 50b of the second substrate 50 can be formed after removing the etch stop layer 80. In the embodiment described in FIG. 4E, after removing a portion of the second structure 400B (e.g., the bonding layer 70 and the etch stop layer 80), the first heavily doped layer 46 is exposed. The formation process and related details of the first heavily doped layer 46 referred to in FIG. 1D above can be applied herein. As shown in FIG. 4F, a semiconductor structure 110 and a memory element 200 are provided. The processes for fabricating the semiconductor structure 110 and the memory element 200 can be substantially similar to the processes referred to in FIGS. 1E to 1I above, and for the sake of brevity, the related descriptions are omitted herein. The methods disclosed in the embodiments shown in FIGS. 2A to 2E, FIGS. 3A to 3E, and FIGS. 4A to 4F above can solve the problems of a large number of particles and contamination generated when removing a portion of the second structure, and can provide additional options for fabricating vertical structures. FIGS. 5A to 5H are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 5A, a first structure 500A is provided (step (a)). The first structure 500A may be substantially similar to the first structure 100A shown in FIG. 1A, where like element symbols indicate like elements. The first structure 500A including the first substrate 10 and the first wiring layer 31 further includes a first memory cell 100a and a second memory cell 100b between the first wiring layer 31 and the first substrate 10. In some embodiments, the first substrate 10 may include functional elements (e.g., the functional element 11 shown in FIG. 5F). The first memory cell 100a may have a first end 101a and a second end 102a. In some embodiments, the first memory cell 100a extends from the first end 101a of the first memory cell 100a to the second end 102a of the first memory cell 100a. The second memory cell 100b may have a first end 101b and a second end 102b. In some embodiments, the second memory cell 100b extends from the first end 101b of the second memory cell 100b to the second end 102b of the second memory cell 100b. The first memory cell 100a and the second memory cell 100b may respectively include a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material. In the embodiment shown in FIG. 5A, the first wiring layer 31 may be electrically connected to the second end 102a of the first memory cell 100a. The first wiring layer 31 may also be electrically connected to the second end 102b of the second memory cell 100b (as described in more detail below with reference to FIGS. 5D to 5F). The formation processes and related details of the memory cells 100a and 100b with reference to FIGS. 1H and 1I above may be applicable here. In some embodiments, the first structure 500A may further include a third memory cell 100b' (shown in FIGS. 5F and 5H) between the first wiring layer 31 and the first substrate 10, which is similar to the second memory cell 100b. The third memory cell 100b' may have a first end 101b' and a second end 102b'. In some embodiments, the third memory cell 100b' extends from the first end 101b' of the third memory cell 100b' to the second end 102b' of the third memory cell 100b'. As shown in FIG. 5A, the first structure 500A may include a plurality of bit lines including a first bit line BL1 and a second bit line BL2. In some embodiments, the first bit line BL1 and the second bit line BL2 may include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), some other suitable materials, or combinations thereof. The plurality of bit lines may be fabricated through any suitable process (e.g., photolithography and etching processes, damascene processes, dual damascene processes, or the like). For example, the first bit line BL1 and the second bit line BL2 may be formed in the first dielectric layer 21 using damascene or dual damascene or any suitable method. In some embodiments, the first end 101a of the first memory cell 100a may be electrically connected to the first bit line BL1, and the first end 101b of the second memory cell 100b may be electrically connected to the second bit line BL2. The fabrication and related details of the first structure 100A with reference to FIG. 1A above may be applicable herein. As shown in FIG. 5A, a second structure 200B is provided (step (b)). The second structure 200B may be substantially similar to the second structure 200B shown in FIG. 2A, where like element symbols indicate like elements. The fabrication and related details of the second structure 200B with reference to FIG. 2A above may be applicable herein. As shown in FIG. 5B, before bonding the first structure 500A and the second structure 200B, a first metal bonding layer 41 is formed on the first structure 500A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). The formation process and related details with reference to FIG. 1B above may be applicable herein. As shown in FIG. 5C, the first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). Flip and bond the second structure 200B to the first structure 500A through the bonding metal layer 40 to form a bonded structure 500C. The bonding process and related details with reference to FIG. 1C above may be applicable herein. As shown in FIG. 5D, a portion of the second structure 200B is removed, and the second surface 50b of the second substrate 50 is formed (step (e)), the second substrate 50 is patterned to form a plurality of vertical elements including a first vertical element 54a and a second vertical element 55a (step (f)), and the bonding metal layer 40 is patterned to form a plurality of contact structures including a first contact structure 40a and a second contact structure 40b for the first vertical element 54a and the second vertical element 55a (step (g)). The removal and patterning processes may be substantially similar to the processes with reference to FIGS. 2D and 1E above, and for the sake of brevity, the related descriptions are omitted herein. FIG. 5E is a schematic top view of the semiconductor structure shown in FIG. 5D, and FIG. 5F is another cross-sectional view of the semiconductor structure shown in FIG. 5D. Specifically, FIG. 5D is a cross-sectional view of the semiconductor structure along line A-A' in FIG. 5E, and FIG. 5F is a cross-sectional view of the semiconductor structure along line B-B' in FIG. 5E. As shown in FIGS. 5D to 5F, trenches 59 can be formed through the second substrate 50 and the bonding metal layer 40 by one or more of the foregoing etching processes, such that the first vertical element 54a is separated from the second vertical element 55a, and the first contact structure 40a is separated from the second contact structure 40b. As shown in FIGS. 5D to 5F, the vertical stack of the first contact structure 40a and the first vertical element 54a is island-shaped, and the vertical stack of the second contact structure 40b and the second vertical element 55a is island-shaped. In the embodiment shown in FIGS. 5D to 5F, the conductive features in the first wiring layer 31 are also island-shaped. The processes described herein can provide process flexibility, and depending on the circuit design, whether the conductive features in the wiring layer are linear (e.g., the first wiring layer 31 shown in FIG. 1F) or island-shaped (e.g., the first wiring layer 31 shown in FIG. 5E) can be applicable. As shown in FIG. 5F, a third vertical element 55a' similar to the second vertical element 55a and a third contact structure 40b' similar to the second contact structure 40b can also be formed. As shown in FIGS. 5D to 5G, the first substrate 10 can include functional elements 11, and the first wiring layer 31 is electrically connected to the functional elements 11. In some embodiments, the first wiring layer 31 is electrically connected to the functional elements 11 through the first interconnect structure 35. The materials and processes for forming the functional elements 11 and the first interconnect structure 35 have been described above with reference to FIGS. 1A to 1G, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIGS. 5G and 5H, after patterning the bonding metal layer 40 (step (g)), a second dielectric layer 22 is formed (step (h)). The formation processes and related details described above with reference to FIGS. 1H and 1I can be applicable herein. As shown in FIGS. 5G and 5H, a second wiring layer 32 is formed over the first vertical element 54a and the second vertical element 55a. The second wiring layer 32 can be formed using similar materials and methods as described above with reference to FIGS. 1H and 1I. Referring to FIGS. 5G and 5H, a semiconductor structure 120 including a first wiring layer 31, a first contact structure 40a, a second contact structure 40b, a first vertical element 54a, a second vertical element 55a, and a second dielectric layer 22 is provided. The semiconductor structure 120 can be substantially similar to the semiconductor structure 110 shown in FIGS. 1H and 1I, where like reference numerals indicate like elements. The fabrication and related details of the semiconductor structure 110 described above with reference to FIGS. 1H and 1I can be applicable herein. In the embodiments shown in FIGS. 5G and 5H, the first contact structure 40a and the second contact structure 40b are located on the island vias of the corresponding first wiring layer 31. The first contact structure 40a includes a first metal layer 41a, a second metal layer, and a metal bonding interface 43a, where the second metal layer 42a is located above the first metal layer 41a, and the metal bonding interface 43a is located between the first metal layer 41a and the second metal layer 42a. The second contact structure 40b includes a first metal layer 41b, a second metal layer 42b, and a metal bonding interface 43b, where the second metal layer 42b is located above the first metal layer 41b, and the metal bonding interface 43b is located between the first metal layer 41b and the second metal layer 42b. By using the process disclosed herein, the processes of the logic part and the memory cell part can be separated, which can prevent contamination between different processes. Other relevant details of the first contact structure 40a, the second contact structure 40b, the first vertical element 54a, the second vertical element 55a, and the second dielectric layer 22 can be similar to the descriptions with reference to FIGS. 1A to 1I, FIGS. 2A to 2E, FIGS. 3A to 3E, or FIGS. 4A to 4F mentioned above, and will not be repeated here. Referring to FIGS. 5G and 5H, a memory element 210 is provided. The memory element 210 includes a first wiring layer 31, a first contact structure 40a, a first vertical element 54a, a first memory cell 100a, and a second wiring layer 32. The memory element 210 may include a plurality of bit lines extending in the first direction 103a. In the embodiments shown in FIGS. 5G and 5H, as described above, the plurality of bit lines include a first bit line BL1 and a second bit line BL2. In the embodiments shown in FIGS. 5G and 5H, the first vertical element 54a is electrically connected from the first end 54g of the first vertical element 54a to the second end 102a of the first memory cell 100a. In the embodiments shown in FIGS. 5G and 5H, the second vertical element 55a is electrically connected from the first end 55g of the second vertical element 55a to the second end 102b of the second memory cell 100b. As shown in FIG. 5H, the third vertical element 55a' is electrically connected to the second end 102b' of the third memory cell 100b'. The second wiring layer 32 can be electrically connected from the second end 54h of the first vertical element 54a to the first vertical element 54a. The second wiring layer 32 can also be electrically connected from the second end 55h of the second vertical element 55a to the second vertical element 55a. The second wiring layer 32 can include a plurality of word lines extending in a second direction 103b different from the first direction 103a. In the embodiments shown in FIGS. 5G and 5H, the plurality of word lines includes a first word line WL1 and a second word line WL2. In the embodiments shown in FIGS. 5G and 5H, the first vertical element 54a is electrically connected from the second end 54h of the first vertical element 54a to the first word line WL1, and the third vertical element 55a' is electrically connected from the second end 55h' of the third vertical element 55a' to the second word line WL2. If applicable, the relevant details of the features of the memory element 200 with reference to FIGS. 1H and 1I can be applied herein. In the embodiments shown in FIGS. 5A to 5H, a memory element including a PN diode as a selector can be fabricated using the method disclosed herein. In some embodiments, the semiconductor structure 120 and the memory element 210 can be fabricated through the processes with reference to FIGS. 1A to 1I, FIGS. 3A to 3E, or FIGS. 4A to 4F, and for the sake of brevity, the related descriptions are omitted herein. FIGS. 6A to 6F are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 6A, a first structure 100A is provided (step (a)). The first structure 100A can be substantially similar to the first structure 100A shown in FIG. 1A, where like element symbols indicate like elements. The fabrication and related details of the first structure 100A with reference to FIG. 1A can be applied herein. As shown in FIG. 6A, a second structure 600B is provided (step (b)). The second structure 600B including the second substrate 50 further includes a third substrate 60 and a bonding layer 70. The second substrate 50, the third substrate 60, and the bonding layer 70 may be substantially similar to the second substrate 50, the third substrate 60, and the bonding layer 70 shown in FIG. 2A, where like reference numerals indicate like elements. The processes and related details of the second substrate 50 with reference to FIG. 2A are applicable herein. The second substrate 50 includes a first semiconductor material layer 51 and a first metal material layer 44. The first metal layer 44 may be located on the first semiconductor material layer 51. In some embodiments, the first metal material layer 44 may be formed in contact with the first semiconductor material layer 51. In some embodiments, the first metal material layer 44 may include a first metal material. The first metal material may include a suitable metal, alloy, or conductive metal compound, such as platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), or a combination thereof. In some embodiments, the first metal material layer 44 may be formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the first metal material layer 44 may be formed by sputtering, evaporation, or electroplating. In some embodiments, after forming the first metal material layer 44, a first surface 50a of the second substrate 50 may be formed. As shown in FIG. 6B, before bonding the first structure 100A and the second structure 600B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). In some embodiments, the second metal bonding layer 42 may be formed in contact with the first metal material layer 44. The forming process and related details with reference to FIG. 1B are applicable herein. In one embodiment, the second metal bonding layer 42 may also serve as the first metal material layer, such that no additional metal element (such as the first metal material layer 44) is required. As shown in FIG. 6C, the first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 600B is flipped and bonded to the first structure 100A through the bonding metal layer 40 to form a bonded structure 600C. The bonding process and related details with reference to FIG. 1C are applicable herein. As shown in FIG. 6D, a portion of the second structure 600B is removed, and a second surface 50b of the second substrate 50 is formed (step (e)). The removal process and related details with reference to FIG. 2D are applicable herein. In the embodiment shown in FIG. 6D, a first heavily doped layer 46 is exposed after removing a portion of the second structure 600B (such as the bonding layer 70). The forming process and related details of the first heavily doped layer 46 with reference to FIG. 1D are applicable herein. As shown in FIG. 6D, after removing a part of the second structure 600B and forming the second surface 50b of the second substrate 50 (step (e)), a second metal material layer 45 can be formed on the second surface 50b of the second substrate 50 (step (j1)). The second metal material layer 45 can be located above the first semiconductor material layer 51. The second metal material layer 45 in contact with the second surface 50b of the second substrate 50 can be formed. In one embodiment, the second metal material layer 45 in contact with the first semiconductor material layer 51 can be formed. In some embodiments, the second metal material layer 45 in contact with the first heavily doped layer 46 of the first semiconductor material layer 51 can be formed. In some embodiments, the first heavily doped layer 46 is formed before the second metal material layer 45 is formed. In some embodiments, the second metal material layer 45 can include a second metal material. The second metal material can include a suitable metal, alloy, or conductive metal compound, such as: Mo, Ag, TiN, or a combination thereof. In one embodiment, the second metal material layer 45 is formed through a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the second metal material layer 45 can be formed through sputtering, evaporation, or electroplating. In one embodiment, as described above, the first metal material layer 44 and the second metal material layer 45 can have different compositions; however, in some other embodiments, as long as a Schottky interface can be formed between the first metal material layer 44 and the first semiconductor material layer 51, and an ohmic interface can be formed between the second metal material layer 45 and the first heavily doped layer 46. The first metal material layer 44 and the second metal material layer 45 can have the same composition. The compositions of the first metal material layer 44 and the second metal material layer 45, as well as the doping concentrations of the first semiconductor material layer 51 and the first heavily doped layer 46, can be adjusted according to the desired diode properties. As shown in FIG. 6E, the second substrate 50 is patterned to form a plurality of vertical elements including a first vertical element 54b and a second vertical element 55b (step (f)). In the embodiment shown in FIG. 6E, each of the first vertical element 54b and the second vertical element 55b is a vertical Schottky diode. The present disclosure is not limited thereto. In some embodiments, the second substrate 50 may be patterned after and / or during the patterning of the second metal material layer 45. The second metal material layer 45 may be patterned by any suitable process (e.g., photolithography and etching processes). For example, a dry etching process (e.g., reactive ion etching and inductively coupled plasma) may be used to pattern the second metal material layer 45. In some embodiments, the first metal material layer 44 may serve as an etch stop layer in the etching process for patterning the second substrate 50. In the embodiment shown in FIG. 6E, the second metal material layer 45 is patterned to form a second metal portion 45a of the first vertical element 54b and a second metal portion 45b of the second vertical element 55b. The patterning process may be substantially similar to the process described above with reference to FIG. 1E, and for the sake of brevity, the related description is omitted herein. As shown in FIG. 6E, the bonding metal layer 40 is patterned to form a plurality of contact structures including a first contact structure 40a and a second contact structure 40b for the first vertical element 54b and the second vertical element 55b (step (g)). In some embodiments, the bonding metal layer 40 may be patterned after and / or during the patterning of the first metal material layer 44. For example, in some embodiments, when the bonding metal layer 40 includes a material similar to the first metal material layer 44, the bonding metal layer 40 may also be patterned during the patterning of the first metal material layer 44. The first metal material layer 44 may be patterned by any suitable process (e.g., photolithography and etching processes). For example, a dry etching process (e.g., reactive ion etching and inductively coupled plasma) may be used to pattern the first metal material layer 44. In the embodiment shown in FIG. 6E, the first metal material layer 44 is patterned to form a first metal portion 44a of the first vertical element 54b and a first metal portion 44b of the second vertical element 55b. The patterning process may be substantially similar to the process described above with reference to FIG. 1E, and for the sake of brevity, the related description is omitted herein. As shown in FIG. 6F, after the bonding metal layer 40 is patterned (step (g)), a second dielectric layer 22 is formed (step (h)). The second dielectric layer 22 may fill the trenches 59 such that the first vertical element 54b and the second vertical element 55b are laterally isolated by the second dielectric layer 22, and the first contact structure 40a and the second contact structure 40b are laterally isolated by the second dielectric layer 22. The formation process and related details described above with reference to FIG. 1H may be applicable herein. As shown in FIG. 6F, first memory cell 100a and second memory cell 100b are formed above vertical elements 54b and 55b (step (i)). First memory cell 100a is formed above first vertical element 54b, and second memory cell 100b is formed above second vertical element 55b. The materials and processes for forming first memory cell 100a and second memory cell 100b have been described with reference to FIG. 1H, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 6F, second wiring layer 32 is formed above first memory cell 100a and second memory cell 100b. The materials and processes for forming second wiring layer 32 have been described with reference to FIG. 1H, and for the sake of brevity, the related descriptions are omitted herein. Referring to FIG. 6F, semiconductor structure 130 is provided, which includes first wiring layer 31, first contact structure 40a, second contact structure 40b, first vertical element 54b, second vertical element 55b, and second dielectric layer 22. Except for first vertical element 54b and second vertical element 55b, semiconductor structure 130 may be substantially similar to semiconductor structure 110 shown in FIG. 1H, and the fabrication and related details of semiconductor structure 110 with reference to FIG. 1H may be applicable herein. As shown in FIG. 6F, the first vertical element 54b extends between a first end 54g and a second end 54h of the first vertical element 54b, wherein the first vertical element 54b is located above and in contact with the first contact structure 40a. In some embodiments, the first vertical element 54b contacts the first contact structure 40a at the first end 54g of the first vertical element 54b. In some embodiments, the height H1 of the first vertical element 54b (e.g., the height between the first end 54g and the second end 54h of the first vertical element 54b) can be between about 10 nanometers and about 300 nanometers. In some embodiments, the width W3 of the first vertical element 54b is substantially equal to the width W2 of the second metal layer 42a of the first contact structure 40a. The second vertical element 55b extends between a first end 55g and a second end 55h of the second vertical element 55b, wherein the second vertical element 55b is located above and in contact with the second contact structure 40b. In some embodiments, the second vertical element 55b contacts the second contact structure 40b at the first end 55g of the second vertical element 55b. In some embodiments, the width W3' of the second vertical element 55b is substantially equal to the width W2' of the second metal layer 42b of the second contact structure 40b. In some embodiments, the first vertical element 54b and the second vertical element 55b are at the same level. In some embodiments, the height H1 of the first vertical element 54b is substantially equal to the height H2 of the second vertical element 55b (e.g., the height between the first end 55g and the second end 55h of the second vertical element 55b). In some embodiments, each of the first vertical element 54b and the second vertical element 55b can include a single crystal semiconductor material, such as made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In the embodiment shown in FIG. 6F, each of the first vertical element 54b and the second vertical element 55b is a vertical Schottky diode. The present disclosure is not limited thereto. The first metal portions 44a and 44b can be the Schottky contacts of the first vertical element 54b and the second vertical element 55b, respectively. The second metal portions 45a and 45b can be the ohmic contacts of the first vertical element 54b and the second vertical element 55b, respectively. The first vertical element 54b and the second vertical element 55b can be arranged in the same direction, as shown in FIG. 6F, such that the first vertical element 54b allows a first current I1 (e.g., from the first end 54g to the second end 54h of the first vertical element 54b) having the same direction as a second current I2 allowed by the second vertical element 55b under the same conditions (e.g., from the first end to the second end 55h of the second vertical element 55b). Referring to FIG. 6F, a memory element 220 is provided. The memory element 220 includes a first wiring layer 31, a first contact structure 40a, a first vertical element 54b, a first memory cell 100a, and a second wiring layer 32. In the embodiment shown in FIG. 6F, the first vertical element 54b is electrically connected to the second end 102a of the first memory cell 100a by the second end 54h of the first vertical element 54b. In the embodiment shown in FIG. 6F, the second vertical element 55b is electrically connected to the second end 102b of the second memory cell 100b by the second end 55h of the second vertical element 55b. Except for the first vertical element 54b and the second vertical element 55b, the memory element 220 may be substantially similar to the memory element 200 shown in FIG. 1H, and the fabrication and related details of the memory element 200 with reference to FIG. 1H above may be applicable here. The relevant details of the features of the memory element 220 have been described above and will not be repeated here. In the embodiments shown in FIGS. 6A to 6F, a memory element including a Schottky diode as a selector can be fabricated using the method disclosed herein. In some embodiments, the semiconductor structure 130 and the memory element 220 can be fabricated by a method similar to that described above with reference to FIGS. 1A to 1I, FIGS. 3A to 3E, or FIGS. 4A to 4F, and for the sake of brevity, the relevant description is omitted here. FIG. 7 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to FIG. 7, a semiconductor structure 140 and a memory element 230 are provided. Except for the structure and orientation of the first vertical element 54b and the second vertical element 55b, the semiconductor 140 and the memory element 230 may be substantially similar to the semiconductor structure 130 and the memory element 220 shown in FIG. 6F, and the fabrication and related details of the semiconductor structure 130 and the memory element 220 with reference to FIGS. 6A to 6F above may be adjusted as follows and applied here. In fabricating the structure shown in FIG. 7, the first semiconductor material layer may include a first heavily doped layer extending from the first surface of the second substrate. The first heavily doped layer may be formed using materials and methods similar to those described above with reference to FIG. 1A. The first metal material layer for forming the structure shown in FIG. 7 may include a second metal material as described above with reference to FIG. 6D, and the second metal material layer for forming the structure shown in FIG. 7 may include a first metal material as described above with reference to FIG. 6A. In some embodiments, as previously disclosed, the first metal material layer and the second metal material layer may have different compositions; however, in some other embodiments, as long as an ohmic interface can be formed between the first metal material layer and the first heavily doped layer, and a Schottky interface can be formed between the second metal material layer and the first semiconductor material layer, the first metal material layer and the second metal material layer may have the same composition. The compositions of the first metal material layer and the second metal material layer, as well as the doping concentrations of the first semiconductor material layer and the first heavily doped layer, may be adjusted according to the desired diode properties. In the embodiment shown in FIG. 7, each of the first vertical element 54b and the second vertical element 55b is a vertical Schottky diode. The present disclosure is not limited thereto. The first metal portions 44a and 44b may be ohmic contacts of the first vertical element 54b and the second vertical element 55b, respectively. The second metal portions 45a and 45b may be Schottky contacts of the first vertical element 54b and the second vertical element 55b, respectively. The first vertical element 54b may be arranged in the same direction as the second vertical element 55b, as shown in FIG. 7, such that the first vertical element 54b allows a first current I1 (e.g., from the second end 54h to the first end 54g of the first vertical element 54b) having the same direction as a second current I2 (e.g., from the second end 55h to the first end 55g of the second vertical element 55b) allowed by the second vertical element 55b under similar conditions. The relevant details of the characteristics of the memory element 230 have been described above and will not be repeated here. In the embodiment shown in FIG. 7, a memory element including a Schottky diode as a selector in a direction opposite to that of the embodiment shown in FIG. 6F may be fabricated using the methods disclosed herein. In some embodiments, the semiconductor structure 140 and the memory element 230 may be fabricated through processes similar to those described above with reference to FIGS. 1A to 1I, 3A to 3E, or 4A to 4F, and for the sake of brevity, the relevant descriptions are omitted herein. Figures 8A to 8F are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 8A, a first structure 100A is provided (step (a)). In some embodiments, the first wiring layer 31 may include a plurality of conductive lines (e.g., a first source line SL1 and a second source line SL2). The first structure 100A may be substantially similar to the first structure 100A shown in FIG. 1A, where like element symbols indicate like elements. The fabrication and related details of the first structure 100A with reference to FIG. 1A above may apply here. As shown in FIG. 8A, a second structure 800B is provided (step (b)). The second structure 800B may be substantially similar to the second structure 200B shown in FIG. 2A, where like element symbols indicate like elements. The second structure 800B includes a second substrate 50, a second semiconductor material layer 52, and a third semiconductor material layer 53, and the second substrate 50 includes a first semiconductor material layer 51. The second semiconductor material layer 52 may be located on the first semiconductor material layer 51, and the third semiconductor material layer 53 may be located between the first semiconductor material layer 51 and the second semiconductor material layer 52. In some embodiments, the first semiconductor material layer 51 and the second semiconductor material layer 52 may be doped with a first type of dopant. For example: the aforementioned n-type dopant or p-type dopant. In some embodiments, the third semiconductor material layer 53 may be doped with a second type of dopant different from the first type of dopant. For example: the aforementioned p-type dopant or n-type dopant. In some embodiments, the doping concentration of the first semiconductor material layer 51, the second semiconductor material layer 52, and / or the third semiconductor material layer 53 may be about 1.0×10 14 atoms / cm 3 to about 5.0×10 17 atoms / cm 3 . In one embodiment, the thickness of the second substrate 50 may be between about 100 nanometers and 1 nanometer. These values are only examples and are not intended to be limiting. The fabrication and related details of the second substrate 50, the third substrate 60, and the bonding layer 70 with reference to FIG. 2A above may apply here. In some embodiments, the first semiconductor material layer 51 may further include a first heavily doped layer, and the first heavily doped layer may be similar to the first heavily doped layer 46 shown in FIG. 2A. In some embodiments, the second semiconductor material layer 52 may further include a second heavily doped layer extending from the first surface 50a of the second substrate 50, and the second heavily doped layer may be similar to the second heavily doped layer 47 shown in FIG. 2A. The formation processes and related details of the first heavily doped layer and the second heavily doped layer with reference to FIGS. 1A and 2A above may apply here. As shown in FIG. 8B, before joining the first structure 100A and the second structure 800B, a first metal joining layer 41 is formed on the first structure 100A, and a second metal joining layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). In some embodiments, the second metal joining layer 42 may be formed in contact with the first surface 50a of the second substrate 50. In some embodiments, the second metal joining layer 42 may be formed in contact with the second semiconductor material layer 52. In some embodiments, when the second semiconductor material layer 52 further includes a second heavily doped layer, the second metal joining layer 42 may be formed in contact with the second heavily doped layer of the second semiconductor material layer 52. The formation process and related details referred to in FIG. 1B above may be applicable here. As shown in FIG. 8C, the first metal joining layer 41 and the second metal joining layer 42 are joined to form a joining metal layer 40 (step (d)). The second structure 800B is flipped and joined to the first structure 100A through the joining metal layer 40 to form a joined structure 800C. The joining process and related details referred to in FIG. 1C above may be applicable here. As shown in FIG. 8D, a part of the second structure 800B is removed, and the second surface 50b of the second substrate 50 is formed (step (e)). The removal process and related details referred to in FIG. 2D above may be applicable here. In the embodiment shown in FIG. 8D, the first semiconductor material layer 51 is exposed after removing a part of the second structure 800B (e.g., the joining layer 70). In some embodiments, when the first semiconductor material layer 51 further includes a first heavily doped layer, the first heavily doped layer may be exposed after the removal process. The formation process and related details of the first heavily doped layer referred to in FIG. 1D above may be applicable here. As shown in FIG. 8E, the second substrate 50 is patterned to form a plurality of vertical elements including a first vertical element 54c and a second vertical element 55c (step (f)). In the embodiment shown in FIG. 8E, each of the first vertical element 54c and the second vertical element 55c is a vertical bipolar transistor. The present disclosure is not limited thereto. In the embodiment shown in FIG. 8E, the first semiconductor material layer 51 is patterned to form a first semiconductor region 51a and a first semiconductor region 51b of the first vertical element 54c and the second vertical element 55c, the second semiconductor material layer 52 is patterned to form a second semiconductor region 52a and a second semiconductor region 52b of the first vertical element 54c and the second vertical element 55c, and the third semiconductor material layer 53 is patterned to form a third semiconductor region 53a and a third semiconductor region 53b of the first vertical element 54c and the second vertical element 55c. The patterning process may be substantially similar to the process referred to in FIG. 1E above, and for the sake of brevity, the related description is omitted here. As shown in FIG. 8E, the patterned bonding metal layer 40 is formed to form a plurality of contact structures including a first contact structure 40a for the first vertical element 54c and a second contact structure 40b for the second vertical element 55c (step (g)). The patterning process may be substantially similar to the process described above with reference to FIG. 1E, and for the sake of brevity, the related description is omitted herein. As shown in FIG. 8F, after the patterned bonding metal layer 40 is formed (step (g)), a second dielectric layer 22 is formed (step (h)). The second dielectric layer 22 may fill the trench 59 such that the first vertical element 54c and the second vertical element 55c are laterally isolated by the second dielectric layer 22, and the first contact structure 40a and the second contact structure 40b are laterally isolated by the second dielectric layer 22. The formation process and related details described above with reference to FIG. 1H may be applicable herein. As shown in FIG. 8F, first memory cells 100a and second memory cells 100b are formed above vertical elements 54c and 55c (step (i)). The first memory cells 100a are formed above the first vertical element 54c, and the second memory cells 100b are formed above the second vertical element 55c. The materials and processes for forming the first memory cells 100a and the second memory cells 100b have been described with reference to FIG. 1H above, and for the sake of brevity, the related descriptions are omitted herein. The first memory cells 100a and the second memory cells 100b may respectively include a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material. The MTJ structure may include a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer located between the free magnetic layer and the fixed magnetic layer. The fixed magnetic layer may have a fixed magnetization and the free magnetic layer may have a magnetization that can be switched by a program current. Relative to the fixed magnetic layer, the magnetization orientation in the free magnetic layer determines whether the MTJ structure is in a high resistance state or a low resistance state (i.e., whether the memory cell stores a 1 or a 0). For example, if the magnetizations of the free magnetic layer and the fixed magnetic layer are in parallel orientation, the MTJ structure may be in a low resistance state (i.e., the "0" state); and if the magnetizations of the free magnetic layer and the fixed magnetic layer are in an anti-parallel (opposite) orientation, the MTJ structure may be in a high resistance state (i.e., the "1" state). Data writing can be performed by switching the magnetization orientation of the free magnetic layer. In some embodiments, to improve the performance of the MTJ structure, the free magnetic layer and / or the fixed magnetic layer may include a multi-layer structure. In some embodiments, an anti-ferromagnetic layer (AFM layer) may be added between the electrode and the fixed magnetic layer, and the anti-ferromagnetic layer may allow cancellation of the dipole fields around the free magnetic layer. The MTJ structure can be formed by any suitable method and any materials suitable for each layer therein. As shown in FIG. 8F, a second wiring layer 32 is formed above the first memory cells 100a and the second memory cells 100b. The materials and processes for forming the second wiring layer 32 have been described with reference to FIG. 1H above, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 8F, a semiconductor structure including a first wiring layer 31, a first contact structure 40a, a second contact structure 40b, a first vertical element 54c, a second vertical element 55c, and a second dielectric layer 22 is provided. Except for the first vertical element 54c and the second vertical element 55c, the semiconductor structure 150 may be substantially similar to the semiconductor structure 110 shown in FIG. 1H, and the fabrication and related details of the semiconductor structure 110 with reference to FIG. 1H may be applicable herein. In some embodiments, the first contact structure 40a and the second contact structure 40b are located on the first wiring layer 31. Specifically, the first wiring layer 31 may have conductive features including vias and conductive lines. In the embodiment shown in FIG. 8F, the first contact structure 40a and the second contact structure 40b are respectively located on the first source line SL1 and the second source line SL2. In another embodiment, the first contact structure 40a and the second contact structure 40b may be respectively located on vias or conductive lines of the first wiring layer 31. The first contact structure 40a includes a first metal layer 41a, a second metal layer 42a, and a metal bonding interface 43a, where the second metal layer 42a is located above the first metal layer 41a, and the metal bonding interface 43a is located between the first metal layer 41a and the second metal layer 42a. The second contact structure 40b includes a first metal layer 41b, a second metal layer 42b, and a metal bonding interface 43b, where the second metal layer 42b is located above the first metal layer 41b, and the metal bonding interface 43b is located between the first metal layer 41b and the second metal layer 42b. As shown in FIG. 8F, the first vertical element 54c extends between a first end 54g and a second end 54h of the first vertical element 54c, wherein the first vertical element 54c is located above and in contact with the first contact structure 40a. In some embodiments, the first vertical element 54c contacts the first contact structure 40a at the first end 54g of the first vertical element 54c. In some embodiments, the height H1 of the first vertical element 54c (e.g., the height between the first end 54g and the second end 54h of the first vertical element 54c) can be between about 10 nanometers and about 300 nanometers. In some embodiments, the width W3 of the first vertical element 54c is substantially equal to the width W2 of the second metal layer 42a of the first contact structure 40a. The second vertical element 55c extends between a first end and a second end 55h of the second vertical element 55c, wherein the second vertical element 55c is located above and in contact with the second contact structure 40b. In some embodiments, the second vertical element 55c contacts the second contact structure 40b at the first end 55g of the second vertical element 55c. In some embodiments, the width W3' of the second vertical element 55c is substantially equal to the width W2' of the second metal layer 42b of the second contact structure 40b. In some embodiments, the first vertical element 54c and the second vertical element 55c are at the same level. In some embodiments, the height H1 of the first vertical element 54c is substantially equal to the height H2 of the second vertical element 55c (e.g., the height between the first end 55g and the second end 55h of the second vertical element 55c). In some embodiments, the first vertical element 54c and the second vertical element 55c can include single-crystalline semiconductor materials, such as made of silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In the embodiment shown in FIG. 8F, each of the first vertical element 54c and the second vertical element 55c is a vertical bipolar transistor. The present disclosure is not limited thereto. As shown in FIG. 8F, the first semiconductor regions 51a and 51b can be the first emitter / collector regions of the first vertical bipolar transistor 54c and the second vertical bipolar transistor 55c, respectively. The second semiconductor regions 52a and 52b can be the second emitter / collector regions of the first vertical bipolar transistor 54c and the second vertical bipolar transistor 55c, respectively. The third semiconductor regions 53a and 53b can be the base regions of the first vertical bipolar transistor 54c and the second vertical bipolar transistor 55c, respectively. In other words, the first emitter / collector region 51a, the second emitter / collector region 52a, and the base region 53a can together form the first vertical bipolar transistor 54c, and the first emitter / collector region 51b, the second emitter / collector region 52b, and the base region 53b can together form the second vertical bipolar transistor 55c. As shown in FIG. 8F, a first emitter / collector contact 37a may be formed above the first vertical element 54c. A first emitter / collector contact 37b may be formed above the second vertical element 55c. In some embodiments, base contacts 36a and 36b that respectively contact third semiconductor regions 53a and 53b (base regions) of the first vertical element 54c and the second vertical element 55c may be formed. In some embodiments, first emitter / collector contacts 37a and 37b that respectively contact first semiconductor regions 51a and 51b (first emitter / collector regions) of the first vertical element 54c and the second vertical element 55c may be formed. The base contacts 36a and 36b and the first emitter / collector contacts 37a and 37b may respectively include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), some other suitable materials, or combinations of the foregoing. The base contacts 36a and 36b and the first emitter / collector contacts 37a and 37b may be fabricated by any suitable process (e.g., photolithography and etching processes, damascene processes, dual damascene processes, or the like). For example, the base contacts 36a and 36b and the first emitter / collector contacts 37a and 37b may be formed in the second dielectric layer 22 through a damascene or dual damascene process or any suitable method. In the embodiment shown in FIG. 8F, the first contact structure 40a and the second contact structure 40b may be second emitter / collector contacts of the first vertical element 54c and the second vertical element 55c, respectively. As shown in FIG. 8F, a first word line WL1 and a second word line WL2 are formed. The first word line WL1 may be electrically connected to the base contact 36a of the first vertical element 54c. The second word line WL2 may be electrically connected to the base contact 36b of the second vertical element 55c. The first word line WL1 and the second word line WL2 may include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), some other suitable materials, or combinations of the foregoing. The first word line WL1 and the second word line WL2 may be fabricated through any suitable process (e.g., photolithography and etching processes, damascene processes, dual damascene processes, or the like). For example, the first word line WL1 and the second word line WL2 may be formed in the second dielectric layer 22 by using a damascene or dual damascene process or any suitable method. Referring to FIG. 8F, a memory element 240 is provided. The memory element 240 includes a first wiring layer 31, a first contact structure 40a, a first vertical element 54c, a first memory cell 100a, and a second wiring layer 32. The first wiring layer 31 may include a plurality of source lines extending in a first direction 103a. In the embodiment shown in FIG. 8F, the plurality of source lines includes a first source line SL1 and a second source line SL2. The memory element 240 may further include a first word line WL1 and a second word line WL2 extending in the first direction 103a. The memory element 240 may further include a second contact structure 40b, wherein as described above, the first contact structure 40a may be located on the first source line SL1 and the second contact structure 40b may be located on the second source line SL2. In the embodiment shown in FIG. 8F, the first vertical element 54c is electrically connected to the second end 102b of the first memory cell 100a by the second end 54h of the first vertical element 54c. The first vertical element 54c may be electrically connected to the second end 102b of the first memory cell 100a through a first emitter / collector contact 37a. In the embodiment shown in FIG. 8F, the second vertical element 55c is electrically connected to the second end 102b of the second memory cell 100b by the second end 55h of the second vertical element 55c. The second vertical element 55c may be electrically connected to the second end 102b of the second memory cell 100b through a first emitter / collector contact 37b. The second wiring layer 32 may be electrically connected to the first end 101a of the first memory cell 100a. The second wiring layer 32 may also be electrically connected to the first end 101b of the second memory cell 100b. The second wiring layer 32 may include a plurality of bit lines extending in a second direction 103b different from the first direction 103a. In the embodiment shown in FIG. 8F, the plurality of bit lines includes a first bit line BL1, and the first ends 101a and 101b of the memory cells 100a and 100b are electrically connected to the first bit line BL1. In some embodiments, the memory element 240 may further include an alignment mark 90 located on the first substrate 10. The relevant details of the features of the memory element 240 have been described above and will not be repeated here. When the first memory cell 100a and the second memory cell 100b each include a magnetic tunnel junction (MTJ) structure, the memory element 240 shown in FIG. 8F can be a spin-transfer torque type MRAM device (STT-MRAM). For example, in order to perform data writing in the first memory cell 100a, the write current can flow through the first current path from the first source line SL1 through the first vertical element 54c and the memory cell 100a to the first bit line BL1; alternatively, the write current can flow through the second current path from the first bit line BL1 through the memory cell 100a and the first vertical element 54c to the first source line SL1. The flow and direction of the write current can be controlled by the voltages applied to the source line, the word line, and the bit line. Although only two memory cells are depicted in FIGS. 8A-8F, multiple memory cells or an array of memory cells can be fabricated simultaneously using the methods disclosed herein. In the embodiments shown in FIGS. 8A to 8F, a memory element including a vertical bipolar transistor as a selector can be fabricated using the methods disclosed herein. In some embodiments, the semiconductor structure 150 and the memory element 240 can be fabricated through a process similar to that described above with reference to FIGS. 1A to 1I, FIGS. 3A to 3E, or FIGS. 4A to 4F, and for the sake of brevity, the relevant details are omitted herein. FIG. 9 is a schematic diagram showing an intermediate stage of fabricating a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 9, a semiconductor structure 160 and a memory element 250 are provided. Except for the first vertical element 54d and the second vertical element 55d, the semiconductor structure 160 and the memory element 250 can be substantially similar to the semiconductor structure 150 and the memory element 240 shown in FIG. 8F, and the fabrication and relevant details of the semiconductor structure 150 and the memory element 240 described above with reference to FIGS. 8A to 8F can be adjusted and applied herein. In the embodiment shown in FIG. 9, each of the first vertical element 54d and the second vertical element 55d is a vertical field-effect transistor. The present disclosure is not limited thereto. As shown in FIG. 9, the first semiconductor regions 51a and 51b can be the first source / drain regions of the first vertical field-effect transistor 54d and the second vertical field-effect transistor 55d, respectively. The second semiconductor regions 52a and 52b can be the second source / drain regions of the first vertical field-effect transistor 54d and the second vertical field-effect transistor 55d, respectively. The third semiconductor regions 53a and 53b can be the channel regions of the first vertical field-effect transistor 54d and the second vertical field-effect transistor 55d, respectively. As shown in FIG. 9, a gate dielectric 38a and a gate structure 39a of the first vertical element 54d can be formed. A gate dielectric 38b and a gate structure 39b of the second vertical element 55d can be formed. The gate dielectrics 38a and 38b can respectively include silicon oxide, silicon nitride, high-k (high dielectric constant) materials, including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide, combinations thereof, or multiple layers thereof. The gate structures 39a and 39b can respectively include semiconductor materials (e.g., polysilicon), metal materials (e.g., metals or conductive metal compounds), combinations thereof, or multiple layers thereof. In some embodiments, the gate dielectric material layer and the gate structure material layer can be deposited or thermally grown according to acceptable techniques and then lithographically patterned and etched to form the gate dielectrics 38a and 38b and the gate structures 39a and 39b. In some embodiments, a subsequent gate replacement process can also be implemented. A gate dielectric 38a and a gate structure 39a overlapping with the channel region 53a of the first vertical element 54d can be formed, such that the first source / drain region 51a, the second source / drain region 52a, the channel region 53a, and the gate structure 39a can together serve as the first vertical field-effect transistor 54d. A gate dielectric 38b and a gate structure 39b overlapping with the second vertical element 55d can be formed, such that the first source / drain region 51b, the second source / drain region 52b, the channel region 53b, and the gate structure 39b can together serve as the second vertical field-effect transistor 55d. As shown in FIG. 9, a gate contact 36c and a first source / drain contact 37c of the first vertical element 54d can be formed. A gate contact 36d and a first source / drain contact 37d of the second vertical element 55d can be formed. The gate contacts 36c and 36d and the first source / drain contacts 37c and 37d can respectively include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), some other suitable materials, or combinations of the foregoing. The gate contacts 36c and 36d and the first source / drain contacts 37c and 37d can be fabricated through any suitable process (e.g., photolithography and etching processes, damascene processes, dual damascene processes, or the like). For example, the gate contacts 36c and 36d and the first source / drain contacts 37c and 37d can be formed in the second dielectric layer using a damascene or dual damascene process or any suitable method. In the embodiment shown in FIG. 9, the first contact structure 40a and the second contact structure 40b can respectively be the second source / drain contacts of the first vertical element 54d and the second vertical element 44d. As shown in FIG. 9, a first word line WL1 and a second word line WL2 are formed. The first word line WL1 can be electrically connected to the gate contact 36c of the first vertical element 54d. The second word line WL2 can be electrically connected to the gate contact 36d of the second vertical element 55d. The materials and processes for forming the first word line WL1 and the second word line WL2 have been described with reference to FIG. 8F above, and for the sake of brevity, the related descriptions are omitted herein. In the embodiment shown in FIG. 9, a memory element 250 including a vertical field effect transistor as a selector can be fabricated using the method disclosed herein. In some embodiments, the semiconductor structure 160 and the memory element 250 can be fabricated through a process similar to that described above with reference to FIGS. 1A-1I, 3A-3E, or 4A-4F, and for the sake of brevity, the related descriptions are omitted herein. FIG. 10 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 10, a semiconductor structure 161 and a memory element 251 are provided. The semiconductor structure 161 can be substantially similar to the semiconductor structure 160 in FIG. 9, and the semiconductor structure 161 can serve as a memory element (memory element 251), and the fabrication and related details of the semiconductor structure 160 with reference to FIG. 9 above can be applied herein with the following adjustments. As shown in FIG. 10, a first gate dielectric 38a, a second gate dielectric 38a', a first gate structure 39a, and a second gate structure 39a' for forming a first vertical element 54d can be formed. A first gate dielectric 38b, a second gate dielectric 38b', a first gate structure 39b, and a second gate structure 39b' for forming a second vertical element 55d can be formed. The gate dielectrics 38a, 38a', 38b, and 38b' can include silicon oxide, silicon nitride, high-k materials, including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide, combinations thereof, or multiple layers thereof, respectively. The gate structures 39a, 39a', 39b, and 39b' can include semiconductor materials (e.g., polysilicon), metal materials (e.g., metals or conductive metal compounds), combinations thereof, or multiple layers thereof, respectively. In some embodiments, the gate dielectric material layer and the gate structure material layer can be deposited or thermally grown according to acceptable techniques and then lithographically patterned and etched to form the gate dielectrics 38a, 38a', 38b, and 38b' and the gate structures 39a, 39a', 39b, and 39b'. In some embodiments, a successive gate replacement process can also be implemented. The channel region 53a of the first vertical element 54d can be surrounded by the first gate dielectric 38a, the second gate dielectric 38a', the first gate structure 39a, and the second gate structure 39a', such that the first source / drain region 51a, the second source / drain region 52a, the channel region 53a, the first gate structure 39a, and the second gate structure 39a' can jointly serve as a first vertical field-effect transistor 54d. The channel region 53b of the second vertical element 55d can be surrounded by the first gate dielectric 38b, the second gate dielectric 38b', the first gate structure 39b, and the second gate structure 39b', such that the first source / drain region 51b, the second source / drain region 52b, the channel region 53b, the first gate structure 39b, and the second gate structure 39b' can jointly serve as a second vertical field-effect transistor 55d. In the embodiment shown in FIG. 10, the first gate structure 39a and the second gate structure 39a' are spaced apart. In the embodiment shown in FIG. 10, the first gate structure 39b and the second gate structure 39b' are spaced apart. As shown in FIG. 10, a first gate contact 36c, a second gate contact 36c', and a first source / drain contact 37c of the first vertical element 54d can be formed. A first gate contact 36d, a second gate contact 36d', and a first source / drain contact 37d of the second vertical element 55d can be formed. In some embodiments, the gate contacts 36c and 36c' that contact the gate structures 39a and 39a' of the first vertical element 54d can be formed respectively. In some embodiments, the gate contacts 36d and 36d' that contact the gate structures 39b and 39b' of the second vertical element 55d can be formed respectively. The gate contacts 36c, 36c', 36d, and 36d' can respectively include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), some other suitable materials, or a combination of the foregoing. The gate contacts 36c, 36c', 36d, and 36d' can be fabricated through any suitable process (such as: photolithography and etching processes, damascene processes, dual damascene processes, or the like). In the embodiment shown in FIG. 10, the first contact structure 40a and the second contact structure 40b can be the second source / drain contacts of the first vertical element 54d and the second vertical element 55d respectively. The memory element 251 shown in FIG. 10 can be a surrounding gate transistor (SGT) non-volatile memory element. Although only two memory cells are shown in FIG. 10, multiple memory cells or a memory cell array can be fabricated simultaneously using the method disclosed herein. In some embodiments, the semiconductor structure 161 and the memory element 251 can be fabricated through a process similar to that described above with reference to FIGS. 1A to 1I, FIGS. 3A to 3E, or FIGS. 4A to 4F, and for the sake of brevity, the related descriptions are omitted herein. FIG. 11 is a schematic diagram showing an intermediate stage of fabricating a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 11, a semiconductor structure 162 and a memory element 252 are provided. The semiconductor structure 162 and the memory element 252 can be substantially similar to the semiconductor structure 161 and the memory element 251 in FIG. 10, and the fabrication and related details of the semiconductor structure 161 and the memory element 251 described above with reference to FIG. 10 can be adjusted as follows and applied herein. In the embodiment shown in FIG. 11, a first gate structure 39a and a first gate dielectric 38a can be formed on a first side 54e of a channel region 53a of the first vertical field-effect transistor 54d, and a second gate structure 39a' and a second gate dielectric 38a' can be formed on a second side 54f of the channel region 53a of the first field-effect transistor 54d, such that the first source / drain region 51a, the second source / drain region 52a, the channel region 53a, the first gate structure 39a, and the second gate structure 39a' can jointly serve as the first vertical field-effect transistor 54d. The second side 54f can be opposite to the first side 54e. In the embodiment shown in FIG. 11, a first gate structure 39b and a first gate dielectric 38b can be formed on a first side 55e of a channel region 53b of the second vertical field-effect transistor 55d, and a second gate structure 39b' and a second gate dielectric 38b' can be formed on a second side 55f of the channel region 53b of the second vertical field-effect transistor 55d, such that the first source / drain region 51b, the second source / drain region 52b, the channel region 53b, the first gate structure 39b, and the second gate structure 39b' can jointly serve as the second vertical field-effect transistor 55d. The second side 55f can be opposite to the first side 55e. As shown in FIG. 11, a first gate contact 36c, a second gate contact 36c', and a first source / drain contact 37c of the first vertical element 54d can be formed. A first gate contact 36d, a second gate contact 36d', and a first source / drain contact 37d of the second vertical element 55d can be formed. The materials and processes for forming the gate contacts and the first source / drain contacts have been described with reference to FIG. 10, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 11, a first word line WL1 and a second word line WL2 extending in the first direction 103a are formed. The first word line WL1 can be electrically connected to the first gate contact 36c of the first vertical element 54d. The second word line WL2 can be electrically connected to the second gate contact 36c' of the first vertical element 54d. The materials and processes for forming the first word line WL1 and the second word line WL2 have been described with reference to FIG. 8F, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 11, a third word line WL1' and a fourth word line WL2' extending in the first direction 103a are formed. The third word line WL1' can be electrically connected to the first gate contact 36d of the second vertical element 55d. The fourth word line WL2' can be electrically connected to the second gate contact 36d' of the second vertical element 55d. The materials and processes for forming the third word line WL1' and the fourth word line WL2' are substantially similar to the materials and processes of the first word line WL1 and the second word line WL2 with reference to FIG. 8F, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 11, a second wiring layer 32 is formed above the first source / drain contact 37c of the first vertical element 54d and the first source / drain contact 37d of the second vertical element 55d. The materials and processes for forming the second wiring layer 32 have been described with reference to FIG. 1H, and for the sake of brevity, the related descriptions are omitted herein. The second wiring layer 32 may include a plurality of bit lines extending in a second direction 103b different from the first direction 103a. In the embodiment shown in FIG. 11, the plurality of bit lines includes a first bit line BL1, and the first source / drain contacts 37c and 37d of the vertical elements 54d and 55d are electrically connected to the first bit line BL1. The memory element 252 shown in FIG. 11 may be a zero-capacitance random access memory (ZRAM) element. Although only two memory cells are shown in FIG. 11, a plurality of memory cells or an array of memory cells can be fabricated simultaneously using the methods disclosed herein. In some embodiments, the semiconductor structure 162 and the memory element 252 can be fabricated through a process similar to that described with reference to FIGS. 1A-1I, 3A-3E, or 4A-4F, and for the sake of brevity, the related descriptions are omitted herein. FIGS. 12A-12E are schematic diagrams showing intermediate stages of fabricating a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 12A, the semiconductor structure may be substantially similar to the semiconductor structures shown in FIGS. 1D, 2D, 3D, 4E, or 15B, where like reference numerals indicate like elements. In some embodiments, the semiconductor structure shown in FIG. 12A can be fabricated through the processes described with reference to FIGS. 1A-1D, 2A-2D, 4A-4E, or 15A-15B, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 12B, the second substrate 50 is patterned to form a plurality of vertical elements including a first vertical element 54a and a second vertical element 55a (step (f)), and the bonding metal layer 40 is patterned to form a plurality of contact structures including a first contact structure 40a and a second contact structure 40b for the first vertical element 54a and the second vertical element 55a (step (g)). The patterning process may be substantially similar to the process described with reference to FIG. 1E, and for the sake of brevity, the related descriptions are omitted herein. Specifically, in the embodiments shown in FIGS. 12B and 12C, the first wiring layer 31 may include island features (e.g., the first wiring layer 31 under the second contact structure 40b) and / or line features (e.g., the first word line WL1 under the first contact structure 40a). FIG. 12C is a schematic top view of the semiconductor structure shown in FIG. 12B, and FIG. 12D is another cross-sectional view of the semiconductor structure shown in FIG. 12B. Specifically, FIG. 12B is a cross-sectional view of the semiconductor structure in FIG. 12C along line A-A', and FIG. 12D is a cross-sectional view of the semiconductor structure in FIG. 12C along line B-B'. As shown in FIGS. 12B to 12D, as described above, trenches 59 can be formed through the second substrate 50 and the bonding metal layer 40 by one or more etching processes, so that the first vertical element 54a and the second vertical element 55a are separated, and the first contact structure 40a and the second contact structure 40b are separated. As shown in FIGS. 12B to 12D, the vertical stack of the first contact structure 40a and the first vertical element 54a is island-shaped. As shown in FIGS. 12B to 12D, a third vertical element 54a' similar to the first vertical element 54a and a third contact structure 40a' similar to the first contact structure 40a can be formed. As shown in FIGS. 12B to 12D, the first substrate 10 may include functional elements 11, and the first wiring layer 31 is electrically connected to the functional elements 11. In some embodiments, the first wiring layer 31 is electrically connected to the functional elements 11 through the first interconnect structure 35. The formation process and related details of the functional elements 11 and the first interconnect structure 35 have been described with reference to FIGS. 1E to 1G above, and for the sake of brevity, the related description is omitted herein. As shown in FIG. 12E, after patterning the bonding metal layer 40 (step (g)), a second dielectric layer 22 is formed (step (h)). The second dielectric layer 22 can fill the trenches 59, so that the first vertical element 54a and the second vertical element 55a are laterally isolated by the second dielectric layer 22, and the first contact structure 40a and the second contact structure 40b are laterally isolated by the second dielectric layer 22. The formation process and related details referred to in FIG. 1H above can be applied herein. As shown in FIG. 12E, vias 30 are formed. The vias 30 can be electrically connected to the first vertical element 54a at the second end 54h of the first vertical element 54a, and the vias 30 can be electrically connected to the second vertical element 55a at the first end 55g of the second vertical element 55a. In some embodiments, the vias 30 can be electrically connected to the second vertical element 55a through the second contact structure 40b. The vias 30 can include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), some other suitable materials, or a combination of the foregoing. The vias 30 can be formed by any suitable process (such as: photolithography and etching processes, damascene processes, dual damascene processes, or the like). For example, the vias 30 can be formed in the second dielectric layer 22 using a damascene or dual damascene process or any suitable method. As shown in FIG. 12E, a fourth wiring layer is formed above the first vertical element 54a and the second vertical element 55a. The fourth wiring layer 34 can be electrically connected to the first vertical element 54a by the second end 54h of the first vertical element 54a. The fourth wiring layer 34 can include a second word line WL2 that is electrically connected to the second vertical element 55a by the second end 55h of the second vertical element 55a. In the embodiment shown in FIG. 12E, the via 30 can be electrically connected to the first vertical element 54a by the second end 54h of the first vertical element 54a through the fourth wiring layer 34. The material and process for forming the fourth wiring layer 34 can be substantially similar to the material and process of the second wiring layer 32 with reference to FIG. 1H described above. In the embodiment shown in FIG. 12E, the fourth wiring layer 34 can include island-shaped conductive features (e.g., the fourth wiring layer 34 above the first vertical element 54a) and / or linear conductive features (e.g., the second word line WL2 above the second vertical element 55a). As shown in FIG. 12E, a first memory cell 100a is formed above the first vertical element 54a (step (i)). A first memory cell 100a is formed above the first vertical element 54a. In some embodiments, a first memory cell 100a is formed above the fourth wiring layer 34. The first memory cell 100a can have a first end 101a and a second end 102a. In some embodiments, the first memory cell 100a extends from the first end 101a of the first memory cell 100a to the second end 102a of the first memory cell 100a. The materials and processes for forming the first memory cell 100a have been described above with reference to FIG. 1H, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 12E, a second wiring layer 32 is formed above the first memory cell 100a. The materials and processes for forming the second wiring layer 32 have been described above with reference to FIG. 1H, and for the sake of brevity, the related descriptions are omitted herein. In some other embodiments, a via that is electrically connected to a contact structure similar to the contact structure 40 at one end and electrically connected to the second wiring layer 32 at the other end can be formed. The via is similar to the via 30 shown in FIG. 12E, so that the second wiring layer 32 can be electrically connected to the functional elements in the first substrate 10 and / or the conductive features (if any) located on / or in the first substrate 10 through the via and individual contact structures. As shown in FIG. 12E, a semiconductor structure 170 is provided. The semiconductor structure can be substantially similar to the semiconductor structure 110 in FIG. 1H, where like element symbols indicate like elements. In some embodiments, the first vertical element 54a and the second vertical element 55a of the semiconductor structure 170 can be replaced by vertical Schottky diodes of the first vertical element 54b and the second vertical element 55b similar to those shown in FIG. 6F or FIG. 7, respectively As shown in FIG. 12E, a first vertical element 54a extends between a first end 54g and a second end 54h of the first vertical element 54a, wherein the first vertical element 54a is located above and in contact with the first contact structure 40a. In some embodiments, the first vertical element 54a contacts the first contact structure 40a at the first end 54g of the first vertical element 54a. A second vertical element 55a extends between a first end 55g and a second end 55h of the second vertical element 55a, wherein the second vertical element 55a is located above and in contact with the second contact structure 40b. In some embodiments, the second vertical element 55a contacts the second contact structure 40b at the first end 55g of the second vertical element 55a. Referring to FIG. 12E, a memory element 260 is provided. The memory element 260 includes a first wiring layer 31, a first contact structure 40a, a first vertical element 54a, a first memory cell 100a, and a second wiring layer 32. The first wiring layer 31 may include a plurality of word lines extending in a first direction 103a. In the embodiment shown in FIG. 12E, the plurality of word lines includes a first word line WL1. The memory element 260 may further include a second contact structure 40b, wherein the first contact structure 40a may land on the first word line WL1, and the second contact structure 40b may land on an island feature of the first wiring layer 31. In the embodiment shown in FIG. 12E, the first vertical element 54a is electrically connected to a second end 102a of the first memory cell 100a by a second end 54h of the first vertical element 54a. In the embodiment shown in FIG. 12E, the second vertical element 55a is electrically connected to a second end 102a of the first memory cell 100a by a first end 55g of the second vertical element 55a. In some embodiments, the second vertical element 55a is electrically connected to the second end 102a of the first memory cell 100a through a via 30. The second wiring layer 32 may be electrically connected to a first end 101a of the first memory cell 100a. The second wiring layer 32 may include a plurality of bit lines extending in a second direction 103b different from the first direction 103a. In the embodiment shown in FIG. 12E, the plurality of bit lines includes a first bit line BL1, and the first end 101a of the first memory cell 100a is electrically connected to the first bit line BL1. A fourth wiring layer 34 may be electrically connected to a second end 102a of the first memory cell 100a. The fourth wiring layer 34 may include a plurality of word lines extending in the first direction 103a. In the embodiment shown in FIG. 12E, the plurality of word lines includes a second word line WL2. When the first memory cell 100a includes a magnetic tunnel junction (MTJ) structure, the memory element 260 shown in FIG. 12E can be a spin transfer torque type MRAM element (STT-MRAM). For example, to perform data writing in the first memory cell 100a, a write current can flow through a first current path from the first word line WL1 through the first vertical element 54a and the memory element 100a to the first bit line BL1; alternatively, the write current can flow through a second current path from the first bit line BL1 through the memory element 100a and the second vertical element 55a to the second word line WL2. The flow and direction of the write current can be controlled by voltages applied to the word lines and bit lines. Although only one memory cell is illustrated in FIGS. 12A-12E, multiple memory cells or an array of memory cells can be fabricated simultaneously using the methods disclosed herein. In the embodiments shown in FIGS. 12A to 12E, a memory element including two PN diodes as selectors can be fabricated using the methods disclosed herein. In some embodiments, the first vertical element 54a and the second vertical element 55a of the memory element 260 can be replaced with vertical Schottky diodes substantially similar to the first vertical element 54b and the second vertical element 55b shown in FIGS. 6 or 7, respectively, to provide a memory element including two Schottky diodes as selectors. FIGS. 13A to 13E are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 13A, the semiconductor structure can be substantially similar to the semiconductor structures of FIGS. 1D, 2D, 3D, 4E, or 15B, where like element symbols indicate like elements. In some embodiments, the semiconductor structure shown in FIG. 13A can be fabricated through the processes described above with reference to FIGS. 1A to 1D, FIGS. 2A to 2D, FIGS. 3A to 3D, FIGS. 4A to 4E, or FIGS. 15A to 15B, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 13B, the second substrate 50 is patterned to form a plurality of vertical elements including the first vertical element 54a and the second vertical element 55a (step (f)), and the bonding metal layer 40 is patterned to form a plurality of contact structures including a first contact structure 40a and a second contact structure 40b for use by the first vertical element 54a and the second vertical element 55a (step (g)). The patterning process can be substantially similar to the process described above with reference to FIG. 1E, and for the sake of brevity, the related descriptions are omitted herein. As shown in FIG. 13C, after patterning the bonding metal layer 40 (step (g)), a second dielectric layer 22 is formed (step (h)). The second dielectric layer 22 can fill the trenches 59 such that the first vertical element 54a and the second vertical element 55a are laterally isolated by the second dielectric layer 22, and the first contact structure 40a and the second contact structure 40b are laterally isolated by the second dielectric layer 22. The formation process and related details referred to in FIG. 1H above can be applied here. As shown in FIG. 13C, an electrode 105 is formed above the first vertical element 54a and the second vertical element 55a. The electrode 105 can be electrically connected to the first vertical element 54a by the second end 54h of the first vertical element 54a. The electrode 105 can be electrically connected to the second vertical element 55a by the second end 55h of the second vertical element 55a. In some embodiments, the electrode 105 can include materials with a high spin Hall effect, such as β-Tantalum (β-Ta), β-Tungsten (β-W), Tantalum (Ta), Tungsten (W), Platinum (Pt), Copper (Cu) doped with elements such as Iridium (Ir) and Bismuth (Bi), any other suitable materials with high spin-orbit coupling, or combinations of the foregoing. The electrode 105 can be fabricated through any suitable process (e.g., photolithography and etching processes, damascene processes, dual damascene processes, or the like). As shown in FIG. 13C, a first memory cell 100a is formed above the first vertical element 54a (step (i)). In some embodiments, the first memory cell 100a is formed above the electrode 105. The electrode 105 can laterally extend from the first side 104a of the first memory cell 100a to the second side 104b of the first memory cell 100a. The first memory cell 100a can have a first end 101a and a second end 102a. In some embodiments, the first memory cell 100a extends from the first end 101a of the first memory cell 100a to the second end 102a of the first memory cell 100a. The electrode 105 can be electrically connected to the second end 102a of the first memory cell 100a. The first memory cell 100a can include a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material. The materials and processes for forming the first memory cell 100a have been described above with reference to FIG. 1H, and for the sake of brevity, the related descriptions are omitted here. As shown in FIG. 13C, a second wiring layer 32 is formed above the first memory cell 100a. The materials and processes for forming the second wiring layer 32 have been described above with reference to FIG. 1H, and for the sake of brevity, the related descriptions are omitted here. As shown in FIG. 13C, a plurality of vias including a first via 30a and a second via 30b are formed. The first via 30a can be formed above the first vertical element 54a. The first via 30a can be formed on the first side 104a of the first memory cell 100a. The second via 30b can be formed above the second vertical element 55a. The second via 30b can be formed on the second side 104b of the first memory cell 100a. In the embodiment shown in FIG. 13C, the first via 30a can be electrically connected to the first vertical element 54a by the second end 54h of the first vertical element 54a, and the second via 30b can be electrically connected to the second vertical element 55a by the second end 55h of the second vertical element 55a. In some embodiments, the contacts 30a and 30b can be electrically connected to the vertical elements 54a and 55a through the electrodes 105. In some embodiments, the first via 30a is electrically connected to the electrode 105 on the first side 104a of the first memory cell 100a, and the second via 30b is electrically connected to the electrode 105 on the second side 104b of the first memory cell 100a. The materials and processes for forming the vias 30a and 30b can be similar to the materials and processes of the via 30 with reference to FIG. 12E described above. As shown in FIG. 13D, the second structure 200B shown in FIG. 2A is flipped and bonded to the first structure 1100A shown in FIG. 13C through the bonding metal layer 40 to form the bonding structure 1100C. Specifically, before bonding the first structure 1100A and the second structure 200B, a first metal bonding layer 41 is formed on the first structure 1100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). The first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form the bonding metal layer 40 (step (d)). The processes and related details with reference to FIGS. 2B and 2C described above can be applied herein. As shown in FIG. 13E, a part of the second structure 200B is removed, and the second surface (not shown) of the second substrate 50 is formed (step (e)). Then, the second substrate 50 is patterned to form a plurality of vertical elements including a third vertical element 56a and a fourth vertical element 57a (step (f)), and the bonding metal layer 40 is patterned to form a plurality of contact structures including a third contact structure 40c and a fourth contact structure 40d for the third vertical element 56a and the fourth vertical element 57a (step (g)). The third contact structure 40c and the fourth contact structure 40d can be fabricated through a process similar to that of the first contact structure 40a and the second contact structure 40b in FIG. 1E described above, and if applicable, the related details about the first contact structure 40a and the second contact structure 40b described above can also be applied herein. As shown in FIG. 13E, after patterning the bonding metal layer 40 (step (g)), a third dielectric layer 23 is formed (step (h)). The third dielectric layer 23 can surround the vertical elements 56a and 57a and the contact structures 40c and 40d. The third dielectric layer 23 can include one or more stacked dielectric layers. The third dielectric layer 23 can fill a trench (not shown) between the third vertical element 56a and the fourth vertical element 57a such that the third vertical element 56a and the fourth vertical element 57a are laterally isolated by the third dielectric layer 23, and the third contact structure 40c and the fourth contact structure 40d are laterally isolated by the third dielectric layer 23. The materials and processes for forming the third dielectric layer 23 can be similar to those of the second dielectric layer 22 with reference to FIG. 1H described above. As shown in FIG. 13E, a third wiring layer 33 is formed over the third vertical element 56a and the fourth vertical element 57a. The materials and processes for forming the third wiring layer 33 can be similar to those of the second wiring layer 32 with reference to FIG. 1H described above. For example, an inlay or dual inlay process or any suitable method can be used to form the third wiring layer 33 in the third dielectric layer 23. As shown in FIG. 13E, a semiconductor structure 180 is provided that includes a first wiring layer 31, a first contact structure 40a, a second contact structure 40b, a first vertical element 54a, a second vertical element 55a, and a second dielectric layer 22. The first wiring layer 31 is located over the first substrate 10. The fabrication and related details of the first wiring layer 31, the first contact structure 40a, the second contact structure 40b, the first vertical element 54a, the second vertical element 55a, and the second dielectric layer 22 can be substantially similar to those with reference to FIGS. 1A to 1I, FIGS. 2A to 2E, FIGS. 3A to 3E, or FIGS. 4A to 4F described above, and for the sake of brevity, are not repeated herein. As shown in FIG. 13E, the semiconductor structure 180 can further include a third contact structure 40c, a fourth contact structure 40d, a third vertical element 56a, a fourth vertical element 57a, and a third dielectric layer 23. The third contact structure 40c includes a first metal layer 41c, a second metal layer 42c, and a metal bonding interface 43c, where the second metal layer 42c is located over the first metal layer 41c, and the metal bonding interface 43c is located between the first metal layer 41c and the second metal layer 42c. The fourth contact structure 40d includes a first metal layer 41d, a second metal layer 42d, and a metal bonding interface 43d, where the second metal layer 42d is located over the first metal layer 41d, and the metal bonding interface 43d is located between the first metal layer 41d and the second metal layer 42d. In some embodiments, as previously described with reference to FIGS. 13D to 13E, each of the third contact structure 40c and the fourth contact structure 40d can be formed by patterning a bonding metal layer, where the bonding metal layer is formed by bonding a first metal bonding layer and a second metal bonding layer. Thus, the second metal layer 42c of the third contact structure 40c can be directly bonded to the first metal layer 41c of the third contact structure 40c, such that a metal bonding interface 43c is formed between the first metal layer 41c and the second metal layer 42c; and the second metal layer 42d of the fourth contact structure 40d can be directly bonded to the first metal layer 41d of the fourth contact structure 40d, such that a metal bonding interface 43d is formed between the first metal layer 41d and the second metal layer 42d. Each of the first metal layers 41c and 41d and the second metal layers 42c and 42d can include a multi-layer structure. However, the present disclosure is not limited thereto. The first metal layer 41c of the third contact structure 40c can be in contact with the first viaduct 30a, and the second metal layer 42c of the third contact structure 40c can be in contact with the third vertical element 56a. The first metal layer 41d of the fourth contact structure 40d can be in contact with the second viaduct 30b, and the second metal layer 42d of the fourth contact structure 40d can be in contact with the fourth vertical element 57a. Thus, the third vertical element 56a and the fourth vertical element 57a can be electrically connected to the first viaduct 30a and the second viaduct 30b through the third contact structure 40c and the fourth contact structure 40d, respectively. The third vertical element 56a and the fourth vertical element 57a can be substantially similar to the first vertical element 54a and the second vertical element 55a, and can be formed through a process similar to that previously described with reference to FIG. 1E. If applicable, the related descriptions regarding the first vertical element 54a and the second vertical element 55a can be applied herein. However, the present disclosure is not limited thereto. As shown in FIG. 13E, the third vertical element 56a extends between a first end 56g and a second end 56h of the third vertical element 56a, where the third vertical element 56a is located above and in contact with the third contact structure 40c. In some embodiments, the third vertical element 56a is in contact with the third contact structure 40c at the first end 56g of the third vertical element 56a. In some embodiments, the height H3 of the third vertical element 56a (e.g., the height between the first end 56g and the second end 56h of the third vertical element 56a) can be between about 10 nanometers and 300 nanometers. The fourth vertical element 57a extends between a first end 57g and a second end 57h of the fourth vertical element 57a, where the fourth vertical element 57a is located above and in contact with the fourth contact structure 40d. In some embodiments, the fourth vertical element 57a is in contact with the fourth contact structure 40d at the first end 57g of the fourth vertical element 57a. In some embodiments, the third vertical element 56a and the fourth vertical element 57a are at the same level. In other words, the top end (e.g., the second end 56h) of the third vertical element 56a and the top end (e.g., the second end 57h) of the fourth vertical element 57a can be substantially horizontal, and the bottom end (e.g., the first end 56g) of the third vertical element 56a and the bottom end (e.g., the first end 57g) of the fourth vertical element 57a can be substantially horizontal. In some embodiments, the third vertical element 56a and the fourth vertical element 57a are located above the first vertical element 54a. In some embodiments, the height H3 of the third vertical element 56a is substantially equal to the height H4 of the fourth vertical element 57a (e.g., the height between the first end 57g and the second end 57h of the fourth vertical element 57a). In some embodiments, each of the third vertical element 56a and the fourth vertical element 57a can include single-crystalline semiconductor material, such as silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In the embodiment shown in FIG. 13E, each of the first vertical element 54a, the second vertical element 55a, the third vertical element 56a, and the fourth vertical element 57a is a vertical PN diode. This disclosure is not limited thereto. The first vertical element 54a and the second vertical element 55a can be arranged in the same direction, as shown in FIG. 13E, such that the first current I1 allowed by the first vertical element 54a (e.g., from the first end 54g to the second end 54h of the first vertical element 54a) and the second current I2 allowed by the second vertical element 55a under similar conditions (e.g., from the first end 55g to the second end 55h of the second vertical element 55a) have the same direction. The third vertical element 56a and the fourth vertical element 57a can be arranged in the same direction, as shown in FIG. 13E, such that the third current I3 allowed by the third vertical element 56a (e.g., from the first end 56g to the second end 56h of the third vertical element 56a) and the fourth current I4 allowed by the fourth vertical element 57a under similar conditions (e.g., from the first end 57g to the second end 57h of the fourth vertical element 57a) have the same direction. As shown in FIG. 13E, the first vertical element 54a and the third vertical element 56a can be arranged in the same direction such that the first current I1 has the same direction as the third current I3; the second vertical element 55a and the fourth vertical element 57a can be arranged in the same direction such that the second current I2 and the fourth current I4 have the same direction. Referring to FIG. 13E, a memory element 270 is provided. The memory element 270 includes a first wiring layer 31, a first contact structure 40a, a first vertical element 54a, an electrode 105, a first memory cell 100a, a second wiring layer 32, a second contact structure 40b, a second vertical element 55a, a third contact structure 40c, a third vertical element 56a, a fourth contact structure 40d, and a fourth vertical element 54a. The first wiring layer 31 may include a plurality of word lines. In the embodiment shown in FIG. 13E, the plurality of word lines includes a first word line WL1 and a second word line WL2. As shown in FIG. 13E, the first word line WL1 extends in a first direction 103a, and the second word line WL2 may extend in a second direction 103b different from the first direction 103a. The first contact structure 40a may be located on the first word line WL1, and the second contact structure 40b may be located on the second word line WL2. In the embodiment shown in FIG. 13E, the first vertical element 54a is electrically connected to the second end 102a of the first memory cell 100a by the second end 54h of the first vertical element 54a. In the embodiment shown in FIG. 13E, the second vertical element 55a is electrically connected to the second end 102a of the first memory cell 100a by the second end 55h of the second vertical element 55a. In the embodiment shown in FIG. 13E, the third vertical element 56a is electrically connected to the second end 102a of the first memory cell 100a by the first end 56g of the third vertical element 56a. In the embodiment shown in FIG. 13E, the fourth vertical element 57a is electrically connected to the second end 102a of the first memory cell 100a by the first end 57g of the fourth vertical element 57a. In the embodiment shown in FIG. 13E, the first via 30a may be electrically connected to the third vertical element 56a by the first end 56g of the third vertical element 56a, and the second via 30b may be electrically connected to the fourth vertical element 57a by the first end 57g of the fourth vertical element 57a. Thus, the third vertical element 56a and the fourth vertical element 57a may be electrically connected to the electrode 105 through the first via 30a and the second via 30b, respectively. The electrode 105 may be electrically connected to the third vertical element 56a by the first end 56g of the third vertical element 56a. The electrode 105 may be electrically connected to the fourth vertical element 57a by the first end 57g of the fourth vertical element 57a. In some embodiments, the first vertical element 54a and the third vertical element 56a are both electrically connected to the electrode 105 on the first side 104a of the first memory cell 100a, and the second vertical element 55a and the fourth vertical element 57a are both electrically connected to the electrode 105 on the second side 104b of the first memory cell 100a. In the embodiment shown in FIG. 13E, the second wiring layer 32 may be electrically connected to the first end 101a of the first memory cell 100a. The second wiring layer 32 may include a plurality of bit lines extending in the second direction 103b. In the embodiment shown in FIG. 13E, the plurality of bit lines includes a first bit line BL1, and the first end 101a of the first memory cell 100a is electrically connected to the first bit line BL1. In the embodiment shown in FIG. 13E, the memory element 270 further includes a third wiring layer 33. The third vertical element 56a may be electrically connected to the third wiring layer 33 by the second end 56h of the third vertical element 56a. The fourth vertical element 57a may be electrically connected to the third wiring layer 33 by the second end 57h of the fourth vertical element 57a. The third wiring layer 33 may include a plurality of word lines. In the embodiment shown in FIG. 13E, the plurality of word lines includes a third word line WL3 and a fourth word line WL4. As shown in FIG. 13E, the third word line WL3 extends in the first direction 103a, and the fourth word line WL4 extends in the second direction 103b. The third word line WL3 may be electrically connected to the third vertical element 56a by the second end 56h of the third vertical element 56a. The fourth word line WL4 may be electrically connected to the fourth vertical element 57 by the second end 57h of the fourth vertical element 57a. Each of the vertical elements 54a - 57a has a length 1F and a width 1F, where F represents half of the minimum feature size or minimum feature pitch typically associated with a particular photolithography process. As shown in FIG. 13E, the memory element 270 has cell dimensions of 6F and 2F in the first direction 103a and the second direction 103b, respectively, providing a cell size of 12 feature squares (F 2 ) of cell size. When the first memory cell 100a includes a magnetic tunnel junction (MTJ) structure, the memory cell 270 shown in FIG. 13E can be a spin-orbit torque type MRAM (SOT-MRAM) device. When a write current flows through the electrode 105, the spin Hall effect (SHE) of the electrode 105 provides spin injection into the free magnetic layer of the MTJ structure. A large spin Hall effect provides sufficient spin injection to switch the orientation of the magnetism in the free magnetic layer. A large spin Hall effect can be achieved by using a suitable material with a high spin electron effect (high spin injection efficiency) for the electrode 105 or by flowing a large write current through the electrode 105. To reduce power consumption, it is more feasible to select a suitable material with a high spin Hall effect, and some materials have been described above with reference to FIG. 13C. For example, to perform the data writing process in the first memory cell 100a, the write current can flow through the first current path from the first word line WL1 through the first vertical element 54a, the electrode 105, and the fourth vertical element 57a to the fourth word line WL4; or, the write current can flow through the second current path from the second word line WL2 through the second vertical element 55a, the electrode 105, and the third vertical element 56a to the third word line WL3. The flow and direction of the write current can be controlled by the voltage applied to the word lines. Although FIGS. 13A-13E only show one memory cell, multiple memory cells or an array of memory cells can be fabricated simultaneously by the methods disclosed herein. In the embodiments shown in FIGS. 13A to 13E, a memory element including four PN diodes as selectors can be fabricated using the methods disclosed herein. In some embodiments, the vertical elements 54a-57a of the memory element 270 can be replaced by vertical Schottky diodes substantially similar to the vertical elements 54b and 55b shown in FIGS. 6F or 7, respectively, to provide a memory element including four Schottky diodes as selectors. FIG. 14 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 14, a semiconductor structure 181 and a memory element 271 are provided. Except that the semiconductor structure 181 and the memory element 271 do not include the second contact structure 40b, the second vertical element 55a, the second via 30b, the fourth contact structure 40d, and the fourth vertical element 57a connected to the electrode 105 as shown in FIG. 13E, the semiconductor structure 181 and the memory element 271 can be substantially similar to the semiconductor structure 180 and the memory element 270 shown in FIG. 13E, and for the sake of brevity, the related descriptions are omitted herein. When the first memory cell 100a includes a magnetic tunnel junction (MTJ) structure, the memory element 271 shown in FIG. 14 can be a spin transfer torque type MRAM element (STT-MRAM). For example, to perform a data writing process in the first memory cell 100a, a writing current can flow through a first current path from the first word line WL1 through the first vertical element 54a and the memory cell 100a to the first bit line BL1; alternatively, the writing current can flow through a second current path from the first bit line BL1 through the memory cell 100a and the third vertical element 56a to the third word line WL3. The flow and direction of the writing current can be controlled by voltages applied to the word lines and bit lines. Although only one memory cell is shown in FIG. 14, multiple memory cells or an array of memory cells can be fabricated simultaneously using the methods disclosed herein. The arrangement shown in FIG. 14 can further reduce the memory cell size from 12F compared to the memory element 260 shown in FIG. 12E 2 to 8F 2 . The structure shown in FIG. 14 has a cell size of 4F in the first direction 103a and a cell size of 2F in the second direction 103b, providing a cell size of 8 feature squares (F 2 ); while the memory element 260 shown in FIG. 12E has a cell size of 6F in the second direction 103b and a cell size of 2F in the first direction 103a, providing a unit size of 12 feature squares (F 2 ). Different architectures can further reduce the memory cell size. In the embodiment shown in FIG. 14, a memory element including two PN diodes as selectors can be fabricated using the methods disclosed herein. In some embodiments, the first vertical element 54a and the third vertical element 56a of the memory element 271 can be replaced with vertical Schottky diodes substantially similar to the first vertical element 54b and the second vertical element 55b shown in FIGS. 6F or 7, respectively, to provide a memory element including two Schottky diodes as selectors. FIGS. 15A to 15B are schematic diagrams showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG. 15A, a bonding structure 100C' is provided. The bonding structure 100C' may be substantially similar to the bonding structure 100C shown in FIG. 1C, except that the bonding structure 100C' does not include an implanted hydrogen layer similar to the implanted hydrogen layer 58 shown in FIG. 1C, where like element symbols indicate like elements. The bonding structure 100C' shown in FIG. 15A may be fabricated through a process similar to the foregoing process with reference to FIGS. 1A to 1C, and for the sake of brevity, the related description is omitted herein. In the embodiment shown in FIGS. 15A to 15B, the upper layer 50p of the second substrate 50 may include silicon, and the first semiconductor material layer 51 and the second semiconductor material layer 52 may include germanium (Ge) or silicon germanium (Si x Ge y ). The present disclosure is not limited thereto. The semiconductor material layers 51 and 52 may have a high etching selectivity with respect to the upper layer 50p of the second substrate 50. In other words, under the same etching conditions, the etching rate of the upper layer 50p of the second substrate 50 is substantially faster than the etching rates of the semiconductor material layers 51 and 52. If applicable, the relevant details of the second substrate 50 with reference to FIG. 1A may be applicable herein. As shown in FIG. 15B, a part of the second structure is removed, and a second surface 50b of the second substrate 50 is formed (step (e)). In the embodiment shown in FIG. 15B, removing the second structure includes removing the upper layer 50p of the second substrate 50. The upper layer 50p of the second substrate 50 may be removed through an etching process under suitable etching conditions. In some embodiments, the first semiconductor material layer 51 (e.g., Ge or Si x Ge y ) may serve as an etching stop layer for the etching process of the removed part of the second structure (e.g., silicon). After removal, the second surface 50b of the second substrate 50 is formed. The subsequent process may be substantially similar to the process with reference to FIGS. 1E to 1H, and for the sake of brevity, the related description is omitted herein. The process disclosed herein may provide additional options for fabricating vertical devices and may reduce the process steps and process time. For example, the implanted hydrogen process may be omitted. And the process disclosed herein may also provide vertical devices including germanium (Ge) or silicon germanium (Si x Ge y ) for high-frequency and high-power applications. The description of the embodiments provided is for the purpose of enabling a person having ordinary skill in the art to make and use the present invention. Various modifications to the embodiments will be apparent to those of ordinary skill in the art, and the basic principles determined herein can be applied to other embodiments without creative effort. The claimed subject matter is not limited to the embodiments shown herein, but rather is to be accorded the broadest scope consistent with the principles and novel features disclosed herein. Other embodiments are contemplated as being within the spirit and scope of the present invention. Accordingly, the present invention is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents. 10: First substrate 11: Functional element 21: First dielectric layer 21a: Uppermost surface 22: Second dielectric layer 23: Third dielectric layer 30a: First via 30b: Second via 31: First wiring layer 32: Second wiring layer 33: Third wiring layer 34: Fourth wiring layer 35: First interconnect structure 36a, 36b: Base contact 36c, 36c’, 36d, 36d’: Gate contact 37a, 37b: First emitter / collector contact 37c, 37d: First source / drain contact 38a, 38a’, 38b, 38b’: Second gate dielectric 39a, 39a’, 39b, 39b’: Gate structure 40: Bonding metal layer 40a: First contact structure 40b: Second contact structure 40a’, 40b’, 40c: Third contact structure 40d: Fourth contact structure 41, 41a, 41b, 41c, 41d: First metal layer 42, 42a, 42b, 42c, 42d: Second metal layer 43, 43a, 43b, 43c, 43d: Metal bonding interface 44: First metal material layer 44a, 44b: First metal part 45: Second metal material layer 45a, 45b: Second metal part 46: First heavily doped layer 47: Second heavily doped layer 50: Second substrate 50a: First surface 50b: Second surface 50p: Upper layer 51: First semiconductor material layer 51a, 51b: First semiconductor region 52: Second semiconductor material layer 52a, 52b: Second semiconductor region 53: Third semiconductor material layer 53a, 53b: Third semiconductor region 54a, 54b, 54c, 54d: First vertical element 55a, 55b, 55c, 55d: Second vertical element 54a’, 55a’, 56a,: Third vertical element 57a: Fourth vertical element 54g, 55g, 56g, 57g: First end 54h, 55h, 55h’, 56h, 57h: Second end 54e, 55e: First side 55e, 55f: Second side 58: Implanted hydrogen layer 59: Groove 60: Third substrate 70: Bonding layer 80: Etch stop layer 90: Alignment mark 100A, 500A: First structure 100B, 200B, 300B, 400B, 600B, 800B: Second structure 100C, 200C, 300C, 400C, 500C, 600C, 800C, 100C’: Bonding structure 100a: First memory cell 100b: Second memory cell 100b’: Third memory cell 101a, 101b, 101b’: First end 102a, 102b: Second end 103a: First direction 103b: Second direction 104a: First side 104b: Second side 105: Electrode 110, 120, 130, 140,150, 160, 161, 162, 170, 180, 181: Semiconductor structure 200, 210, 220, 230, 240, 250, 251, 252, 260, 270, 271: Memory element H1, H2, H3, H4: Height W1, W1’, W2, W2’, W3, W3’: Width I1: First current I2: Second current I3: Third current I4: Fourth current BL1: First bit line BL2: Second bit line WL1: First word line WL2: Second word line WL1’: Third word line WL2’: Fourth word line SL1: First source line SL2: Second source line WL3: Third word line WL4: Fourth word line A - A’, B - B’: Line, Figures 1A to 1I are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 2A to 2E are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 3A to 3E are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 4A to 4F are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 5A to 5H are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 6A to 6F are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 7 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 8A to 8F are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 9 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 10 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 11 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 12A to 12E are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 13A to 13E are schematic diagrams showing intermediate stages of manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 14 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. FIGS. 15A to 15B are schematic diagrams showing an intermediate stage of manufacturing a semiconductor structure according to an embodiment of the present disclosure. 10: First substrate 21: First dielectric layer 31: First wiring layer 40: Bonding metal layer 41: First metal layer 42: Second metal layer 43: Metal bonding interface 44: First metal layer 51: First semiconductor material layer 60: Third substrate 70: Bonding layer 90: Alignment mark 600C: Bonding structure WL1: First word line WL2: Second word line

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a first structure including a first substrate and a wiring layer located above the first substrate; providing a second structure including a second substrate; forming a first metal bonding layer on the first structure and forming a second metal bonding layer on a first surface of the second substrate; bonding the first metal bonding layer and the second metal bonding layer to form a bonding metal layer; removing a portion of the second structure and forming a second surface of the second substrate; patterning the second substrate to form a plurality of vertical elements; and patterning the bonding metal layer according to an alignment mark to form a plurality of contact structures for use by the plurality of vertical elements.

2. The method as described in claim 1, wherein patterning of the second substrate is performed to form the plurality of vertical elements after bonding the first metal bonding layer and the second metal bonding layer to form the bonding metal layer.

3. The method as described in claim 1, wherein patterning of the bonding metal layer to form the plurality of contact structures is performed after bonding the first metal bonding layer and the second metal bonding layer to form the bonding metal layer.

4. The method as claimed in claim 1, wherein in bonding the first metal bonding layer and the second metal bonding layer to form the bonding metal layer, at least one of the first metal bonding layer and the second metal bonding layer is an unpatterned metal layer.

5. The method as claimed in claim 1, wherein joining the first metal bonding layer and the second metal bonding layer to form the bonding metal layer comprises joining the first metal bonding layer and the second metal bonding layer through thermocompression bonding, eutectic bonding or reactive bonding.

6. The method as claimed in claim 1, wherein each of the first metal bonding layer and the second metal bonding layer comprises aluminum (Al), gold (Au), indium (In), palladium (Pd), germanium (Ge), copper (Cu), aluminum-silicon alloy (Al-Si), titanium nitride (TiN), lead-tin alloy (Pb-Sn), aluminum-tin alloy (Al-Sn), gold-tin alloy (Au-Sn), indium-palladium alloy (In-Pd), indium-tin alloy (In-Sn), silver-tin alloy (Ag-Sn), gold-indium alloy (Au-In), or copper-tin alloy (Cu-Sn).

7. The method as claimed in claim 1, wherein the first structure further includes the alignment mark, and patterning the second substrate to form the plurality of vertical elements includes patterning the second substrate according to the alignment mark.

8. The method as described in claim 1 further includes forming a dielectric layer around the plurality of vertical elements and the plurality of contact structures after patterning the bonding metal layer to form the plurality of contact structures for use by the plurality of vertical elements.

9. The method as described in claim 1 further includes forming a plurality of memory cells above the vertical element.

10. The method as described in claim 1, wherein the first substrate includes a functional element, and the wiring layer is electrically connected to the functional element.

11. The method as described in claim 1, wherein the first structure further includes a plurality of memory cells located between the wiring layer and the first substrate.

12. The method as described in claim 1, wherein each of the vertical elements is a vertical PN diode, a vertical Schottky diode, a vertical bipolar transistor, or a vertical field-effect transistor.

13. The method as described in claim 1, wherein the wiring layer comprises a plurality of conductive lines.

14. The method as described in claim 1, wherein the second substrate comprises a single-crystal semiconductor material.

15. The method of claim 1, wherein the second substrate includes a first semiconductor material layer and a second semiconductor material layer thereon the first semiconductor material layer, the first semiconductor material layer being doped with a first type of dopant and the second semiconductor material layer being doped with a second type of dopant; and after the formation of the first metal bonding layer and the formation of the second metal bonding layer, the second metal bonding layer is in contact with the second semiconductor material layer.

16. The method of claim 15, wherein the second semiconductor material layer includes a second heavily doped layer extending from the first surface of the second substrate.

17. The method of claim 1, wherein the second substrate includes a first semiconductor material layer, a second semiconductor material layer on the first semiconductor material layer, and a third semiconductor material layer located between the first semiconductor material layer and the second semiconductor material layer; the first semiconductor material layer and the second semiconductor material layer are doped with a first type of dopant, and the third semiconductor material layer is doped with a second type of dopant; and after the formation of the first metal bonding layer and the formation of the second metal bonding layer, the second metal bonding layer contacts the second semiconductor material layer.

18. The method of claim 1, wherein the second substrate includes a semiconductor material layer and a first metal material layer thereon the semiconductor material layer, and the second metal bonding layer contacts the first metal material layer after the first metal bonding layer is formed and the second metal bonding layer is formed.

19. The method as described in claim 1 further includes forming a second metal material layer on the second surface of the second substrate after removing the portion of the second structure and forming the second surface of the second substrate.

20. The method as claimed in claim 1 further includes, after removing the portion of the second structure and forming the second surface of the second substrate, forming a first heavily doped layer extending from the second surface of the second substrate.

21. The method of claim 1, wherein the second substrate further includes a first heavily doped layer, and the first heavily doped layer is exposed after the portion of the second structure is removed and the second surface of the second substrate is formed.

22. The method of claim 1, wherein the second substrate further includes an implanted hydrogen layer, and removing the portion of the second structure and forming the second surface of the second substrate includes removing a portion of the second substrate from approximately the implanted hydrogen layer.

23. The method of claim 1, wherein the second structure further includes a third substrate and an etch stop layer located between the second substrate and the third substrate, and removing the portion of the second structure to form the second surface of the second substrate includes removing the etch stop layer.

24. The method of claim 1, wherein the second structure further includes a third substrate and a bonding layer between the second substrate and the third substrate, and removing the portion of the second structure and forming the second surface of the second substrate includes removing the bonding layer.

25. The method of claim 24, wherein the second structure further includes an etch stop layer located between the bonding layer and the second substrate, and removing the portion of the second structure to form the second surface of the second substrate includes removing the bonding layer to expose the etch stop layer.

26. The method as claimed in claim 1, wherein each of the first metal bonding layer and the second metal bonding layer comprises a metal, a conductive metal compound, or a metal alloy.

27. The method as claimed in claim 1, wherein each of the first metal bonding layer and the second metal bonding layer comprises a metal silicate or a metal nitride.

28. A semiconductor structure comprising: a wiring layer disposed in a first dielectric layer; a first contact structure disposed in the wiring layer; a second contact structure disposed in the wiring layer; a first vertical element disposed above and in contact with the first contact structure; a second vertical element disposed above and in contact with the second contact structure, the first vertical element and the second vertical element being at the same level; and a second dielectric layer disposed above the first dielectric layer, the second dielectric layer surrounding each of the first vertical element, the second vertical element, the first contact structure, and the second contact structure; wherein each of the first contact structure and the second contact structure includes a first metal layer, a second metal layer disposed above the first metal layer, and a metal bonding interface disposed between the first metal layer and the second metal layer, wherein each of the first contact structure and the second contact structure is formed by patterning a bonding metal layer.

29. The semiconductor structure as claimed in claim 28, wherein a height of the first vertical element is substantially equal to a height of the second vertical element.

30. The semiconductor structure as claimed in claim 28, wherein a height range of the first vertical element is between about 10 nanometers and about 300 nanometers.

31. The semiconductor structure as claimed in claim 28, wherein each of the first vertical element and the second vertical element is a vertical PN diode, a vertical Schottky diode, a vertical bipolar transistor, or a vertical field-effect transistor.

32. The semiconductor structure as claimed in claim 28, wherein the first vertical element and the second vertical element are arranged in the same direction.

33. The semiconductor structure as claimed in claim 28, wherein each of the first vertical element and the second vertical element comprises a single-crystal semiconductor material.

34. The semiconductor structure as described in claim 28 further includes a first memory cell located above the first vertical element.

35. The semiconductor structure as claimed in claim 34, wherein the first memory cell includes a magnetic tunneling junction (MTJ) structure, a phase change material, or a variable resistance material.

36. The semiconductor structure as claimed in claim 28, wherein the first metal layer and the second metal layer of the first contact structure are vertically aligned without misalignment, and the first metal layer and the second metal layer of the second contact structure are vertically aligned without misalignment.

37. The semiconductor structure as described in claim 28, wherein the wiring layer is electrically connected to a functional element.

38. The semiconductor structure as claimed in claim 28, wherein the second dielectric layer extends continuously from a topmost surface of the first dielectric layer without a bonding interface located between the first contact structure and the second contact structure and at substantially the same level as the metal bonding interface of the first contact structure and the second contact structure.

39. The semiconductor structure of claim 28, wherein the second dielectric layer is formed by depositing a dielectric material on the uppermost surface of the first dielectric layer, and the second dielectric layer is formed around the first metal layer and the second metal layer of the first contact structure and the second contact structure.

40. The semiconductor structure as claimed in claim 28, wherein the bonding metal layer is formed by bonding a first metal bonding layer and a second metal bonding layer.

41. A memory element, comprising: a first wiring layer located above a first substrate and electrically connected to a functional element in the first substrate; a first contact structure resting on the first wiring layer, the first contact structure including a first metal layer and a second metal layer located above the first metal layer and directly bonded to the first metal layer; a first vertical element located above the first contact structure and contacting the first contact structure at a first end; a first memory cell located above the first vertical element and having a first end and a second end, and the first vertical element being electrically connected from the second end of the first vertical element to the second end of the first memory cell; and a second wiring layer electrically connected to the first end of the first memory cell; wherein the first metal layer is in contact with the first wiring layer and the second metal layer is in contact with the first vertical element, wherein the first contact structure is formed by patterning a bonding metal layer.

42. The memory element as claimed in claim 41, wherein the width of the first metal layer is substantially equal to the width of the second metal layer.

43. The memory element as claimed in claim 41, wherein the width of the first vertical element is substantially equal to the width of the second metal layer.

44. The memory element as claimed in claim 41, wherein the first memory cell includes a magnetic tunneling junction (MTJ) structure, a phase change material, or a variable resistance material.

45. The memory element as claimed in claim 41, wherein the first vertical element is a vertical PN diode, a vertical Schottky diode, a vertical bipolar transistor, or a vertical field-effect transistor.

46. ​​The memory element as claimed in claim 41, wherein the first vertical element comprises a single-crystal semiconductor material.

47. The memory element as described in claim 41 further includes an alignment mark located on the first substrate.

48. The memory element as claimed in claim 41, wherein the second wiring layer is located above the first memory cell.

49. The memory element as claimed in claim 41 further comprises: a second contact structure resting on the first wiring layer, the second contact structure including a first metal layer and a second metal layer located above the first metal layer and directly bonded to the first metal layer; and a second vertical element located above the second contact structure and in contact with the second contact structure at a first end of the second vertical element.

50. The memory element as claimed in claim 49, wherein the first vertical element and the second vertical element are located at the same level.

51. The memory element as claimed in claim 49, wherein the first vertical element and the second vertical element are arranged in the same direction.

52. The memory element as claimed in claim 49, wherein the second vertical element is electrically connected from the first terminal of the second vertical element to the second terminal of the first memory cell.

53. The memory element as claimed in claim 49 further includes a second memory cell having a first end and a second end, wherein the second memory cell is located above the second vertical element, and the second vertical element is electrically connected to the second end of the second memory cell from a second end of the second vertical element.

54. The memory element as claimed in claim 49, wherein the first wiring layer includes a plurality of word lines extending in a first direction, the first contact structure resting on a first word line, and the second contact structure resting on a second word line.

55. The memory element as claimed in claim 49, wherein the first wiring layer includes a plurality of word lines extending in a first direction, and the first contact structure and the second contact structure both fall on a first word line.

56. The memory element as claimed in claim 54, wherein the second wiring layer includes a plurality of bit lines extending in a second direction different from the first direction, and the first terminal of the first memory cell is electrically connected to a first bit line.

57. The memory element as claimed in claim 41, further comprising: a second contact structure resting on the first wiring layer; a second vertical element located above the second contact structure and in contact with the second contact structure at a first end, the second vertical element being electrically connected from a second end of the second vertical element to the second end of the first memory cell; an electrode extending laterally from a first side of the first memory cell to a second side of the first memory cell, the electrode being in contact with the first memory cell at the second end of the first memory cell; a third contact structure; a third vertical element located above the third contact structure and in contact with the third contact structure at a first end; a fourth contact structure; and a fourth vertical element located above the fourth contact structure and in contact with the fourth contact structure at a first end; The first vertical element and the third vertical element are electrically connected to the electrode on the first side of the first memory cell, and the second vertical element and the fourth vertical element are electrically connected to the electrode on the second side of the first memory cell; and each of the second contact structure, the third contact structure and the fourth contact structure includes a first metal layer and a second metal layer above the first metal layer and directly bonded to the first metal layer.

58. The memory element as described in claim 57, wherein the first vertical element and the second vertical element are located at the same level.

59. The memory element as claimed in claim 57, wherein the third vertical element and the fourth vertical element are located at the same level.

60. The memory element as claimed in claim 57, wherein the third vertical element and the fourth vertical element are both located above the first vertical element.

61. The memory element as claimed in claim 57, wherein a height of the first vertical element is substantially equal to a height of the second vertical element.

62. The memory element as claimed in claim 57, wherein a height of the third vertical element is substantially equal to a height of the fourth vertical element.

63. The memory element as claimed in claim 57, wherein the first vertical element and the second vertical element are arranged in the same direction.

64. The memory element as claimed in claim 57, wherein the third vertical element and the fourth vertical element are arranged in the same direction.

65. The memory element as claimed in claim 57, wherein the first vertical element and the third vertical element are arranged in the same direction, and the second vertical element and the fourth vertical element are arranged in the same direction.

66. The memory element as claimed in claim 57 further includes a third wiring layer, the third vertical element being electrically connected to the third wiring layer from a second end of the third vertical element, and the fourth vertical element being electrically connected to the third wiring layer from a second end of the fourth vertical element.

67. The memory element as claimed in claim 57, wherein the memory element has a cell size of about 12 feature squares (F2).

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