Semiconductor device

Abstract

This invention provides a transistor using an oxide semiconductor with high conductivity characteristics. This invention provides a high-performance semiconductor device having a transistor capable of high-speed response and high-speed drive. The transistor includes an oxide semiconductor film having a channel formation region and a low-resistance region containing a metal element and a dopant. The channel formation region is located between the low-resistance regions along the channel length direction. In the transistor manufacturing method, a metal element is introduced by heat treatment while in contact with the film containing the metal element, and a dopant is introduced through the film containing the metal element by implantation, thereby forming a low-resistance region containing the metal element and the dopant.

Description

semiconductor devices The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Therefore, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. The technology of forming transistors (also known as thin-film transistors (TFTs)) using a semiconductor thin film formed on a substrate with an insulating surface has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. Transistors using oxide semiconductors are required to have higher electrical characteristics in order to be applied to semiconductor devices with higher functions. Technologies for forming low-resistance source and drain regions using an aluminum reaction method to achieve high electrical characteristics in transistors using oxide semiconductors have been reported (for example, see Non-Patent Document 1). [Non-Patent Document 1] N. Morosawa et al., SID 11 DIGEST pp. 479-482 When the conduction characteristics (eg, on-current and field-effect mobility) of a transistor using an oxide semiconductor are improved, high-speed response and high-speed driving can be achieved in the semiconductor device, thereby realizing a higher-performance semiconductor device. Therefore, one object of one embodiment of the present invention is to provide a transistor using an oxide semiconductor having high on-state characteristics. Another object of one embodiment of the present invention is to provide a high-performance semiconductor device having a transistor capable of high-speed response and high-speed driving. During the manufacturing process of a transistor having an oxide semiconductor film including a channel formation region, a low-resistance region is formed in the oxide semiconductor film. This low-resistance region includes a metal element introduced by heat treatment while in contact with a film containing the metal element, and a dopant introduced through the metal element film by implantation. The low-resistance region is formed sandwiching the channel formation region along the length of the channel. Examples of the film containing a metal element include a metal film, a metal oxide film, and a metal nitride film. As the metal element in the film containing a metal element, any one or more elements selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni) can be used. As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) containing any one or more of the above-mentioned metal elements can be used. In addition, a dopant such as phosphorus (P) or boron (B) can also be included in the film containing a metal element. By forming a film containing a metal element in contact with the oxide semiconductor film and performing a heat treatment while the film containing the metal element is in contact with the oxide semiconductor film, the metal element can be introduced from the film containing the metal element into the oxide semiconductor film. Preferably, the heat treatment is performed in an oxygen atmosphere. The heat treatment can also be performed under reduced pressure or in a nitrogen atmosphere. In addition, the heating temperature is set to be greater than 100°C and less than 700°C, preferably greater than 200°C and less than 400°C. In addition, by the heat treatment used to introduce the metal element from the film containing the metal element into the oxide semiconductor film, the film containing the metal element having conductivity is changed into a film containing the metal element having insulating properties. For example, by the heat treatment used to introduce the metal element from the metal film into the oxide semiconductor film, the metal film is changed into a metal oxide film or a metal nitride film. When the metal oxide film or the metal nitride film has insulating properties, it can be used as an insulating film. Dopants are impurities that change the conductivity of the oxide semiconductor film. As dopants, one or more elements selected from Group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used. The above-mentioned dopant may also be contained in a film containing a metal element. A dopant is introduced into the oxide semiconductor film by implantation through a film containing a metal element (a metal film, a metal oxide film, or a metal nitride film). Methods for introducing the dopant include ion implantation, ion doping, and plasma immersion ion implantation. In this case, a single ion of the dopant or ions of a hydride, fluoride, or chloride is preferably used. The dopant concentration in the low resistance region is preferably 5×10 18 atoms / cm 3 Above and 1×10 22 atoms / cm 3 the following. Furthermore, a heat treatment may be performed after the dopant introduction process, and this heat treatment may also serve as a heat treatment in the process of introducing the metal element from the film containing the metal element. Furthermore, in the manufacturing process, there is no restriction on the order of the process of introducing the metal element from the film containing the metal element by heat treatment and the process of introducing the dopant by implantation; either process can be performed first. Furthermore, the above processes can be performed multiple times. For example, when a metal film is used as a film containing a metal element, and heat treatment is performed in an oxygen atmosphere to introduce the metal element into the oxide semiconductor film, if a dopant is introduced before the heat treatment, the dopant penetrates the metal film, while if the dopant is introduced after the heat treatment, the dopant penetrates the metal oxide film. By having an oxide semiconductor film including a low-resistance region sandwiching a channel formation region in the channel length direction, the transistor has high conduction characteristics (eg, on-current and field-effect mobility) and is capable of high-speed operation and high-speed response. Therefore, by using this transistor with high electrical characteristics, a high-performance and high-reliability semiconductor device can be provided. One embodiment of the structure of the invention disclosed in this specification is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film including a channel formation region; forming a low-resistance region in the oxide semiconductor film, the low-resistance region having a resistance lower than that of the channel formation region and containing a metal element and a dopant, with the channel formation region sandwiched therebetween, the low-resistance region being formed by the following two processes: forming a film containing a metal element in contact with the oxide semiconductor film, and introducing the metal element from the film containing the metal element into the oxide semiconductor film by heat treatment while the oxide semiconductor film is in contact with the film containing the metal element; and introducing the dopant into the oxide semiconductor film through the film containing the metal element. One embodiment of the structure of the invention disclosed in this specification is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film including a channel formation region; selectively forming a stack of a gate insulating film and a gate electrode layer on the oxide semiconductor film so as to overlap with the channel formation region; forming a film containing a metal element on the oxide semiconductor film, the gate insulating film, and the gate electrode layer in contact with a portion of the oxide semiconductor film; using the gate insulating film and the gate electrode layer as a mask to selectively introduce a dopant into the oxide semiconductor film through the film containing the metal element; and heating the oxide semiconductor film into which the dopant is introduced and the film containing the metal element to introduce the metal element from the film containing the metal element into the oxide semiconductor film into which the dopant is introduced, thereby forming a low-resistance region containing the metal element and the dopant, the region being sandwiched between the channel formation region and having a resistance lower than that of the channel formation region, in the oxide semiconductor film. One embodiment of the structure of the invention disclosed in this specification is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film including a channel formation region; selectively forming a stack of a gate insulating film and a gate electrode layer on the oxide semiconductor film so as to overlap with the channel formation region; forming a film containing a metal element on the oxide semiconductor film, the gate insulating film, and the gate electrode layer in contact with a portion of the oxide semiconductor film; heating the oxide semiconductor film and the film containing the metal element to introduce the metal element from the film containing the metal element into the oxide semiconductor film; and using the gate insulating film and the gate electrode layer as a mask to selectively introduce a dopant into the oxide semiconductor film into which the metal element has been introduced through the film containing the metal element; and forming a low-resistance region in the oxide semiconductor film, which has a resistance lower than that of the channel formation region and contains the metal element and the dopant, with the channel formation region sandwiched therebetween. In the above structure, heat treatment (dehydration or dehydrogenation treatment) may be performed to release hydrogen or water from the oxide semiconductor film before the process of forming a film containing a metal element. Furthermore, dehydration or dehydrogenation may also cause oxygen in the main component material of the oxide semiconductor to be desorbed, thereby reducing the amount of oxygen. Oxygen vacancies exist in the oxide semiconductor film where oxygen is desorbed. These oxygen vacancies generate donor states that can cause changes in the electrical properties of the transistor. Therefore, it is preferable to supply oxygen to the oxide semiconductor film that has been subjected to a dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor film, oxygen vacancies in the film can be filled. For example, by providing an oxide insulating film containing a large amount (excess) of oxygen as an oxygen supply source in contact with the oxide semiconductor film, oxygen can be supplied from the oxide insulating film to the oxide semiconductor film. In the above structure, oxygen can also be supplied to the oxide semiconductor film by performing a heating process while the oxide semiconductor film subjected to the heating process is in contact with at least a portion of the oxide insulating film. Alternatively, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor film that has been subjected to a dehydration or dehydrogenation treatment to supply oxygen into the film. Examples of methods for introducing oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. Furthermore, it is preferable that the oxide semiconductor film provided in the transistor be a film in which the oxide semiconductor includes a region whose oxygen content exceeds the stoichiometric oxygen content of the oxide semiconductor in a crystalline state. In this case, the oxygen content exceeds the stoichiometric oxygen content of the oxide semiconductor. Alternatively, the oxygen content exceeds the oxygen content of a single crystal. Oxygen may exist between the crystal lattices of the oxide semiconductor. By removing hydrogen or water from the oxide semiconductor, the oxide semiconductor is purified to contain as few impurities as possible. By supplying oxygen to fill oxygen vacancies, a type I (intrinsic) oxide semiconductor or an oxide semiconductor that is infinitely close to type I (intrinsic) can be achieved. As a result, the Fermi level (Ef) of the oxide semiconductor can be made equal to the intrinsic Fermi level (Ei). Therefore, by using this oxide semiconductor film in a transistor, the deviation in the transistor's threshold voltage Vth and the drift of the threshold voltage ΔVth caused by oxygen vacancies can be reduced. By introducing a metal element from a film containing the metal element formed in contact with the oxide semiconductor film and introducing a dopant by implantation, a low-resistance region containing the metal element and the dopant is formed in the oxide semiconductor film. By having oxide semiconductor films containing the low-resistance regions sandwiching the channel formation region along the channel length, the transistor exhibits high on-state characteristics (e.g., on-state current and field-effect mobility) and is capable of high-speed operation and response. Therefore, by using this transistor with high electrical characteristics, a high-performance and high-reliability semiconductor device can be provided. 106: component isolation insulation layer 108: Gate insulating film 110: Gate electrode 116: Channel formation area 120: Impurity area 124: Metal compound area 128: Insulation film 130: Insulation film 140: Transistor 142a: source electrode or drain electrode 142b: Source electrode or drain electrode 144: Oxide semiconductor film 146: Gate insulating film 148: Gate electrode layer 150: Film containing metal elements 152: Insulation film 153:Electrode layer 156: Wiring 162: Transistor 164: Capacitor element 185:Substrate 400:Substrate 401: Gate electrode layer 402: Gate insulating film 403: Oxide semiconductor film 404a: low resistance area 404b: low resistance area 405a: Source electrode layer 405b: Drain electrode layer 406a: low resistance area 406b: low resistance area 406c: low resistance area 406d: low resistance area 407: Film containing metal elements 409: Channel formation area 410: Transistor 412a: sidewall insulating layer 412b: sidewall insulating layer 414a: low resistance area 414b: low resistance area 415: Planarization insulating film 416: Insulation film 426a: low resistance area 426b: low resistance area 417: Film containing metal elements 420a: Transistor 420b: Transistor 421: Dopant 427: Insulation film 436:Insulating film 440: Transistor 442: Gate insulating film 445: Transistor 450: Transistor 465a: Wiring layer 465b: Wiring layer 601:Substrate 602: Photodiode 606a: semiconductor film 606b: Semiconductor film 606c: Semiconductor film 608: Adhesive layer 613:Substrate 631: Insulating film 633: Interlayer insulating film 634: Interlayer insulating film 640: Transistor 641:Electrode layer 642:Electrode layer 643: conductive layer 645: conductive layer 656: Transistor 658: Photodiode reset signal line 659: Gate signal line 671: Photoelectric sensor output signal line 672: Photoelectric sensor reference signal line 2701: Shell 2703: Shell 2705: Display unit 2707: Display unit 2711: shaft 2721: Power Supply 2723: Operation keys 2725: Speaker 2800: Shell 2801: Shell 2802: Display Panel 2803: Speaker 2804: Microphone 2805: Operation keys 2806:Pointing device 2807: Image shooting lens 2808: External connection terminal 2810:Solar cell 2811: External storage tank 3001: Subject 3002: Shell 3003: Display unit 3004:Keyboard 3021: Main Body 3022:Stylus 3023: Display unit 3024: Operation button 3025: External interface 3051: Main body 3053:Viewfinder 3054: Operation switch 3056:Battery 4001: first substrate 4002: Pixel unit 4003:Signal line driver circuit 4004: Scan line driver circuit 4005: Sealing material 4006: Second substrate 4008: Liquid crystal layer 4010: Transistor 4011: Transistor 4013: Liquid crystal element 4015:Connecting terminal electrode 4016:Terminal electrode 4018:FPC 4019: Anisotropic conductive film 4020:Insulating film 4021:Insulating film 4023:Insulating film 4030: first electrode layer 4031: Second electrode layer 4032:Insulating film 4033:Insulating film 4510: Partition wall 4511:Electroluminescent layer 4513: Light-emitting element 4514:Filling material 9601: Housing 9603: Display unit 9605: Bracket In the diagram: 1A to 1F are diagrams illustrating one embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 2A to 2D are diagrams illustrating one embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 3A to 3F are diagrams illustrating one embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 4A to 4F are diagrams illustrating one embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 5A to 5D are diagrams illustrating one embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 6A to 6D are diagrams illustrating one embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 7A and 7B are diagrams illustrating one embodiment of a semiconductor device; 8A to 8F are diagrams illustrating one embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 9A to 9C are diagrams illustrating one embodiment of a semiconductor device; 10A and 10B are diagrams illustrating one embodiment of a semiconductor device; 11A and 11B are diagrams illustrating one embodiment of a semiconductor device; 12A to 12C are diagrams illustrating one embodiment of a semiconductor device; 13A to 13F are diagrams illustrating an electronic device. Below, the embodiments of the invention disclosed in this specification are described in detail with reference to the drawings. However, a person skilled in the art can easily understand that the methods and details of the invention disclosed in this specification can be transformed into various forms and are not limited to the following description. Moreover, the invention disclosed in this specification should not be regarded as limited to the description of the following embodiments. In addition, for the sake of convenience, ordinal numbers such as first and second are added, which do not indicate the order of the process or the order of stacking. In addition, the ordinal numbers in this specification do not represent the inherent names of the matters of a specific invention. Implementation Method 1 In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device is described with reference to Figures 1A to 1F. In this embodiment, a transistor including an oxide semiconductor film is described as an example of a semiconductor device. There are no particular limitations on the transistor structure; for example, a top-gate or bottom-gate structure, a staggered or planar structure, etc., can be used. Furthermore, the transistor can have a single-gate structure with a single channel formation region, a dual-gate structure with two channel formation regions, or a triple-gate structure with three channel formation regions. Alternatively, a dual-gate structure with two gate electrode layers disposed above and below the channel formation region with a gate insulating film interposed therebetween is also possible. The transistor 440 shown in FIG. 1A to FIG. 1F is an example of a transistor with a top gate structure. As shown in FIG1F , transistor 440 includes a channel formation region 409, low-resistance regions 404a and 404b, an oxide semiconductor film 403 including low-resistance regions 406a and 406b, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating film 402, and a gate electrode layer 401 on a substrate 400 having an insulating surface provided with an insulating film 436. A film 407 containing a metal element is formed on transistor 440. 1A to 1F illustrate an example of a method for manufacturing the transistor 440 . First, an insulating film 436 is formed on a substrate 400 having an insulating surface. There are no particular limitations on the substrate that can be used as substrate 400 having an insulating surface; however, substrate 400 must have heat resistance sufficient to withstand the subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminum borosilicate glass, ceramic substrates, quartz substrates, and sapphire substrates can be used. Alternatively, single crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates made of silicon germanium, and SOI substrates can be used as substrate 400, and semiconductor elements can be provided on these substrates. Furthermore, a semiconductor device can be manufactured using a flexible substrate as the substrate 400. When manufacturing a flexible semiconductor device, the transistor 440 including the oxide semiconductor film 403 can be formed directly on the flexible substrate, or the transistor 440 including the oxide semiconductor film 403 can be formed on another manufacturing substrate and then peeled off from the manufacturing substrate and transferred to the flexible substrate. Furthermore, in order to peel off from the manufacturing substrate and transfer to the flexible substrate, a peeling layer is preferably provided between the manufacturing substrate and the transistor including the oxide semiconductor film. The insulating film 436 can be formed using silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, or a mixed material thereof by a plasma CVD method or a sputtering method. The insulating film 436 may be a single layer or a stacked layer, and an oxide insulating film is preferably used as a film in contact with the oxide semiconductor film 403. In this embodiment, a silicon oxide film formed by a sputtering method is used as the insulating film 436. Next, the oxide semiconductor film 403 is formed over the insulating film 436 . Since the insulating film 436 is in contact with the oxide semiconductor film 403, it is preferable that at least an amount of oxygen exceeding the stoichiometric composition ratio is present in the film (in the bulk). For example, when a silicon oxide film is used as the insulating film 436, SiO 2+α(Note that α > 0). By using such an insulating film 436, oxygen can be supplied to the oxide semiconductor film 403, thereby improving the characteristics. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be filled. For example, by providing an insulating film 436 containing a large amount (excess) of oxygen as an oxygen supply source in contact with the oxide semiconductor film 403, oxygen can be supplied from the insulating film 436 to the oxide semiconductor film 403. Alternatively, oxygen can be supplied to the oxide semiconductor film 403 by performing heat treatment while the oxide semiconductor film 403 is in contact with a portion of the insulating film 436. In the process of forming the oxide semiconductor film 403, in order to minimize the inclusion of hydrogen and water in the oxide semiconductor film 403, it is preferable to preheat the substrate on which the insulating film 436 is formed in a preheating chamber of a sputtering apparatus as a pretreatment for forming the oxide semiconductor film 403. This desorbs and discharges impurities such as hydrogen and water adhering to the substrate and the insulating film 436. Furthermore, a cryopump is preferably used as an exhaust unit provided in the preheating chamber. The oxide semiconductor used as the oxide semiconductor film 403 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferably In and Zn. In addition, in addition to the above elements, it is preferably gallium (Ga) as a stabilizer (stabilizer), which is used to reduce the electrical characteristic deviation of the transistor using the oxide. In addition, tin (Sn) is preferably used as a stabilizer. In addition, hafnium (Hf) is preferably used as a stabilizer. In addition, aluminum (Al) is preferably used as a stabilizer. In addition, as other stabilizers, any one or more of the lanthanide elements lanthanum (La), cerium (Ce), protozollum (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), zirconium (Tb), dysprosium (Dy), thulium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) can be included. For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide; binary metal oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and In-Ga oxides; ternary metal oxides such as In-Ga-Zn oxides (also called IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, and Sn-Al-Zn oxides can be used. n-type oxides, In-Hf-Zn-type oxides, In-La-Zn-type oxides, In-Ce-Zn-type oxides, In-Pr-Zn-type oxides, In-Nd-Zn-type oxides, In-Sm-Zn-type oxides, In-Eu-Zn-type oxides, In-Gd-Zn-type oxides, In-Tb-Zn-type oxides, In-Dy-Zn-type oxides, In-Ho-Zn-type oxides, In-Er-Zn-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn-type oxides, In-Lu-Zn-type oxides; quaternary metal oxides of In-Sn-Ga-Zn-type oxides, In-Hf-Ga-Zn-type oxides, In-Al-Ga-Zn-type oxides, In-Sn-Al-Zn-type oxides, In-Sn-Hf-Zn-type oxides, In-Hf-Al-Zn-type oxides. Note that, for example, an In-Ga-Zn oxide refers to an oxide containing In, Ga, and Zn as main components, and there is no limitation on the ratio of In, Ga, and Zn. Furthermore, metal elements other than In, Ga, and Zn may also be contained. In addition, as an oxide semiconductor, InMO 3(ZnO) m (m>0, and m is not an integer). Here, M represents one or more metal elements selected from Ga, Fe, Mn and Co. In addition, as an oxide semiconductor, a material composed of In can also be used. 2SnO 5(ZnO) n (n>0, and n is an integer) represented by the material. For example, an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:Ga:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) or an oxide having a composition close thereto may be used. Alternatively, an In-Sn-Zn oxide having an atomic ratio of In:Sn:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3 (=1 / 3:1 / 6:1 / 2), or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) or an oxide having a composition close thereto may be used. However, the materials are not limited to the above ones, and materials of appropriate composition can be used depending on the required semiconductor characteristics (mobility, threshold value, deviation, etc.). In addition, in order to obtain the required semiconductor characteristics, it is preferable to appropriately set conditions such as carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bonding distance, density, etc. For example, using In-Sn-Zn oxides can easily achieve higher mobility, but using In-Ga-Zn oxides can also improve mobility by reducing the defect density within the bulk. Here, for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c (a+b+c=1) is close to the composition of an oxide in which the atomic ratio is In:Ga:Zn=A:B:C (A+B+C=1) means that a, b, and c satisfy the following formula: (aA) 2 +(bB) 2 +(cC) 2 r 2 r can be, for example, 0.05. The same applies to other oxides. The oxide semiconductor may be either single crystal or non-single crystal. In the latter case, it may be amorphous or polycrystalline. In addition, a structure in which amorphous material contains a crystalline portion or a non-amorphous structure may be used. An amorphous oxide semiconductor can more easily form a flat surface. Therefore, when a transistor is formed using the amorphous oxide semiconductor, interface scattering can be reduced and higher mobility can be more easily achieved. Furthermore, a crystalline oxide semiconductor can further reduce defects within the bulk and, by improving surface flatness, achieve a mobility exceeding that of an amorphous oxide semiconductor. To improve surface flatness, the oxide semiconductor is preferably formed on a flat surface. Specifically, the oxide semiconductor is formed on a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. Note that Ra is the centerline average roughness defined in JIS B0601 expanded three-dimensionally to enable its application to surfaces. It can be expressed as "the value obtained by averaging the absolute values ​​of deviations from a reference surface to a specified surface" and is defined by the following formula. Note that in the above formula, S 0 represents the measuring surface (by coordinates (x 1,y 1)(x 1,y 2)(x 2,y 1)(x 2,y 2) The area of ​​the quadrilateral represented by the four points, Z 0 represents the average height of the measurement surface. Ra can be evaluated using an atomic force microscope (AFM). Therefore, a planarization process may also be performed on a region of the insulating film 436 that is formed in contact with the oxide semiconductor film 403. The planarization process is not particularly limited, and polishing (for example, chemical mechanical polishing (CMP)), dry etching, and plasma treatment can be used as the planarization process. As a plasma treatment, for example, reverse sputtering can be performed, in which argon gas is introduced to generate plasma. Reverse sputtering is a method of applying a voltage to one side of the substrate in an argon atmosphere using an RF power supply to generate plasma near the substrate for surface modification. Alternatively, nitrogen, helium, oxygen, or the like can be used instead of the argon atmosphere. Reverse sputtering can remove powdery substances (also called particles or dust) adhering to the surface of the insulating film 436. As the planarization process, polishing, dry etching, and plasma treatment may be performed multiple times, or they may be combined. Furthermore, when these are combined, there is no particular limitation on the order of the processes, and they may be appropriately set according to the concave-convex state of the surface of the insulating film 436. An oxide semiconductor film containing crystals and having crystallinity (a crystalline oxide semiconductor film) can be used as the oxide semiconductor film 403. The crystal state of the crystalline oxide semiconductor film may be a state in which the directions of the crystal axes are disordered or a state in which the directions have a certain orientation. For example, a crystalline oxide semiconductor film having a crystal c-axis substantially perpendicular to the surface can be used as the crystalline oxide semiconductor film. An oxide semiconductor layer including crystals having a c-axis substantially perpendicular to the surface (hereinafter also referred to as a crystalline oxide semiconductor layer) has a structure that is neither a single crystal structure nor an amorphous structure, and includes an oxide containing crystals having a c-axis orientation (C Axis Aligned Crystal: also referred to as CAAC). CAAC-OS refers to an oxide semiconductor including the following crystals: the crystals are c-axis aligned and have a triangular or hexagonal atomic arrangement when viewed from the ab plane, surface or interface, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers on the c-axis, and the direction of the a-axis or b-axis on the ab plane (or surface or interface) is different (rotated around the c-axis). In a broader sense, CAAC-OS refers to non-single crystal and refers to a material including the following phase, in which the atomic arrangement is triangular, hexagonal, equilateral triangle or regular hexagonal when viewed in the direction perpendicular to its ab plane, and the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers when viewed in the direction perpendicular to the c-axis. Although CAAC-OS is not a single crystal, it is not formed solely of amorphous materials. In addition, although CAAC-OS includes crystallized portions (crystalline portions), the boundaries between one crystalline portion and another crystalline portion may not be clearly distinguished. Alternatively, nitrogen may be substituted for a portion of the oxygen atoms constituting CAAC-OS. Furthermore, the c-axis of each crystalline portion constituting CAAC-OS may be aligned in direction (e.g., perpendicular to the substrate plane, surface, film surface, or interface forming the CAAC-OS). Alternatively, the normal to the ab plane of each crystalline portion constituting CAAC-OS may be oriented in a fixed direction (e.g., perpendicular to the substrate plane, surface, film surface, or interface). By using this crystalline oxide semiconductor film, changes in the electrical characteristics of the transistor caused by irradiation with visible light or ultraviolet light can be further suppressed, thereby enabling the manufacture of a highly reliable semiconductor device. Three methods can be cited as methods for obtaining a crystalline oxide semiconductor film having a c-axis orientation. The first method is to set the film formation temperature to be greater than 200°C and less than 500°C to form an oxide semiconductor film with a c-axis orientation approximately perpendicular to the surface. The second method is to form a thin oxide semiconductor film and then perform a heat treatment at a temperature of greater than 200°C and less than 700°C to form a c-axis orientation approximately perpendicular to the surface. The third method is to form a thin first layer and then perform a heat treatment at a temperature of greater than 200°C and less than 700°C to form a second layer with a c-axis orientation approximately perpendicular to the surface. The thickness of the oxide semiconductor film 403 is set to be greater than or equal to 1 nm and less than or equal to 200 nm (preferably greater than or equal to 5 nm and less than or equal to 30 nm). Sputtering, MBE (Molecular Beam Epitaxy), CVD, pulsed laser deposition, ALD (Atomic Layer Deposition), or the like can be used as appropriate. Alternatively, the oxide semiconductor film 403 can be formed using a sputtering apparatus that forms films with multiple substrate surfaces arranged approximately perpendicular to a sputtering target surface, a so-called CP sputtering apparatus (Columnar Plasma Sputtering System). In addition, it is preferable to form the film under conditions that contain a large amount of oxygen during film formation (for example, forming the film by sputtering in an atmosphere of 100% oxygen, etc.), so that the oxide semiconductor film 403 is a film containing a large amount of oxygen (preferably including a region with an excess oxygen content compared to the stoichiometric composition ratio when the oxide semiconductor is in a crystalline state). As a target for forming the oxide semiconductor film 403 by a sputtering method, for example, a target having a composition ratio of In 2O 3: Ga 2O 3: ZnO = 1:1:2 [molar ratio] oxide target, to form In-Ga-Zn film. In addition, not limited to the above target material and composition, for example, can also be used with a composition ratio of In 2O 3: Ga 2O 3: Metal oxide target with ZnO=1:1:1 [molar ratio]. Furthermore, the filling rate of the metal oxide target is 90% to 100%, preferably 95% to 99.9%. Using a metal oxide target with a high filling rate allows the formation of a dense oxide semiconductor film. As a sputtering gas used when forming the oxide semiconductor film, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, and hydrides have been removed is preferably used. The substrate is maintained in a deposition chamber maintained in a reduced pressure state. Then, a sputtering gas from which hydrogen and water have been removed is introduced while removing the residual water in the deposition chamber, and an oxide semiconductor film 403 is formed on the substrate 400 using the above-mentioned target material. In order to remove the residual water in the deposition chamber, it is preferable to use an adsorption type vacuum pump, such as a cryopump, an ion pump, or a titanium sublimation pump. In addition, a turbo pump with a cold trap added can also be used as an exhaust unit. Because in a deposition chamber that uses a cryopump for exhaust, for example, hydrogen atoms, water (H 2O) or the like (more preferably, a compound containing a carbon atom) is exhausted, so that the concentration of impurities contained in the oxide semiconductor film 403 formed in the deposition chamber can be reduced. The insulating film 436 and the oxide semiconductor film 403 are preferably formed successively without being exposed to the air. By forming the insulating film 436 and the oxide semiconductor film 403 successively without being exposed to the air, impurities such as hydrogen and moisture can be prevented from adhering to the surface of the insulating film 436. Alternatively, the oxide semiconductor film 403 may be subjected to a heat treatment for removing excess hydrogen (including water or hydroxyl groups) (dehydration or dehydrogenation). The heat treatment temperature is set to 300° C. or higher and 700° C. or lower than the strain point of the substrate. The heat treatment may be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate is introduced into an electric furnace in one of the heat treatment apparatuses, and the oxide semiconductor film is heat treated at 450° C. for one hour in a nitrogen atmosphere. In addition, the heat treatment device is not limited to an electric furnace, and a device that heats the object to be treated by heat conduction or heat radiation generated by a heating element such as a resistance heating element may also be used. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device may be used. The LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that uses a high-temperature gas for heat treatment. As the high-temperature gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated due to the heat treatment is used. For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650° C. to 700° C., and after heating for several minutes, the substrate is taken out of the inert gas. In addition, heat treatment for dehydration or dehydrogenation can be performed at any time in the manufacturing process of the transistor 440 as long as it is after forming the oxide semiconductor film 403, before forming a film containing a metal element, and before the process of introducing oxygen into the oxide semiconductor film 403. It is preferable to perform heat treatment for dehydration or dehydrogenation before processing the oxide semiconductor film into an island shape because release of oxygen contained in the insulating film 436 due to the heat treatment can be prevented. Furthermore, during the heat treatment, nitrogen or a rare gas such as helium, neon, or argon preferably does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is preferably set to 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher (i.e., the impurity concentration is set to 1 ppm or lower, more preferably 0.1 ppm or lower). In addition, after the oxide semiconductor film 403 is heated by heat treatment, high-purity oxygen gas, high-purity nitrous oxide gas or ultra-dry air (the moisture content when measured by a dew point meter using CRDS (cavity ring-down laser spectroscopy) is 20 ppm or less (dew point conversion, -55°C), preferably 1 ppm or less, and more preferably 10 ppb or less of air) can be introduced into the same furnace. The oxygen gas or nitrous oxide gas preferably does not contain water, hydrogen, etc. Alternatively, it is preferable to set the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device to 6N or more, preferably to 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide gas is set to 1 ppm or less, preferably to 0.1 ppm or less). By supplying oxygen, which is a main component material of the oxide semiconductor and is reduced during the impurity removal process by dehydration or dehydrogenation treatment, using oxygen or nitrous oxide gas, the oxide semiconductor film 403 can be highly purified and electrically made I-type (intrinsic). The oxide semiconductor film may be processed into an island shape or may remain in a film shape without being processed. In addition, an element isolation region composed of an insulating film may be provided to isolate the oxide semiconductor film from each element. In this embodiment, the formed oxide semiconductor film is processed by photolithography to form the island-shaped oxide semiconductor film 403. Alternatively, a photoresist mask for forming the island-shaped oxide semiconductor film 403 can be formed by an inkjet method. When forming the photoresist mask by an inkjet method, a photomask is not required, thereby reducing manufacturing costs. The oxide semiconductor film can be etched using either dry etching or wet etching, or both. For example, a solution containing a mixture of phosphoric acid, acetic acid, and nitric acid can be used as an etchant for wet etching of the oxide semiconductor film. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. Next, a conductive film serving as a source electrode layer and a drain electrode layer (including wiring formed on the same layer as them) is formed on the oxide semiconductor film 403. As the conductive film, a material that can withstand subsequent heat treatment is used. As a conductive film for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements can be used. In addition, a structure can be adopted in which a high-melting-point metal film such as Ti, Mo, or W or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) is stacked on one or both of the lower and upper sides of the metal film of Al, Cu, etc. In addition, a conductive metal oxide can also be used as a conductive film for the source electrode layer and the drain electrode layer. As a conductive metal oxide, indium oxide (In2O3) can be used. 2O 3) Tin oxide (SnO 2) Zinc oxide (ZnO), indium oxide, tin oxide (In 2O 3-SnO 2) Indium oxide zinc oxide (In 2O 3-ZnO) or materials in which their metal oxide materials contain silicon oxide. A photoresist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b. The photoresist mask is then removed. In this embodiment, a tungsten film having a thickness of 10 nm is formed as the source electrode layer 405a and the drain electrode layer 405b. In this manner, when the thickness of the source electrode layer 405a and the drain electrode layer 405b is thin, not only does the gate insulating film 442 formed thereon have excellent coverage, but dopants can also be introduced into the oxide semiconductor film 403 below the source electrode layer 405a and the drain electrode layer 405b through the source electrode layer 405a and the drain electrode layer 405b. Next, a gate insulating film 442 is formed to cover the oxide semiconductor film 403 , the source electrode layer 405 a , and the drain electrode layer 405 b (see FIG. 1A ). Furthermore, the surfaces of the oxide semiconductor film 403, the source electrode layer 405a, and the drain electrode layer 405b may be subjected to the above-mentioned planarization treatment to improve coverage of the gate insulating film 442. In particular, when a thin insulating film is used as the gate insulating film 442, it is preferable that the surfaces of the oxide semiconductor film 403, the source electrode layer 405a, and the drain electrode layer 405b have excellent planarity. The thickness of the gate insulating film 442 is set to be not less than 1 nm and not more than 100 nm, and can be appropriately formed using a sputtering method, MBE method, CVD method, pulsed laser deposition method, ALD method, or the like. Alternatively, the gate insulating film 442 can be formed using a sputtering apparatus that performs film formation while multiple substrate surfaces are arranged approximately perpendicular to the sputtering target surface, namely a so-called CP sputtering apparatus. The gate insulating film 442 can be formed using a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film. It is preferable that the gate insulating film 442 also contains oxygen in a portion in contact with the oxide semiconductor film 403. In particular, the gate insulating film 442 preferably contains at least an amount of oxygen exceeding the stoichiometric composition ratio in its film (in the bulk). For example, when a silicon oxide film is used as the gate insulating film 442, SiO 2+α (Note that α>0). In this embodiment, SiO 2+α A silicon oxide film (note: α > 0) is used as the gate insulating film 442. Using this silicon oxide film as the gate insulating film 442 allows oxygen to be supplied to the oxide semiconductor film 403, thereby improving characteristics. Furthermore, the gate insulating film 442 is preferably formed in consideration of the size of the transistor being manufactured and the step coverage of the gate insulating film 442. In addition, by using hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y(x>0, y>0)) and high-k materials such as lanthanum oxide can reduce the gate-drain current. Moreover, the gate insulating film 442 can have a single-layer structure or a stacked-layer structure. Next, a gate electrode layer 401 is formed on the gate insulating film 442 by plasma CVD or sputtering. The gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material primarily composed of one of these metals. Alternatively, a semiconductor film, typically a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide can be used as the gate electrode layer 401. The gate electrode layer 401 can have either a single-layer structure or a stacked-layer structure. Alternatively, the gate electrode layer 401 may be made of a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon oxide. Furthermore, a stacked structure of the above conductive materials and the above metal materials may be employed. Furthermore, as a layer of the gate electrode layer 401 in contact with the gate insulating film 442, a metal oxide film containing nitrogen can be used. Specifically, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, a Sn-O film containing nitrogen, an In-O film containing nitrogen, and a metal nitride film (such as InN and SnN) can be used. When these films have a work function of 5 eV, preferably 5.5 eV or higher, and are used as the gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, thereby realizing a so-called normally-off switching element. Next, the gate insulating film 442 is etched using the gate electrode layer 401 as a mask to expose a portion of the oxide semiconductor film 403 , thereby forming the gate insulating film 402 (see FIG. 1B ). Next, a film 417 containing a metal element is formed over the oxide semiconductor film 403 , the source electrode layer 405 a , the drain electrode layer 405 b , the gate insulating film 402 , and the gate electrode layer 401 in contact with a portion of the oxide semiconductor film 403 (see FIG. 1C ). Examples of the film 417 containing a metal element include a metal film, a metal oxide film, and a metal nitride film. As the metal element in the film containing a metal element, one or more selected from aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni) can be used. As the film containing a metal element, a metal film, a metal oxide film, or a metal nitride film (for example, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) containing one or more selected from the above metal elements can be used. In addition, a dopant such as phosphorus (P) or boron (B) can be included in the film containing a metal element. In this embodiment, the film 417 containing a metal element has conductivity. The film 417 containing a metal element can be formed by plasma CVD, sputtering, vapor deposition, etc. The thickness of the film 417 containing a metal element can be set to be greater than or equal to 5 nm and less than or equal to 30 nm. In this embodiment, a 10 nm-thick aluminum film is formed as the film 417 containing a metal element by a sputtering method. Next, using the gate insulating film 402 and the gate electrode layer 401 as masks, a dopant 421 is selectively introduced into the oxide semiconductor film 403 through the film 417 containing a metal element, the source electrode layer 405a, and the drain electrode layer 405b, thereby forming low resistance regions 414a and 414b (see FIG. 1D ). In this embodiment, since the source electrode layer 405a and the drain electrode layer 405b are formed as thin films, an example is shown in which the dopant 421 is also introduced into the oxide semiconductor film below the source electrode layer 405a and the drain electrode layer 405b, thereby forming low-resistance regions 414a and 414b. Depending on the thickness of the source electrode layer 405a and the drain electrode layer 405b or the conditions for introducing the dopant 421, the dopant 421 may not be introduced into the oxide semiconductor film 403 below the source electrode layer 405a and the drain electrode layer 405b. Alternatively, even if the dopant 421 is introduced, the concentration is low, resulting in the oxide semiconductor film 403 below the source electrode layer 405a and the drain electrode layer 405b having a higher resistance than the low-resistance region other than below the source electrode layer 405a and the drain electrode layer 405b. The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor film 403. As the dopant 421, one or more elements selected from Group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used. The above-mentioned dopant may be contained in the film 417 containing a metal element. The dopant 421 is introduced into the oxide semiconductor film 403 by an implantation method through the film 417 containing the metal element, the source electrode layer 405a, and the drain electrode layer 405b. Ion implantation, ion doping, plasma immersion ion implantation, or the like can be used as a method for introducing the dopant 421. In this case, a single ion or ions of hydride, fluoride, or chloride of the dopant 421 are preferably used. The introduction process of the dopant 421 can be controlled by appropriately setting the introduction conditions such as the acceleration voltage and the dose or by allowing the dopant to penetrate the thickness of the film 417 containing the metal element. For example, when boron ions are implanted by ion implantation, the acceleration voltage is 15 kV and the dose is 1×10 15 ions / cm 2 The preferred dosage is 1×10 13 ions / cm 2 Above and 5×10 16 ions / cm 2 the following. The concentration of the dopant 421 in the low resistance region is preferably 5×10 18 atoms / cm 3 Above and 1×10 22 atoms / cm 3 the following. The substrate 400 may also be heated while the dopant is being introduced. Alternatively, the process of introducing the dopant 421 into the oxide semiconductor film 403 may be performed a plurality of times, or a plurality of dopants may be used. After the dopant 421 is introduced, a heat treatment may be performed. Preferred heating conditions include a temperature of 300°C to 700°C, preferably 300°C to 450°C, in an oxygen atmosphere for one hour. Alternatively, the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in air (super dry air). When a crystalline oxide semiconductor film is used as the oxide semiconductor film 403, amorphization may occur in part of the oxide semiconductor film due to the introduction of the dopant 421. In this case, the crystallinity of the oxide semiconductor film 403 can be restored by performing heat treatment after the introduction of the dopant 421. Next, heat treatment is performed while the film 417 containing the metal element is in contact with a portion of the oxide semiconductor film 403. Heat treatment is preferably performed in an oxygen atmosphere. Heat treatment can also be performed under reduced pressure or in a nitrogen atmosphere. The heating temperature is set to 100° C. to 700° C., preferably 200° C. to 400° C. For example, the substrate is placed in an electric furnace, which is one of heat treatment apparatuses, and the film 417 containing a metal element and the oxide semiconductor film 403 are heat treated at 300° C. for one hour in an oxygen atmosphere. In addition, the heating treatment device is not limited to an electric furnace, and a device that heats the object to be treated by heat conduction or heat radiation generated by a heating element such as a resistance heating element may also be used. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device may be used. The LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that uses a high-temperature gas for heat treatment. As the high-temperature gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated due to the heat treatment is used. For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650° C. to 700° C., and after heating for several minutes, the substrate is taken out of the inert gas. Heat treatment can be performed under nitrogen, oxygen, ultra-dry air (water content is less than 20 ppm, preferably less than 1 ppm, more preferably less than 10 ppb) or rare gas (argon, helium, etc.) atmosphere. However, the atmosphere of the above-mentioned nitrogen, oxygen, ultra-dry air, rare gas, etc. preferably does not contain water, hydrogen, etc. In addition, it is preferred that the purity of the nitrogen, oxygen or rare gas introduced into the heat treatment device is set to 6N (99.9999%) or more, preferably to 7N (99.99999%) or more (that is, the impurity concentration is set to less than 1 ppm, preferably less than 0.1 ppm). By performing the heat treatment, the metal element is introduced from the film 417 containing the metal element into the oxide semiconductor film 403, thereby forming low-resistance regions 404a and 404b. Consequently, in the oxide semiconductor film 403, low-resistance regions 404a and 404b containing a dopant and a metal element, and low-resistance regions 406a and 406b containing a dopant are formed, sandwiching the channel formation region 409. The resistance of the low-resistance regions 404a and 404b containing a dopant and a metal element can be made lower than the resistance of the low-resistance regions 406a and 406b containing a dopant. In this embodiment, boron is used as a dopant and aluminum is used as a metal element. Therefore, the low-resistance regions 404 a and 404 b contain boron and aluminum, and the low-resistance regions 406 a and 406 b contain boron. Furthermore, by heat treatment for introducing the metal element from the film containing the metal element 417 into the oxide semiconductor film 403, the film containing the metal element 417 becomes the film containing the metal element 407. For example, the metal film used for the film containing the metal element 417 becomes a metal oxide insulating film as the film containing the metal element 407. Such a metal oxide film can be used as an insulating film. In this embodiment, since an aluminum film is used as the film containing the metal element 417, the heat treatment converts the film into an aluminum oxide film. Since the aluminum oxide film is a metal oxide insulating film, it can be used as an insulating film. The above-described process can be used to manufacture the transistor 440 of this embodiment (see FIG. 1E ). By having the oxide semiconductor film 403 including the low-resistance regions 404 a and 404 b and the low-resistance regions 406 a and 406 b sandwiching the channel formation region 409 in the channel length direction, the transistor 440 has high on-state characteristics (e.g., on-state current and field-effect mobility) and is capable of high-speed operation and response. The low-resistance regions 404a, 404b and the low-resistance regions 406a, 406b can be used as source regions or drain regions. Providing the low-resistance regions 404a, 404b can mitigate the electric field applied to the channel formation region 409 formed between the low-resistance regions 404a, 404b. Furthermore, by electrically connecting the oxide semiconductor film 403 to the source electrode layer 405a and the drain electrode layer 405b at the low-resistance regions 406a, 406b, the contact resistance between the oxide semiconductor film 403 and the source electrode layer 405a and the drain electrode layer 405b can be reduced. Another insulating film may be stacked over the film 407 containing a metal element, which is a metal oxide insulating film. Alternatively, the film 407 containing a metal element may be removed. For example, when the film 407 containing a metal element has conductivity, the film 407 containing a metal element may be removed and another insulating film 416 may be formed as shown in FIG. 6A to FIG. 6D . FIG6A corresponds to FIG1E , and a film 407 containing a metal element is formed to cover the transistor 440. When the film 407 containing a metal element has insulating properties, it can be used as an insulating film. However, when it has conductive properties or when another insulating film is to be provided, the film 407 containing a metal element is removed (see FIG6B ). Next, an insulating film 416 is formed to cover the transistor 440 (see FIG. 6C ). The insulating film 416 is preferably formed by a method such as sputtering that does not introduce impurities such as water and hydrogen into the insulating film 416. Furthermore, it is preferable to use a film containing excess oxygen as the insulating film 416 because the film can serve as an oxygen supply source for the oxide semiconductor film 403. In this embodiment, a 100 nm-thick silicon oxide film is formed by sputtering as the insulating film 416. The silicon oxide film can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. As with the formation of the oxide semiconductor film, an adsorption-type vacuum pump (such as a cryopump) is preferably used to remove moisture remaining in the deposition chamber for the insulating film 416. This can reduce the concentration of impurities contained in the insulating film 416 formed in the deposition chamber evacuated using the cryopump. Alternatively, a turbomolecular pump equipped with a cold trap can be used as an exhaust unit for removing moisture remaining in the deposition chamber for the insulating film 416. As a sputtering gas used when forming the insulating film 416, a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed is preferably used. When stacking the insulating film 416, in addition to the silicon oxide film, an inorganic insulating film such as an aluminum oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can typically be used. For example, a stack of silicon oxide and aluminum oxide films can be used as the insulating film 416. The aluminum oxide film that can be used for the film 407 containing a metal element or the insulating film 416 provided over the oxide semiconductor film 403 has a high blocking effect (barrier effect), that is, an effect of preventing both impurities such as hydrogen and moisture and oxygen from passing through the film. Therefore, the aluminum oxide film serves as a protective film to prevent impurities such as hydrogen and moisture, which may cause variations during and after the manufacturing process, from being mixed into the oxide semiconductor film 403, and to prevent oxygen, which is a main component material of the oxide semiconductor, from being released from the oxide semiconductor film 403. A planarizing insulating film can also be formed to reduce surface irregularities caused by the transistor. Organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used as the planarizing insulating film. In addition to these organic materials, low-k dielectric materials (low-k materials) can also be used. Alternatively, a planarizing insulating film can be formed by stacking multiple insulating films made of these materials. In this embodiment, a planarization insulating film 415 is formed on the film 407 containing a metal element or the insulating film 416. Furthermore, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the film 407 containing a metal element or the insulating film 416 and the planarization insulating film 415, and wiring layers 465a and 465b electrically connected to the source electrode layer 405a and the drain electrode layer 405b are formed in the openings (see FIG. 1F and FIG. 6D ). 3A to 3F , the source electrode layer 405 a and the drain electrode layer 405 b may be provided over the film 407 including a metal element and the insulating film 416 , like the wiring layers 465 a and 465 b . In Figures 3A to 3F , since the source electrode layer 405a and the drain electrode layer 405b are not formed to cover a portion of the oxide semiconductor film 403 as in Figures 1A to 1F , metal elements and dopants are introduced into the region other than the channel formation region 409 that overlaps with the gate electrode layer 401. Consequently, the low-resistance regions formed in the oxide semiconductor film 403 sandwiching the channel formation region 409 constitute the transistor 445, which includes the low-resistance regions 404a and 404b containing metal elements and dopants. 3F , a film 407 containing a metal element and an insulating film 416, which form a metal oxide insulating film, are stacked on a transistor 445. A source electrode layer 405a and a drain electrode layer 405b are formed in openings formed in the film 407 containing a metal element and the insulating film 416, reaching the low-resistance regions 404a and 404b. Furthermore, as shown in Figures 7A and 7B, sidewall insulating layers 412a and 412b with sidewall structures may be provided on the sides of the gate electrode layer 401. After forming an insulating film covering the gate electrode layer 401, the insulating film is anisotropically etched using RIE (reactive ion etching), thereby forming the sidewall insulating layers 412a and 412b with sidewall structures in a self-aligned manner on the sidewalls of the gate electrode layer 401. The insulating film is not particularly limited; for example, silicon oxide with good step coverage can be used, which is formed by reacting TEOS (tetraethyl-ortho-silane) or silane with oxygen or nitrous oxide. The insulating film can be formed by methods such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECRCVD, and sputtering. Alternatively, silicon oxide formed by low-temperature oxidation (LTO) can be used. In FIG. 7A and FIG. 7B , the gate electrode layer 401 and the sidewall insulating layers 412 a and 412 b can be used as masks to etch the gate insulating film to form the gate insulating film 402 . In addition, in Figures 7A and 7B , when etching the insulating film, the insulating film on the gate electrode layer 401 is removed to expose the gate electrode layer 401. However, the sidewall insulating layers 412a and 412b may be formed so that the insulating film remains on the gate electrode layer 401. Furthermore, a protective film may be formed on the gate electrode layer 401 in a later process. By protecting the gate electrode layer 401 in this way, thinning of the gate electrode layer can be prevented during etching. The etching method may be dry etching or wet etching, and various etching methods may be used. When the process of forming the sidewall insulating layers 412a and 412b is performed before the process of introducing the dopant, as shown in Figure 7A, since the sidewall insulating layers 412a and 412b are also used as masks when the process of introducing the dopant is performed, a transistor 420a having a structure in which no dopant is introduced into the oxide semiconductor film 403 under the sidewall insulating layers 412a and 412b is formed. On the other hand, when the process of forming sidewall insulating layers 412a and 412b is performed after the process of introducing dopants, as shown in Figure 7B, since the sidewall insulating layers 412a and 412b are not used as masks when the process of introducing dopants is performed, a transistor 420b is formed having a structure in which dopants are introduced into the oxide semiconductor film 403 under the sidewall insulating layers 412a and 412b to include low resistance regions 406c and 406d containing dopants. The oxide semiconductor film 403 is highly purified and has its oxygen vacancies filled, and impurities such as hydrogen and water are fully removed. The hydrogen concentration in the oxide semiconductor film 403 is 5×10 19 atoms / cm 3 Below, preferably 5×10 18 atoms / cm 3 The following is the result of measurement. The hydrogen concentration in the oxide semiconductor film 403 was measured using secondary ion mass spectrometry (SIMS). In such an oxide semiconductor film 403, the number of carriers is extremely small (approximately 0) and the carrier concentration is less than 1×10 14 / cm 3 , less than 1×10 12 / cm 3 Better, less than 1×10 11 / cm 3 Better. In the transistor 440 using the highly purified oxide semiconductor film 403 containing excess oxygen to fill oxygen vacancies, which is manufactured in this embodiment, the current value per channel width of 1 μm (off-state current value) at room temperature in the off state can be reduced to 100 zA / μm (1 zA (zeptoampere) is 1×10 -21 A) or less, preferably reduced to 10zA / μm or less, more preferably reduced to 1zA / μm or less, and further preferably reduced to a level of 100yA / μm or less. As described above, by using the transistor having high electrical characteristics, a high-performance and high-reliability semiconductor device can be provided. Implementation Method 2 In this embodiment, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device is described with reference to FIG2A to FIG2D . The same parts or parts having the same functions as those in the above embodiment and the same processes can be performed in the same manner as in the above embodiment, and repeated description thereof will be omitted. Detailed description of the same parts will be omitted. This embodiment mode describes an example in which a process of introducing a metal element into an oxide semiconductor film is performed before a process of introducing a dopant in a method of manufacturing a semiconductor device according to the disclosed invention. 2A to 2D illustrate an example of a method for manufacturing the transistor 440 of this embodiment. 2A corresponds to FIG. 1C , and an oxide semiconductor film 403 , a source electrode layer 405 a , a drain electrode layer 405 b , a gate insulating film 402 , a gate electrode layer 401 , and a film 417 containing a metal element are formed on a substrate 400 having an insulating surface provided with an insulating film 436 . In this embodiment, a 10 nm-thick aluminum film is formed as the film 417 containing a metal element by a sputtering method. Next, heat treatment is performed while the film 417 containing the metal element is in contact with a portion of the oxide semiconductor film 403. Heat treatment is preferably performed in an oxygen atmosphere. Heat treatment can also be performed under reduced pressure or in a nitrogen atmosphere. The heating temperature can be set to 100° C. or higher and 700° C. or lower, preferably 200° C. or higher and 400° C. or lower. For example, the substrate is placed in an electric furnace, which is one of heat treatment apparatuses, and the film 417 containing a metal element and the oxide semiconductor film 403 are heat treated at 300° C. for one hour in an oxygen atmosphere. By performing the heat treatment, the metal element is introduced from the film 417 containing the metal element into the oxide semiconductor film 403, thereby forming low-resistance regions 426a and 426b (see FIG. 2B ). The low-resistance regions 426a and 426b contain the metal element. Furthermore, by heat treatment for introducing the metal element from the film 417 containing the metal element into the oxide semiconductor film 403, the film 417 containing the metal element becomes the film 407 containing the metal element. For example, the metal film used for the film 417 containing the metal element becomes a metal oxide insulating film, which is the film 407 containing the metal element. Such a metal oxide film can be used as an insulating film. In this embodiment, since an aluminum film is used as the film 417 containing the metal element, the heat treatment converts the film into an aluminum oxide film. Since the aluminum oxide film is a metal oxide insulating film, it can be used as an insulating film. Next, using the gate insulating film 402 and the gate electrode layer 401 as masks, a dopant 421 is selectively introduced into the oxide semiconductor film 403 through the film 407 including the metal element, the source electrode layer 405a, and the drain electrode layer 405b, thereby forming low resistance regions 404a and 404b. In this embodiment, an example is shown in which the source electrode layer 405a and the drain electrode layer 405b are formed as thin films. Therefore, the dopant 421 is also introduced into the oxide semiconductor film below the source electrode layer 405a and the drain electrode layer 405b, thereby forming the low-resistance regions 406a and 406b. Depending on the thickness of the source electrode layer 405a and the drain electrode layer 405b and the conditions for introducing the dopant 421, the dopant 421 may not be introduced into the oxide semiconductor film 403 below the source electrode layer 405a and the drain electrode layer 405b. In this embodiment, boron is used as the dopant 421 , and boron ions are implanted by an ion implantation method. Therefore, in the oxide semiconductor film 403, low-resistance regions 404a and 404b containing a dopant and a metal element and low-resistance regions 406a and 406b containing a dopant are formed across the channel formation region 409. Here, the resistance of the low-resistance regions 404a and 404b containing a dopant and a metal element can be made lower than the resistance of the low-resistance regions 406a and 406b containing a dopant. The above-described process can be used to manufacture the transistor 440 of this embodiment (see FIG. 2C ). The oxide semiconductor film 403 includes the low-resistance regions 404 a and 404 b and the low-resistance regions 406 a and 406 b sandwiching the channel formation region 409 in the channel length direction. This transistor 440 exhibits high on-state characteristics (e.g., on-state current and field-effect mobility) and is capable of high-speed operation and response. The low-resistance regions 404a, 404b and the low-resistance regions 406a, 406b can be used as source regions or drain regions. Providing the low-resistance regions 404a, 404b can mitigate the electric field applied to the channel formation region 409 formed between the low-resistance regions 404a, 404b. Furthermore, by electrically connecting the oxide semiconductor film 403 to the source electrode layer 405a and the drain electrode layer 405b at the low-resistance regions 406a, 406b, the contact resistance between the oxide semiconductor film 403 and the source electrode layer 405a and the drain electrode layer 405b can be reduced. In this embodiment, a planarization insulating film 415 is formed on the film 407 containing a metal element. In addition, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the film 407 containing a metal element and the planarization insulating film 415, and wiring layers 465a and 465b electrically connected to the source electrode layer 405a and the drain electrode layer 405b are formed in the openings (see FIG. 2D ). As described above, by using the transistor having high electrical characteristics, a high-performance and high-reliability semiconductor device can be provided. This embodiment mode can be implemented in combination with other embodiment modes as appropriate. Implementation 3 In this embodiment, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device is described with reference to FIG4A to FIG4F . The same parts or parts having the same functions as those in the above embodiment and the same processes can be performed in the same manner as in the above embodiment, and repeated description thereof will be omitted. Detailed description of the same parts will be omitted. This embodiment describes an example of a method for manufacturing a transistor having a connection structure between a source electrode layer, a drain electrode layer, and an oxide semiconductor film that is different from that in Embodiments 1 and 2. 4A to 4F illustrate an example of a method for manufacturing the transistor 450 in this embodiment. First, an insulating film 436 is formed on the substrate 400 . Next, a conductive film serving as a source electrode layer and a drain electrode layer (including wiring formed using the same layer) is formed over the insulating film 436 . A photoresist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form a source electrode layer 405 a and a drain electrode layer 405 b . The photoresist mask is then removed. Then, the oxide semiconductor film 403 is formed over the insulating film 436, the source electrode layer 405a, and the drain electrode layer 405b. A gate insulating film 442 is formed to cover the oxide semiconductor film 403 (see FIG. 4A). The gate electrode layer 401 is formed on the gate insulating film 442 . Next, the gate insulating film 442 is etched using the gate electrode layer 401 as a mask to expose a portion of the oxide semiconductor film 403 , thereby forming the gate insulating film 402 (see FIG. 4B ). Next, a film 417 containing a metal element is formed over the source electrode layer 405 a , the drain electrode layer 405 b , the oxide semiconductor film 403 , the gate insulating film 402 , and the gate electrode layer 401 in contact with a portion of the oxide semiconductor film 403 (see FIG. 4C ). In this embodiment, a 10 nm-thick aluminum film is formed as the film 417 containing a metal element by a sputtering method. Next, using the gate insulating film 402 and the gate electrode layer 401 as masks, a dopant 421 is selectively introduced into the oxide semiconductor film 403 through the film 417 containing a metal element, thereby forming low resistance regions 414 a and 414 b (see FIG. 4D ). In this embodiment, phosphorus is used as the dopant 421 , and phosphorus ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The concentration of the dopant 421 in the low resistance region is preferably 5×10 18 atoms / cm 3 Above and 1×10 22 atoms / cm 3 the following. After the dopant 421 is introduced, a heat treatment may be performed. Preferred heating conditions include a temperature of 300°C to 700°C, preferably 300°C to 450°C, in an oxygen atmosphere for one hour. Alternatively, the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in air (super dry air). Next, heat treatment is performed while the film 417 containing the metal element is in contact with a portion of the oxide semiconductor film 403. Heat treatment is preferably performed in an oxygen atmosphere. Heat treatment can also be performed under reduced pressure or in a nitrogen atmosphere. The heating temperature can be set to 100° C. or higher and 700° C. or lower, preferably 200° C. or higher and 400° C. or lower. For example, the substrate is placed in an electric furnace, which is one of heat treatment apparatuses, and the film 417 containing a metal element and the oxide semiconductor film 403 are heat treated at 300° C. for one hour in an oxygen atmosphere. By performing the heat treatment, the metal element is introduced from the film 417 containing the metal element into the oxide semiconductor film 403, thereby forming low-resistance regions 404a and 404b. Consequently, low-resistance regions 404a and 404b containing a dopant and a metal element are formed in the oxide semiconductor film 403, sandwiching the channel formation region 409. The low-resistance regions 404a and 404b containing a dopant and a metal element can be made to have a low resistance. In this embodiment, phosphorus is used as a dopant and aluminum is used as a metal element. Therefore, the low-resistance regions 404 a and 404 b contain phosphorus and aluminum. Furthermore, by heat treatment for introducing the metal element from the film 417 containing the metal element into the oxide semiconductor film 403, the film 417 containing the metal element becomes the film 407 containing the metal element. For example, the metal film used for the film 417 containing the metal element becomes a metal oxide insulating film, which is the film 407 containing the metal element. Such a metal oxide film can be used as an insulating film. In this embodiment, since an aluminum film is used as the film 417 containing the metal element, the heat treatment converts the film into an aluminum oxide film. Since the aluminum oxide film is a metal oxide insulating film, it can be used as an insulating film. The above-described process can be used to manufacture the transistor 450 of this embodiment (see FIG. 4E ). By having the oxide semiconductor film 403 including the low-resistance regions 404 a and 404 b sandwiching the channel formation region 409 in the channel length direction, the transistor 450 has high on-state characteristics (e.g., on-state current and field-effect mobility) and is capable of high-speed operation and response. The low-resistance regions 404a and 404b can be used as source regions or drain regions. Providing the low-resistance regions 404a and 404b can mitigate the electric field applied to the channel formation region 409 formed between the low-resistance regions 404a and 404b. Furthermore, by electrically connecting the oxide semiconductor film 403 to the source electrode layer 405a and the drain electrode layer 405b at the low-resistance regions 404a and 404b, the contact resistance between the oxide semiconductor film 403 and the source electrode layer 405a and the drain electrode layer 405b can be reduced. In this embodiment, a planarization insulating film 415 is formed on the film 407 containing a metal element. In addition, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the film 407 containing a metal element and the planarization insulating film 415, and wiring layers 465a and 465b electrically connected to the source electrode layer 405a and the drain electrode layer 405b are formed in the openings (see FIG. 4F ). As described above, by using the transistor having high electrical characteristics, a high-performance and high-reliability semiconductor device can be provided. This embodiment mode can be implemented in combination with other embodiment modes as appropriate. Implementation 4 In this embodiment, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device is described with reference to FIG5A to FIG5D . The same parts or parts having the same functions as those in the above embodiment and the same processes can be performed in the same manner as in the above embodiment, and repeated description thereof will be omitted. Detailed description of the same parts will be omitted. This embodiment mode describes an example in which a process of introducing a metal element into an oxide semiconductor film is performed before a process of introducing a dopant in a method of manufacturing a semiconductor device according to the disclosed invention. 5A to 5D illustrate an example of a method for manufacturing the transistor 450 of this embodiment. 5A corresponds to FIG. 4C , and a source electrode layer 405 a , a drain electrode layer 405 b , an oxide semiconductor film 403 , a gate insulating film 402 , a gate electrode layer 401 , and a film 417 containing a metal element are formed on a substrate 400 having an insulating surface provided with an insulating film 436 . In this embodiment, a 10 nm-thick aluminum film is formed as the film 417 containing a metal element by a sputtering method. Next, heat treatment is performed while the film 417 including the metal element is in contact with part of the oxide semiconductor film 403. The heat treatment can be performed in an oxygen atmosphere. For example, the substrate is placed in an electric furnace, which is one of heat treatment apparatuses, and the film 417 containing a metal element and the oxide semiconductor film 403 are heat treated at 300° C. for one hour in an oxygen atmosphere. By performing the heat treatment, the metal element is introduced from the film 417 containing the metal element into the oxide semiconductor film 403, thereby forming low-resistance regions 426a and 426b (see FIG5B). The low-resistance regions 426a and 426b contain the metal element. Furthermore, by heat treatment for introducing the metal element from the film 417 containing the metal element into the oxide semiconductor film 403, the film 417 containing the metal element becomes the film 407 containing the metal element. For example, the metal film used for the film 417 containing the metal element becomes a metal oxide insulating film, which is the film 407 containing the metal element. Such a metal oxide film can be used as an insulating film. In this embodiment, since an aluminum film is used as the film 417 containing the metal element, the heat treatment converts the film into an aluminum oxide film. Since the aluminum oxide film is a metal oxide insulating film, it can be used as an insulating film. Next, using the gate insulating film 402 and the gate electrode layer 401 as masks, a dopant 421 is selectively introduced into the oxide semiconductor film 403 through the film 407 including the metal element, the source electrode layer 405a, and the drain electrode layer 405b, thereby forming low resistance regions 404a and 404b. In this embodiment, phosphorus is used as the dopant 421 , and phosphorus ions are implanted by an ion implantation method. Therefore, in the oxide semiconductor film 403, low-resistance regions 404a and 404b containing a dopant and a metal element are formed across the channel formation region 409. The low-resistance regions 404a and 404b containing a dopant and a metal element can have low resistance. The above-described process can be used to manufacture the transistor 450 of this embodiment (see FIG. 5C ). By having the oxide semiconductor film 403 including the low-resistance regions 404 a and 404 b sandwiching the channel formation region 409 in the channel length direction, the transistor 450 has high on-state characteristics (e.g., on-state current and field-effect mobility) and is capable of high-speed operation and response. The low-resistance regions 404a and 404b can be used as source regions or drain regions. Providing the low-resistance regions 404a and 404b can mitigate the electric field applied to the channel formation region 409 formed between the low-resistance regions 404a and 404b. Furthermore, by electrically connecting the oxide semiconductor film 403 to the source electrode layer 405a and the drain electrode layer 405b at the low-resistance regions 404a and 404b, the contact resistance between the oxide semiconductor film 403 and the source electrode layer 405a and the drain electrode layer 405b can be reduced. In this embodiment, a planarization insulating film 415 is formed on the film 407 containing a metal element. In addition, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the film 407 containing a metal element and the planarization insulating film 415, and wiring layers 465a and 465b electrically connected to the source electrode layer 405a and the drain electrode layer 405b are formed in the openings (see FIG. 5D ). As described above, by using the transistor having high electrical characteristics, a high-performance and high-reliability semiconductor device can be provided. This embodiment mode can be implemented in combination with other embodiment modes as appropriate. Implementation 5 In this embodiment, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device is described with reference to FIG8A to FIG8F . The same parts or parts having the same functions as those in the above embodiment and the same processes can be performed in the same manner as in the above embodiment, and repeated description thereof will be omitted. Detailed description of the same parts will be omitted. In this embodiment, an example of a transistor having a bottom gate structure is shown. The transistor 410 shown in FIG8A to FIG8F is one of the bottom gate structures called a channel protection type (also called a channel stop type), and is also called an inverted staggered transistor. 8A to 8F illustrate an example of a method for manufacturing the transistor 410 . First, after forming a conductive film on a substrate 400 having an insulating surface, a gate electrode layer 401 is formed by a first photolithography process. A gate insulating film 402 is formed over the gate electrode layer 401 . Then, an oxide semiconductor film 403 is formed over the gate electrode layer 401 and the gate insulating film 402 . An insulating film 427 functioning as a channel protective film is formed over the oxide semiconductor film 403 overlapping with the gate electrode layer 401 (see FIG. 8A ). The insulating film 427 can be formed using the same materials and methods as the insulating film 416. As the insulating film 427, a single layer or a stack of inorganic insulating films such as silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, hafnium oxide film, gallium oxide film, silicon nitride film, aluminum nitride film, silicon oxynitride film, and aluminum oxynitride film can be typically used. When the insulating film 427 in contact with the oxide semiconductor film 403 (when the insulating film 427 has a stacked structure, the film in contact with the oxide semiconductor film 403) is made to contain a large amount of oxygen, the insulating film 427 can be appropriately used as a supply source for supplying oxygen to the oxide semiconductor film 403. Next, a film 417 containing a metal element is formed over the gate electrode layer 401 , the gate insulating film 402 , the oxide semiconductor film 403 , and the insulating film 427 so as to be in contact with part of the oxide semiconductor film 403 (see FIG. 8B ). In this embodiment, a 10 nm-thick aluminum film is formed as the film 417 containing a metal element by a sputtering method. Next, using the gate insulating film 402 and the gate electrode layer 401 as masks, a dopant 421 is selectively introduced into the oxide semiconductor film 403 through the film 417 containing a metal element, thereby forming low resistance regions 414 a and 414 b (see FIG. 8C ). In this embodiment, the insulating film 427 serving as the channel protection film is used as a mask in the process of introducing the dopant 421. However, a separate photoresist mask may be formed to selectively introduce the dopant 421. Furthermore, when a channel-etched transistor without a channel protection film is used, a separate photoresist mask may be formed to selectively introduce the dopant. In this embodiment, boron is used as the dopant 421 , and boron ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The concentration of the dopant 421 in the low resistance region is preferably 5×10 18 atoms / cm 3 Above and 1×10 22 atoms / cm 3 the following. In addition, after the introduction process of the dopant 421, heat treatment may be performed. Next, heat treatment is performed while the film 417 including the metal element is in contact with part of the oxide semiconductor film 403. The heat treatment can be performed in an oxygen atmosphere. For example, the substrate is placed in an electric furnace, which is one of heat treatment apparatuses, and the film 417 containing a metal element and the oxide semiconductor film 403 are heat treated at 300° C. for one hour in an oxygen atmosphere. By performing the heat treatment, the metal element is introduced from the film 417 containing the metal element into the oxide semiconductor film 403, thereby forming low-resistance regions 404a and 404b. Consequently, low-resistance regions 404a and 404b containing a dopant and a metal element are formed in the oxide semiconductor film 403, sandwiching the channel formation region 409. The low-resistance regions 404a and 404b containing a dopant and a metal element can be made to have a low resistance. In this embodiment, boron is used as a dopant and aluminum is used as a metal element. Therefore, the low-resistance regions 404 a and 404 b contain boron and aluminum. Furthermore, by heat treatment for introducing the metal element from the film 417 containing the metal element into the oxide semiconductor film 403 , the film 417 containing the metal element becomes the film 407 containing the metal element (see FIG. 8D ). Next, the film 407 containing the metal element is removed, and the source electrode layer 405a and the drain electrode layer 405b are formed so as to contact the low-resistance regions 404a and 404b. Alternatively, if the film 407 containing the metal element is conductive, the film 407 containing the metal element may be etched using the source electrode layer 405a and the drain electrode layer 405b as a mask, thereby forming a portion of the source electrode layer 405a and the drain electrode layer 405b. The above-described process can be used to manufacture the transistor 410 of this embodiment (see FIG. 8E ). By having the oxide semiconductor film 403 including the low-resistance regions 404 a and 404 b sandwiching the channel formation region 409 in the channel length direction, the transistor 410 has high conduction characteristics (e.g., on-state current and field-effect mobility) and is capable of high-speed operation and response. The low-resistance regions 404a and 404b can be used as source regions or drain regions. Providing the low-resistance regions 404a and 404b can mitigate the electric field applied to the channel formation region 409 formed between the low-resistance regions 404a and 404b. Furthermore, by electrically connecting the oxide semiconductor film 403 to the source electrode layer 405a and the drain electrode layer 405b at the low-resistance regions 404a and 404b, the contact resistance between the oxide semiconductor film 403 and the source electrode layer 405a and the drain electrode layer 405b can be reduced. In this embodiment, an insulating film 416 is formed as a protective film on the transistor 410 (see FIG. 8F ). As described above, by using the transistor having high electrical characteristics, a high-performance and high-reliability semiconductor device can be provided. This embodiment mode can be implemented in combination with other embodiment modes as appropriate. Implementation Method 6 This embodiment describes another method for manufacturing a semiconductor device. The same parts or parts with the same functions and processes as those in the previous embodiment can be performed in the same manner as in the previous embodiment, and repeated descriptions thereof will be omitted. Detailed descriptions of the same parts will be omitted. Note that this embodiment can be applied to the transistors 440 , 445 , 420 a , 420 b , 450 , and 410 described in any one of Embodiments 1 to 5. This embodiment describes an example in which, in a method for manufacturing a semiconductor device according to the disclosed invention, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the oxide semiconductor film 403 that has been dehydrated or dehydrogenated, thereby supplying oxygen into the film. Furthermore, the dehydration or dehydrogenation treatment may also cause oxygen, a main component of the oxide semiconductor, to be released and reduced. Oxygen vacancies may form in the oxide semiconductor film 403 where oxygen has been released. These oxygen vacancies generate donor states that can cause changes in the electrical characteristics of the transistor. Therefore, it is preferable to supply oxygen to the dehydrated or dehydrogenated oxide semiconductor film 403. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be filled. By using this oxide semiconductor film in a transistor, variations in the transistor's threshold voltage Vth and threshold voltage drift ΔVth caused by oxygen vacancies can be reduced. Furthermore, by shifting the transistor's threshold voltage in the positive direction, the transistor can be made normally off. In this embodiment, oxygen is introduced into the oxide semiconductor film 403 as an example. However, oxygen may also be introduced into the gate insulating film 402, the gate insulating film 442, the insulating film 436, the film 407 containing a metal element, the insulating film 416, the insulating film 427, and the like that are in contact with the oxide semiconductor film 403. By introducing oxygen into the gate insulating film 402, the gate insulating film 442, the insulating film 436, the film 407 containing a metal element, the insulating film 416, and the insulating film 427 that are in contact with the oxide semiconductor film 403, these films contain excess oxygen, thereby supplying oxygen to the oxide semiconductor film 403. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used. When oxygen is introduced into the oxide semiconductor film 403, oxygen may be introduced directly into the oxide semiconductor film 403 or introduced through another film such as a gate insulating film or an insulating film. When oxygen is introduced through another film, ion implantation, ion doping, plasma immersion ion implantation, or the like may be used. However, when oxygen is introduced directly into the exposed oxide semiconductor film, plasma treatment or the like may be used. In transistors 440, 445, 420a, 420b, and 450, oxygen can be introduced into the exposed oxide semiconductor film 403 after forming the source electrode layer 405a, the drain electrode layer 405b, after forming the gate insulating film 442 or the gate insulating film 402, after forming the gate electrode layer 401, after forming the film 417 containing metal elements, after forming the film 407 containing metal elements, after forming the insulating film 416, or after forming the planarizing insulating film 415. In addition, in the transistor 410, oxygen can be introduced into the exposed oxide semiconductor film 403 after forming the insulating film 427, after forming the film 417 containing the metal element, after forming the film 407 containing the metal element, after forming the source electrode layer 405a, the drain electrode layer 405b, or after forming the insulating film 416. As described above, oxygen may be introduced into the oxide semiconductor film after the dehydration or dehydrogenation treatment without any particular limitation. Alternatively, oxygen may be introduced into the oxide semiconductor film that has undergone the dehydration or dehydrogenation treatment a plurality of times. For example, it is preferable to set the concentration of oxygen introduced into the oxide semiconductor film 403 by the oxygen introduction process to 1×10 18 atoms / cm 3 Above and 5×10 21 atoms / cm 3 the following. Furthermore, oxygen is a major component of oxide semiconductors. Therefore, it is difficult to accurately estimate the oxygen concentration in oxide semiconductor films using methods such as SIMS (Secondary Ion Mass Spectrometry). In other words, it is difficult to determine whether oxygen has been intentionally added to oxide semiconductor films. In addition, oxygen 17 O and 18 O and other isotopes, and it is generally believed that 17 O and 18The abundance ratios of O are approximately 0.037% and 0.204% of the total oxygen atoms, respectively. In other words, the concentrations of these isotopes in the oxide semiconductor film are estimated using methods such as SIMS. Therefore, by measuring these concentrations, it is sometimes possible to more accurately estimate the oxygen concentration in the oxide semiconductor film. Therefore, by measuring these concentrations, it is possible to determine whether oxygen has been intentionally added to the oxide semiconductor film. Furthermore, when oxygen is directly introduced into the oxide semiconductor film as in this embodiment, it is not necessary for the insulating film in contact with the oxide semiconductor film to be a film containing a large amount of oxygen. Of course, the insulating film in contact with the oxide semiconductor film may be a film containing a large amount of oxygen, or oxygen may be directly introduced into the oxide semiconductor film using various oxygen supply methods. In order to prevent the introduced oxygen from being re-emitted from the oxide semiconductor film and to prevent hydrogen, water, and other impurities containing hydrogen from being re-introduced into the oxide semiconductor film, it is preferable to provide a film having a high blocking effect (barrier effect) against oxygen and impurities containing hydrogen, such as hydrogen and water, as an insulating film covering the oxide semiconductor film. For example, it is preferable to use an aluminum oxide film or the like, which has a high blocking effect (barrier effect) against both impurities such as hydrogen and water and oxygen. Furthermore, after oxygen is introduced into the oxide semiconductor film, a heating process is preferably performed. By introducing oxygen into the oxide semiconductor film that has been subjected to a dehydration or dehydrogenation treatment and supplying oxygen into the film, the oxide semiconductor film can be highly purified and electrically made I-type (intrinsic). A transistor having a highly purified and electrically I-type (intrinsic) oxide semiconductor film has its electrical characteristics suppressed from fluctuating, so the transistor is electrically stable. As described above, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. Therefore, a highly reliable semiconductor device can be provided. This embodiment mode can be implemented in combination with other embodiment modes as appropriate. Implementation 7 A semiconductor device having a display function (also referred to as a display device) can be manufactured by using the transistors described in any of Embodiments 1 to 6. Furthermore, by integrally forming part or all of a driver circuit including transistors with a pixel portion on the same substrate, a system-on-panel can be formed. In FIG9A , a sealing material 4005 is provided to surround a pixel portion 4002 provided on a first substrate 4001, and a second substrate 4006 is used for sealing. In FIG9A , a scan line driver circuit 4004 and a signal line driver circuit 4003, formed on a separately prepared substrate using a single crystal semiconductor film or a polycrystalline semiconductor film, are mounted in an area on the first substrate 4001 that is different from the area surrounded by the sealing material 4005. Various signals and potentials are supplied to the separately formed signal line driver circuit 4003, scan line driver circuit 4004, or pixel portion 4002 via FPCs (Flexible Printed Circuits) 4018a and 4018b. In Figures 9B and 9C , a sealant 4005 is provided to surround a pixel portion 4002 and a scan line driver circuit 4004 provided on a first substrate 4001. Furthermore, a second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Thus, the pixel portion 4002, the scan line driver circuit 4004, and the display element are sealed together by the first substrate 4001, the sealant 4005, and the second substrate 4006. In Figures 9B and 9C , a signal line driver circuit 4003 formed on a separately prepared substrate using a single crystal semiconductor film or a polycrystalline semiconductor film is mounted in an area on the first substrate 4001 that is different from the area surrounded by the sealant 4005. In Figures 9B and 9C , various signals and potentials supplied to the separately formed signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002 are supplied from an FPC 4018. 9B and 9C illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, the present invention is not limited to this structure. The scan line driver circuit may be formed separately and mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be formed separately and mounted. Furthermore, the connection method for the separately formed driver circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method, etc., can be used. FIG9A shows an example of mounting the signal line driver circuit 4003 and the scan line driver circuit 4004 using the COG method, FIG9B shows an example of mounting the signal line driver circuit 4003 using the COG method, and FIG9C shows an example of mounting the signal line driver circuit 4003 using the TAB method. Furthermore, the display device includes a panel in which a display element is sealed, and a module in which an IC including a controller is mounted on the panel. Note that the term "display device" in this specification refers to an image display device, display device, or light source (including lighting equipment). Display devices also include modules equipped with connectors such as FPCs, TAB tape, or TCP; modules with printed circuit boards attached to the ends of TAB tape or TCP; or modules with integrated circuits (ICs) directly mounted on display elements using a COG method. Furthermore, the pixel portion and the scan line driver circuit provided on the first substrate include a plurality of transistors, and the transistors exemplified in any one of Embodiments 1 to 6 can be applied. As display elements provided in a display device, liquid crystal elements (also called liquid crystal display elements) and light-emitting elements (also called light-emitting display elements) can be used. Light-emitting elements include elements whose brightness is controlled by current or voltage, and specifically include inorganic EL (electroluminescence) and organic EL. In addition, display media such as electronic ink that change contrast due to electrical effects can also be used. One embodiment of a semiconductor device will be described with reference to Figures 9A to 9C and Figures 10A and 10B. Figures 10A and 10B correspond to cross-sectional views taken along line MN in Figure 9A. As shown in FIG. 9A to FIG. 9C and FIG. 10A and FIG. 10B , the semiconductor device includes a connection terminal electrode 4015 and a terminal electrode 4016 . The connection terminal electrode 4015 and the terminal electrode 4016 are electrically connected to terminals of an FPC 4018 via an anisotropic conductive film 4019 . The connection terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030 , and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the transistor 4010 and the transistor 4011 . Furthermore, the pixel portion 4002 and the scan line driver circuit 4004 provided on the first substrate 4001 include a plurality of transistors. FIG9A to FIG9C and FIG10A and FIG10B illustrate examples of a transistor 4010 included in the pixel portion 4002 and a transistor 4011 included in the scan line driver circuit 4004. FIG10A shows an insulating film 4020 provided over transistors 4010 and 4011, and FIG10B also shows an insulating film 4021 provided over transistors 4010 and 4011. Furthermore, an insulating film 4023 serves as a base film. The transistor 4010 and the transistor 4011 can use the transistor described in any of Embodiments 1 to 6. This embodiment describes an example in which a transistor having the same structure as the transistor 440 described in Embodiment 1 is used. Transistors 4010 and 4011 each include an oxide semiconductor film containing a low-resistance region sandwiching a channel formation region along the channel length direction. Therefore, transistors 4010 and 4011 have high on-state characteristics (e.g., on-state current and field-effect mobility), and are capable of high-speed operation and response. Furthermore, miniaturization is also possible. Therefore, as the semiconductor device of this embodiment shown in FIG. 9A to FIG. 9C and FIG. 10A and FIG. 10B , a high-performance and highly reliable semiconductor device can be provided. The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element, thereby forming a display panel. The display element is not particularly limited as long as it can provide display, and various display elements can be used. Figure 10A shows an example of a liquid crystal display device using a liquid crystal element as a display element. In Figure 10A , the liquid crystal element 4013 serving as the display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Furthermore, insulating films 4032 and 4033 serving as alignment films are provided to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on one side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 interposed therebetween. Reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film and provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Alternatively, a spherical spacer may be used. When a liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials (liquid crystal compositions) can exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on the conditions. Alternatively, a liquid crystal composition exhibiting a blue phase without an alignment film can be used as the liquid crystal layer 4008. The blue phase is a type of liquid crystal phase that appears just before the transition from the cholesteric phase to the homogeneous phase when the temperature of the cholesteric phase liquid crystal is raised. The blue phase can be produced using a liquid crystal composition comprising a mixed liquid crystal and a chiral agent. Furthermore, to expand the temperature range over which the blue phase is produced, a polymerizable monomer and a polymerization initiator are added to the liquid crystal composition exhibiting the blue phase, and a polymer stabilization treatment is performed to form a liquid crystal layer. Because liquid crystal compositions exhibiting a blue phase have a short response time and are optically isotropic, alignment treatment is not required and viewing angle dependence is low. Furthermore, since an alignment film is not required, friction treatment is not required, thereby preventing electrostatic damage caused by friction treatment and reducing malfunctions and damage to the liquid crystal display device during the manufacturing process. Consequently, the productivity of the liquid crystal display device can be improved. In transistors using oxide semiconductor films, the electrical characteristics of the transistor may vary significantly due to static electricity, exceeding the design range. Therefore, it is more effective to use a liquid crystal composition exhibiting a blue phase for a liquid crystal display device having a transistor using an oxide semiconductor film. In addition, the intrinsic resistance of liquid crystal material is 1×10 9 Ω.cm or more, preferably 1×10 11 Ω.cm or more, preferably 1×10 12 Ω.cm or more. In addition, the specific resistance values ​​in this specification are values ​​measured at 20°C. The size of the storage capacitor provided in the liquid crystal display device is set to be able to retain charge for a predetermined period, taking into account factors such as the drain current of the transistors arranged in the pixel portion. The size of the storage capacitor can be set in consideration of factors such as the transistor's off-state current. By using a transistor having the oxide semiconductor film disclosed in this specification, it is sufficient to provide a storage capacitor having a capacitance of less than one-third, preferably less than one-fifth, of the liquid crystal capacitance in each pixel. Transistors using the oxide semiconductor film disclosed in this specification can reduce the current value in the off state (off-state current value). Therefore, the retention time of electrical signals such as image signals can be extended, and the writing interval can also be extended when the power is on. As a result, the frequency of refresh operations can be reduced, thereby achieving the effect of suppressing power consumption. In addition, transistors using the oxide semiconductor film disclosed in this specification can obtain high field-effect mobility, so they can be driven at high speed. For example, by using such transistors capable of high-speed driving in a liquid crystal display device, switching transistors for the pixel portion and driving transistors for the driving circuit portion can be formed on the same substrate. In other words, since a semiconductor device formed of a silicon wafer or the like does not need to be used separately as a driving circuit, the number of components of the semiconductor device can be reduced. In addition, by using transistors capable of high-speed driving in the pixel portion, high-quality images can be provided. Therefore, high reliability as a semiconductor device can also be achieved. Liquid crystal display devices can adopt TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti Ferroelectric Liquid Crystal) mode, etc. In addition, a normally black liquid crystal display device can also be used, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode. As a vertical alignment mode, there are several examples, such as the MVA (Multi-Domain Vertical Alignment: multi-quadrant vertical alignment) mode, the PVA (Patterned Vertical Alignment: vertical alignment configuration) mode, the ASV (Advanced Super View) mode, etc. can be used. In addition, it can also be used for a VA type liquid crystal display device. A VA type liquid crystal display device is a way of controlling the arrangement of liquid crystal molecules of a liquid crystal display panel. A VA type liquid crystal display device is a way of oriented liquid crystal molecules in a direction perpendicular to the panel when no voltage is applied. In addition, a method called multi-domain or multi-domain design can also be used, in which a pixel (pixel) is divided into several areas (sub-pixels) and the molecules are tilted in different directions. In addition, in the display device, optical components (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a phase difference member, and an anti-reflection member are appropriately provided. For example, circular polarization using a polarizing substrate and a phase difference substrate can also be used. In addition, backlights, sidelights, etc. can also be used as light sources. In addition, as a display method in the pixel portion, a progressive scanning method or an interlaced scanning method can be used. In addition, as a color factor controlled in the pixel when performing color display, it is not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white) or one or more colors such as yellow, cyan, and magenta can be added to RGB. In addition, the size of the display area can also be different according to the point of each color factor. However, the disclosed invention is not limited to a display device for color display, but can also be applied to a display device for monochrome display. Furthermore, as a display element included in a display device, a light-emitting element utilizing electroluminescence can be applied. Light-emitting elements utilizing electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, while the latter is called an inorganic EL element. In an organic EL device, when voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, causing current to flow. These carriers (electrons and holes) then recombine, causing the light-emitting organic compound to reach an excited state. When the excited state returns to the ground state, light is emitted. Due to this mechanism, such light-emitting elements are called current-excited light-emitting elements. Inorganic EL elements are classified into dispersed-type inorganic EL elements and thin-film-type inorganic EL elements based on their element structure. Dispersed-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and their luminescence mechanism is donor-acceptor recombination-type luminescence utilizing donor and acceptor energy levels. Thin-film-type inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers, and the dielectric layers sandwiching the light-emitting layer are sandwiched by electrodes, and their luminescence mechanism is localized type light emission utilizing inner-shell electron transitions of metal ions. In addition, an organic EL element is used as a light-emitting element for explanation. To extract light, at least one of the pair of electrodes in the light-emitting element can be made light-transmissive. Furthermore, a transistor and a light-emitting element are formed on a substrate. The light-emitting element can be top-emitted, emitting light from the surface opposite the substrate; bottom-emitted, emitting light from the surface on one side of the substrate; or dual-emission, emitting light from both the substrate and the surface opposite the substrate. Any of these emission structures can be used. FIG10B illustrates an example of a light-emitting device using a light-emitting element as a display element. The light-emitting element 4513, serving as a display element, is electrically connected to the transistor 4010 provided in the pixel portion 4002. The structure of the light-emitting element 4513 is a stacked-layer structure comprising a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the illustrated structure. The structure of the light-emitting element 4513 can be appropriately modified depending on, for example, the direction of light emitted from the light-emitting element 4513. The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, preferably a photosensitive resin material. An opening is formed in the first electrode layer 4030, and the sidewall of the opening is formed into an inclined surface with a continuous curvature. The electroluminescent layer 4511 may be formed of a single layer or a stack of a plurality of layers. In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from invading the light-emitting element 4513, a protective film may be formed on the second electrode layer 4031 and the partition wall 4510. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. may be formed. In addition, a filler material 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. In this way, in order to prevent exposure to external air, it is preferable to use a protective film (such as an adhesive film, a UV-curable resin film, etc.) with high airtightness and low degassing, or a covering material for packaging (encapsulation). As filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet curable resins or thermosetting resins may be used. Examples of filler materials include PVC (polyvinyl chloride), acrylic resins, polyimide, epoxy resins, silicone resins, PVB (polyvinyl butyral), and EVA (ethylene vinyl acetate). For example, nitrogen may be used as the filler. Furthermore, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a phase difference plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately disposed on the emitting surface of the light-emitting element. Furthermore, an anti-reflection film may be disposed on the polarizing plate or circularly polarizing plate. For example, an anti-glare treatment may be applied, which utilizes surface irregularities to diffuse reflected light and reduce glare. Furthermore, electronic paper that drives electronic ink can also be provided as a display device. Electronic paper, also known as an electrophoretic display (EPD), has the following advantages: readability similar to paper, lower power consumption than other display devices, and a thin and lightweight design. Electrophoretic display devices can be implemented in a variety of forms, but they typically involve a plurality of microcapsules containing positively charged first particles and negatively charged second particles dispersed in a solvent or solute. Applying an electric field to the microcapsules causes the particles within the microcapsules to move in opposite directions, resulting in the display of the color of only the particles clustered on one side. Alternatively, the first or second particles contain a dye that does not migrate in the absence of an electric field. Furthermore, the color of the first particles differs from that of the second particles (including being colorless). Thus, an electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect, in which a substance with a high dielectric constant moves to a high electric field region. The solvent in which the microcapsules are dispersed is called electronic ink, and this electronic ink can be printed on surfaces such as glass, plastic, cloth, and paper. In addition, color display can be achieved by using color filters or particles containing pigments. In addition, as the first particles and second particles in the microcapsule, one material selected from conductive materials, insulating materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electrochromic materials, and magnetophoretic materials, or a composite material of these materials can be used. Furthermore, electronic paper can also be applied to display devices using a twisting ball display method. The twisting ball display method involves placing spherical particles painted white and black, respectively, between a first electrode layer and a second electrode layer, which serve as electrode layers for a display element. A potential difference is generated between the first and second electrode layers to control the direction of the spherical particles and produce a display. In addition, in Figures 9A to 9C and Figures 10A and 10B, as the first substrate 4001 and the second substrate 4006, in addition to glass substrates, flexible substrates can also be used. For example, a plastic substrate with light transmittance can be used. As plastic, FRP (Fiberglass-Reinforced Plastics; glass fiber reinforced plastic) board, PVF (polyvinyl fluoride) film, polyester film or acrylic resin film can be used. In addition, if light transmittance is not required, a metal substrate (metal film) such as aluminum or stainless steel can also be used. For example, a thin sheet with a structure in which aluminum foil is sandwiched between PVF film or polyester film can also be used. In this embodiment, an aluminum oxide film containing a metal element that becomes a metal oxide insulating film by heat treatment is used as the insulating film 4020 . The aluminum oxide film provided as the insulating film 4020 over the oxide semiconductor film has a high blocking effect (barrier effect), that is, an effect of preventing impurities such as hydrogen and water and oxygen from passing through the film. Therefore, the aluminum oxide film serves as a protective film to prevent impurities such as hydrogen and moisture, which are the main causes of fluctuations during and after the manufacturing process, from being mixed into the oxide semiconductor film, and to prevent oxygen, which is the main component material of the oxide semiconductor, from being released from the oxide semiconductor film. The insulating film 4021 serving as the planarizing insulating film can be made of a heat-resistant organic material such as an acrylic resin, polyimide, a benzocyclobutene-based resin, polyamide, or an epoxy resin. In addition to the above-mentioned organic materials, low-k dielectric materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), and the like can also be used. Alternatively, the insulating film can be formed by stacking a plurality of insulating films made of these materials. There is no particular restriction on the method for forming the insulating film 4021. The insulating film 4021 can be formed by sputtering, SOG, spin coating, dipping, spraying, droplet jetting (inkjet, etc.), printing (screen printing, offset printing, etc.), scraper, roller coater, curtain coater, blade coater, etc. depending on its material. Display devices display by transmitting light from a light source or display element. Therefore, thin films such as substrates, insulating films, and conductive films provided in the light-transmitting pixel portion are all translucent to light in the visible wavelength range. Regarding the first electrode layer and the second electrode layer (also called pixel electrode layer, common electrode layer, counter electrode layer, etc.) that apply voltage to the display element, the transmittance and reflectivity can be selected according to the direction of light extraction, the location where the electrode layer is set, and the pattern structure of the electrode layer. As the first electrode layer 4030 and the second electrode layer 4031, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, or graphene can be used. In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), their alloys, or their metal nitrides. The first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition including a conductive polymer (also called a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, and copolymers composed of two or more of aniline, pyrrole, and thiophene, or their derivatives. Furthermore, since transistors are easily damaged by static electricity, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably constructed using nonlinear elements. As described above, by applying the transistor described in any one of Embodiments 1 to 6, a semiconductor device having various functions can be provided. Implementation 8 By using the transistor described as an example in any one of Embodiments 1 to 6, a semiconductor device having an image sensor function for reading information of an object can be manufactured. FIG11A shows an example of a semiconductor device having an image sensor function. FIG11A is an equivalent circuit of a photoelectric sensor, and FIG11B is a cross-sectional view showing a portion of the photoelectric sensor. One electrode of photodiode 602 is electrically connected to photodiode reset signal line 658, while the other electrode of photodiode 602 is electrically connected to the gate of transistor 640. One of the source and drain of transistor 640 is electrically connected to photosensor reference signal line 672, while the other of the source and drain of transistor 640 is electrically connected to one of the source and drain of transistor 656. The gate of transistor 656 is electrically connected to gate signal line 659, and the other of the source and drain of transistor 656 is electrically connected to photosensor output signal line 671. Note that in the circuit diagrams of this specification, transistors using an oxide semiconductor film are denoted by the symbol "OS" to clearly identify transistors using an oxide semiconductor film. In FIG11A , transistors 640 and 656 can be applied to the transistors described in Embodiments 1 to 6 and are transistors using an oxide semiconductor film. This embodiment shows an example in which a transistor having the same structure as transistor 440 described in Embodiment 1 is applied. FIG11B is a cross-sectional view showing a photodiode 602 and a transistor 640 in a photoelectric sensor, wherein the photodiode 602 and the transistor 640 serving as sensors are provided on a substrate 601 (TFT substrate) having an insulating surface. A substrate 613 is provided on the photodiode 602 and the transistor 640 using an adhesive layer 608. An insulating film 631, an interlayer insulating film 633, and an interlayer insulating film 634 are provided over the transistor 640. The photodiode 602 is provided over the interlayer insulating film 633 and has a structure in which a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c are stacked in this order from the interlayer insulating film 633 side between an electrode layer 641 formed on the interlayer insulating film 633 and an electrode layer 642 provided on the interlayer insulating film 634. Electrode layer 641 is electrically connected to conductive layer 643 formed in interlayer insulating film 634, and electrode layer 642 is electrically connected to conductive layer 645 via electrode layer 641. Conductive layer 645 is electrically connected to the gate electrode layer of transistor 640, and photodiode 602 is electrically connected to transistor 640. Here, a pin-type photodiode is illustrated, in which a semiconductor film with p-type conductivity as a first semiconductor film 606a, a high-resistance semiconductor film (I-type semiconductor film) as a second semiconductor film 606b, and a semiconductor film with n-type conductivity as a third semiconductor film 606c are stacked. The first semiconductor film 606a is a p-type semiconductor film and can be formed of an amorphous silicon film containing an impurity element imparting p-type conductivity. The first semiconductor film 606a is formed by plasma CVD using a semiconductor source gas containing an impurity element belonging to Group 13 of the periodic table (e.g., boron (B)). Silane (SiH 4). Alternatively, Si 2H 6. SiH 2Cl 2. SiHCl 3. SiCl 4. SiF 4, etc. Alternatively, a method may be used in which, after forming an amorphous silicon film that does not contain an impurity element, an impurity element is introduced into the amorphous silicon film using a diffusion method or an ion implantation method. Preferably, after introducing the impurity element using an ion implantation method or the like, heating or the like is performed to diffuse the impurity element. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, or a sputtering method may be used. The thickness of the first semiconductor film 606a is preferably set to be greater than or equal to 10 nm and less than or equal to 50 nm. The second semiconductor film 606b is an I-type semiconductor film (intrinsic semiconductor film) and can be formed of an amorphous silicon film. To form the second semiconductor film 606b, an amorphous silicon film is formed using a semiconductor material gas by plasma CVD. As the semiconductor material gas, silane (SiH 4). Alternatively, Si 2H 6. SiH 2Cl 2. SiHCl 3. SiCl 4 or SiF 4, etc. The second semiconductor film 606b can also be formed by LPCVD, vapor phase growth, sputtering, etc. The thickness of the second semiconductor film 606b is preferably set to 200 nm or more and 1000 nm or less. The third semiconductor film 606c is an n-type semiconductor film and can be formed of an amorphous silicon film containing an impurity element imparting n-type conductivity. The third semiconductor film 606c is formed by plasma CVD using a semiconductor source gas containing an impurity element belonging to Group 15 of the periodic table (e.g., phosphorus (P)). Silane (SiH 4). Alternatively, Si 2H 6. SiH 2Cl 2. SiHCl 3. SiCl 4 or SiF 4, etc. Alternatively, a method may be used in which, after forming an amorphous silicon film that does not contain an impurity element, an impurity element is introduced into the amorphous silicon film using a diffusion method or an ion implantation method. Preferably, after introducing the impurity element using ion implantation or the like, heating or the like is performed to diffuse the impurity element. In this case, the amorphous silicon film can be formed using an LPCVD method, a vapor phase growth method, or a sputtering method. The thickness of the third semiconductor film 606c is preferably set to be greater than or equal to 20 nm and less than or equal to 200 nm. Alternatively, the first semiconductor film 606 a , the second semiconductor film 606 b , and the third semiconductor film 606 c may be formed using a polycrystalline semiconductor or a microcrystalline semiconductor (Semi Amorphous Semiconductor: SAS) instead of an amorphous semiconductor. When considering Gibbs free energy, microcrystalline semiconductors belong to an intermediate metastable state between amorphous and single crystal. That is, microcrystalline semiconductors are in a third state that is stable in free energy and have short-range order and lattice distortion. In addition, columnar or needle-shaped crystals grow in the normal direction relative to the substrate surface. Microcrystalline silicon, a typical example of microcrystalline semiconductors, has a Raman spectrum that is 520 cm-1, which represents single crystal silicon. -1 That is, the peak of the Raman spectrum of microcrystalline silicon is located at 520 cm, which represents the peak of single crystal silicon. -1 and 480cm representing amorphous silicon -1 In addition, at least 1 at.% or more of hydrogen or halogen is contained to terminate dangling bonds. Furthermore, the inclusion of rare gas elements such as helium, argon, krypton, and neon further promotes lattice distortion, improving stability and resulting in a superior microcrystalline semiconductor film. The microcrystalline semiconductor film can be formed by a high-frequency plasma CVD method with a frequency of tens to hundreds of MHz or a microwave plasma CVD device with a frequency of 1 GHz or more. Typically, hydrogen can be used to dilute SiH 4. Si 2H 6. SiH 2Cl 2. SiHCl 3. SiCl 4. SiF 4 etc. to form the microcrystalline semiconductor film. In addition, in addition to the silicon-containing compound (such as silicon hydride) and hydrogen, one or more rare gas elements selected from helium, argon, krypton, and neon can also be used for dilution to form the microcrystalline semiconductor film. In the above case, the flow rate of hydrogen is set to be more than 5 times and less than 200 times that of the silicon-containing compound (such as silicon hydride), preferably more than 50 times and less than 150 times, and more preferably 100 times. Furthermore, CH 2 O can also be mixed into the silicon-containing gas. 4. C 2H 6th grade carbide gas, GeH 4. GeF 4th grade germanium gas, F 2nd level. Furthermore, because the mobility of holes generated by the photoelectric effect is lower than that of electrons, pin-type photodiodes exhibit superior properties when the surface on the p-type semiconductor film side serves as the light-receiving surface. Here, an example is shown in which light received by a photodiode 602 from the surface of a substrate 601 on which a pin-type photodiode is formed is converted into an electrical signal. Furthermore, light from the side of the semiconductor film whose conductivity type is opposite to that of the semiconductor film serving as the light-receiving surface is interference light, so it is preferable to use a light-shielding conductive film for the electrode layer. Alternatively, the surface on the n-type semiconductor film side can also serve as the light-receiving surface. Interlayer insulating films 633 and 634 can be formed by using insulating materials and using sputtering, plasma CVD, SOG, spin coating, dipping, spraying, droplet jetting (inkjet, etc.), printing (screen printing, offset printing, etc.), scrapers, roller coaters, curtain coaters, blade coaters, etc. according to the materials. In this embodiment, an aluminum oxide film containing a metal element that is converted into a metal oxide insulating film by heat treatment is used as the insulating film 631. The insulating film 631 can be formed by a sputtering method or a plasma CVD method. The aluminum oxide film provided as the insulating film 631 over the oxide semiconductor film has a high blocking effect (barrier effect), that is, an effect of preventing both impurities such as hydrogen and water and oxygen from passing through the film. Therefore, the aluminum oxide film serves as a protective film to prevent impurities such as hydrogen and moisture, which may cause fluctuations during and after the manufacturing process, from being mixed into the oxide semiconductor film, and to prevent oxygen, which is a main component material of the oxide semiconductor, from being released from the oxide semiconductor film. Interlayer insulating films 633 and 634 are preferably used as flattening insulating films to reduce surface irregularities. Heat-resistant organic insulating materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used as interlayer insulating films 633 and 634. In addition to these organic insulating materials, single layers or stacked layers of low-k dielectric materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass) can also be used. The information of the detection target can be read by detecting the light 622 incident on the photodiode 602. In addition, a light source such as a backlight can be used to read the information of the detection target. As described above, a transistor having an oxide semiconductor film including a low-resistance region sandwiching a channel formation region along the channel length direction has high conduction characteristics (e.g., on-current and field-effect mobility), and is capable of high-speed operation and high-speed response. Furthermore, miniaturization is also possible. Therefore, by using this transistor, a high-performance and highly reliable semiconductor device can be provided. This embodiment mode can be used in combination with the configurations described in other embodiment modes as appropriate. Implementation Method 9 The transistor described in any of Embodiments 1 to 6 can be applied to a semiconductor device having an integrated circuit in which a plurality of transistors are stacked. In this embodiment, a storage medium (memory element) is described as an example of a semiconductor device. In this embodiment, a semiconductor device is manufactured. The semiconductor device includes: a transistor 140 as a first transistor manufactured on a single crystal semiconductor substrate; and a transistor 162 as a second transistor manufactured using a semiconductor film with an insulating film interposed therebetween. The transistor described in any of Embodiments 1 to 6 can be applied to transistor 162. This embodiment shows an example in which a transistor having the same structure as transistor 440 described in Embodiment 1 is used as transistor 162. The semiconductor material and structure of the stacked transistor 140 may be the same as or different from the semiconductor material and structure of the transistor 162. This embodiment is an example of using transistors of suitable materials and structures for the circuit of the storage medium (memory element). Figures 12A to 12C are examples of the structure of a semiconductor device. Figure 12A shows a cross-section of the semiconductor device, while Figure 12B shows a plan view of the semiconductor device. Here, Figure 12A corresponds to a cross-section along lines C1-C2 and D1-D2 of Figure 12B. In addition, Figure 12C shows an example of a circuit diagram when the semiconductor device is used as a memory element. The semiconductor device shown in Figures 12A and 12B has a transistor 140 using a first semiconductor material at the bottom and a transistor 162 using a second semiconductor material at the top. In this embodiment, a semiconductor material other than an oxide semiconductor is used as the first semiconductor material, and an oxide semiconductor is used as the second semiconductor material. Semiconductor materials other than oxide semiconductors can be, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, preferably single crystal semiconductors. Alternatively, organic semiconductor materials can be used. Transistors using such semiconductor materials are prone to high-speed operation. On the other hand, transistors using oxide semiconductors can retain charge for a long time due to their characteristics. A method for manufacturing the semiconductor device in FIG. 12A to FIG. 12C will be described. The transistor 140 includes: a channel forming region 116 provided in a substrate 185 comprising a semiconductor material (e.g., silicon, etc.); an impurity region 120 provided so as to sandwich the channel forming region 116; a metal compound region 124 in contact with the impurity region 120; a gate insulating film 108 provided on the channel forming region 116; and a gate electrode 110 provided on the gate insulating film 108. As the substrate 185 containing a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SOI substrate can be used. In addition, generally speaking, an "SOI substrate" refers to a substrate having a silicon semiconductor film provided on an insulating surface. However, in this specification, etc., an "SOI substrate" also includes a substrate having a structure in which a semiconductor film containing a material other than silicon is provided on an insulating surface. In other words, the semiconductor film of the "SOI substrate" is not limited to a silicon semiconductor film. In addition, an SOI substrate also includes a substrate having a structure in which a semiconductor film is provided on an insulating substrate such as a glass substrate with an insulating film interposed therebetween. As methods for manufacturing SOI substrates, the following methods can be used: a method of manufacturing an SOI substrate by implanting oxygen ions into a mirror-polished wafer and then heating it at high temperature to form an oxide layer at a certain depth from the surface, thereby eliminating defects generated in the surface layer; a method of cleaving a semiconductor substrate by growing micropores formed by irradiating hydrogen ions through heat treatment; or a method of forming a single crystal semiconductor film by crystal growth on an insulating surface, etc. For example, ions are added from one surface of a single crystal semiconductor substrate to form a brittle layer at a certain depth from the surface of the single crystal semiconductor substrate, while an insulating film is formed on either the surface of the single crystal semiconductor substrate or on the element substrate. While the single crystal semiconductor substrate and the element substrate are overlapped with the insulating film interposed therebetween, a heat treatment is performed to generate cracks in the brittle layer, separating the single crystal semiconductor substrate at the brittle layer. A single crystal semiconductor film, serving as a semiconductor film, is then formed from the single crystal semiconductor substrate onto the element substrate. SOI substrates manufactured using the above method can also be used. An element isolation insulating layer 106 is provided on the substrate 185 to surround the transistor 140. Furthermore, to achieve high integration, as shown in Figures 12A to 12C , it is preferable to adopt a structure in which the transistor 140 does not have a sidewall insulating layer serving as a sidewall. Alternatively, if the characteristics of the transistor 140 are important, a sidewall insulating layer serving as a sidewall may be provided on the side of the gate electrode 110, and an impurity region 120 including regions with different impurity concentrations may be provided. Transistor 140, made of a single crystal semiconductor substrate, is capable of high-speed operation. Therefore, using this transistor as a readout transistor enables high-speed data reading. Two insulating films are formed to cover transistor 140. Prior to forming transistor 162 and capacitor 164, these two insulating films are subjected to CMP to form planarized insulating films 128 and 130, exposing the top surface of gate electrode 110. Inorganic insulating films such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride, aluminum nitride, silicon oxynitride, or aluminum oxynitride can be typically used as the insulating films 128 and 130. The insulating films 128 and 130 can be formed using a plasma CVD method, a sputtering method, or the like. Alternatively, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the aforementioned organic materials, low-k dielectric materials (low-k materials) can also be used. When using organic materials, insulating films 128 and 130 can be formed using a wet process such as spin coating or printing. In addition, in the insulating film 130 , a silicon oxide film is used as a film in contact with the semiconductor film. In this embodiment, a 50 nm thick silicon oxynitride film is formed as the insulating film 128 by sputtering, and a 550 nm thick silicon oxide film is formed as the insulating film 130 by sputtering. A semiconductor film is formed on the insulating film 130 that has been sufficiently planarized by the CMP process. In this embodiment, an oxide semiconductor film is formed as the semiconductor film by a sputtering method using an In-Ga-Zn-based oxide target. Next, the oxide semiconductor film is selectively etched to form an island-shaped oxide semiconductor film 144. Over the oxide semiconductor film 144, a source or drain electrode 142a and a source or drain electrode 142b are formed. A gate insulating film 146 and a gate electrode layer 148 are formed over the oxide semiconductor film. The gate electrode layer 148 can be formed by selectively etching the conductive layer after forming the conductive layer. The gate insulating film 146 is formed by etching the insulating film using the gate electrode layer 148 as a mask. As the gate insulating film 146, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or a gallium oxide film can be formed by plasma CVD or sputtering. The conductive layer that can be used for the gate electrode 110, the source or drain electrode 142a, and the source or drain electrode 142b can be formed using a PVD method such as sputtering or a CVD method such as plasma CVD. Furthermore, the conductive layer can be made of an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W, or an alloy containing these elements. Alternatively, any one of Mn, Mg, Zr, Be, Nd, and Sc, or a combination of multiple thereof, can be used. The conductive layer can have a single-layer structure or a stacked structure of two or more layers. Examples include a single-layer structure of a titanium film or titanium nitride film; a single-layer structure of an aluminum film containing silicon; a double-layer structure of a titanium film stacked on an aluminum film; a double-layer structure of a titanium film stacked on a titanium nitride film; and a triple-layer structure of a titanium film, an aluminum film, and a titanium film stacked together. Furthermore, when a single-layer structure of a titanium film or titanium nitride film is used as the conductive layer, there is an advantage in that the conductive layer can be easily processed into the source or drain electrode 142a and the source or drain electrode 142b having a tapered shape. Next, a film containing a metal element is formed over the oxide semiconductor film 144, the gate insulating film 146, and the gate electrode layer 148 so as to be in contact with a portion of the oxide semiconductor film 144. In this embodiment, an aluminum film is formed as the film containing a metal element. A dopant (boron in this embodiment) is introduced into the oxide semiconductor film 144 through a film containing a metal element. A heat treatment is performed while the oxide semiconductor film 144 containing the dopant and the film containing the metal element are in contact. The heat treatment introduces the metal element from the film containing the metal element into the oxide semiconductor film 144, forming a low-resistance region containing the dopant and the metal element in the oxide semiconductor film 144. Consequently, a transistor 162 can be manufactured that includes the oxide semiconductor film 144 with the low-resistance region containing the dopant and the metal element sandwiched between the channel formation region. By having the oxide semiconductor film 144 including the low-resistance region sandwiching the channel formation region in the channel length direction, the transistor 162 has high conduction characteristics (eg, on-current and field-effect mobility) and is capable of high-speed operation and high-speed response. The low-resistance regions can be used as source or drain regions. Providing the low-resistance regions can mitigate the electric field applied to the channel formation region formed between the low-resistance regions. Furthermore, the oxide semiconductor film 144 is electrically connected to the source or drain electrode 142 a and the oxide semiconductor film 144 is electrically connected to the source or drain electrode 142 b in the low-resistance regions, thereby reducing the contact resistance between the oxide semiconductor film 144 and the source or drain electrode 142 a and the oxide semiconductor film 144 and the source or drain electrode 142 b. Furthermore, by heat treatment for introducing the metal element from the film containing the metal element, the film containing the metal element becomes the film containing the metal element 150. For example, the metal film used for the film containing the metal element can be a metal oxide insulating film as the film containing the metal element 150. Such a metal oxide film can be used as an insulating film. In this embodiment, since an aluminum film is used as the film containing the metal element, the heat treatment converts the film into an aluminum oxide film. Since the aluminum oxide film is a metal oxide insulating film, it can be used as an insulating film. The aluminum oxide film that can be used for the film 150 containing a metal element provided over the oxide semiconductor film 144 has a high blocking effect (barrier effect), that is, an effect of preventing both impurities such as hydrogen and moisture and oxygen from passing through the film. Therefore, the aluminum oxide film serves as a protective film to prevent impurities such as hydrogen and moisture, which are the main causes of variations during and after the manufacturing process, from being mixed into the oxide semiconductor film 144 , and to prevent oxygen, which is the main component material of the oxide semiconductor, from being released from the oxide semiconductor film 144 . Alternatively, the film 150 containing a metal element may be removed or an insulating film may be separately formed on the film 150 containing a metal element. As the insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or a gallium oxide film can be formed by plasma CVD or sputtering. An electrode layer 153 is formed on the film 150 containing a metal element in a region overlapping with the source electrode or the drain electrode 142 a . Next, an insulating film 152 is formed over the transistor 162 and the film 150 containing the metal element. The insulating film 152 can be formed using a sputtering method, a CVD method, or the like. Alternatively, the insulating film 152 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, or aluminum oxide. Next, an opening reaching the source electrode or drain electrode 142b is formed in the gate insulating film 146, the film 150 containing a metal element, and the insulating film 152. The opening is formed by selective etching using a mask or the like. Then, a wiring 156 is formed in the opening so as to be in contact with the source or drain electrode 142b. 12A to 12C do not show the connection portion between the source or drain electrode 142b and the wiring 156. Wiring 156 is formed by forming a conductive layer using a PVD method such as sputtering or a CVD method such as plasma CVD, followed by etching. The conductive layer can be made of an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W, or an alloy containing these elements. Alternatively, a material selected from the group consisting of Mn, Mg, Zr, Be, Nd, and Sc, or a combination of multiple thereof, can be used. Details are similar to those for the source and drain electrodes 142 a and the like. The above process completes transistor 162 and capacitor 164. Transistor 162 includes a highly purified oxide semiconductor film 144 containing excess oxygen to fill oxygen vacancies. Consequently, fluctuations in the electrical characteristics of transistor 162 are suppressed, resulting in electrical stability. Capacitor 164 is comprised of a source or drain electrode 142a and an electrode layer 153. When a capacitor is not required, a structure without providing the capacitance element 164 may be employed. FIG12C shows an example of a circuit diagram when the semiconductor device described above is used as a memory element. In FIG12C , one of the source and drain electrodes of transistor 162 is electrically connected to one electrode of capacitor 164 and the gate electrode of transistor 140. Furthermore, a first wiring (also called a source line) is electrically connected to the source electrode of transistor 140, and a second wiring (also called a bit line) is electrically connected to the drain electrode of transistor 140. Furthermore, a third wiring (also called a first signal line) is electrically connected to the other of the source and drain electrodes of transistor 162, and a fourth wiring (also called a second signal line) is electrically connected to the gate electrode of transistor 162. Furthermore, a fifth wiring (also called a word line) is electrically connected to the other electrode of capacitor 164. Since transistor 162, which is made of an oxide semiconductor, has an extremely low off-state current, by turning transistor 162 off, the potential of a node (hereinafter referred to as node FG) at which one of the source and drain electrodes of transistor 162 is electrically connected to one electrode of capacitor 164 and the gate electrode of transistor 140 can be maintained for an extremely long period of time. Furthermore, the presence of capacitor 164 facilitates retention of charge applied to node FG, and facilitates reading of the retained information. When storing information in the semiconductor device (writing), first, the potential of the fourth wiring is set to a potential that turns on transistor 162, thereby turning on transistor 162. As a result, the potential of the third wiring is supplied to node FG, causing node FG to accumulate a predetermined amount of charge. Here, one of two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. Then, by setting the potential of the fourth wiring to a potential that turns off transistor 162, transistor 162 is turned off, and node FG becomes floating, thereby holding the predetermined charge. As described above, by causing node FG to accumulate and hold a predetermined amount of charge, the memory cell can store information. Because the off-state current of transistor 162 is extremely low, the charge supplied to node FG is retained for a long time. Consequently, refresh operations are unnecessary or can be performed at an extremely low frequency, significantly reducing power consumption. Furthermore, even without power, stored data can be retained for an extended period. When the stored information is read (read), when a suitable potential (read potential) is applied to the fifth wiring while a predetermined potential (constant potential) is supplied to the first wiring, the transistor 140 is in a different state depending on the amount of charge held at the node FG. This is because, in general, when the transistor 140 is an n-channel type, the apparent threshold value V of the transistor 140 when the node FG holds a high level of charge is V. th_H is lower than the apparent threshold V of the transistor 140 when the node FG maintains a low level charge th_L Here, the apparent threshold refers to the potential of the fifth wiring required to put the transistor 140 in the "on state". Therefore, by setting the potential of the fifth wiring to V th_H With V th_L The potential between V 0, the charge held by the node FG can be identified. For example, when a high level charge is applied during writing, when the potential of the fifth wiring is V 0(>V th_H ), the transistor 140 is in the "on state". When a low level charge is applied, even if the potential of the fifth wiring is V 0( <V th_L ), the transistor 140 also remains in the "off state". Thus, by controlling the potential of the fifth wiring to read the on state or off state of the transistor 140 (reading the potential of the second wiring), the stored information can be read. Furthermore, when rewriting the stored information, a new potential is supplied to node FG, which has already been holding a predetermined amount of charge due to the aforementioned write operation, to cause node FG to hold the charge associated with the new information. Specifically, the potential of the fourth wiring is set to a potential that turns on transistor 162, thereby turning on transistor 162. As a result, the potential of the third wiring (the potential associated with the new information) is supplied to node FG, causing node FG to accumulate the predetermined amount of charge. Subsequently, the potential of the fourth wiring is set to a potential that turns off transistor 162, turning off transistor 162 and causing node FG to hold the charge associated with the new information. In other words, by performing the same operation as the first write operation (second write operation) while node FG holds the predetermined amount of charge due to the first write operation, the stored information can be rewritten. The transistor 162 shown in this embodiment mode can sufficiently reduce the off-state current of the transistor 162 by using a highly purified oxide semiconductor film containing excess oxygen as disclosed in this specification for the oxide semiconductor film 144. Furthermore, the use of such a transistor can provide a semiconductor device capable of retaining stored data for an extremely long period of time. As described above, a transistor having an oxide semiconductor film including a low-resistance region sandwiching a channel formation region in the channel length direction has low off-state current, high on-state characteristics (e.g., on-state current and field-effect mobility), and is capable of high-speed operation and high-speed response. Furthermore, miniaturization is also possible. Therefore, by using this transistor, a high-performance and highly reliable semiconductor device can be provided. The structure, method, and the like described in this embodiment can be used in combination with the structure, method, and the like described in other embodiment modes as appropriate. Implementation 10 The semiconductor devices disclosed in this specification can be applied to a variety of electronic devices (including game consoles). Examples of electronic devices include televisions (also known as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, and other image capture devices, digital photo frames, mobile phones (also known as cell phones or mobile phone devices), portable game consoles, mobile information terminals, audio playback devices, and large-scale game consoles such as pinball machines. The following describes examples of electronic devices that include the semiconductor devices described in the above embodiments. 13A shows a notebook personal computer including a main body 3001, a housing 3002, a display portion 3003, and a keyboard 3004. By applying the semiconductor device described in any of Embodiments 1 to 9 to the display portion 3003, a high-performance and highly reliable notebook personal computer can be provided. FIG13B shows a portable information terminal (PDA) having a main body 3021 provided with a display portion 3023, an external interface 3025, and operation buttons 3024. A stylus pen 3022 is also provided as an accessory for operation. By using the semiconductor device described in any of Embodiments 1 to 9 for the display portion 3023, a high-performance and highly reliable portable information terminal (PDA) can be provided. Figure 13C shows an example of an e-book reader. For example, the e-book reader consists of two housings: housing 2701 and housing 2703. Housing 2701 and housing 2703 are integrated with a shaft 2711, and can be opened and closed using shaft 2711 as an axis. This structure allows for easy handling similar to a paper book. The housing 2701 is assembled with a display unit 2705, and the housing 2703 is assembled with a display unit 2707. The display unit 2705 and the display unit 2707 can be a structure for displaying a continuous screen or a structure for displaying different screens. By adopting a structure for displaying different screens, for example, an article can be displayed in the display unit on the right (the display unit 2705 in FIG13C ) and an image can be displayed in the display unit on the left (the display unit 2707 in FIG13C ). By applying the semiconductor device shown in any of the embodiments 1 to 9 to the display unit 2705 and the display unit 2707, a high-performance and high-reliability e-book reader can be provided. When a transflective or reflective liquid crystal display device is used as the display unit 2705, it can be expected that the e-book reader will also be used in brighter conditions, so a solar cell can be provided to generate electricity using the solar cell and charge the battery. In addition, when a lithium-ion battery is used as the battery, there is an advantage that miniaturization can be achieved. In addition, FIG13C shows an example in which the housing 2701 includes an operating unit, etc. For example, the housing 2701 includes a power supply 2721, operating keys 2723, a speaker 2725, etc. The operating keys 2723 can be used to turn pages. In addition, a keyboard, pointing device, etc. can be provided on the same surface as the display portion of the housing. Alternatively, a structure can be adopted in which external connection terminals (headphone terminals, USB terminals, etc.), a storage medium insertion portion, etc. are provided on the back or side of the housing. Furthermore, the e-book reader can also function as an electronic dictionary. Furthermore, the e-book reader may also be configured to transmit and receive information wirelessly, or to allow users to purchase desired books and other materials from an e-book server wirelessly and then download them. FIG13D shows a mobile phone, which is composed of two housings, housing 2800 and housing 2801. Housing 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, and external connection terminals 2808. Housing 2800 also includes a solar cell 2810 for charging the mobile phone, an external storage slot 2811, and other components. Housing 2801 also includes an antenna. By using the semiconductor device described in any of Embodiments 1 to 9 for display panel 2802, a high-performance and highly reliable mobile phone can be provided. The display panel 2802 includes a touch screen, and a plurality of operation keys 2805 displayed as images are shown by dashed lines in Fig. 13D. A booster circuit is also provided for boosting the voltage outputted by the solar cell 2810 to a voltage required by each circuit. Display panel 2802 changes its display orientation appropriately depending on usage. Furthermore, since image capture lens 2807 is provided on the same surface as display panel 2802, video calls can be implemented. Speaker 2803 and microphone 2804 are not limited to audio calls; they can also be used for video calls, recording, and playback. Furthermore, by sliding housing 2800 and housing 2801 from an unfolded state (as shown in Figure 13D) to an overlapped state, the device can be miniaturized for portability. The external connection terminal 2808 can be connected to an AC adapter and various cables such as a USB cable, allowing charging and data communication with a personal computer, etc. In addition, by inserting a storage medium into the external storage slot 2811, it can correspond to the storage and movement of larger amounts of data. Furthermore, in addition to the above functions, the mobile phone may also have an infrared communication function, a television reception function, and the like. FIG13E shows a digital video camera including a main body 3051, a display portion (A) 3057, a viewfinder 3053, an operation switch 3054, a display portion (B) 3055, and a battery 3056. By using the semiconductor device described in any of Embodiments 1 to 9 for the display portion (A) 3057 and the display portion (B) 3055, a high-performance and highly reliable digital video camera can be provided. FIG13F shows an example of a television set. In the television set, a display portion 9603 is incorporated into a housing 9601. The display portion 9603 can display images. Furthermore, a structure in which the housing 9601 is supported by a bracket 9605 is shown. By using the semiconductor device described in any of Embodiments 1 to 9 for the display portion 9603, a high-performance and highly reliable television set can be provided. The television can be operated by using an operation switch included in the housing 9601 or a separately provided remote controller. Alternatively, the remote controller may be provided with a display portion that displays information output from the remote controller. Televisions are typically equipped with a receiver and modem. The receiver can receive standard television broadcasts. Furthermore, by connecting the modem to a wired or wireless communication network, information can be transmitted in one direction (from sender to receiver) or in two directions (between sender and receiver, or between receivers). This embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate. 414a: low resistance area 414b: low resistance area 421: Dopant

Claims

1. A semiconductor device comprising: a first transistor having a first channel forming region comprising silicon; a second transistor having a second channel forming region comprising an oxide semiconductor; a first insulating film having a region on the first channel forming region; a first conductive layer having a region on the first insulating film; a second insulating film having a region in contact with a side of the first conductive layer; a third insulating film having a region on the second insulating film; an oxide semiconductor layer having a region in contact with a top surface of the third insulating film and having the second channel forming region; a fourth insulating film having a region on the oxide semiconductor layer; and a second conductive layer having a region on the fourth insulating film and overlapping the second channel forming region; the third... A conductive layer having a region in contact with the top surface of the oxide semiconductor layer and functioning as one of the source electrode and drain electrode of the second transistor; a fourth conductive layer having a region in contact with the top surface of the oxide semiconductor layer and functioning as the other of the source electrode and drain electrode of the second transistor; a fifth insulating film having a region on the second conductive layer, a region on the third conductive layer, and a region on the fourth conductive layer; and a fifth conductive layer having a region on the fifth insulating film; the fifth conductive layer overlapping the third conductive layer; a region on the top surface of the first conductive layer in contact with the third conductive layer; the fifth conductive layer overlapping the first channel forming region; and the fifth conductive layer overlapping the first conductive layer.

2. A semiconductor device comprising: a first transistor having a first channel forming region comprising silicon; a second transistor having a second channel forming region comprising an oxide semiconductor; a first insulating film having a region on the first channel forming region; a first conductive layer having a region on the first insulating film; a second insulating film having a region in contact with a side of the first conductive layer; a third insulating film having a region on the second insulating film; an oxide semiconductor layer having a region in contact with a top surface of the third insulating film and having the second channel forming region; a fourth insulating film having a region on the oxide semiconductor layer; a second conductive layer having a region on the fourth insulating film and overlapping the second channel forming region; and a third conductive layer having a region in contact with the oxide semiconductor layer. The first conductive layer has a region on top of the oxide semiconductor layer that is in contact with it and functions as one of the source and drain electrodes of the second transistor; a fourth conductive layer has a region on top of the oxide semiconductor layer that is in contact with it and functions as the other of the source and drain electrodes of the second transistor; a fifth insulating film has a region on the second conductive layer, a region on the third conductive layer, and a region on the fourth conductive layer; and a fifth conductive layer has a region on the fifth insulating film; the fifth conductive layer overlaps with the third conductive layer; the first conductive layer has a region on top of it that is in contact with the third conductive layer; the fifth conductive layer overlaps with the first channel forming region; the fifth conductive layer overlaps with the first conductive layer; the oxide semiconductor layer does not overlap with the first channel forming region.

3. A semiconductor device comprising: a first transistor having a first channel forming region comprising silicon; a second transistor having a second channel forming region comprising an oxide semiconductor; a first insulating film having a region on the first channel forming region; a first conductive layer having a region on the first insulating film; a second insulating film having a region in contact with a side of the first conductive layer; a third insulating film having a region on the second insulating film; an oxide semiconductor layer having a region in contact with a top surface of the third insulating film and having the second channel forming region; a fourth insulating film having a region on the oxide semiconductor layer; a second conductive layer having a region on the fourth insulating film and overlapping the second channel forming region; and a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and having a region serving as the second transistor. The first conductive layer has the function of one of the source electrode and the drain electrode; a fourth conductive layer has a region that contacts the upper surface of the oxide semiconductor layer and has the function of the other of the source electrode and the drain electrode of the second transistor; a fifth insulating film has a region on the second conductive layer, a region on the third conductive layer, and a region on the fourth conductive layer; and a fifth conductive layer has a region on the fifth insulating film; the fifth conductive layer overlaps with the third conductive layer; the upper surface of the first conductive layer has a region that contacts the third conductive layer; the fifth conductive layer overlaps with the first channel forming region; the fifth conductive layer overlaps with the first conductive layer; the oxide semiconductor layer has a region that does not overlap with the second conductive layer; the non-overlapping region contains at least one element selected from phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, indium, fluorine, chlorine, titanium, and zinc.

4. A semiconductor device comprising: a first transistor having a first channel forming region comprising silicon; a second transistor having a second channel forming region comprising an oxide semiconductor; a first insulating film having a region on the first channel forming region; a first conductive layer having a region on the first insulating film; a second insulating film having a region in contact with a side of the first conductive layer; a third insulating film having a region on the second insulating film; an oxide semiconductor layer having a region in contact with a top surface of the third insulating film and having the second channel forming region; a fourth insulating film having a region on the oxide semiconductor layer; a second conductive layer having a region on the fourth insulating film and overlapping the second channel forming region; and a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer and having a source electrode and a drain electrode as the second transistor. One of the functions; a fourth conductive layer having a region in contact with the upper surface of the oxide semiconductor layer, and having another function as the source electrode and the drain electrode of the second transistor; a fifth insulating film having a region on the second conductive layer, a region on the third conductive layer, and a region on the fourth conductive layer; and a fifth conductive layer having a region on the fifth insulating film; the fifth conductive layer overlaps with the third conductive layer; the upper surface of the first conductive layer has a region in contact with the third conductive layer; the fifth conductive layer overlaps with the first channel forming region; the fifth conductive layer overlaps with the first conductive layer; the oxide semiconductor layer has a region that does not overlap with the second conductive layer; the non-overlapping region contains at least one element selected from phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, indium, fluorine, chlorine, titanium, and zinc; the oxide semiconductor layer does not overlap with the first channel forming region.

5. A semiconductor device as described in any of claims 1 to 4, wherein, The thickness of the oxide semiconductor layer is greater than 1 nm and less than 200 nm.

6. A semiconductor device as described in any of claims 1 to 4, wherein, The oxide semiconductor layer contains In, Ga, and Zn.

7. The semiconductor device according to any one of claims 1 to 4 further comprises: a silicon nitride film as the second insulating film; and a silicon oxide film as the third insulating film and the fourth insulating film, respectively.

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