Oxide semiconductor films, thin-film transistors, and electronic devices

Abstract

This invention provides an oxide semiconductor film with a novel crystalline structure. The oxide semiconductor film of this invention is crystalline and contains indium (In) and a first metallic element (M1) selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanides. The crystalline structure of the oxide semiconductor film is a manganese oxide type structure. In the diffraction pattern of the oxide semiconductor film obtained by out-of-plane XRD measurement using Cu-Kα rays, at least a first peak on the (222) plane and a second peak on the (440) plane are observed, and the ratio of the intensity of the first peak to the intensity of the second peak is 125 or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a polycrystalline oxide semiconductor (Poly-OS) film. Another embodiment of the present invention relates to a thin film transistor including the Poly-OS film. Another embodiment of the present invention relates to an electronic device including the thin film transistor. Prior Art

[0002] In recent years, thin-film transistors (TFTs) that use oxide semiconductor films as channels, replacing silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystalline silicon, have been developed (see, for example, Patent Documents 1 to 6). Like TFTs containing amorphous silicon films, these TFTs containing oxide semiconductor films have a simple structure and can be formed using low-temperature processes. Furthermore, TFTs containing oxide semiconductor films are known to have higher field-effect mobility than TFTs containing amorphous silicon films. [Prior Art Literature] [Patent Document]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2021-141338 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-099601 [Patent Document 3] Japanese Patent Application Laid-Open No. 2021-153196 [Patent Document 4] Japanese Patent Application Publication No. 2018-006730 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-184771 [Patent Document 6] Japanese Patent Application Laid-Open No. 2021-108405 Summary of the Invention

[0004] [Problems to be solved by the invention]

[0005] However, the field-effect mobility of conventional thin-film transistors (TFTs) containing oxide semiconductor films is not particularly high, even when using crystalline oxide semiconductor films. Therefore, improvements in the crystal structure of oxide semiconductor films used in TFTs are being sought to increase the field-effect mobility of TFTs.

[0006] One embodiment of the present invention is proposed in response to the above-mentioned problems, and one object of the present invention is to provide an oxide semiconductor film having a novel crystal structure. Another object of one embodiment of the present invention is to provide a thin-film transistor including an oxide semiconductor film having a novel crystal structure. Another object of one embodiment of the present invention is to provide an electronic device including the thin-film transistor. [Technical means to solve the problem]

[0007] An oxide semiconductor film according to one embodiment of the present invention is crystalline and contains indium (In) and a first metal element (M1) selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanide elements. The crystal structure of the oxide semiconductor film is a bixbyite structure. In a diffraction pattern of the oxide semiconductor film obtained by out-of-plane XRD (X-ray diffraction) measurement using Cu-Kα rays, at least a first peak of the (222) plane and a second peak of the (440) plane are observed, and the ratio of the intensity of the first peak to the intensity of the second peak is less than 125.

[0008] A thin film transistor according to one embodiment of the present invention includes the aforementioned oxide semiconductor thin film as a channel.

[0009] An electronic device according to one embodiment of the present invention includes the above-mentioned thin film transistor. Simple diagram description

[0010] FIG. 1 shows an example of a diffraction pattern of an oxide semiconductor film according to one embodiment of the present invention obtained by out-of-plane XRD measurement. FIG2 is a schematic cross-sectional view showing the structure of a thin film transistor according to one embodiment of the present invention. FIG3 is a schematic top view showing the structure of a thin film transistor according to one embodiment of the present invention. FIG. 4 is a flow chart showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG5 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG6 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG7 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG8 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG9 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG10 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG11 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG12 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention. FIG13 is a schematic diagram showing an electronic device according to an embodiment of the present invention. FIG14 is a graph showing the field effect mobility of a thin film transistor plotted against the (222) / (440) peak intensity ratio of an oxide semiconductor film. Implementation Method

[0011] The following describes various embodiments of the present invention with reference to the drawings. The following disclosure is ultimately just an example. Any configuration that can be easily conceived by the industry by ensuring the main purpose of the invention and appropriately changing the configuration of the embodiment naturally falls within the scope of the present invention. In order to make the description clearer, the drawings sometimes schematically show the width, film thickness, shape, etc. of each part compared to the actual state. However, the shapes shown in the drawings are ultimately just examples and do not limit the interpretation of the present invention. In this specification and each figure, the same symbols are marked for the same elements as those described in the figures shown above, and the detailed description is sometimes appropriately omitted.

[0012] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below." For convenience, the terms "above" or "below" are used for explanation, but for example, the substrate and the oxide semiconductor layer may be arranged in a direction opposite to the above-below relationship shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on substrate" only describes the above-below relationship between the substrate and the oxide semiconductor layer, and other components may be arranged between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order of a plurality of layers in a structure. When expressed as a pixel electrode above a thin film transistor, it may also refer to a positional relationship in which the thin film transistor and the pixel electrode do not overlap when viewed from above. On the other hand, when expressed as a pixel electrode vertically above the thin film transistor, it refers to a positional relationship in which the thin film transistor and the pixel electrode overlap when viewed from above.

[0013] In this specification, the terms "film" and "layer" can be used interchangeably as appropriate.

[0014] In this specification, a "display device" refers to a structure that uses an electro-optical layer to display images. For example, the term "display device" sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure in which other optical components (such as a polarizer, backlight, or touch panel) are incorporated into a display unit. Unless technical inconsistencies arise, an "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer. Therefore, while the following embodiments illustrate liquid crystal displays including a liquid crystal layer and organic EL displays including an organic EL layer, the structure described in this embodiment can also be applied to display devices including these other electro-optical layers.

[0015] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other elements.

[0016] Furthermore, the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0017] <First embodiment> An oxide semiconductor film according to one embodiment of the present invention will be described.

[0018] [1. Composition of Oxide Semiconductor Film] The oxide semiconductor film of this embodiment contains indium (In) and at least one metal element (M) other than indium. That is, the metal element other than indium contained in the oxide semiconductor film may be one metal element or a plurality of metal elements. Regarding the composition ratio of the oxide semiconductor film, the atomic ratio of indium and at least one metal element preferably satisfies formula (1). In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, a crystalline oxide semiconductor film can be formed. In addition, the crystalline structure of the oxide semiconductor film preferably has a pyroxenite structure. By increasing the ratio of indium, an oxide semiconductor film having a pyroxenite structure can be formed.

[0019] [Number 1]

[0020] The at least one metal element is preferably one or more elements selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanide elements.

[0021] The first metal element included in the at least one metal element is preferably gallium. Because gallium, like indium, belongs to Group 13, it does not hinder the crystallinity of the oxide semiconductor film. In other words, even if the oxide semiconductor film contains gallium as the first metal element, an oxide semiconductor film having a bixbyite-type structure can be formed.

[0022] When the first metal element is gallium, the oxide semiconductor film may also contain a second metal element (M2) selected from the group consisting of aluminum, yttrium, scandium, and lanthanide elements. In this case, the atomic ratios of indium, gallium, and the second metal element in the composition of the oxide semiconductor film preferably satisfy equations (2), (3), and (4). Since the ratio of the second metal element is lower than that of indium or gallium, the second metal element does not hinder the crystallinity of the oxide semiconductor film.

[0023] [Number 2]

[0024] [Number 3]

[0025] [Number 4]

[0026] The detailed method for manufacturing an oxide semiconductor film is described together with the method for manufacturing a thin-film transistor described later. The oxide semiconductor film can be formed using a sputtering method. The composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target. In the case of a sputtering target having the above composition, an oxide semiconductor film having no compositional deviation of the metal elements can be formed by sputtering. Therefore, the composition of the metal elements (indium and other metal elements) of the oxide semiconductor film can also be the same as the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor film can be specified based on the composition of the metal elements of the sputtering target. Furthermore, the oxygen element contained in the oxide semiconductor film will vary depending on the sputtering process conditions, etc., and is therefore not limited.

[0027] The metal element composition of the oxide semiconductor film can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. Furthermore, since the oxide semiconductor film has a polycrystalline structure, the composition of the oxide semiconductor film can also be determined using X-ray diffraction (XRD). Specifically, the metal element composition of the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained using XRD.

[0028] [2. Crystal Structure of Oxide Semiconductor Film] The oxide semiconductor film of this embodiment has a polycrystalline structure comprising multiple crystal grains. By using Poly-OS (Poly-crystalline Oxide Semiconductor) technology, an oxide semiconductor film with a novel polycrystalline structure, different from conventional ones, can be formed. Details of this process will be described later. Therefore, to distinguish it from conventional oxide semiconductor films with polycrystalline structures, the oxide semiconductor film with a polycrystalline structure of this embodiment will sometimes be referred to as a Poly-OS film.

[0029] The crystal structure of the Poly-OS film is not particularly limited, but is preferably a bixbyite structure. The crystal structure of the Poly-OS film can be determined using XRD or electron beam diffraction.

[0030] The crystal structure of a Poly-OS film differs from that of conventional oxide semiconductor films having a polycrystalline structure. Specifically, the present inventors discovered that, although the Poly-OS film has a polycrystalline structure, its polycrystalline structure differs from that of conventional oxide semiconductor films. Consequently, the present inventors conducted various repeated experiments and ultimately developed an oxide semiconductor film (Poly-OS film) having a novel polycrystalline structure that differs from conventional oxide semiconductor films. The crystallinity of the Poly-OS film can be characterized using XRD.

[0031] XRD includes two measurement methods: out-of-plane and in-plane. Out-of-plane measurement evaluates crystal planes parallel to the film surface, while in-plane measurement evaluates crystal planes perpendicular to the film surface. The characteristics of the Poly-OS film can be determined using out-of-plane measurements.

[0032] In this specification, among the crystal planes of the bixbyite structure, the (001) plane includes the (001) plane and its equivalent (100) and (010) planes. Similarly, the (101) plane includes the (101) plane and its equivalent (110) and (011) planes. Furthermore, the (111) plane refers to the (111) plane. Furthermore, within each plane, "1" may also be "-1" to be considered as a plane equivalent to that plane.

[0033] Furthermore, among the crystal planes, in addition to the (001) plane, the (101) plane, and the (111) plane, there are also the (hk0) plane (h≠k, h and k are natural numbers), the (hhl) plane (h≠l, h and l are natural numbers), and the (hkl) plane (h≠k≠l, h, k, and l are natural numbers).

[0034] [2-1. Intensity of peaks in the diffraction pattern] When the oxide semiconductor film is crystalline, a peak appears at a predetermined diffraction angle (2θ) in the diffraction pattern measured out of plane. For example, in a previous crystalline oxide semiconductor film containing 50% or more indium and having a bixbyite structure, the diffraction pattern has peaks at diffraction angles of approximately 31° and 44°. The peak at the diffraction angle of approximately 31° belongs to the (222) plane of the bixbyite structure. The peak at the diffraction angle of approximately 44° belongs to the (422) plane of the bixbyite structure. Furthermore, the peak intensity at the diffraction angle of approximately 31° is significantly greater than the peak intensity at the diffraction angle of approximately 44°. This means that there are many crystals having a (222) plane in a direction parallel to the surface of the oxide semiconductor film.

[0035] Furthermore, the diffraction angle of the diffraction pattern of an oxide semiconductor film may vary depending on the composition of the metal elements contained in the oxide semiconductor film or the conditions under which the oxide semiconductor film is produced. Therefore, in this specification, the vicinity of the diffraction angle peak includes a range of ±2°.

[0036] The diffraction pattern of the Poly-OS film having a bixbyite structure also has a peak at a diffraction angle of approximately 31° corresponding to the (222) plane of the bixbyite structure. However, the peak intensity of the diffraction angle of the Poly-OS film at approximately 31° is less than the peak intensity of the diffraction angle of the conventional crystalline oxide semiconductor film at approximately 31° under the same film thickness conditions. For example, the peak intensity of the diffraction angle of the Poly-OS film at approximately 31° is less than 1 / 2 of the peak intensity of the diffraction angle of the conventional crystalline oxide semiconductor film at approximately 31° under the same film thickness conditions.

[0037] In addition, the diffraction pattern of the Poly-OS film sometimes shows a peak at a diffraction angle of approximately 44°. When a peak appears at a diffraction angle of approximately 44°, the ratio of the peak intensity at a diffraction angle of approximately 31° to the peak intensity at a diffraction angle of approximately 44° is 3.0 or less. However, in the diffraction pattern of the Poly-OS film, a peak sometimes does not appear at a diffraction angle of approximately 44°. On the other hand, in the diffraction pattern of the Poly-OS film, a peak sometimes appears at a diffraction angle of approximately 52°, corresponding to the (440) plane of the bixbyite structure. These phenomena indicate that in the Poly-OS film, the number of crystals having (222) planes parallel to the surface of the Poly-OS film is relatively small, and the orientation is relaxed. As a result, a state is achieved in which the number of crystals having (440) planes parallel to the surface of the Poly-OS film is relatively large, and the Poly-OS film has a specific crystal arrangement different from that previously described.

[0038] In the diffraction pattern of the Poly-OS film, in order to observe not only the peak of the (222) plane but also the peak of the (440) plane, it is necessary to reduce noise. In order to reduce noise in XRD measurement, the scanning speed of the goniometer is set to 1.0° / min or less, preferably 0.5° / min or less, and the intensity of each diffraction angle is increased. The measurement width is, for example, 0.05° or more, but is not limited thereto. If the measurement is performed in this way, a diffraction pattern with an S / N ratio of 15 or more, preferably 30 or more, is obtained, and the reliability of the data is very high. Furthermore, the above-mentioned range of scanning speed and measurement width is an example of a condition for improving the S / N ratio, and is not limited to such range. Here, the S / N ratio is defined as the ratio of the maximum intensity (S) of the peak of the (222) plane to the noise width (N). The maximum intensity (S) of the peak of the (222) plane is obtained based on the diffraction pattern of the Poly-OS film after background removal. The noise width (N) is calculated by applying the least squares method to the intensity data corresponding to diffraction angles between 29° and 30° in the diffraction pattern of the Poly-OS film before background subtraction. This method then performs a linear approximation to define a baseline. The standard deviation of the difference from the baseline is doubled (i.e., 2σ).

[0039] FIG1 shows an example of a diffraction pattern of an oxide semiconductor film (Poly-OS film) according to one embodiment of the present invention, obtained by out-of-plane XRD measurement. The measurement conditions were a goniometer scanning speed of 0.5° / min and a measurement width of 0.05°. As shown in FIG1 , a peak for the (222) plane and a peak for the (440) plane were observed near 31° and 52°, respectively. The calculated S / N ratio was 27.0, indicating that the intensity of the (440) plane peak was sufficiently high and reliable.

[0040] As described above, the Poly-OS film exhibits a characteristic diffraction pattern that is different from that of conventional crystalline oxide semiconductor films. In the Poly-OS film having a bixbyite structure, a (440) plane peak is more likely to appear than in conventional crystalline oxide semiconductor films. This means that the orientation of the (222) plane relative to the surface of the Poly-OS film is relaxed, and the (440) plane is arranged in a direction parallel to the surface of the Poly-OS film. As a result, the crystals contained in the Poly-OS film have a characteristic crystal arrangement that is different from that of conventional films.

[0041] As one of the parameters that characterize the crystallinity of such a Poly-OS film, the ratio of the intensity of the peak of the (222) plane to the intensity of the peak of the (440) plane (hereinafter referred to as the "(222) / (440) peak intensity ratio") can be cited. In previous crystalline oxide semiconductor films, the intensity of the peak of the (222) plane is relatively large, and the peak of the (440) plane is almost not observed. Therefore, the (222) / (440) peak intensity ratio of the previous crystalline oxide semiconductor film cannot be calculated, or the ratio exceeds 500. On the other hand, the (222) / (440) peak intensity ratio of the Poly-OS film is 300 or less. In a thin film transistor using a Poly-OS film as a channel, when the (222) / (440) peak intensity ratio of the Poly-OS film is 125 or less, a field effect mobility of 30 cm2 / Vs or more can be obtained, as will be described in detail later. Furthermore, the (222) / (440) peak intensity ratio of the Poly-OS film is preferably 50 or less, and further preferably 15 or less. When the (222) / (440) peak intensity ratio of the Poly-OS film is 50 or less, a field-effect mobility of 34 cm 2 / Vs or more can be obtained. Furthermore, when the (222) / (440) peak intensity ratio of the Poly-OS film is 15 or less, a field-effect mobility of 38 cm 2 / Vs or more can sometimes be obtained. Furthermore, the lower limit of the (222) / (440) peak intensity ratio of the Poly-OS film is not particularly limited, but is preferably 1 or more. When the (222) / (440) peak intensity ratio of the Poly-OS film is greater than 1, it means that the Poly-OS film has a cubic crystal structure and has both the (222) plane and the (440) plane parallel to the film thickness direction (the direction perpendicular to the film surface). It can be judged that the Poly-OS film is in a state where the long-range order of atoms is maintained.

[0042] [2-2. Crystallite diameter] The crystal grains contained in the Poly-OS film may also include a plurality of crystallites. The crystallite diameter D can be calculated using the Scherrer formula shown in Equation (5) using the peak width of the diffraction pattern. Here, K is the Scherrer constant, λ is the wavelength of the X-ray, β is the peak half-maximum width, and θ is the Bragg angle (equivalent to 1 / 2 of the diffraction angle 2θ).

[0043] [Number 5]

[0044] In a Poly-OS film having a bixbyite structure, the half-width of the peak corresponding to the (222) plane can be used to calculate the crystallite diameter D of the grains contained in the Poly-OS film. In the out-of-plane diffraction pattern using Cu-Kα radiation, the crystallite diameter D is preferably approximately equal to the film thickness t of the Poly-OS. For example, the ratio of the crystallite diameter D to the film thickness t of the Poly-OS film (D / t) is 0.75 or more, preferably 0.85 or more, and further preferably 0.95 or more. Although the film thickness t of the Poly-OS film is not particularly limited, if the film thickness t becomes smaller, a Poly-OS film with a larger D / t and a relatively small (222) / (440) peak intensity can be obtained. The film thickness t of the Poly-OS film is, for example, 30 nm or less, preferably 20 nm or less, and further preferably 15 nm or less. In particular, when the film thickness is less than 20 nm, a Poly-OS film with a D / t ratio of 0.95 or greater can be achieved. Furthermore, when the Poly-OS film thickness is relatively small, a crystallite diameter D exceeding the film thickness t of the Poly-OS film can sometimes be achieved. In this case, when the crystallite diameter D is near the film thickness t of the Poly-OS film, meaning that the crystallite diameter D is approximately equal to the film thickness t of the Poly-OS film, it can be determined that D / t is 0.95 or greater.

[0045] As described above, the peak intensity of the (222) plane in the diffraction pattern of the Poly-OS film is relatively low. However, the crystallite diameter D of the Poly-OS film is approximately equal to the film thickness t of the Poly-OS film. Therefore, the Poly-OS film has a novel crystalline structure in which the orientation of the crystals is relaxed while the long-range order of atoms is maintained in the film thickness direction (the direction perpendicular to the film surface).

[0046] As described above, the oxide semiconductor film, or Poly-OS film, according to one embodiment of the present invention has a novel crystal structure. Even when this Poly-OS film with a novel crystal structure is used as a channel for a thin-film transistor (TFT), the field-effect mobility does not decrease, but rather improves. This will be described in detail later. Consequently, the electrical properties of the TFT including the Poly-OS film are improved.

[0047] <Second embodiment> 2 to 12 , a thin film transistor 10 according to an embodiment of the present invention is described. The thin film transistor 10 can be used, for example, in an integrated circuit (IC) of a display device, a microprocessing unit (MPU), or a memory circuit.

[0048] [1. Configuration of Thin Film Transistor 10] The structure of a thin film transistor 10 according to one embodiment of the present invention will be described with reference to Figures 2 and 3. Figure 2 is a schematic cross-sectional view showing the structure of a thin film transistor 10 according to one embodiment of the present invention. Figure 3 is a schematic top view showing the structure of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 2 is a cross-sectional view taken along line AA' in Figure 3.

[0049] As shown in FIG2 , the thin film transistor 10 includes a substrate 100, a light shielding layer 105, a first insulating layer 110, a second insulating layer 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203. The light shielding layer 105 is disposed on the substrate 100. The first insulating layer 110 covers the upper surface and end faces of the light shielding layer 105 and is disposed on the substrate 100. The second insulating layer 120 is disposed on the first insulating layer 110. The metal oxide layer 130 is disposed on the second insulating layer 120. The oxide semiconductor layer 140 is disposed in contact with the metal oxide layer 130. The gate insulating layer 150 covers the end faces of the metal oxide layer 130 and the upper surface and end faces of the oxide semiconductor layer 140 and is disposed on the second insulating layer 120. The gate electrode 160 overlaps with the oxide semiconductor layer 140 and is disposed on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surface of the gate electrode 160 and is disposed on the gate insulating layer 150. The fourth insulating layer 180 is disposed on the third insulating layer 170. The gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 have openings 171 and 173 that partially expose the upper surface of the oxide semiconductor layer 140. The source electrode 201 is disposed on the fourth insulating layer 180 and within the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is disposed on the fourth insulating layer 180 and within the opening 173, and is in contact with the oxide semiconductor layer 140. In the following text, when the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they are sometimes collectively referred to as the source / drain electrode 200.

[0050] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the gate electrode 160. Specifically, the oxide semiconductor layer 140 includes a channel region CH that overlaps with the gate electrode 160, and a source region S and a drain region D that do not overlap with the gate electrode 160. In the thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has semiconductor properties. The source region S and the drain region D each have conductor properties. Therefore, the conductivity of the source region S and the drain region D is greater than that of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a stacked-layer structure.

[0051] As shown in Figure 3, the light shielding layer 105 and the gate electrode 160 each have a certain width in the D1 direction and extend in the D2 direction, which is orthogonal to the D1 direction. In the D1 direction, the width of the light shielding layer 105 is greater than the width of the gate electrode 160. The channel region CH completely overlaps with the light shielding layer 105. In the thin film transistor 10, the D1 direction corresponds to the direction in which current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0052] The substrate 100 can support each layer constituting the thin film transistor 10. As the substrate 100, for example, a glass substrate, a quartz substrate, or a sapphire substrate, which is a rigid substrate with light transparency, can be used. Alternatively, a silicon substrate, or other rigid substrate that is not light transparent can be used as the substrate. Alternatively, a polyimide resin substrate, an acrylic resin substrate, a silicone resin substrate, or a fluororesin substrate, which is a flexible substrate with light transparency, can be used as the substrate. In order to improve the heat resistance of the substrate 100, impurities can be introduced into the above-mentioned resin substrate. Furthermore, a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can be used as the substrate 100.

[0053] The light-shielding layer 105 can reflect or absorb external light. As described above, since the light-shielding layer 105 is configured to have an area larger than the channel region CH of the oxide semiconductor layer 140, it can block external light incident on the channel region CH. The light-shielding layer 105 can be made of, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof. Furthermore, the light-shielding layer 105 does not necessarily need to contain a metal when conductivity is not required. For example, a black matrix composed of a black resin can be used as the light-shielding layer 105. Furthermore, the light-shielding layer 105 can have a single-layer structure or a multilayer structure. For example, the light-shielding layer 105 can have a multilayer structure of a red color filter, a green color filter, and a blue color filter.

[0054] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 prevent the diffusion of impurities contained in the substrate 100, while the third insulating layer 170 and the fourth insulating layer 180 prevent the diffusion of impurities (e.g., water) that penetrate from the outside. The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 are each made of, for example, silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon oxynitride (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum oxynitride (AlNxOy), or aluminum nitride (AlNx). Here, silicon oxynitride (SiOxNy) and aluminum oxynitride (AlOxNy) are silicon compounds and aluminum compounds, respectively, containing nitrogen (N) at a ratio less than oxygen (O) (x>y). Furthermore, silicon oxynitride (SiNxOy) and aluminum oxynitride (AlNxOy) are silicon compounds and aluminum compounds, respectively, containing oxygen at a ratio less than nitrogen (x>y). Furthermore, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can each have a single-layer structure or a stacked-layer structure.

[0055] Furthermore, each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarization function and may also have a function of releasing oxygen through heat treatment. For example, if the second insulating layer 120 has a function of releasing oxygen through heat treatment, oxygen released from the second insulating layer 120 during the heat treatment performed during the manufacturing steps of the thin film transistor 10 can be supplied to the oxide semiconductor layer 140.

[0056] The gate electrode 160, source electrode 201, and drain electrode 203 are conductive. They can each be made of, for example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), or alloys or compounds thereof. Each of the gate electrode 160, source electrode 201, and drain electrode 203 can have a single-layer structure or a multilayer structure.

[0057] The gate insulating layer 150 comprises an insulating oxide. Specifically, silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), etc. are used as the gate insulating layer 150. The gate insulating layer 150 preferably has a composition close to that of a stoichiometric ratio. Furthermore, the gate insulating layer 150 preferably has few defects. For example, an oxide that exhibits no defects when evaluated using electron spin resonance (ESR) can also be used as the gate insulating layer 150.

[0058] The metal oxide layer 130 comprises an insulating metal oxide. Specifically, a metal oxide with a band gap of 4 eV or greater is used as the metal oxide layer 130. Furthermore, metal oxides containing one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), calcium (Ca), scandium (Sc), gallium (Ga), germanium (Ge), strontium (Sr), nickel (Ni), tantalum (Ta), yttrium (Y), zirconium (Zr), barium (Ba), hafnium (Hf), cobalt (Co), and lanthanide elements are used as the metal oxide layer 130. In particular, a metal oxide containing aluminum (e.g., aluminum oxide) is preferably used as the metal oxide layer 130. Metal oxides containing aluminum have high barrier properties against gases such as oxygen and hydrogen.

[0059] Furthermore, the metal oxide layer 130 can function as a buffer layer for the oxide semiconductor layer 140. For example, by heat treating the oxide semiconductor layer 140 in contact with the metal oxide layer 130, the crystallinity of the oxide semiconductor layer 140 can be improved.

[0060] The thickness of the metal oxide layer 130 is not particularly limited. The thickness of the metal oxide layer 130 may be 20 nm or less, 15 nm or less, or even 10 nm or less. For example, the thickness of the metal oxide layer 130 is 2 nm or more and 20 nm or less, preferably 2 nm or more and 15 nm or less, and even more preferably 2 nm or more and 10 nm or less.

[0061] As the oxide semiconductor layer 140 , the Poly-OS film described in the first embodiment can be used.

[0062] The structure of the thin-film transistor 10 has been described above. However, the thin-film transistor 10 described above is a so-called top-gate transistor. The thin-film transistor 10 can be modified in various ways. For example, if the light-shielding layer 105 is conductive, the thin-film transistor 10 can be configured such that the light-shielding layer 105 functions as a gate electrode, and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin-film transistor 10 is a so-called dual-gate transistor. Furthermore, if the light-shielding layer 105 is conductive, the light-shielding layer 105 can serve as a floating electrode connected to the source electrode 201. Furthermore, the thin-film transistor 10 can be a so-called bottom-gate transistor, in which the light-shielding layer 105 functions as the main gate electrode.

[0063] [2. Manufacturing Method of Thin Film Transistor 10] A method for manufacturing a thin film transistor 10 according to an embodiment of the present invention will be described with reference to Figures 4 to 12. Figure 4 is a flow chart illustrating a method for manufacturing a thin film transistor 10 according to an embodiment of the present invention. Figures 5 to 12 are schematic cross-sectional views illustrating a method for manufacturing a thin film transistor 10 according to an embodiment of the present invention.

[0064] As shown in FIG4 , the method for manufacturing a thin film transistor 10 includes steps S1010 to S1110. Steps S1010 to S1110 are described below in order, but the order of the steps may be altered in the method for manufacturing a thin film transistor 10. Furthermore, the method for manufacturing a thin film transistor 10 may include further steps.

[0065] In step S1010, a light shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light shielding layer 105 is patterned using photolithography. Furthermore, a first insulating layer 110 and a second insulating layer 120 are formed on the light shielding layer 105 (see FIG5 ). The first insulating layer 110 and the second insulating layer 120 are formed using CVD (Chemical Vapor Deposition). For example, silicon nitride and silicon oxide are formed as the first insulating layer 110 and the second insulating layer 120, respectively. When silicon nitride is used as the first insulating layer 110, the first insulating layer 110 can block the diffusion of impurities from the substrate 100 side into the oxide semiconductor layer 140. When silicon oxide is used as the second insulating layer 120, oxygen can be released from the second insulating layer 120 by heat treatment.

[0066] In step S1015, a metal oxide film 135 is formed on the second insulating layer 120 (see FIG6 ). The metal oxide film 135 is formed by sputtering. For example, the thickness of the metal oxide film 135 is 2 nm to 20 nm, preferably 2 nm to 15 nm, and even more preferably 2 nm to 10 nm.

[0067] In step S1020, an oxide semiconductor film 145 is formed on the metal oxide film 135 (see FIG6 ). The oxide semiconductor film 145 is formed by sputtering. The thickness of the oxide semiconductor film 145 is, for example, not less than 10 nm and not more than 100 nm, preferably not less than 15 nm and not more than 70 nm, and even more preferably not less than 15 nm and not more than 40 nm.

[0068] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, the oxide semiconductor film 145 is preferably amorphous after film formation and before heat treatment, so that the oxide semiconductor layer 140 has a uniform polycrystalline structure across the substrate surface. Therefore, the film formation conditions for the oxide semiconductor film 145 are preferably such that crystallization of the oxide semiconductor layer 140 immediately after film formation is minimized. When the oxide semiconductor film 145 is formed by sputtering, the temperature of the object to be formed (the substrate 100 and the layers formed thereon) is controlled to be below 100°C, preferably below 80°C, and more preferably below 50°C, while the oxide semiconductor film 145 is formed. Furthermore, the oxide semiconductor film 145 is formed under conditions of a low oxygen partial pressure. The oxygen partial pressure is between 2% and 20%, preferably between 3% and 15%, and more preferably between 3% and less than 10%.

[0069] In step S1030, the oxide semiconductor film 145 is patterned (see FIG7 ). The patterning of the oxide semiconductor film 145 is performed using photolithography. The oxide semiconductor film 145 can be etched using either wet or dry etching. Wet etching can be performed using an acidic etchant. Examples of etchants include oxalic acid, PAN (phosphoric-acetic-nitric acid), sulfuric acid, hydrogen peroxide, or hydrofluoric acid.

[0070] In step S1040, the oxide semiconductor film 145 is thermally treated. Hereinafter, the thermal treatment performed in step S1040 is referred to as "OS annealing." During the OS annealing process, the oxide semiconductor film 145 is maintained at a predetermined endpoint temperature for a predetermined time. The predetermined endpoint temperature is between 300°C and 500°C, preferably between 350°C and 450°C. Furthermore, the predetermined time (holding time) at the endpoint temperature is between 15 minutes and 120 minutes, preferably between 30 minutes and 60 minutes. The OS annealing crystallizes the oxide semiconductor film 145, forming an oxide semiconductor layer 140 having a polycrystalline structure (i.e., an oxide semiconductor layer 140 comprising a Poly-OS film).

[0071] In step S1045, the metal oxide film 135 is patterned to form the metal oxide layer 130 ( FIG. 8 ). The metal oxide film 135 is etched using the oxide semiconductor layer 140 as a mask. By using the patterned oxide semiconductor layer 140 as a mask, the photolithography step can be omitted. The metal oxide film 135 can be etched using either wet or dry etching. For example, diluted hydrofluoric acid (DHF) is used in wet etching.

[0072] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see FIG9 ). The gate insulating layer 150 is formed using a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. To reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a deposition temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is between 50 nm and 300 nm, preferably between 60 nm and 200 nm, and even more preferably between 70 nm and 150 nm. After forming the gate insulating layer 150, a treatment to introduce oxygen into a portion of the gate insulating layer 150 may be performed.

[0073] In step S1060, the oxide semiconductor layer 140 is thermally treated. Hereinafter, the thermal treatment performed in step S1060 is referred to as "oxidation annealing." Forming the gate insulating layer 150 on the oxide semiconductor layer 140 generates numerous oxygen vacancies on the upper surface and side surfaces of the oxide semiconductor layer 140. Performing the oxidation annealing causes oxygen to be supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, thereby repairing the oxygen vacancies.

[0074] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see FIG10 ). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the patterning of the gate electrode 160 is performed by photolithography.

[0075] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see FIG10 ). The source region S and the drain region D are formed by ion implantation. Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask. As the implanted impurities, for example, argon (Ar), phosphorus (P), or boron (B) are used. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen vacancies are generated by the ion implantation, and hydrogen is trapped by the generated oxygen vacancies. This reduces the resistance of the source region S and the drain region D. On the other hand, in the channel region CH that overlaps with the gate electrode 160, no impurities are implanted, so no oxygen vacancies are generated, and the resistance of the channel region CH does not decrease.

[0076] Furthermore, in the thin film transistor 10, since impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150, the gate insulating layer 150 may also contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0077] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see FIG11 ). The third insulating layer 170 and the fourth insulating layer 180 are formed using a CVD method. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is not less than 50 nm and not more than 500 nm. The thickness of the fourth insulating layer 180 is also not less than 50 nm and not more than 500 nm.

[0078] In step S1100, openings 171 and 173 (see FIG. 12 ) are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180. By forming the openings 171 and 173, the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0079] In step S1110, a source electrode 201 is formed above the fourth insulating layer 180 and within the opening 171. A drain electrode 203 is formed above the fourth insulating layer 180 and within the opening 173. The source electrode 201 and the drain electrode 203 can be formed on the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a deposited conductive film. The above steps produce the thin film transistor 10 shown in FIG. 1 .

[0080] The above describes the method for manufacturing the thin film transistor 10 , but the method for manufacturing the thin film transistor 10 is not limited thereto.

[0081] In the thin-film transistor 10 of this embodiment, the oxide semiconductor layer 140 comprises a Poly-OS film having a novel crystal structure. Specifically, the Poly-OS film is used as the semiconductor material for the thin-film transistor 10. The thin-film transistor 10 comprising this Poly-OS film having a novel crystal structure exhibits improved electrical properties, as will be described in detail later. For example, the field-effect mobility of the thin-film transistor 10 is improved. Furthermore, semiconductor materials comprising the Poly-OS film can also be used in electronic devices other than thin-film transistors.

[0082] <Third embodiment> 13, an electronic device according to an embodiment of the present invention will be described.

[0083] Figure 13 is a schematic diagram of an electronic device 1000 according to one embodiment of the present invention. Specifically, Figure 13 shows a smartphone as an example of electronic device 1000. Electronic device 1000 includes a display device 1100 with curved sides. Display device 1100 includes a plurality of pixels for displaying images, and these pixels are controlled by pixel circuits and driver circuits. The pixel circuits and driver circuits include the thin-film transistor 10 described in the second embodiment. Because thin-film transistor 10 has a high field-effect mobility, it improves the responsiveness of the pixel circuit and driver circuit, thereby enhancing the performance of electronic device 1000.

[0084] Furthermore, the electronic device 1000 of this embodiment is not limited to smartphones. The electronic device 1000 also includes electronic devices with display devices, such as watches, tablets, laptops, car navigation systems, and televisions. Furthermore, the thin-film transistor 10 described in the first embodiment can be applied to any electronic device, regardless of whether it has a display device or not. [Example]

[0085] As samples, thin film samples including oxide semiconductor films and thin film transistors were fabricated. The following describes the Poly-OS film in more detail based on the fabricated samples.

[0086] [1. Sample production] Thin film samples or oxide semiconductor films in thin film transistors were fabricated using a sputtering process followed by an OS annealing process. The sputtering process used a sputtering target containing 70% indium atomically relative to the total metal content of the sintered body. For all samples, the chemical composition of the oxide semiconductor film after the OS annealing process was identical to that of the sputtering target. Furthermore, the endpoint temperature during the OS annealing process was controlled between 350°C and 450°C.

[0087] [1-1. Example 1] [1-1-1. Film sample] A laminated film of silicon oxide (SiOx) and aluminum oxide (AlOx) is formed on a glass substrate as a base film. The silicon oxide film is deposited on the glass substrate using plasma CVD using silane (SiH4) and nitrous oxide (N2O) gases. The aluminum oxide film is deposited on the silicon oxide film using sputtering using an aluminum (Al) target.

[0088] A 15 nm oxide semiconductor film was deposited on a glass substrate with a base film (AlOx / SiOx) by sputtering. The oxide semiconductor film was deposited under an oxygen partial pressure of 3% (Example 1-1) or 5% (Example 1-2). The deposited oxide semiconductor film then underwent an OS annealing process in an air atmosphere.

[0089] [1-1-2. Thin Film Transistors] In the manufacturing method described in the second embodiment, the conditions of Example 1-1 or Example 1-2 are applied to manufacture a thin film transistor.

[0090] Furthermore, 9 thin film samples and thin film transistors were made under the conditions of Example 1-1 (Example 1-1-1 to Example 1-1-9), and 2 samples were made under the conditions of Example 1-2 (Example 1-2-1 and Example 1-2-2).

[0091] [1-2. Example 2] [1-2-1. Film sample] A 20 nm oxide semiconductor film was deposited on a glass substrate with a base film (AlOx / SiOx) by sputtering. The oxide semiconductor film was deposited under an oxygen partial pressure of 3% (Example 2-1) or 5% (Example 2-2). The deposited oxide semiconductor film then underwent an OS annealing process in an air atmosphere.

[0092] [1-2-2. Thin Film Transistors] In the manufacturing method described in the second embodiment, the conditions of Example 2-1 or Example 2-2 are applied to manufacture a thin film transistor.

[0093] Furthermore, two samples of thin film samples and thin film transistors were made under the conditions of Example 2-1 (Example Sample 2-1-1 and Example Sample 2-1-2), and two samples were made under the conditions of Example 2-2 (Example Sample 2-2-1 and Example Sample 2-2-2).

[0094] [1-3. Example 3] [1-3-1. Film sample] A 25 nm oxide semiconductor film was deposited on a glass substrate with a base film (AlOx / SiOx) by sputtering. The oxide semiconductor film was deposited under an oxygen partial pressure of 3% (Example 3-1) or 4% (Example 3-2). The deposited oxide semiconductor film then underwent an OS annealing process in an air atmosphere.

[0095] [1-3-2. Thin Film Transistors] In the manufacturing method described in the second embodiment, the conditions of Example 3-1 or Example 3-2 are applied to manufacture a thin film transistor.

[0096] Furthermore, two samples of thin film samples and thin film transistors were made under the conditions of Example 3-1 (Example Sample 3-1-1 and Example Sample 3-1-2), and two samples were made under the conditions of Example 3-2 (Example Sample 3-2-1 and Example Sample 2-2-2).

[0097] [1-4. Example 4] [1-4-1. Film sample] A 30 nm oxide semiconductor film was deposited on a glass substrate with a base film (AlOx / SiOx) by sputtering. The oxide semiconductor film was deposited under an oxygen partial pressure of 3% (Example 4-1) or 4% (Example 4-2). The deposited oxide semiconductor film then underwent an OS annealing process in an air atmosphere.

[0098] [1-4-2. Thin Film Transistors] In the manufacturing method described in the second embodiment, the conditions of Example 4-1 or Example 4-2 are applied to manufacture a thin film transistor.

[0099] Furthermore, two samples of thin film samples and thin film transistors were made under the conditions of Example 4-1 (Example Sample 4-1-1 and Example Sample 4-1-2), and two samples were made under the conditions of Example 4-2 (Example Sample 4-2-1 and Example Sample 4-2-2).

[0100] [1-5. Comparative Example] [1-5-1. Film sample] A 30 nm thick oxide semiconductor film was deposited via sputtering on a glass substrate with only a silicon oxide (SiOx) film as a base film. The oxide semiconductor film was deposited under an oxygen partial pressure of 5%. The deposited oxide semiconductor film then underwent an OS annealing process in an air atmosphere.

[0101] [1-5-2. Thin Film Transistors] In the manufacturing method described in the second embodiment, a thin film transistor is produced without providing a metal oxide layer. That is, the oxide semiconductor layer in the thin film transistor of the comparative example is formed in contact with the second insulating layer (SiO x ).

[0102] The conditions of the samples produced are shown in Table 1.

[0103] [Table 1] Sample name basement membrane Thickness of oxide semiconductor film Oxygen partial pressure during oxide semiconductor film formation Example 1-1 AlOx / SiOx 15 nm 3% Example 1-2 AlOx / SiOx 15 nm 5% Example 2-1 AlOx / SiOx 20 nm 3% Example 2-2 AlOx / SiOx 20 nm 5% Example 3-1 AlOx / SiOx 25 nm 3% Example 3-2 AlOx / SiOx 25 nm 4% Example 4-1 AlOx / SiOx 30 nm 3% Example 4-2 AlOx / SiOx 30 nm 4% Comparative Example SiOx 30 nm 5%

[0104] [2. Crystal structure analysis using XRD method] The crystal structure of the oxide semiconductor film of the fabricated thin film sample was analyzed using XRD. This analysis was performed using a SmartLab instrument (Rigaku Corporation) under the conditions shown in Table 2 that improve the S / N ratio.

[0105] [Table 2] X-ray source Cu-Kα Tube voltage 45 kV Tube current 200 mA Optical system parallel beam method Slit composition Soller slit 5°, Entrance slit 1 mm, Light receiving slit 1 mm, Incident length limiting slit 10 mm Scan range (2θ measurement: (out-of-plane)) 29~33°, 50~54° Measuring width 0.05° Scan speed 0.5° / min

[0106] To calculate the maximum intensity of the peaks for the (222) and (440) planes based on the measurement results, the peaks were smoothed using the Savitzky-Golay method at five points using the analytical program (JADE 6). Crystalline phase identification was performed using the ICSD (Inorganic Crystal Structure Database) 14388 bixbyite-type crystal structure file. Background subtraction was then performed using linear approximation within the scanning ranges of 29-33° and 50-54°, ​​respectively.

[0107] In the diffraction patterns of all the thin film samples, peaks of the (222) plane and the (440) plane of the bixbyite structure were observed. In other words, all the thin film samples were Poly-OS films. The ratio of the crystallite diameter D to the film thickness t of the oxide semiconductor film (D / t) was calculated, and the results showed that D / t was greater than 0.75 for all the thin film samples. Furthermore, D / t was greater than 0.95 for the thin film samples of Examples 1-1-1 to 1-1-9.

[0108] The (222) / (440) peak intensity ratio of the oxide semiconductor film was calculated based on the diffraction patterns of the thin film samples, and the field-effect mobility was calculated based on the electrical characteristics of the thin film transistor. Table 3 shows the (222) / (440) peak intensity ratio and field-effect mobility for each sample. Furthermore, FIG14 shows a graph plotting the field-effect mobility against the (222) / (440) peak intensity ratio.

[0109] [Table 3] Sample name (222) / (440) peak intensity ratio Field-effect mobility [cm 2 / Vs] S / N ratio Sample name (222) / (440) peak intensity ratio Field-effect mobility [cm 2 / Vs] S / N ratio Example 1-1-1 10.97 41.3 34 Example 2-1-1 5.29 35.6 33 Example 1-1-2 10.57 41.2 33 Example 2-1-2 5.57 37.2 26 Example 1-1-3 9.95 41.1 30 Example 2-2-1 44.14 36.5 74 Example 1-1-4 9.49 40.3 19 Example 2-2-2 105.64 34.9 133 Example 1-1-5 7.00 39.5 25 Example 3-1-1 4.08 35.9 42 Example 1-1-6 12.64 39.3 27 Example 3-1-2 4.39 34.9 36 Example 1-1-7 7.04 38.7 twenty one Example 3-2-1 63.02 35.8 152 Example 1-1-8 7.68 38.5 15 Example 3-2-2 31.80 34.3 93 Example 1-1-9 8.25 38.4 19 Example 4-1-1 4.77 35.0 69 Example 1-2-1 17.24 37.3 44 Example 4-1-2 4.08 34.5 41 Example 1-2-2 21.63 35.8 41 Example 4-2-1 82.00 33.7 244 Example 4-2-2 120.96 35.2 207 Comparative Example 154.10 20.7 181

[0110] As shown in Table 3 and Figure 14, when the (222) / (440) peak intensity ratio of the oxide semiconductor film is 125 or less, the field-effect mobility of the thin film transistor exceeds 30 cm 2 / Vs. It can be seen that although all samples are Poly-OS films, the field-effect mobility can be improved by controlling the crystallinity of the Poly-OS film (more specifically, the (222) / (440) peak intensity ratio). For example, when the (222) / (440) peak intensity ratio is 50 or less, the field-effect mobility of the thin film transistor exceeds 34 cm 2 / Vs. In particular, in the thin film transistors of Examples 1-1-1 to 1-1-9, where the (222) / (440) peak intensity ratio is 15 or less, a field-effect mobility of 38 cm 2 / Vs or more can be obtained.

[0111] The (222) / (440) peak intensity ratio of the Poly-OS film changes depending on the base film. As the Poly-OS film is formed on the metal oxide film, the (222) / (440) peak intensity ratio of the Poly-OS film decreases. In addition, the (222) / (440) peak intensity ratio of the Poly-OS film can be controlled by the film thickness of the Poly-OS film and the oxygen partial pressure during film formation. If the film thickness of the Poly-OS film is smaller or the oxygen partial pressure during film formation is reduced, the (222) / (440) peak intensity ratio of the Poly-OS film decreases. In this way, by controlling the (222) / (440) peak intensity ratio of the Poly-OS film, the electrical characteristics of the thin film transistor can be improved.

[0112] The various embodiments and variations described above as embodiments of the present invention may be combined and implemented as appropriate, as long as they do not conflict with each other. Furthermore, any addition, deletion, or design modification of components, or any addition, omission, or condition modification made by the industry as appropriate based on the various embodiments shall fall within the scope of the present invention as long as they retain the spirit of the present invention.

[0113] As for other effects different from the effects brought about by the aspects of the above-mentioned embodiments, as long as they are known from the description of this specification or can be easily predicted by the industry, they should naturally be understood to be obtained by the present invention.

[0114] 10: Thin Film Transistor 100:Substrate 105: light shielding layer 110: First insulation layer 120: Second insulation layer 130:Metal oxide layer 135:Metal oxide film 140: oxide semiconductor layer 145: Oxide semiconductor film 150: Gate insulation layer 160: Gate electrode 170: 3rd insulation layer 171: Open 173: Opening 180: 4th insulation layer 200: Source and drain electrodes 201: Source electrode 203: Drain electrode 1000: Electronic equipment 1100: Display device CH: Channel area D: Drain area D1: Direction D2: Direction L: channel length S: Source region W: channel width

Claims

1. An oxide semiconductor film, which is crystalline, and the oxide semiconductor film contains indium (In) and a first metal element (M1) selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc) and lanthanides, wherein the crystalline structure of the oxide semiconductor film is a manganese oxide type structure, and in the diffraction pattern of the oxide semiconductor film obtained by out-of-plane XRD measurement using Cu-Kα rays, at least a first peak on the (222) plane and a second peak on the (440) plane are observed, and the ratio of the intensity of the first peak to the intensity of the second peak is 4.77 or more and 125 or less.

2. The oxide semiconductor film of claim 1, wherein the ratio of the intensity of the first peak to the intensity of the second peak is 7.04 or more and 15 or less.

3. The oxide semiconductor film of claim 1, wherein in the diffraction pattern, the ratio (S / N ratio) of the intensity of the first peak to the noise width calculated based on a diffraction angle (2θ) of 29° to 30° is 15 or more.

4. The oxide semiconductor film of claim 3, wherein the above-mentioned noise width is calculated using the standard deviation in a linear approximation.

5. The oxide semiconductor film of claim 1, wherein the ratio of indium to all metal elements is 50% or more.

6. The oxide semiconductor film of claim 5, wherein the first metal element is gallium, and the oxide semiconductor film further contains a second metal element (M2) selected from the group consisting of aluminum, yttrium, scandium and lanthanides, wherein the atomic ratio of the indium, gallium and the second metal element satisfies formula (1), formula (2) and formula (3); [Number 1] [Number 2] [Number 3] .

7. The oxide semiconductor film of claim 1, wherein the thickness of the oxide semiconductor film is 30 nm or less.

8. The oxide semiconductor film of claim 1, wherein the oxide semiconductor film is grounded to the metal oxide film.

9. The oxide semiconductor film of claim 8, wherein the metal oxide film comprises a metal oxide having a band gap of 4 eV or more.

10. The oxide semiconductor film of claim 9, wherein the metal oxide film contains one or more metal elements selected from aluminum, magnesium, calcium, scandium, gallium, germanium, strontium, nickel, tantalum, yttrium, zirconium, barium, hafnium, cobalt, and lanthanides.

11. The oxide semiconductor film of claim 8, wherein the metal oxide film comprises aluminum oxide.

12. The oxide semiconductor film of claim 8, wherein the thickness of the aforementioned metal oxide film is 20 nm or less.

13. The oxide semiconductor film of claim 1, wherein the ratio of the crystallite diameter calculated based on the first peak to the thickness of the oxide semiconductor film is 0.95 or more.

14. A thin-film transistor comprising an oxide semiconductor film as a channel, as claimed in any one of claims 1 to 13.

15. An electronic device comprising a thin-film transistor as claimed in claim 14.

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