Electronic package and manufacturing method thereof

TWI943128BActive Publication Date: 2026-10-21SILICONWARE PRECISION IND CO LTD
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Patent Information

Application Number
TW113109039
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2024-03-12
Publication Date
2026-10-21
Estimated Expiration
2044-03-11

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    Figure TWG2TB001916864_003
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Abstract

An electronic package and its manufacturing method are disclosed. The electronic package includes a photonic element, an electronic element, and an optical element. The photonic element has a first surface and a second surface facing each other, and the first surface has a non-overlapping electrical bonding region and an optical coupling region. The electronic element is disposed on the electrical bonding region and electrically connected to the photonic element. The optical element is disposed on the optical coupling region and optically connected to the photonic element. The above-described electronic package and its manufacturing method employ a 2.5-dimensional stacked structure and can couple the optical element without forming a cantilever structure, thus offering advantages such as high heat dissipation efficiency, simplified process, higher yield, and shorter process cycle.
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Description

Technical Field

[0001] This invention relates to a semiconductor packaging process, and more particularly to an electronic package and its manufacturing method. Prior Technology

[0002] To meet the massive data transmission demands of modern networked electronic products, co-packaged optics (CPOs) utilizing silicon photonics technology have become an inevitable trend. Conventional CPOs consist of an optical engine composed of a photonic chip and an electronic chip. The photonic chip is stacked on top of the electronic chip to form an overhang structure for coupling with optical fibers. However, this overhang structure is prone to fiber alignment difficulties, resulting in optical signal loss and reduced chip module gross die utilization. Furthermore, because the electronic chip is embedded in the encapsulation, it cannot contact a heat sink, leading to poor heat dissipation and reduced overall performance of the optical engine. Summary of the Invention

[0003] To address the aforementioned problems, the present invention provides an electronic package comprising a photonic element, an electronic element, and an optical element. The photonic element has opposing first and second surfaces, and the first surface has non-overlapping electrical bonding regions and optical coupling regions. The electronic element is disposed on the electrical bonding region and electrically connected to the photonic element. The optical element is disposed on the optical coupling region and optically connected to the photonic element.

[0004] The present invention also provides a method for manufacturing an electronic package, comprising: providing a photonic element, wherein the photonic element has opposing first and second surfaces, and the first surface is provided with non-overlapping electrical bonding regions and optical coupling regions; disposing an electronic element on the electrical bonding region to electrically connect the electronic element to the photonic element; and disposing an optical element on the optical coupling region to optically connect the optical element to the photonic element.

[0005] The electronic package and its manufacturing method of the present invention adopt a 2.5-dimensional (2.5D) stacked structure, and can couple optical components without forming a cantilever structure. Therefore, it has the advantages of high heat dissipation efficiency, simplified process, higher yield and shorter process cycle. Simple Explanation of the Diagram

[0006] Figures 1 to 3 are cross-sectional schematic diagrams illustrating the manufacturing process of the electronic package of the present invention.

[0007] Figure 4 is a partial top view schematic diagram of the manufacturing method of the electronic package of the present invention.

[0008] Figures 5 and 6 are cross-sectional schematic diagrams illustrating the manufacturing process of the electronic package of the present invention. Implementation

[0009] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0010] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "below," "first," and "second" used in this specification are merely for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0011] Figures 1 to 6 are schematic diagrams of the manufacturing method of the electronic package 2 of the present invention. Figures 1 to 3 and 5 to 6 are cross-sectional schematic diagrams of the electronic package 2, while Figure 4 is a partial top view schematic diagram of the electronic package 2.

[0012] First, as shown in Figure 1, the photonic element 20 is placed on the carrier 25. The photonic element 20 may be, for example, a photonic chip, and has opposing first surfaces 20a and second surfaces 20b. For example, the first surface 20a is the upper surface of the photonic element 20, and the second surface 20b is the lower surface of the photonic element 20. A plurality of conductive lines 201 are formed in the photonic element 20. The conductive lines 201 are, for example, conductive through-silicon vias (TSVs) or other forms of conductive materials. The carrier 25 is a carrier plate or other object that can be used to support the photonic element 20.

[0013] As shown in Figure 2, an electronic component 21 is disposed on a photonic element 20 so that the electronic component 21 is electrically connected to the photonic element 20. The electronic component 21 has an active surface 21a and a non-active surface 21b, and is disposed on the photonic element 20 by flip-chip method through the active surface 21a, a plurality of conductive elements 24 and an adhesive 23, so that the electronic component 21 is electrically connected to the conductive line 201 of the photonic element 20 through the plurality of conductive elements 24.

[0014] Electronic component 21 is, for example, an active component, a passive component, or a combination of both, and the active component 21 is, for example, a semiconductor wafer, while the passive component is, for example, a resistor, a capacitor, and / or an inductor. The plurality of conductive elements 24 are, for example, conductive pillars or conductive bumps.

[0015] As shown in Figure 3, an optical element 22 is disposed on a photonic element 20 so that the optical element 22 is optically connected to the photonic element 20. The optical element 22 is, for example, an optical fiber connector.

[0016] As shown in Figure 4, the first surface 20a of the photonic element 20 is provided with a non-overlapping electrical bonding region 41 and an optical coupling region 42. A plurality of conductive elements 24 are provided in the electrical bonding region 41 for electrically connecting electronic elements 21, so that the electronic elements 21 are disposed on the electrical bonding region 41 in the aforementioned flip-chip manner and electrically connected to the photonic element 20.

[0017] The optical coupling region 42 is used to couple the optical element 22. Specifically, the optical coupling region 42 includes an optical coupling surface 43. A grating or light guide element (not shown) is provided in the optical coupling surface 43, and the photonic element 20 is optically connected to the optical element 22 through the grating or light guide element.

[0018] Furthermore, the optical coupling region 42 further includes at least one limiting structure 44 disposed outside the optical coupling surface 43. The limiting structure 44 is used to restrict the position of the optical element 22 when the optical element 22 is optically connected to the aforementioned grating or light guide element, so as to ensure good coupling efficiency between the optical element 22 and the optical coupling surface 43.

[0019] In one embodiment of the present invention, the photonic chip 20 is in wafer form, and the electronic package is part of a large-format package. In other words, the large-format package is composed of a plurality of electronic packages. Therefore, the large-format package must be cut into individual packages to separate each electronic package.

[0020] Next, as shown in Figure 5, the carrier 25 is removed, and the photonic element 20, electronic element 21, and optical element 22 are then placed on the carrier structure 27. Specifically, the photonic element 20 is disposed on the carrier structure 27 via a plurality of conductors 26 on its second surface 20b, and is electrically connected to the carrier structure 27. This allows the carrier structure 27 to be electrically connected to the electronic element 21 through the conductors 26, the conductive lines 201 in the photonic element 20, and the conductive element 24.

[0021] The complex conductor 26 is, for example, a conductive pillar or a conductive bump.

[0022] The supporting structure 27 is, for example, a packaging substrate with a core layer and circuit structure, a packaging substrate with a coreless circuit structure, a silicon interposer (TSI) with conductive lines such as conductive through-silicon vias (TSVs), or other board types.

[0023] Next, as shown in Figure 6, the heat sink 29 is attached to the electronic component 21 and mounted on the support structure 27. Specifically, the heat sink 29 is a metal structure and includes a sheet 291 and a support portion 292. The heat sink 29 is attached to the electronic component 21 by the sheet 291 and a bonding layer 281, and is mounted on the support structure 27 by the support portion 292 and an adhesive layer 282.

[0024] In this embodiment, the bonding layer 281 is a thermal interface material (TIM), thermally conductive adhesive, or other suitable material, and the adhesive layer 282 is an insulating adhesive, conductive adhesive, or other suitable material.

[0025] As shown in Figures 4 to 6, the electronic package 2 obtained by the aforementioned manufacturing method includes a photonic element 20, an electronic element 21, an optical element 22, a carrier structure 27, and a heat sink 29.

[0026] Electronic component 21 is disposed on the electrical bonding region 41 of the first surface 20a of photonic component 20 and is electrically connected to photonic component 20. In detail, electronic component 21 is disposed on the electrical bonding region 41 of photonic component 20 by means of adhesive 23 and multiple conductive elements 24 in flip-chip manner with its working surface 21a, and is electrically connected to photonic component 20.

[0027] Optical element 22 is disposed on optical coupling region 42 of first surface 20a of photonic element 20 and is optically connected to photonic element 20.

[0028] The photonic element 20 is disposed on the carrier structure 27 via a plurality of conductors 26 on its second surface 20b, so that the carrier structure 27 is electrically connected to the photonic element 20 through its second surface 20b, and then electrically connected to the electronic element 21 through the photonic element 20.

[0029] The heat sink 29 is attached to the electronic component 21 and mounted on the support structure 27. Specifically, the heat sink 29 is attached to the electronic component 21 by means of its sheet 291 and bonding layer 281, and the heat sink 29 is mounted on the support structure 27 by means of its support portion 292 and adhesive layer 282.

[0030] The electronic package and its manufacturing method of the present invention mainly stack electronic components on top of photonic components, and place bonding layers and heat dissipation components on the electronic components, which can greatly improve the heat dissipation efficiency of electronic components.

[0031] In addition, the electronic package and its manufacturing method of the present invention do not require the formation of a cantilever structure to couple optical components, thus improving the utilization rate of the die module and reducing the difficulty of optical coupling between photonic components and optical components.

[0032] Furthermore, the electronic package and its manufacturing method of the present invention adopt a 2.5-dimensional (2.5D) stacked structure, that is, a stacked structure in which both electronic components and optical components are placed on photonic components. Therefore, compared with the fan-out structure, the electronic package and its manufacturing method of the present invention can simplify the manufacturing process to achieve higher yield and shorter process cycle time.

[0033] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Anyone skilled in the art can modify and alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention should be as set forth in the following patent claims.

[0034] 2: Electronic packaging components 20: Photonic elements 20a: First surface 20b: Second surface 201: Conductive circuit 21: Electronic Components 21a: Surface of Action 21b: Non-acting surface 22: Optical Components 23: Base rubber 24: Conductive elements 25: Bearing components 26: Conductor 27: Load-bearing structure 281: Bonding layer 282: Adhesive layer 29: Heat sink 291: Sheet 292: Support section 41: Electrical junction area 42: Optical coupling region 43: Optical coupling surface 44: Limiting Structure

Claims

1. An electronic package, comprising: A photonic element has a first surface and a second surface opposite to each other, and the first surface is provided with a non-overlapping electrical bonding region and an optical coupling region; An electronic component is disposed on the electrical bonding area and electrically connected to the photonic element; an optical component is disposed on the optical coupling area and optically connected to the photonic element, wherein the optical coupling area includes a limiting structure, and the limiting structure is used to limit the position of the optical element when the optical element is optically connected to the photonic element; a carrier structure is electrically connected to the second surface of the photonic element to electrically connect the electronic component through the photonic element; and a heat sink is attached to the electronic component and includes a sheet and a support portion, wherein the heat sink is attached to the electronic component by the sheet through a bonding layer, and the heat sink is mounted on the carrier structure by the support portion through an adhesive layer.

2. The electronic package as described in claim 1, wherein, The first surface is the upper surface of the photonic element, and the second surface is the lower surface of the photonic element.

3. The electronic package as described in claim 1, wherein, The electronic component has an active surface and a non-active surface, and the electronic component is disposed on the electrical junction area by a plurality of conductive elements in a flip-chip manner on the active surface and electrically connected to the photonic element.

4. The electronic package as described in claim 1, wherein, The optical coupling region includes an optical coupling surface, which is provided with a grating or a light guide element, and the photonic element is optically connected to the optical element by means of the grating or the light guide element.

5. The electronic package as described in claim 4, wherein, The limiting structure is located outside the optical coupling surface, and the limiting structure is used to limit the position of the optical element when the optical element is optically connected to the grating or the light guide element.

6. The electronic package as described in claim 1, wherein, The photonic element is disposed on the carrier structure via a plurality of conductors on the second surface and is electrically connected to the carrier structure.

7. A method for manufacturing an electronic package, comprising: A photonic element is provided, wherein the photonic element has opposing first and second surfaces, and the first surface has non-overlapping electrical bonding regions and optical coupling regions; an electronic element is disposed on the electrical bonding region to electrically connect the electronic element to the photonic element; an optical element is disposed on the optical coupling region to optically connect the optical element to the photonic element, wherein the optical coupling region includes a limiting structure for limiting the position of the optical element when it is optically connected to the photonic element; the photonic element, the electronic element, and the optical element are disposed on a carrier structure to electrically connect the carrier structure to the electronic element through the photonic element; a heat sink is provided, including a sheet and a support portion; the heat sink is bonded to the electronic element by the sheet and a bonding layer; and the heat sink is mounted on the carrier structure by the support portion and an adhesive layer.

8. The method for manufacturing an electronic package as described in claim 7, wherein, The first surface is the upper surface of the photonic element, and the second surface is the lower surface of the photonic element.

9. The method for manufacturing an electronic package as described in claim 7, wherein, The electronic component has opposing active and non-active surfaces, and the manufacturing method of the electronic package further includes: disposing the electronic component on the electrical junction area in a flip-chip manner using the active surface of the electronic component and a plurality of conductive elements, so that the electronic component is electrically connected to the photonic element.

10. The method for manufacturing an electronic package as described in claim 7, wherein, The optical coupling region includes an optical coupling surface, which is provided with a grating or a light guide element, and the photonic element is optically connected to the optical element by means of the grating or the light guide element.

11. The method for manufacturing the electronic package as described in claim 10, wherein, The limiting structure is located outside the optical coupling surface, and the limiting structure is used to limit the position of the optical element when the optical element is optically connected to the grating or the light guide element.

12. The method for manufacturing an electronic package as described in claim 7, wherein, The photonic element is disposed on the carrier structure via a plurality of conductors on the second surface and is electrically connected to the carrier structure.

Citation Information

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