Voltage regulator and its control integrated circuit and control method

Abstract

This disclosure provides a control chip for a voltage regulator, including a first feedback pin, a second feedback pin, an information acquisition circuit, a switching control pin, a first communication pin, a storage circuit, a reference voltage generation circuit, and a programmable control circuit. The first feedback pin receives a voltage feedback signal. The second feedback pin receives a current feedback signal. The information acquisition circuit provides parameter feedback data based on the voltage and current feedback signals. The switching control pin provides a switching control signal. The first communication pin receives a voltage identification code. The reference voltage generation circuit generates a reference voltage based on the voltage identification code or test setting data. The programmable control circuit generates a switching control signal based on the voltage feedback signal and the reference voltage, and performs a self-test according to the test setting data.

Description

Voltage Regulator, Its Control Chip and Control Method This disclosure relates to an electronic circuit, and more particularly, to a voltage regulator, its control chip and control method. With the development of processors, their power supply requirements are also increasing. Voltage regulators are usually used to provide stable power supply for processors, and DC-DC converters are a widely used type of voltage regulator. Processors have an increasing demand for the security of power supply. To prevent processors from being damaged due to power supply, it is necessary to improve the reliability and security of power supply. Generally speaking, comprehensive testing of voltage regulators is required. However, as the power supply requirements of processors become more and more complex, the testing of the voltage regulators that supply power to them also becomes more and more complex. On the one hand, it requires a lot of labor costs, and on the other hand, it is still necessary to ensure the normal operation of the voltage regulators that supply power to them before the actual operation of the processors. According to an embodiment of this disclosure, a control chip for a voltage regulator is proposed, which includes a first feedback pin, a second feedback pin, an information acquisition circuit, a switching control pin, a first communication pin, a storage circuit, a reference voltage generation circuit, and a programmable control circuit. The first feedback pin is used to receive a voltage feedback signal representing the output voltage of the voltage regulator. The second feedback pin is used to receive a current feedback signal representing the output current of the voltage regulator. The information acquisition circuit is used to provide parameter feedback data according to the voltage feedback signal and the current feedback signal. The switching control pin is used to provide a switching control signal to control the conduction and cutoff of at least one switch in the voltage regulator. The first communication pin is used to receive a voltage identification code for setting the output voltage. The storage circuit is used to store the parameter feedback data and the test setting data. The reference voltage generation circuit is used to generate a reference voltage according to the voltage identification code or the test setting data. The programmable control circuit is used to generate a switching control signal according to the voltage feedback signal and the reference voltage, and perform a self-test according to the test setting data. During the self-test process, the programmable control circuit sets multiple working parameters of the voltage regulator according to the test setting data, and judges whether the voltage regulator is likely to be damaged based on the parameter feedback data. According to another embodiment of the present disclosure, a control chip for a voltage regulator is provided, including a first feedback pin, an information acquisition circuit, a switching control pin, a storage circuit, a communication pin, a current control pin, and a programmable control circuit. The first feedback pin is used to receive a voltage feedback signal representing the output voltage of the voltage regulator. The information acquisition circuit is used to provide parameter feedback data according to the voltage feedback signal. The switching control pin is used to provide a switching control signal to control the conduction and cutoff of at least one switch in the voltage regulator. The storage circuit is used to store the parameter feedback data and status data. The communication pin is coupled to the storage circuit. The current control pin is used to be coupled to a load-drawing circuit. The programmable control circuit is used to generate a switching control signal according to the voltage feedback signal and a reference voltage. The programmable control circuit is further used to control the load-drawing circuit through the current control pin to change the output current of the voltage regulator, and the programmable control circuit determines whether the voltage regulator may be damaged based on the parameter feedback data and generates status data. According to another embodiment of the present disclosure, a control chip for a voltage regulator is provided, including a first feedback pin, a switching control pin, a current control pin, and a control circuit. The first feedback pin is used to receive a voltage feedback signal representing the output voltage of the voltage regulator. The switching control pin is used to provide a switching control signal to control the conduction and cutoff of at least one switch in the voltage regulator. The current control pin is used to be coupled to a load-drawing circuit. The control circuit is used to generate a switching control signal according to the voltage feedback signal and a reference voltage. The control circuit is further used to control the load-drawing circuit through the current control pin to change the output current of the voltage regulator, and determines whether the voltage regulator may be damaged based on the voltage feedback signal under the change of the output current. According to another embodiment of the present disclosure, a voltage regulator is provided, including a power circuit that provides an output voltage and an output current, and the control chip as described above. According to another embodiment of the present disclosure, a control method for a voltage regulator is provided, including: receiving a voltage feedback signal representing the output voltage of the voltage regulator; receiving a current feedback signal representing the output current of the voltage regulator; providing parameter feedback data according to the voltage feedback signal and the current feedback signal; storing the parameter feedback data and test setting data in a storage circuit; providing a switching control signal according to a reference voltage and the voltage feedback signal to control the conduction and cutoff of at least one switch in the voltage regulator; setting a plurality of operating parameters of the voltage regulator according to the test setting data to perform a self-test; and determining whether the voltage regulator may be damaged based on the parameter feedback data. Specific embodiments of the flyback converter and control method of the present disclosure will be described in detail below. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those of ordinary skill in the art that the present disclosure does not have to be practiced with these specific details. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present disclosure. Throughout the specification, references to "an embodiment", "embodiments", "an example", or "examples" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present disclosure. Thus, the phrases "in an embodiment", "in embodiments", "an example", or "examples" that appear throughout the specification do not necessarily all refer to the same embodiment or example. Additionally, the particular features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, no intervening elements are present. Like reference numerals designate like elements. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items. FIG. 1 is a circuit schematic diagram of a voltage regulator 100 according to an embodiment of the present disclosure. The voltage regulator 100 includes a power circuit 11 and a control chip 12. The power circuit 11 receives an input voltage Vin at its input terminal 101 and provides an output voltage Vo and an output current Io at its output terminal 102. The power circuit 11 may include, for example, a single-phase or multi-phase switching circuit. The control chip 12 includes a feedback pin 121, a switching control pin 122, a reference voltage generation circuit 13, a programmable control circuit 14, an information acquisition circuit 15, and a storage circuit 17. The feedback pin 121 receives a voltage feedback signal Vfb representing the output voltage Vo of the voltage regulator 100. The switching control pin 122 provides a switching control signal PWM to control the conduction and turn-off of at least one switch in the power circuit 11, so that the power circuit 11 converts the input voltage Vin into the output voltage Vo and the output current Io. In one embodiment, the output terminal 102 of the power circuit 11 is coupled to a load socket 19, and a load 18 can be mounted on or removed from the load socket 19, for example, in a plug-and-play manner. The load 18 includes, for example, a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), etc. In one embodiment, the voltage regulator 100 and the load socket 19 are mounted on the same printed circuit board (PCB). The reference voltage generation circuit 13 is used to generate a reference voltage Vref according to a Voltage Identification (VID) code or test configuration data TCFG. In one embodiment, the specific value represented by the VID code corresponds to the target output voltage value required by the load 18. During normal operation, the load 18 can issue commands for the VID code and the slew rate of the voltage to the voltage regulator 100 according to its operating state. For example, when the load 18 needs to process a large amount of data at high speed, it will send the VID code and the voltage slew rate command to the voltage regulator 100, requesting the output voltage Vo to be adjusted from 0.5V to 0.8V at a voltage slew rate of 10mV / us. The information acquisition circuit 15 receives the voltage feedback signal Vfb and provides parameter feedback data DFB according to the voltage feedback signal Vfb. The parameter feedback data DFB includes, for example, a digital signal obtained by high-speed analog-to-digital conversion of the voltage feedback signal Vfb. In one embodiment, the storage circuit 17 is used to store the parameter feedback data DFB and the test configuration data TCFG. The storage circuit 17 can include, for example, a Read Only Memory (ROM), a Random Access Memory (RAM), a Non-Volatile Memory (NVM), etc. The programmable control circuit 14 generates a switching control signal PWM according to the voltage feedback signal Vfb and the reference voltage Vref, and performs a self-test under the condition that the load 18 is not working according to the test configuration data TCFG. During the self-test process, the programmable control circuit 14 sets the operating parameters of the voltage regulator 100 according to the test configuration data TCFG, determines whether the voltage regulator 100 may be damaged based on the parameter feedback data DFB, and generates status data TR. In one embodiment, the storage circuit 17 is further used to store the status data TR. In one embodiment, the test configuration data TCFG is used to simulate the power supply demand issued by the load 18 to the voltage regulator 100. The self-test performed by the voltage regulator 100 includes one or more of, for example, a voltage self-test, a current self-test, or a parameter self-test. In one embodiment, the test configuration data TCFG is used to simulate the demands of the load 18 for the target output voltage value and the voltage conversion rate under different operating states. The programmable control circuit 14 provides voltage test data VDAT according to the test configuration data TCFG to perform the voltage self-test. In one embodiment, the test configuration data TCFG is used to simulate the demands of the load 18 for the output current Io under different load conditions. The programmable control circuit 14 provides current test data IDAT according to the test configuration data TCFG to change the output current Io and perform the current self-test. In one embodiment, the test configuration data TCFG is used to simulate the load protocol packets or the load power state (PS) issued by the load 18. The programmable control circuit 14 provides parameter test data TDAT according to the test configuration data TCFG to perform the parameter self-test. The load power state is defined by the load supplier and includes, for example, a high power state PS0, low power states PS1 to PS2, an ultra-low power state PS3, etc. Different load power states correspondingly require the voltage regulator to operate in different states, such as having different phase operations and different current modes. In one embodiment, the operating parameters of the voltage regulator 100 set according to the test configuration data TCFG include: the slope of the output voltage change during the self-test, and the target output voltage when the self-test is completed. In yet another embodiment, the operating parameters of the voltage regulator 100 set according to the test configuration data TCFG include: the slope of the output current change during the self-test, the initial output current, and the final output current. In yet another embodiment, the operating parameters of the voltage regulator 100 set according to the test configuration data TCFG include: the slope of the output current change during the self-test, the initial output current, the final output current, the number of times the output current changes between the initial output current and the final output current, the period during which the output current is maintained at the initial output current, and the period during which the output current is maintained at the final output current. In yet another embodiment, the operating parameters of the voltage regulator 100 set according to the test configuration data TCFG include: the initial number of working phases during the self-test, the initial current mode, the final number of working phases, and the final current mode. In one embodiment, during the self-test of the voltage regulator 100, the load 18 does not work, for example, is removed from the load socket 19 or is not enabled. The voltage regulator 100 provides the output voltage Vo and the output current Io according to the test setting data TCFG that simulates the power supply requirements of the load 18, that is, normally provides the output power, and the output voltage Vo, the output current Io, and the output power are consistent with those when the load 18 actually operates. When the self-test of the voltage regulator 100 ends and the control chip 12 determines that there is no possibility of damage to the voltage regulator 100, the control chip 12 switches from the self-test operation to the normal operation, and the load 18 operates normally. For example, the load 18 is connected to the load socket 19 (or is switched from the disabled state to the enabled state), and the voltage regulator 100 supplies electrical energy to the load 18. In one embodiment, when there is a possibility of damage to the voltage regulator 100, the voltage regulator 100 immediately stops working, and the load 18 remains non-operational. In another embodiment, when there is a possibility of damage to the voltage regulator 100, the voltage regulator 100 stops working after performing all self-tests. In one embodiment, the control chip 12 further includes a communication pin 123. The communication pin 123 can be used to receive the voltage identification code VID for setting the output voltage Vo, for example, receive the voltage identification code VID from the load 18 through the communication bus 124. The load 18 can also send a load protocol packet (such as a CPU protocol packet, a GPU protocol packet, etc.) to the voltage regulator 100 through the communication bus 124 or other communication buses, and other requirements for the power supply of the voltage regulator 100 by the load 18 are included in the load protocol packet. In one embodiment, the communication bus 124 includes, for example, a serial communication bus SVID or a parallel communication bus PVID. In one embodiment, the control chip 12 further includes a communication pin 125. The communication pin 125 can be used to receive test configuration data TCFG and output status data TR. For example, the test configuration data TCFG is received from the system controller 20 through the communication bus 126 for setting the content of the self-test of the voltage regulator 100, and the status data TR is output to the system controller 20 through the communication bus 126. The system controller 20 determines whether to enable the load to work according to the status data TR, such as enabling the load. In one embodiment, the user can obtain the status data TR stored in the storage circuit 17 through the communication pin 125 and analyze it. In one embodiment, the test configuration data TCFG is set by the user (for example, set through a graphical user interface). The system controller 20 can be, for example, a Baseboard Management Controller (BMC) provided by the motherboard vendor or a test controller provided by the Integrated Circuit (IC) vendor. In one embodiment, the communication bus 126 includes a serial communication bus, such as an I2C bus (Inter-Integrated Circuit Bus), a System Management Bus (SMBus), or a Power Management Bus (PMBus). The embodiments of the present disclosure automatically perform self-tests by the control chip, which can greatly reduce the labor cost of simple, cumbersome, and repetitive tests and promptly detect damages that occur after the voltage regulator is installed on the printed circuit board where the load is located. After the voltage regulator is installed on the printed circuit board where the load is located, the control chip of the voltage regulator can still perform self-tests to determine whether the voltage regulator is likely to be damaged, without relying on the test environment, test location, and external test equipment connected to the General Purpose Interface Bus (GPIB). Without messy connections to external test equipment and without being on the test bench of the control chip vendor, the self-test can be implemented by the built-in test program of the control chip, thereby improving the flexibility of the self-test while also enhancing the reliability and safety of the voltage regulator and preventing the load from being damaged due to the damage of the voltage regulator. Moreover, the self-tests of the embodiments of the present disclosure can be performed without enabling the load to work. Instead, according to the test configuration data TCFG that simulates different operating conditions of the load, the same output voltage and output current as those during the actual operation of the load are provided, ensuring reliable test results while avoiding the risk of the load being damaged during the test. FIG. 2 is a schematic circuit diagram of a reference voltage generating circuit 13 of a voltage regulator 100 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 2, the reference voltage generating circuit 13 includes a voltage identification code updating circuit 131 and a digital-to-analog conversion circuit 132. The voltage identification code updating circuit 131 receives a voltage identification code VID and test setting data TCFG, and provides an updated voltage identification code VID0 according to the voltage identification code VID or the test setting data TCFG. The digital-to-analog conversion circuit 132 performs digital-to-analog conversion on the updated voltage identification code VID0 to provide a reference voltage Vref. In one embodiment, the voltage identification code updating circuit 131 can control the updated voltage identification code VID0 to change to a predetermined value at a programmable slope according to the test setting data TCFG. In one embodiment, when the control chip 12 and the load 18 are operating normally, the control chip 12 receives the voltage identification code VID from the load 18 through the communication pin 123, and the reference voltage generating circuit 13 generates the reference voltage Vref according to the voltage identification code VID. In one embodiment, during the self-test process, the reference voltage generating circuit 13 generates the reference voltage Vref according to the test setting data TCFG. FIG. 3 is a schematic circuit diagram of a power circuit 11 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 3, the power circuit 11 is a single-phase switching circuit. As is known to those of ordinary skill in the art, the power circuit 11 may also include a multi-phase switching circuit. In the embodiment shown in FIG. 3, the power circuit 11 includes a buck switching circuit, that is, it includes an upper switch S1, a lower switch S2, an inductor L1, and an output capacitor Co, and their circuit connections are as shown in FIG. 3. In one embodiment, the upper switch S1 and the lower switch S2 are alternately turned on under the control of a switching control signal PWM, so as to convert the input voltage Vin into an output voltage Vo. As is known to those of ordinary skill in the art, the power circuit 11 may also include any other suitable circuit topology, and is not limited to the embodiment shown in FIG. 3. FIG. 4 is a schematic circuit diagram of a voltage regulator 200 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 4, the voltage regulator 200 further includes a current control pin 128. In one embodiment, the current control pin 128 is coupled to a load pulling circuit 16. The programmable control circuit 14 controls the load pulling circuit 16 through the current control pin 128 to change the output current Io of the voltage regulator 200. The load pulling circuit 16 includes, for example, one or more transistors, a controllable resistor, etc. In one embodiment, the programmable control circuit 14 controls the load pulling circuit 16 according to the test setting data TCFG to perform a current self-test. In the embodiment shown in FIG. 4, the control chip 12 further includes a feedback pin 127 that receives a current feedback signal Ifb representing the output current Io of the voltage regulator 200. In the embodiment shown in FIG. 4, the information acquisition circuit 15 receives the voltage feedback signal Vfb and the current feedback signal Ifb, and provides parameter feedback data DFB according to the voltage feedback signal Vfb and the current feedback signal Ifb to reflect the operating condition of the voltage regulator 200 during the self-test process, so as to further determine whether the voltage regulator 200 may be damaged. In one embodiment, the parameter feedback data DFB includes, for example, digital signals obtained by high-speed analog-to-digital conversion of the voltage feedback signal Vfb and the current feedback signal Ifb. In one embodiment, during the self-test process, the programmable control circuit 14 determines whether the voltage regulator 200 may be damaged based on the parameter feedback data DFB and provides status data TR. In the embodiment shown in FIG. 4, when the load is not working, the control chip 12 can control the load extraction circuit 16 to change the output current Io, so as to comprehensively simulate the current requirements generated by the load under different states and test whether the voltage regulator 200 may be damaged when the load is in various different states. FIG. 5 is a circuit schematic diagram of the information acquisition circuit 15 in the voltage regulator 200 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 5, the information acquisition circuit 15 includes an analog-to-digital conversion circuit 151. The analog-to-digital conversion circuit 151 performs analog-to-digital conversion on the voltage feedback signal Vfb and the current feedback signal Ifb分时 and outputs parameter feedback data DFB. FIG. 6 is a circuit schematic diagram of the programmable control circuit 14 in the voltage regulator 200 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 6, the programmable control circuit 14 includes a switching control unit 142 and an arithmetic unit 143. It should be noted that in the translation of the Chinese sentence "類比至數位轉換電路151分時對電壓反饋訊號Vfb和電流反饋訊號Ifb進行類比至數位轉換,輸出參數反饋資料DFB.", the "分时" is a bit difficult to accurately translate in a single word. Here, "分时" is translated as "分时" for the time being. If there is a more accurate and common expression in the field of electronics, it can be adjusted accordingly.The switching control unit 142 generates a switching control signal PWM according to the output voltage feedback signal Vfb and the reference voltage Vref. In the embodiment shown in FIG. 6, the switching control unit 142 includes a comparator 41, an RS flip-flop 43, and a conduction time control unit 42. The comparator 41 generates a conduction control signal SET according to the comparison between the voltage feedback signal Vfb and the reference voltage Vref to control the conduction time of at least one switching circuit in the power circuit 11 (such as the conduction of one of the switches). In one embodiment, a ramp signal Ramp can be superimposed on the reference signal Vref or the voltage feedback signal Vfb to increase the stability of the power circuit 11. The conduction time control unit 42 generates a turn-off control signal OFF according to the conduction time signal TON to control the turn-off time of at least one switching circuit in the power circuit 11 (such as the turn-off of one of the switches). The RS flip-flop 43 includes a set terminal S, a reset terminal R, and an output terminal Q. Its set terminal S receives the conduction control signal SET, its reset terminal R receives the turn-off control signal OFF, and its output terminal Q generates a switching control signal PWM according to the conduction control signal SET and the turn-off control signal OFF. In one embodiment, the voltage feedback signal Vfb is coupled to the comparator 41 through a resistor Rd, and the load line control signal LL is used to control the resistance value of the resistor Rd, thereby controlling the curve of the output voltage Vo changing with the output current Io (such as decreasing as the output current Io increases), that is, controlling the load line. Those of ordinary skill in the art will know that the switching control unit 142 is not limited to the embodiment shown in FIG. 6 and may also include other suitable circuit structures. In one embodiment, the operation unit 143 generates status data TR based on the parameter feedback data DFB for determining whether the voltage regulator 200 may be damaged. The operation unit 143 compares the parameter feedback data DFB with one or more preset ranges determined by the test setting data TCFG respectively to generate the status data TR. In one embodiment, the operation unit 143 includes a voltage monitoring unit 44, a current monitoring unit 74, a parameter monitoring unit 84, and an analysis and reporting unit 45. The voltage monitoring unit 44 receives the parameter feedback data DFB and the voltage test data VDAT, and generates comparison data C1 according to whether the parameter feedback data DFB is within one or more preset ranges determined by the voltage test data VDAT. The current monitoring unit 74 receives the parameter feedback data DFB and the current test data IDAT, and generates comparison data C2 according to whether the parameter feedback data DFB is within one or more preset ranges determined by the current test data IDAT. The parameter monitoring unit 84 receives the parameter feedback data DFB and the parameter test data TDAT, and generates comparison data C3 according to whether the parameter feedback data DFB is within one or more preset ranges determined by the parameter test data TDAT. The analysis and reporting unit 45 generates the status data TR according to the comparison data C1 - C3. When the parameter feedback data DFB exceeds the preset range determined by any one of the voltage test data VDAT, the current test data IDAT, or the parameter test data TDAT, the status data TR indicates that the voltage regulator 100 may be damaged. Those of ordinary skill in the art will appreciate that the operation unit 143 is not limited to the embodiment shown in FIG. 6 and may also include other suitable circuit structures. FIG. 7 is a flowchart 110 of a method for the programmable control circuit 14 in the voltage regulator according to an embodiment of the present disclosure to perform a self - test, including steps S11 - S15. In step S11, at least one of voltage test data VDAT, current test data IDAT, and parameter test data TDAT is provided according to test setting data TCFG, where the voltage test data VDAT is obtained by simulating the voltage requirements of the load under different operating states according to the test setting data TCFG, the current test data IDAT is obtained by simulating the output current requirements of the load under different load conditions according to the test setting data TCFG, and the parameter test data TDAT is obtained by simulating the load protocol packet or load power state sent by the load according to the test setting data TCFG. When there is voltage test data VDAT, step S12 is entered, and a voltage self-test is performed according to the voltage test data VDAT. When there is current test data IDAT, step S13 is entered, and a current self-test is performed according to the current test data IDAT. When there is parameter test data TDAT, step S14 is entered, and a parameter self-test is performed according to the parameter test data TDAT. In step S15, status data TR is generated to indicate whether the voltage regulator may be damaged. When the voltage regulator may be damaged, the load is kept from working, and the operation of the voltage regulator is controlled to stop. It should be noted that in the above flowchart, the execution order of each step is not limited to that shown in FIG. 7, and two consecutive steps may be executed simultaneously or in the reverse order. FIG. 8 is a schematic diagram of voltage test data VDAT, current test data IDAT, and parameter test data TDAT according to an embodiment of the present disclosure. In one embodiment, the test setting data TCFG includes at least one of voltage test data VDAT, current test data IDAT, and parameter test data TDAT. In another embodiment, at least one of voltage test data VDAT, current test data IDAT, and parameter test data TDAT is generated according to the test setting data TCFG. In the embodiment shown in FIG. 8, the voltage test data VDAT includes VDAT_SL1, VDAT_SL2, VDAT_Voini, and VDAT_Vocpl. Among them, VDAT_SL1 is used to set the slope SL1 of the output voltage Vo rising during the voltage self-test, and its number of bits includes, for example, 4 bits. VDAT_SL2 is used to set the slope SL2 of the output voltage Vo falling during the voltage self-test, and its number of bits includes, for example, 4 bits. VDAT_Voini is used to set the initial output voltage Voini at the start of the voltage self-test, and its number of bits includes, for example, 4 bits. VDAT_Vocpl is used to set the final output voltage Vocpl at the end of the voltage self-test, and its number of bits includes, for example, 4 bits. In the embodiment shown in FIG. 8, the current test data IDAT includes IDAT_SL3, IDAT_SL4, IDAT_Ioini, IDAT_Iocpl, IDAT_Inum, IDAT_Tdp2, IDAT_Tdp3. Among them, IDAT_SL3 is used to set the slope SL3 of the output current Io rising during the current self-test, and its number of bits includes, for example, 4 bits. IDAT_SL4 is used to set the slope SL4 of the output current Io falling during the current self-test, and its number of bits includes, for example, 4 bits. IDAT_Ioini is used to set the initial output current Ioini at the start of the current self-test, and its number of bits includes, for example, 4 bits. IDAT_Iocpl is used to set the final output current Ioini when the current self-test is completed, and its number of bits includes, for example, 4 bits. IDAT_Inum is used to set the number of times Inum that the output current Io changes between the initial output current Ioini and the final output current Iocpl during the current self-test, and its number of bits includes, for example, 4 bits. IDAT_Tdp2 is used to set the period Tdp2 during which the output current Io remains at the initial output current Ioini during the current self-test, and its number of bits includes, for example, 4 bits. IDAT_Tdp3 is used to set the period Tdp3 during which the output current Io remains at the final output current Iocpl during the current self-test, and its number of bits includes, for example, 4 bits. In the embodiment shown in FIG. 8, the parameter test data TDAT includes TDAT_Pn1, TDAT_Imode1, TDAT_Pn2, TDAT_Imode2, and TDAT_Protocol. When the power circuit 11 includes a multi-phase switching circuit, TDAT_Pn1 is used to set the initial number of working phases Pn1 at the start of the parameter self-test (such as the number of phases in which the switching circuit operates at the start of the parameter self-test), and its number of bits includes, for example, 4 bits. TDAT_Imode1 is used to set the initial current mode Imode1 at the start of the parameter self-test (such as continuous conduction mode or discontinuous conduction mode), and its number of bits includes, for example, 1 bit. TDAT_Pn2 is used to set the final number of working phases Pn2 at the completion of the parameter self-test (such as the number of phases in which the switching circuit operates at the completion of the parameter self-test), and its number of bits includes, for example, 4 bits. TDAT_Imode2 is used to set the final current mode Imode2 at the completion of the parameter self-test (such as continuous conduction mode or discontinuous conduction mode), and its number of bits includes, for example, 1 bit. TDAT_Protocol is used to set the content of the simulated load protocol packet during the parameter self-test, and its number of bits includes, for example, 16 bits. In one embodiment, the content of the simulated load protocol packet of TDAT_Protocol includes, for example: power state command, modified output voltage offset command, modified load line command, voltage regulator reset command, etc. The load line command is used to control the voltage value of the output voltage Vo at different output currents Io, or in other words, the slope of the change of the output voltage Vo with respect to the output current Io. FIG. 9 is a flowchart 120 of a method for performing a voltage self-test according to an embodiment of the present disclosure, including steps S21 to S24. Those of ordinary skill in the art will understand that the method for performing a voltage self-test is not limited to the specific embodiment shown in FIG. 9. In step S21, the programmable control circuit 14 sets parameters related to the output voltage Vo according to the voltage test data VDAT, for example, including at least two of the slope SL1 of the rise of the output voltage Vo during the voltage self-test, the slope SL2 of the fall of the output voltage Vo during the voltage self-test, the initial output voltage Voini at the start of the voltage self-test, and the final output voltage Vocpl at the completion of the voltage self-test. In one embodiment, the voltage regulator sets the above parameters of the output voltage Vo by changing the reference voltage Vref according to the voltage test data VDAT. In step S22, the programmable control circuit 14 generates a command to change the reference voltage Vref. For example, it includes rewriting the voltage identification code VID0, and controlling the output voltage Vo to change according to the setting of the voltage test data VDAT through the voltage identification code VID0. In step S23, the programmable control circuit 14 monitors the entire voltage self-test process according to the parameter feedback data DFB. For example, it includes monitoring whether the output voltage Vo exceeds the preset range, and the response time of the output voltage Vo to the change of the reference voltage Vref. The preset range changes instantaneously following the reference voltage Vref. The preset range includes, for example, the overvoltage tolerance band DOV of the output voltage Vo and the undervoltage tolerance band DUV of the output voltage Vo. The overvoltage tolerance DOV includes the range less than the sum of the reference voltage Vref and an overvoltage threshold OV (Vo < Vref + OV), and the undervoltage tolerance DUV includes the range greater than the difference between the reference voltage Vref and an undervoltage threshold UV (Vo > Vref - UV). The response time includes, for example, the delay time Tdel of the output voltage Vo in response to the change of the reference voltage Vref and the duration Tdp of the output voltage Vo in response to the change of the reference voltage Vref. In step S24, it is determined whether the voltage regulator may be damaged according to the monitoring result. For example, the programmable control circuit 14 determines whether the voltage regulator may be damaged according to the monitoring result, or sends the monitoring result to the system controller 20, and the system controller 20 determines whether the voltage regulator may be damaged. FIG. 10 is a waveform diagram 1201 of performing a voltage self-test according to an embodiment of the present disclosure. As shown in FIG. 10, before time t1, the programmable control circuit 14 sets the slope SL1 of the rising output voltage Vo during the voltage self-test, the initial output voltage Voini at the start of the voltage self-test, and the final output voltage Vocpl at the completion of the voltage self-test according to the voltage test data VDAT. At time t1, the programmable control circuit 14 generates a command VDAT_CMD for rewriting the reference voltage Vref according to the voltage test data VDAT, the voltage self-test is started, and the reference voltage Vref changes according to the voltage test data VDAT. At time t2, the voltage regulator responds to the command VDAT_CMD to cause the output voltage Vo to start changing according to the setting of the voltage test data VDAT, such as increasing from the initial output voltage Voini to the final output voltage Vocpl with a slope SL1. At time t3, the output voltage Vo reaches the final output voltage Vocpl, and the voltage self-test process ends. The programmable control circuit 14 monitors whether the output voltage Vo during the voltage self-test exceeds a preset range, such as whether it exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV. In one embodiment, the programmable control circuit 14 starts timing from time t1 when the voltage self-test is started until time t2 when the output voltage Vo starts to change, to monitor the response delay time Tdel (t2 - t1). In one embodiment, the programmable control circuit 14 starts timing from time t2 when the output voltage Vo starts to change until time t3 when the output voltage Vo reaches the final output voltage Vocpl, to monitor the response duration Tdp (t3 - t2). In one embodiment, the programmable control circuit 14 or the system controller 20 determines whether the voltage regulator may be damaged according to the above parameters monitored during the voltage self-test. FIG. 11 is a waveform diagram 1202 of performing a voltage self-test according to another embodiment of the present disclosure. As shown in FIG. 11, before time t4, the programmable control circuit 14 sets the slope SL2 of the output voltage Vo decreasing during the voltage self-test, the initial output voltage Voini at the start of the voltage self-test, and the final output voltage Vocpl at the end of the voltage self-test according to the voltage test data DVAT. At time t4, the programmable control circuit 14 sends a command VDAT_CMD to rewrite the reference voltage Vref, and the voltage self-test is started. At time t5, the voltage regulator responds to the command VDAT_CMD to make the output voltage Vo start to change as set, such as decreasing from the initial output voltage Voini to the final output voltage Vocpl at a slope of SL2. At time t6, the output voltage Vo reaches the final output voltage Vocpl, and the voltage self-test process ends. The programmable control circuit 14 monitors whether the output voltage Vo during the voltage self-test exceeds a preset range, such as whether it exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV. In one embodiment, the programmable control circuit 14 starts timing from time t4 when the voltage self-test is started until time t5 when the output voltage Vo starts to change, to monitor the response delay time Tdel (t5 - t4). In one embodiment, the programmable control circuit 14 starts timing from time t5 when the output voltage Vo starts to change until time t6 when the output voltage Vo reaches the final output voltage Vocpl, to monitor the response duration Tdp (t6 - t5). In one embodiment, the programmable control circuit 14 or the system controller determines whether the voltage regulator may be damaged according to the above parameters monitored during the voltage self-test. FIG. 12 is a flowchart 130 of a method for performing a current self-test according to an embodiment of the present disclosure, including steps S31 to S34. Those of ordinary skill in the art will understand that the method for performing a current self-test is not limited to the specific embodiment shown in FIG. 12. In step S31, the programmable control circuit 14 sets parameters related to the output current Io according to the current test data IDAT, such as including at least two of the slope SL3 of the output current Io increasing during the current self-test, the slope SL4 of the output current Io decreasing during the current self-test, the initial output current Ioini at the start of the current self-test, the final output current Iocpl at the end of the current self-test, the number of times Inum that the output current Io changes between the initial output current Ioini and the final output current Iocpl, the period Tdp2 during which the output current Io maintains at the initial output current Ioini, and the period Tdp3 during which the output current Io maintains at the final output current Iocpl. In step S32, the programmable control circuit 14 sends a command to control the output current Io to change according to the setting of the current test data IDAT. For example, the programmable control circuit 14 controls the load extraction circuit to extract current according to the current test data IDAT, so as to control the output current Io to change according to the setting of the current test data IDAT. In step S33, the programmable control circuit 14 monitors the entire current self-test process according to the parameter feedback data DFB. For example, it includes monitoring whether the value after the output voltage Vo stabilizes exceeds one or more preset ranges (such as whether it exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV), or is higher than the monitored output voltage overshoot value VOS, or lower than one or more of the monitored output voltage undershoot values VUS. In one embodiment, the preset range changes instantaneously with the output current. For example, when the output voltage Vo decreases with the increase of the output current Io under the control of the load line control signal LL, the overvoltage tolerance DOV and the undervoltage tolerance DUV move down with the increase of the output current Io. In step S34, it is determined whether the voltage regulator may be damaged according to the monitoring result. For example, the programmable control circuit 14 determines whether the voltage regulator may be damaged according to the monitoring result, or sends the monitoring result to the system controller 20, and the system controller determines whether the voltage regulator may be damaged. FIG. 13 is a waveform diagram 1301 of performing a current self-test according to an embodiment of the present disclosure. As shown in FIG. 13, before time t7, the programmable control circuit 14 sets the slope SL3 of the increase of the output current Io during the current self-test, the initial output current Ioini at the start of the current self-test, and the final output current Iocpl at the end of the current self-test according to the current test data IDAT. At time t7, the programmable control circuit 14 sends the command IDAT_CMD, and the current self-test is started. In response to the command IDAT_CMD, the output current Io starts to change according to the setting, such as increasing from the initial output current Ioini to the final output current Iocpl at the slope SL3. The programmable control circuit 14 monitors whether the output voltage Vo exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV after stabilization during the current self-test, and monitors the output voltage overshoot value VOS and the output voltage undershoot value VUS. In one embodiment, the programmable control circuit 14 or the system controller determines whether the voltage regulator may be damaged according to the above parameters monitored during the current self-test. FIG. 14 is a waveform diagram 1302 of performing a current self-test according to another embodiment of the present disclosure. As shown in FIG. 14, before time t8, the programmable control circuit 14 sets the slope SL4 of the output current Io decreasing during the current self-test, the initial output current Ioini at the start of the current self-test, and the final output current Iocpl at the end of the current self-test according to the current test data IDAT. At time t8, the programmable control circuit 14 sends a command IDAT_CMD, and the current self-test is started. The output current Io starts to change according to the setting in response to the command IDAT_CMD, such as decreasing from the initial output current Ioini to the final output current Iocpl with a slope SL4. Monitor whether the output voltage Vo exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV after stabilizing during the current self-test, and monitor the output voltage overshoot value VOS and the output voltage undershoot value VUS. In one embodiment, the programmable control circuit 14 or the system controller determines whether the voltage regulator may be damaged according to the above parameters monitored during the current self-test. FIG. 15 is a waveform diagram 1303 of performing a current self-test according to another embodiment of the present disclosure. As shown in FIG. 15, before time t9, the programmable control circuit 14 sets the slope SL3 of the output current Io increasing during the current self-test, the slope SL4 of the output current Io decreasing during the current self-test, the initial output current Ioini at the start of the current self-test, the final output current Iocpl at the end of the current self-test, the number of times Inum that the output current Io changes between the initial output current Ioini and the final output current Iocpl, the period Tdp2 during which the output current Io maintains at the initial output current Ioini, and the period Tdp3 during which the output current Io maintains at the final output current Iocpl according to the current test data IDAT. At time t9, the programmable control circuit 14 sends a command IDAT_CMD, and the current self-test is started. The output current Io starts to change according to the setting in response to the command IDAT_CMD, as shown in FIG. 15. Monitor whether the output voltage Vo exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV after stabilizing during the current self-test, and monitor the output voltage overshoot value VOS and the output voltage undershoot value VUS. In one embodiment, when the output voltage Vo is not stable, it is not necessary to monitor whether the output voltage Vo exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV. In one embodiment, the programmable control circuit 14 or the system controller determines whether the voltage regulator may be damaged according to the above parameters monitored during the current self-test. FIG. 16 is a waveform diagram 1304 of performing a current self-test according to another embodiment of the present disclosure. As shown in FIG. 16, before time t10, the programmable control circuit 14 sets the slope SL3 of the rising output current Io during the current self-test, the initial output current Ioini at the start of the current self-test, and the final output current Iocpl at the end of the current self-test according to the current test data IDAT. At time t10, the programmable control circuit 14 sends a command IDAT_CMD, and the current self-test is started. The output current Io starts to change according to the setting in response to the command IDAT_CMD, as shown in FIG. 16. In the embodiment shown in FIG. 16, the load line control signal LL controls the output voltage Vo to change non-linearly as the output current Io changes. For example, the slopes of the decrease in the output voltage Vo corresponding to different output current Io ranges are different. Those of ordinary skill in the art will know that the change curves of the output voltage Vo and the output current Io are not limited to the embodiment shown in FIG. 16. For example, the output voltage Vo may change linearly as the output current Io changes, or have a change slope different from that shown in FIG. 16. The programmable control circuit 14 monitors the output voltage Vo and the output current Io during the current self-test according to the parameter feedback data DFB. For example, it monitors whether the output voltage Vo exceeds the overvoltage tolerance DOV and the undervoltage tolerance DUV ranges, and the overvoltage tolerance DOV and the undervoltage tolerance DUV change as the output current Io changes. Another example is to monitor whether the magnitudes of the output current Io and the output voltage Vo correspond. The programmable control circuit 14 or the system controller determines whether the voltage regulator may be damaged according to the above parameters monitored during the current self-test. FIG. 17 is a method flowchart 140 of performing a parameter self-test according to an embodiment of the present disclosure, including steps S41 to S44. Those of ordinary skill in the art will know that the method of performing the parameter self-test is not limited to the specific embodiment shown in FIG. 17. In step S41, the programmable control circuit 14 modifies relevant parameters or commands according to the load protocol packet simulated by the parameter test data TDAT. For example, it modifies the load line control signal LL, modifies the voltage offset, or resets the voltage regulator, etc. In step S42, the programmable control circuit 14 controls the voltage regulator to operate according to the parameters or commands modified by the parameter test data TDAT. In step S43, the programmable control circuit 14 monitors the response process of the entire parameter self-test according to the parameter feedback data DFB. For example, it monitors at least one of the output voltage Vo and the output current Io to monitor the load line, voltage offset, or whether the voltage regulator is reset. In step S44, it is determined whether the voltage regulator may be damaged according to the monitoring result. For example, the programmable control circuit 14 determines whether the voltage regulator may be damaged according to the monitoring result, or sends the monitoring result to the system controller, and the system controller determines whether the voltage regulator may be damaged. In one embodiment, when the programmable control circuit 14 does not respond to the content of the load protocol packet, it indicates that there may be damage to the communication between the voltage regulator and the load. FIG. 18 is a flowchart 150 of a method for performing a parameter self-test according to an embodiment of the present disclosure, including steps S51 to S54. Those of ordinary skill in the art will appreciate that the method for performing a parameter self-test is not limited to the specific embodiments shown in FIG. 18. In step S51, the programmable control circuit 14 modifies relevant operating parameters according to the load power state simulated by the parameter test data TDAT. For example, it modifies one or more of the initial operating phase number Pn1 at the start of the parameter self-test, the initial current mode Mode1 at the start of the parameter self-test, the final operating phase number Pn2 at the end of the parameter self-test, and the final current mode Mode2 at the end of the parameter self-test. In step S52, the programmable control circuit 14 controls the voltage regulator to operate according to the parameters modified according to the parameter test data TDAT. In step S53, the programmable control circuit 14 monitors the response process of the entire parameter self-test according to the parameter feedback data DFB. For example, it monitors at least one of the output voltage Vo and the output current Io to monitor at least two of the start response time Tini1, the end response time Tcpl1, the operating phase number of the voltage regulator, the current mode of the voltage regulator, and whether the output voltage Vo exceeds the preset range during the parameter self-test. In step S54, it is determined whether the voltage regulator may be damaged according to the monitoring result. For example, the programmable control circuit 14 determines whether the voltage regulator may be damaged according to the monitoring result, or sends the monitoring result to the system controller, and the system controller determines whether the voltage regulator may be damaged. In one embodiment, when the programmable control circuit 14 does not respond to the load power state, there may be damage to the communication between the voltage regulator and the load or the power circuit of the voltage regulator. FIG. 19 is a flowchart of a control method 600 for a voltage regulator according to an embodiment of the present disclosure, including steps S61 to S67. In step S61, a voltage feedback signal representing the output voltage of the voltage regulator is received. In step S62, a current feedback signal representing the output current of the voltage regulator is received. In step S63, parameter feedback data is provided according to the voltage feedback signal and the current feedback signal. In step S64, parameter feedback data and test setting data are stored. In one embodiment, the test setting data is used to simulate the requirements of a load for the output voltage value and the voltage conversion rate. In one embodiment, the test setting data is used to simulate the load's requirement for the output current. In one embodiment, the test setting data is used to simulate the load protocol packet or power state sent by the load. In step S65, a switching control signal is provided based on the reference voltage and the voltage feedback signal to control the conduction and cutoff of at least one switch in the voltage regulator. In step S66, the operating parameters of the voltage regulator are set according to the test setting data to perform a self-test. In one embodiment, the operating parameters of the voltage regulator set according to the test setting data include the slope of the output voltage change during the self-test (such as at least one of the slope of the rising output voltage and the slope of the falling output voltage), and the final output voltage when the self-test is completed. In one embodiment, the operating parameters of the voltage regulator set according to the test setting data include the slope of the output current change during the self-test (such as at least one of the slope of the rising output current and the slope of the falling output current), the initial output current, and the final output current. In one embodiment, the operating parameters of the voltage regulator set according to the test setting data include the slope of the output current change during the self-test (such as at least one of the slope of the rising output current and the slope of the falling output current), the initial output current, the final output current, the number of times the output current changes between the initial output current and the final output current, the period during which the output current remains at the initial output current, and the period during which the output current remains at the final output current. In one embodiment, the operating parameters of the voltage regulator set according to the test setting data include a load line control signal, a voltage offset, or a voltage regulator reset command. In one embodiment, the operating parameters of the voltage regulator set according to the test setting data include at least one of the initial operating phase number, the initial current mode, the final operating phase number, and the final current mode of the voltage regulator. In step S67, it is determined based on the parameter feedback data whether the voltage regulator is likely to be damaged. In one embodiment, the control method 600 further includes controlling an external load-drawing circuit according to the test setting data to change the output current of the voltage regulator. It should be noted that the execution order of the steps in the above flowchart is not limited to that shown in FIG. 19, and two consecutive steps can be executed simultaneously or in the reverse order. FIG. 20 is a flowchart of a control method 700 for a voltage regulator according to another embodiment of the present disclosure, including steps S71 to S76. In step S71, a voltage feedback signal representing the output voltage of the voltage regulator is received. In step S72, parameter feedback data is provided according to the voltage feedback signal. In step S73, the parameter feedback data and the status data are stored. In step S74, a switching control signal is provided according to the reference voltage and the voltage feedback signal to control the conduction and cutoff of at least one switch in the voltage regulator. In step S75, an external load circuit is controlled through a current control pin to change the output current of the voltage regulator. In step S76, it is determined whether the voltage regulator is likely to be damaged based on the parameter feedback data. In one embodiment, the control method 700 further includes receiving a current feedback signal representing the output current of the voltage regulator, and further providing parameter feedback data according to the current feedback signal. It should be noted that the execution order of the steps in the above flowchart is not limited to that shown in FIG. 20, and two consecutive steps can be executed simultaneously or in the reverse order. FIG. 21 is a circuit schematic diagram of a voltage regulator 300 according to an embodiment of the present disclosure. The voltage regulator 300 includes a control chip 12 and a power circuit 11. In the embodiment shown in FIG. 21, the power circuit 11 includes a six-phase switching circuit, and the power chip ICi and the inductor Li form the i-th phase switching circuit (i = 1, 2... 6). For example, the power chip IC1 and the inductor L1 form the first phase switching circuit, the power chip IC2 and the inductor L2 form the second phase switching circuit... the power chip IC6 and the inductor L6 form the sixth phase switching circuit. The power chip ICi includes: a voltage input pin VIN coupled to the input terminal 101 to receive the input voltage Vin, a switching pin SW, a bootstrap pin BST, a logic power supply pin VDRV for receiving the logic supply voltage, a power reference ground pin PGND coupled to the power reference ground, a signal reference ground pin AGND coupled to the signal reference ground, a current sampling output pin CS, and a switching control input pin PWM. The power reference ground and the signal reference ground are coupled together on the printed circuit board to form a reference ground GND. In the embodiment shown in FIG. 21, the input voltage Vin is equal to 12V and the logic supply voltage is 3.3V. A capacitor C4 is coupled between the logic supply pin VDRV and the signal reference ground pin AGND of the power chip ICi, a capacitor C5 is coupled between the bootstrap pin BST and the switching pin SW, and a capacitor Cin is coupled between the voltage input pin Vin and the reference ground GND. The switching control input pin PWM of the power chip ICi receives the corresponding switching control signal PWMi, and the current sampling output pin CS outputs a current feedback signal CSi representing the current flowing through the ith phase switching circuit. The switching pin SW of the power chip ICi provides the output voltage Vo through an inductor Li. That is, one end of the inductor Li is coupled to the switching pin SW of the power chip ICi, and the other end is coupled to the output terminal 102 to provide the output voltage Vo. The first end of the output capacitor Co is coupled to the output terminal 102, and the second end of the output capacitor Co is coupled to the reference ground GND. The control chip 12 includes switching control pins PWM1 to PWM6 for outputting switching control signals PWM1 to PWM6, phase current feedback pins CS1 to CS6 for receiving current feedback signals CS1 to CS6, a total current feedback pin CS_SUM for receiving the current feedback signal Ifb, an input voltage feedback pin VINSEN, a remote voltage sense pin VOSEN, and a remote voltage sense return pin VORTN. The input voltage feedback pin VINSEN receives an input voltage feedback signal Vinsen representing the input voltage Vin. The remote voltage sense pin VOSEN is coupled to the first end of the output capacitor Co, and the remote voltage sense return pin VORTN is coupled to the second end of the output capacitor Co. The voltage between the remote voltage sense pin VOSEN and the remote voltage sense return pin VORTN represents the voltage feedback signal Vfb. In one embodiment, the control chip 12 further includes communication pins SCLK and SDIO that can be coupled to the load 18 (shown as the CPU in FIG. 21) through an SVID bus (including a clock bus and a data bus). In the embodiment shown in FIG. 21, the communication pin SCLK is coupled to the clock bus, and the communication pin SDIO is coupled to the data bus. In one embodiment, the control chip 12 further includes communication pins SCLK_P, SDA_P, and ALT_P that can be coupled to the system controller 20 through a PMBus (including a clock bus, a data bus, and an alert bus). In the embodiment shown in FIG. 21, the communication pin SCLK_P is coupled to the clock bus, the communication pin SDA_P is coupled to the data bus, and the communication pin ALT_P is coupled to the alert bus. In one embodiment, the control chip 12 further includes a logic power supply pin VDD33, which is coupled to a 3.3V logic power supply voltage. FIG. 22 is a circuit schematic diagram of the power chip ICi according to an embodiment of the present disclosure. As shown in FIG. 22, the power chip ICi includes an upper switch S1 and a lower switch S2. The first end of the upper switch S1 is coupled to the voltage input pin VIN, the second end of the upper switch S1 is coupled to the switching pin SW, and the control end of the upper switch S1 is coupled to the output end of the driving circuit 46. The first end of the lower switch S2 is coupled to the switching pin SW, the second end of the lower switch S2 is coupled to the power reference ground pin PGND, and the control end of the lower switch S2 is coupled to the output end of the driving circuit 47. The bootstrap pin BST is coupled to the logic power supply pin VDRV through the switch 52. The logic circuit 50 is coupled to the switching control input pin PWM and the signal reference ground pin AGND, and outputs the upper switch control signal HSON and the lower switch control signal LSON. After the potential conversion, the upper switch control signal HSON controls the upper switch S1 through the driving circuit 46, and the lower switch control signal LSON controls the lower switch S2 through the driving circuit 47. The current sampling circuit 49 samples the current flowing through the upper switch S1 or the current flowing through the lower switch S2, and provides a current sampling signal at the current sampling output pin CS. In one embodiment, the current source 51 converts the current sampling signal into a current signal. FIG. 23 is a circuit schematic diagram of the control chip 12 in the voltage regulator 300 shown in FIG. 21 according to an embodiment of the present disclosure. In the embodiment shown in FIG. 23, the programmable control circuit 14 provides the switching control signals PWM1 to PWM6 through the switching control pins PWM1 to PWM6. In one embodiment, the control chip 12 includes a differential amplifier 93. The control chip 12 couples the remote voltage feedback pin VOSEN and the remote voltage feedback return pin VORTN to the two input ends of the differential amplifier 93 respectively, and obtains a voltage feedback signal Vfb at the output end of the differential amplifier 93. In one embodiment, the information acquisition circuit 15 of the control chip 12 generates parameter feedback data DFB according to the voltage feedback signal Vfb, the current feedback signal Ifb, the input voltage feedback signal Vinsen, and the current feedback signals CS1 to CS6, for example, through analog-to-digital conversion. In the embodiment shown in FIG. 23, the control chip 12 further includes a PMBus interface circuit 91 coupled to the communication pins SCLK_P, SDA_P, and ALT_P, and an SVID interface circuit 92 coupled to the communication pins SCLK and SDIO. In one embodiment, the PMBus interface circuit 91 is coupled to the programmable control circuit 14 through the storage circuit 17, and may also be directly coupled to the programmable control circuit 14. In one embodiment, the SVID interface circuit 92 is coupled to the programmable control circuit 14 through the storage circuit 17, and may also be directly coupled to the programmable control circuit 14. Although the present disclosure has been described with reference to several exemplary embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present disclosure can be embodied in many forms without departing from the spirit or essence of the present disclosure, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be broadly construed within the spirit and scope defined by the appended claims. Therefore, all changes and modifications falling within the scope of the appended claims or their equivalents should be covered by the appended claims. 11: Power circuit 12: Control chip 13: Reference voltage generation circuit 14: Programmable control circuit 15: Information acquisition circuit 17: Storage circuit 18: Load 19: Load socket 20: System controller 100: Voltage regulator 101: Input terminal 102: Output terminal 121: Feedback pin 122: Switch control pin 123: Communication pin 124: Communication bus 125: Communication pin 126: Communication bus Vin: Input voltage Vo: Output voltage Vfb: Voltage feedback signal Vref: Reference voltage VID: Voltage identification code PWM: Switch control signal TCFG: Test setting data TR: Status data DFB: Parameter feedback data Io: Output current 131: Voltage identification code update circuit 132: Digital-to-analog conversion circuit VID0: Voltage identification code S1, S2: Switches L1: Inductor Co: Output capacitor 200: Voltage regulator 16: Load shedding circuit 127: Feedback pin 128: Current control pin 151: Analog-to-digital conversion circuit Ifb: Current feedback signal 142: Switch control unit 143: Arithmetic unit 41: Comparator 42: On-time control unit 43: RS flip-flop Ramp: Ramp signal LL: Load line control signal Rd: Resistor TON: On-time signal SET: Turn-on control signal OFF: Turn-off control signal 44: Voltage monitoring unit 45: Analysis and reporting unit 74: Current monitoring unit 84: Parameter monitoring unit C1, C2, C3: Comparison data VDAT: Voltage test data IDAT: Current test data TDAT: Parameter test data 110: Flowchart S11, S12, S13, S14, S15: Steps 120: Flowchart S21, S22, S23, S24: Steps 1201, 1202: Waveform diagram VDAT_CMD: Command SL1: Slope Vocpl: Final output voltage Voini: Initial output voltage Tdel: Delay time Tdp: Duration DOV: Overvoltage tolerance DUV: Undervoltage tolerance SL2: Slope 130: Flowchart S31, S32, S33, S34: Steps 1301: Waveform diagram IDAT_CMD: Command SL3: Slope Iocpl: Final output current Ioini: Initial output current VOS: Output voltage overshoot value VUS: Output voltage undershoot value 1302: Waveform diagram SL4: Slope 1303: Waveform diagram Tdp2: Period Tdp3: Period 1304: Waveform diagram 140: Flowchart S41, S42, S43, S44: Steps 150: Flowchart S51, S52, S53, S54: Steps 600: Control method S61, S62, S63, S64, S65, S66,S67: Step 700: Control method S71, S72, S73, S74, S75, S76: Steps 300: Voltage regulator ICi, IC1, IC2, IC6: Power chips Cin, C4, C5: Capacitors L1, L2, L6: Inductors CS1, CS2, CS3, CS4, CS5, CS6: Phase current feedback pins PWM1, PWM2, PWM3, PWM4, PWM5, PWM6: Switching control pins VDRV: Logic power supply pin AGND: Signal reference ground pin PWM: Switching control input pin CS: Current sampling output pin VIN: Voltage input pin BST: Bootstrap pin SW: Switching pin PGND: Power reference ground pin Vinsen: Input voltage feedback signal Ifb: Current feedback signal SCLK: Communication pin SDIO: Communication pin VINSEN: Input voltage feedback pin VDD33: Logic power supply pin SCLK_P: Communication pin SDA_P: Communication pin ALT_P: Communication pin VOSEN: Remote voltage feedback pin VORTN: Remote voltage feedback return pin CS_SUM: Total current feedback pin 46, 47: Driver circuits 48: Potential conversion circuit 49: Current sampling circuit 50: Logic circuit 51: Current source 52: Switch HSON: Upper side switch control signal LSON: Lower side switch control signal 91: PMBus interface circuit 92: SVID interface circuit 93: Differential amplifier To better understand the embodiments of the present disclosure, the present disclosure will be described in detail with reference to the following drawings. Wherein the same elements have the same reference numerals. The following drawings are for illustrative purposes only and may only show a part of the device and are not necessarily drawn to actual scale. [FIG. 1] is a circuit schematic diagram of a voltage regulator according to an embodiment of the present disclosure. [FIG. 2] is a circuit schematic diagram of a reference voltage generation circuit of a voltage regulator according to an embodiment of the present disclosure. [FIG. 3] is a circuit schematic diagram of a power circuit according to an embodiment of the present disclosure. [FIG. 4] is a circuit schematic diagram of a voltage regulator according to an embodiment of the present disclosure. [FIG. 5] is a circuit schematic diagram of an information acquisition circuit in a voltage regulator according to an embodiment of the present disclosure. [FIG. 6] is a circuit schematic diagram of a programmable control circuit in a voltage regulator according to an embodiment of the present disclosure. [FIG. 7] is a flowchart of a method for a programmable control circuit in a voltage regulator to perform a self-test according to an embodiment of the present disclosure. [FIG. 8] is a schematic diagram of test setting data according to an embodiment of the present disclosure. [FIG. 9] is a flowchart of a method for performing a voltage self-test according to an embodiment of the present disclosure. [FIG. 10] is a waveform diagram of performing a voltage self-test according to an embodiment of the present disclosure. [FIG. 11] is a waveform diagram of performing a voltage self-test according to another embodiment of the present disclosure. [FIG. 12] is a flowchart of a method for performing a current self-test according to an embodiment of the present disclosure. [FIG. 13] is a waveform diagram of performing a current self-test according to an embodiment of the present disclosure. [FIG. 14] is a waveform diagram of performing a current self-test according to another embodiment of the present disclosure. [FIG. 15] is a waveform diagram of performing a current self-test according to another embodiment of the present disclosure. [FIG. 16] is a waveform diagram of performing a current self-test according to another embodiment of the present disclosure. [FIG. 17] is a flowchart of a method for performing a parameter self-test according to an embodiment of the present disclosure. [FIG. 18] is a flowchart of a method for performing a parameter self-test according to an embodiment of the present disclosure. [FIG. 19] is a flowchart of a control method for a voltage regulator according to an embodiment of the present disclosure. [FIG. 20] is a flowchart of a control method for a voltage regulator according to another embodiment of the present disclosure. [FIG. 21] is a circuit schematic diagram of a voltage regulator according to an embodiment of the present disclosure. [FIG. 22] is a circuit schematic diagram of a power chip according to an embodiment of the present disclosure. [FIG. 23] is a circuit schematic diagram of a control chip in the voltage regulator shown in FIG. 21 according to an embodiment of the present disclosure. 11: Power circuit 12: Control chip 13: Reference voltage generation circuit 14: Programmable control circuit 15: Information acquisition circuit 17: Storage circuit 18: Load 19: Load socket 20: System controller 100: Voltage regulator 101: Input terminal 102: Output terminal 121: Feedback pin 122: Switch control pin 123: Communication pin 124: Communication bus 125: Communication pin 126: Communication bus Vin: Input voltage Vo: Output voltage Vfb: Voltage feedback signal Vref: Reference voltage VID: Voltage identification code PWM: Switch control signal TCFG: Test setting data TR: Status data DFB: Parameter feedback data Io: Output current

Claims

1. A control chip for a voltage regulator, comprising: A first feedback pin for receiving a voltage feedback signal representing an output voltage of the regulator; a second feedback pin for receiving a current feedback signal representing an output current of the regulator; an information acquisition circuit for providing parameter feedback data based on the voltage feedback signal and the current feedback signal; a switching control pin for providing a switching control signal to control the on and off of at least one switch in the regulator; a first communication pin for receiving a voltage identification code for setting the output voltage; a storage circuit for storing the parameter feedback data and test setting data; a reference voltage generation circuit for generating a reference voltage based on the voltage identification code or the test setting data; and a programmable control circuit for generating the switching control signal based on the voltage feedback signal and the reference voltage, and performing a self-test based on the test setting data. During the self-test process, the programmable control circuit sets multiple operating parameters of the voltage regulator according to the test setting data, and judges whether the voltage regulator is likely to be damaged based on the parameter feedback data.

2. The control chip as described in claim 1, further comprising: The second communication pin is used to receive the test setting data.

3. The control chip as described in claim 1, wherein: During the self-test, one load of the regulator does not operate; and after the self-test ends and the control chip determines that there is no possibility of damage to the regulator, the control chip and the load begin to operate normally.

4. The control chip as described in claim 3, wherein when the control chip and the load are operating normally, the control chip receives the voltage identification code from the load through the first communication pin, and the reference voltage generation circuit generates the reference voltage based on the voltage identification code.

5. The control chip as claimed in claim 1, wherein during the self-test, the reference voltage generation circuit is used to generate the reference voltage according to the test setting data.

6. The control chip as claimed in claim 1, wherein the programmable control circuit is used to monitor whether the output voltage exceeds a preset range during the self-test based on the parameter feedback data in order to determine whether the regulator may be damaged, the preset range following the reference voltage or the output current.

7. The control chip as claimed in claim 1, wherein: The test setting data is used by the programmable control circuit to perform at least one of a voltage self-test, a current self-test, and a parameter self-test; in the voltage self-test process, the test setting data is used to set the operating parameters related to the output voltage by simulating multiple power supply demands issued by a load; in the current self-test process, the test setting data is used to set the operating parameters related to the output current by simulating the power supply demands issued by the load; and in the parameter self-test process, the test setting data is used to set the operating parameters by simulating multiple load protocol packets or multiple power states issued by the load.

8. The control chip as claimed in claim 1, wherein the operating parameters of the regulator set according to the test setting data include: The slope of the output voltage change during the self-test, and the target output voltage when the self-test is completed.

9. The control chip as claimed in claim 1, wherein the operating parameters of the regulator set according to the test setting data include: The output current varies by a slope, an initial output current, and a final output current.

10. The control chip as claimed in claim 9, wherein the operating parameters of the regulator set according to the test setting data further include: The number of times the output current changes between the initial output current and the final output current, the output current being maintained at the initial output current for a first period, and the output current being maintained at the final output current for a second period.

11. The control chip as claimed in claim 1, further comprising: A current control pin is used to couple to a de-load circuit and control the de-load circuit according to the test settings to change the output current of the regulator during the self-test.

12. The control chip as claimed in claim 1, wherein: The programmable control circuit is further used to generate status data based on the parameter feedback data, which indicates whether the voltage regulator may be damaged; and the storage circuit is further used to store the status data.

13. The control chip as claimed in claim 12, further comprising: A second communication pin is used to receive the test setting data and output the status data.

14. The control chip as claimed in claim 12, wherein the programmable control circuitry comprises: A switching control unit is used to generate the switching control signal based on the voltage feedback signal and the reference voltage; And a calculation unit for comparing the parameter feedback data with one or more preset ranges determined by the test setting data to generate the status data.

15. A control chip for a voltage regulator, comprising: A first feedback pin for receiving a voltage feedback signal representing an output voltage of the regulator; an information acquisition circuit for providing parameter feedback data based on the voltage feedback signal; a switching control pin for providing a switching control signal to control the on and off of at least one switch in the regulator; a storage circuit for storing the parameter feedback data and status data; a communication pin coupled to the storage circuit; and a current control pin coupled to a de-load circuit. And a programmable control circuit for generating the switching control signal based on the voltage feedback signal and a reference voltage, wherein the programmable control circuit is further used to control the de-loading circuit through the current control pin to change an output current of the regulator, and the programmable control circuit determines whether the regulator is likely to be damaged based on the parameter feedback data and generates the status data.

16. The control chip as claimed in claim 15, wherein the programmable control circuit is further configured to control the decompression circuit according to a test setting data.

17. The control chip as claimed in claim 15, wherein during a self-test, a load of the regulator is not operating; and after the self-test ends and the control chip determines that there is no possibility of damage to the regulator, the control chip and the load begin to operate normally.

18. The control chip of claim 15, wherein controlling the deload circuit to change the output current of the regulator via the current control pin includes at least one of the following three groups: (a) a rising slope of the output current during a current self-test, an initial output current at the start of the current self-test, and a final output current at the end of the current self-test; (b) a falling slope of the output current during the current self-test, the initial output current at the start of the current self-test, and the final output current at the end of the current self-test; (c) the rising slope of the output current during the current self-test, the falling slope of the output current during the current self-test, the initial output current, the final output current, a number of times the output current changes between the initial output current and the final output current, the output current being maintained at the initial output current for a first period, and the output current being maintained at the final output current for a second period.

19. The control chip as claimed in claim 15, wherein the programmable control circuit is further configured to monitor, based on the voltage feedback signal under the change of output current, whether the output voltage, after stabilization, exceeds one or more preset ranges, or is higher than an output voltage overshoot value, or is lower than an output voltage undershoot value, in order to determine whether the voltage regulator may be damaged.

20. A control chip for a voltage regulator, comprising: A first feedback pin is used to receive a voltage feedback signal representing an output voltage of the regulator; A switching control pin is used to provide a switching control signal to control the on and off of at least one switch in the regulator; a current control pin is used to couple to a deload circuit. And a control circuit for generating the switching control signal based on the voltage feedback signal and a reference voltage, wherein the control circuit is further used to control the de-loading circuit through the current control pin to change an output current of the regulator, and to determine whether the regulator is likely to be damaged based on the voltage feedback signal under the change of output current.

21. A voltage regulator, comprising: A power circuit providing an output voltage and an output current, and a control chip as described in any one of claims 1 to 20.

22. A control method for a voltage regulator, comprising: Receive a voltage feedback signal representing an output voltage of the regulator; Receive a current feedback signal representing an output current of the voltage regulator; provide parameter feedback data based on the voltage feedback signal and the current feedback signal; store the parameter feedback data and test setting data in a storage circuit; provide a switching control signal based on a reference voltage and the voltage feedback signal to control the on and off of at least one switch in the voltage regulator; set multiple operating parameters of the voltage regulator based on the test setting data to perform a self-test; and determine whether the voltage regulator is likely to be damaged based on the parameter feedback data.

23. The control method as described in claim 22, further comprising: During the self-test, the reference voltage is generated according to the test settings, and one load of the regulator is not working. And after the self-test is completed and a control chip determines that there is no possibility of damage to the voltage regulator, the control chip and the load begin to work normally.

24. The control method as described in claim 22, wherein: The test setup data is used to perform at least one of a voltage self-test, a current self-test, and a parameter self-test; in the voltage self-test process, the test setup data is used to set the operating parameters related to the output voltage by simulating multiple power supply demands issued by a load; in the current self-test process, the test setup data is used to set the operating parameters related to the output current by simulating the power supply demands issued by the load; and in the parameter self-test process, the test setup data is used to set the operating parameters by simulating multiple load protocol packets or multiple power states issued by the load.

25. The control method of claim 22, wherein the operating parameters of the regulator set according to the test setting data include at least one of the following three groups: (a) a slope of the output voltage change during the self-test and a target output voltage when the self-test is completed; (b) a slope of the output current change during the self-test, an initial output current, and a final output current; (c) the slope of the output current change during the self-test, the initial output current, the final output current, a number of times the output current changes between the initial output current and the final output current, the output current being maintained at the initial output current for a first period, and the output current being maintained at the final output current for a second period.

26. The control method as described in claim 22, further comprising: According to the test settings, an external deload circuit is controlled to change the output current of the regulator.

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