Modulation device

Abstract

This disclosure provides a modulation apparatus including a substrate, a modulation unit, a first signal line, and a second signal line. The modulation unit is disposed on the substrate. The first signal line is disposed on the substrate and electrically connected to the modulation unit. The second signal line is disposed on the substrate and has an overlap region that overlaps with the first signal line and a non-overlap region that does not overlap with the first signal line. In a first direction, the second signal line has a first width in the overlap region and a second width in the non-overlap region, wherein the first width is smaller than the second width.

Description

Technical Field

[0001] This invention relates to a modulation device. Prior Technology

[0002] The circuit layout in large-sized modulation devices is relatively complex. Therefore, the coupling between lines used to transmit different signals will increase the resistance-capacitance loading (RC loading), which will affect the signal transmission quality and reduce the reliability of the modulation device. Summary of the Invention

[0003] This disclosure provides a modulation apparatus that can reduce the impedance value and / or capacitive load of lines used to transmit different signals, thereby reducing resistive and capacitive load.

[0004] According to an embodiment disclosed herein, the modulation apparatus includes a substrate, a modulation unit, data lines, and scan lines. The modulation unit is disposed on the substrate. The data lines are disposed on the substrate and electrically connected to the modulation unit. The scan lines are disposed on the substrate and have an overlap region that overlaps with the data lines and a non-overlap region that does not overlap with the data lines. In a first direction, the scan lines have a first width in the overlap region and a second width in the non-overlap region, wherein the first width is smaller than the second width.

[0005] According to embodiments disclosed herein, a modulation apparatus includes a substrate, a modulation unit, data lines, and scan lines. The modulation unit is disposed on the substrate. The data lines are disposed on the substrate and electrically connected to the modulation unit. The scan lines are disposed on the substrate and partially overlap with the data lines. The data lines have an overlap region that overlaps with the scan lines and a non-overlap region that does not overlap with the scan lines. In a second direction, the data lines have a third width in the overlap region and a fourth width in the non-overlap region, and the third width is smaller than the fourth width.

[0006] According to embodiments disclosed herein, the modulation apparatus includes a substrate, a plurality of modulation units, data lines, and scan lines. The plurality of modulation units are disposed on the substrate. The data lines are disposed on the substrate and electrically connected to at least one of the plurality of modulation units. The scan lines are disposed on the substrate and arranged parallel to the data lines.

[0007] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0008] Figure 1A is a partial top view of the modulation apparatus of the first embodiment disclosed herein. Figure 1B is a cross-sectional schematic diagram of an embodiment cut according to section line A1-A1' of Figure 1A. Figure 1C is a partial top view schematic diagram of the arrangement relationship between scan lines and data lines in a modulation apparatus according to an embodiment of the present disclosure. Figure 1D is a partial top view schematic diagram of the arrangement relationship between scan lines and data lines in a modulation apparatus according to another embodiment of this disclosure. Figure 1E is a cross-sectional schematic diagram of an embodiment cut according to section line A2-A2' of Figure 1A. Figure 1F is a cross-sectional schematic diagram of another embodiment cut according to section line A2-A2' of Figure 1A. Figure 1G is a cross-sectional schematic diagram of another embodiment cut according to section line A2-A2' of Figure 1A. Figure 2A is a partial top view of the modulation apparatus of the second embodiment disclosed herein. Figure 2B is a cross-sectional schematic diagram of an embodiment cut according to section line B-B' of Figure 2A. Figure 2C is a cross-sectional view of another embodiment cut along section line B-B' of Figure 2A. Figure 3A is a partial top view of the modulation apparatus according to the third embodiment of this disclosure. Figure 3B is a cross-sectional schematic diagram of an embodiment cut according to section line C-C' of Figure 3A. Figure 4 is a partial top view of the modulation apparatus according to the fourth embodiment of this disclosure. Figure 5A is a partial top view of the modulation apparatus according to the fifth embodiment of this disclosure. Figure 5B is a cross-sectional schematic diagram of an embodiment cut according to section line D1-D1' of Figure 5A. Figure 5C is a cross-sectional schematic diagram of an embodiment cut according to section line D2-D2' of Figure 5A. Figure 5D is a cross-sectional view of another embodiment cut according to section line D2-D2' of Figure 5A. Figure 6A is a partial top view of the modulation apparatus according to the sixth embodiment of this disclosure. Figure 6B is a cross-sectional schematic diagram of an embodiment cut according to section line E-E' of Figure 6A. Figure 7 is a partial top view schematic diagram showing the arrangement relationship between the scan lines and the common wires in a modulation apparatus according to an embodiment of this disclosure. Figure 8A is a partial top view of the modulation apparatus according to the seventh embodiment of this disclosure. Figure 8B is a partial top view of the driving circuit of the modulation device based on Figure 8A. Figure 9A is a partial top view of a photosensitive device according to an embodiment of this disclosure. Figure 9B is a cross-sectional schematic diagram of an embodiment cut according to section line F-F' of Figure 9A. Figure 10 is a partial top view of the modulation apparatus according to the eighth embodiment of this disclosure. Implementation

[0009] This disclosure can be understood by referring to the following detailed description and accompanying drawings. It should be noted that, for ease of understanding and to keep the drawings concise, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0010] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as "comprising," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Therefore, when the terms "comprising," "containing," and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0011] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, the various figures illustrate general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of various films, regions, and / or structures may be reduced or enlarged.

[0012] When a component (e.g., a membrane or region) is referred to as "on another component," it can be directly on that component, or there can be other components between them. Conversely, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when a component is referred to as "on another component," the two components are vertically related in the planar view, and this component can be above or below the other component, depending on the orientation of the device.

[0013] The terms “approximately,” “substantially,” or “roughly” are generally interpreted as being within 10% of a given value or range, or as being within 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0014] The ordinal numbers used in the specification and claims, such as "first" and "second," to modify elements do not inherently imply or represent any prior ordinal number for that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.

[0015] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0016] The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components in two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, other suitable components, or combinations of the above components between the endpoints of the components in two circuits, but not limited to these.

[0017] In this disclosure, the thickness, length, and width can be measured using an optical microscope, while the thickness can be measured from a cross-sectional image obtained using an electron microscope, but these methods are not limited to these. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the two values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0018] The electronic devices disclosed herein may include, but are not limited to, display devices, antenna devices, reconfigurable intelligent surface devices, signal feed devices, waveguide devices, sensing devices, light-emitting devices, or splicing devices. Electronic devices may include bendable or flexible electronic devices. Electronic devices may include electronic components. Electronic devices may include, for example, liquid crystal layers or light-emitting diodes (LEDs). Electronic components may include passive and active components, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS) components, liquid crystal chips, etc., but are not limited to these. Diodes may include light-emitting diodes or photodiodes. Light-emitting diodes (LEDs) may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, quantum dot LEDs, fluorescent, phosphorescent, or other suitable materials, or combinations thereof, but are not limited thereto. Sensors may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but are not limited thereto. The following description uses a display device as an example of an electronic device to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0019] The following examples illustrate exemplary embodiments of this disclosure, where the same element symbols are used in the drawings and description to represent the same or similar parts.

[0020] Figure 1A is a partial top view of the modulation apparatus of the first embodiment of the present disclosure; Figure 1B is a cross-sectional view of an embodiment cut along section line A1-A1' of Figure 1A; Figure 1C is a partial top view of the arrangement relationship between scan lines and data lines in the modulation apparatus of an embodiment of the present disclosure; and Figure 1D is a partial top view of the arrangement relationship between scan lines and data lines in the modulation apparatus of another embodiment of the present disclosure.

[0021] Please refer to Figures 1A and 1B simultaneously. The modulation device 10a of this embodiment includes a substrate SB, a modulation unit AU, a scan line SL, and a data line DL. The modulation device 10a may be applicable, for example, to the fields of communications, radar / light-based systems, reconfigurable intelligent surface (RIS) technology, or other suitable fields / technologies, but this disclosure is not limited thereto.

[0022] The substrate SB can be made of, for example, glass, plastic, or a combination thereof. For instance, the substrate SB may be made of quartz, sapphire, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), silicon germanium (SiGe), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or combinations thereof, and this disclosure is not limited thereto.

[0023] The modulation unit AU is disposed, for example, on the substrate SB. In some embodiments, the modulation unit AU may include a varactor diode, a variable capacitor, a variable resistor, a phase shifter, an amplifier, an antenna, a biometric sensor, a graphene sensor, other suitable components, or combinations thereof. For example, the modulation unit AU of this embodiment includes a varactor diode, which can provide different capacitance values ​​according to signals provided by the driving circuit DC and the transistor TFT, which will be described later; that is, the capacitance value of the varactor diode can be changed by changing the voltage across the varactor diode. Therefore, by adjusting the capacitance value of the varactor diode, the modulation device 10a of this embodiment can adjust the operating frequency band, but this disclosure is not limited thereto. In some embodiments, the pitch P between adjacent modulation units AU in the same row is related to the wavelength of the electromagnetic wave to be adjusted. For example, the pitch P between adjacent modulation units AU is, for example, about half of the wavelength of the electromagnetic wave to be adjusted, but this disclosure is not limited thereto.

[0024] Scan lines SL and data lines DL are disposed, for example, on a substrate SB. Scan line SL is electrically connected, for example, to a transistor TFT (TFT) which will be described later, and data line DL is electrically connected, for example, to a modulation unit AU. In some embodiments, scan line SL extends in a first direction d1, and data line DL extends in a second direction d2, wherein the first direction d1 and the second direction d2 are different. In this embodiment, the first direction d1 and the second direction d2 are perpendicular, but this disclosure is not limited thereto. Scan line SL partially overlaps with data line DL, for example, wherein data line DL partially covers scan line SL, but this disclosure is not limited thereto. In this embodiment, scan line SL and data line DL have overlapping areas and non-overlapping areas. In detail, the aforementioned overlapping area is defined as the region where the scan line SL and the data line DL overlap in the top view direction n of the substrate SB. The top view direction n is, for example, perpendicular to the first direction d1 and the second direction d2. The scan line SL has an overlapping area SL_OA that overlaps with the data line DL and a non-overlapping area SL_NOA that does not overlap with the data line DL; or the data line DL has an overlapping area DL_OA that overlaps with the scan line SL and a non-overlapping area DL_NOA that does not overlap with the scan line SL.

[0025] In this embodiment, the scan line SL and / or data line DL may have the following design to reduce the capacitive load of the modulation device 10a, wherein the capacitive load generated by the scan line SL and the data line DL may, for example, conform to the following relationship: C = (ε*A) / d, where C is the capacitive load generated by the scan line SL and the data line DL, ε is the permittivity of the dielectric between the scan line SL and the data line DL, A is the area of ​​overlap between the scan line SL and the data line DL in the top view direction n of the substrate SB, and d is the distance between the scan line SL and the data line DL in the top view direction n of the substrate SB.

[0026] In some embodiments, as shown in FIG1C, the overlapping region SL_OA and the non-overlapping region SL_NOA of the scan line SL may have different widths in the second direction d2. Specifically, the scan line SL has a first width SL_W1 in the overlapping region SL_OA in the second direction d2, and a second width SL_W2 in the non-overlapping region SL_NOA in the second direction d2, wherein the first width SL_W1 is smaller than the second width SL_W2 (SL_W1 < SL_W2). In other embodiments, as shown in FIG1D, the overlapping region DL_OA and the non-overlapping region DL_NOA of the data line DL may have different widths in the first direction d1. Specifically, the data line DL has a third width DL_W1 in the overlapping region DL_OA in the first direction d1, and a fourth width DL_W2 in the non-overlapping region DL_NOA in the first direction d1, wherein the third width DL_W1 is smaller than the fourth width DL_W2 (DL_W1 < DL_W2).

[0027] Through the aforementioned design, the area of ​​overlap between the scan line SL and the data line DL in the top view direction n of the substrate SB can be reduced, thereby reducing the capacitive load generated by the scan line SL and the data line DL, which can improve the signal transmission quality of the modulation device 10a.

[0028] In some embodiments, the modulation device 10a further includes an insulating layer IL1, an insulating layer IL2, a first electrode C1, a second electrode C2, a transistor TFT, a common wire CL, a driving circuit DC, a heat dissipation structure TC, and a conductor layer M.

[0029] An insulating layer IL1 is disposed, for example, on a substrate SB. In this embodiment, the insulating layer IL1 is disposed between the data line DL and the scan line SL, and covers the scan line SL. The material of the insulating layer IL1 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material (e.g., polytetrafluoroethylene, polyimide, poly(p-xylene), benzocyclobutene, or other suitable materials), or a combination thereof, but this disclosure is not limited thereto. The insulating layer IL1 (dielectric) disposed between the data line DL and the scan line SL may have a relatively low permittivity due to including the aforementioned materials, thereby reducing the capacitive load generated by the scan line SL and the data line DL, thereby improving the signal transmission quality of the modulation device 10a. In some embodiments, the permittivity of the insulating layer IL1 may be less than 5. In other embodiments, the permittivity of the insulating layer IL1 may be less than 4. In still other embodiments, the permittivity of the insulating layer IL1 may be less than 3.

[0030] In some embodiments, the insulating layer IL1 may be a single-layer structure or a multi-layer structure, and this disclosure is not limited thereto. Furthermore, in some embodiments, the thickness IL1_T of the insulating layer IL1 is 0.2 μm-10 μm. In other embodiments, the thickness IL1_T of the insulating layer IL1 is 1 μm-5 μm. Since the thickness IL1_T of the insulating layer IL1 is essentially the distance between the scan line SL and the data line DL in the top view direction n of the substrate SB, when the thickness IL1_T of the insulating layer IL1 is within the aforementioned range, the distance between the data line DL in the top view direction n of the substrate SB can be relatively increased, thereby reducing the capacitive load generated by the scan line SL and the data line DL, and thus improving the signal transmission quality of the modulation device 10a.

[0031] An insulating layer IL2 is disposed, for example, on a substrate SB. In this embodiment, the insulating layer IL2 covers the data line DL. The material comprising the insulating layer IL2 may be the same as or similar to the material comprising the insulating layer IL1, and will not be described further here.

[0032] The first electrode C1 and the second electrode C2 are disposed on the substrate SB, for example. In this embodiment, the first electrode C1 and the second electrode C2 are disposed on the insulating layer IL2, and the first electrode C1 and the second electrode C2 may belong to the same metal layer or to different metal layers. In some embodiments, the first electrode C1 and / or the second electrode C2 may be composed of a single metal layer or multiple sub-metal layers, but this disclosure is not limited thereto. The modulation unit AU is disposed on the first electrode C1 and the second electrode C2, for example, and may be electrically connected to the first electrode C1 and the second electrode C2, for example, through pads PAD1 and PAD2, but this disclosure is not limited thereto. The first electrode C1 may, for example, have an opening C1_OP and / or a slot C1_SLIT, and the second electrode C2 may also, for example, have an opening C2_OP and / or a slot C2_SLIT. By giving the first electrode C1 and the second electrode C2 the aforementioned design, the signal reflected by the first electrode C1 and / or the second electrode C2 can, for example, be reduced to obtain a controllable operating frequency range for the modulation unit AU. It is worth noting that this embodiment does not limit the number of openings and / or slots of the first electrode C1 and the second electrode C2 to one, nor does it limit the first electrode C1 and the second electrode C2 to having both openings and slots simultaneously. The first electrode C1 and the second electrode C2 can be formed, for example, by a conventional patterning process. For instance, the first electrode C1 and the second electrode C2 can be formed using laser direct forming (LDS), but this disclosure is not limited thereto.

[0033] The transistor TFT can be electrically connected, for example, to a modulation unit AU to drive the modulation unit AU. The transistor TFT may include, for example, a gate G, a source S, a drain D, and a semiconductor layer SE, but this disclosure is not limited thereto. In this embodiment, the gate G and the scan line SL belong to the same metal layer, and the source S and the drain D and the data line DL belong to the same metal layer, wherein the gate G is covered by an insulating layer IL1, the source S is covered by an insulating layer IL2, and the drain D is partially covered by an insulating layer IL2, but this disclosure is not limited thereto. The transistor TFT can be electrically connected to the modulation unit AU, for example, through a via V1 penetrating the insulating layer IL2. Specifically, the via V1 penetrates the insulating layer IL2 in the top view n of the substrate SB and exposes a portion of the drain D of the transistor TFT, wherein the first electrode C1 is electrically connected to the drain D of the transistor TFT through the via V1, so that the modulation unit AU disposed on the first electrode C1 can be electrically connected to the transistor TFT.

[0034] In some embodiments, the scan line SL can be electrically connected to the gate G of the transistor TFT, and the data line DL can be electrically connected to the source S of the transistor TFT. The scan line SL and the data line DL can each provide a scan signal and a data signal to the corresponding transistor TFT, enabling it to operate the modulation unit AU, but this disclosure is not limited thereto. Additionally, in this embodiment, the data line DL can be electrically connected to the first electrode C1 through the transistor TFT.

[0035] In some embodiments, the material of the semiconductor layer SE includes low-temperature polysilicon (LTPS), metal oxide, or amorphous silicon (a-Si), or a combination thereof, but this disclosure is not limited thereto. For example, the material of the semiconductor layer SE may include, but is not limited to, amorphous silicon, polysilicon, germanium, compound semiconductors (e.g., gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe alloy, GaAsP alloy, AlInAs alloy, AlGaAs alloy, GaInAs alloy, GaInP alloy, GaInAsP alloy), or a combination thereof. The material of the semiconductor layer SE may also include, but is not limited to, metal oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZTO), or organic semiconductors containing polycyclic aromatic compounds, or a combination thereof. The gate G overlaps at least partially with the semiconductor layer SE in the top view n of the substrate SB. The source S and drain D are, for example, separated from each other and covered at least a portion of the semiconductor layer SE, and are electrically connected to the semiconductor layer SE. Alternatively, the source S and drain D may be electrically connected to each other through vias (not shown) in an insulating layer (not shown) between themselves and the semiconductor layer SE. It is worth noting that the transistor TFT is any bottom-gate thin-film transistor known to those skilled in the art. However, although this embodiment uses a bottom-gate thin-film transistor as an example, this disclosure is not limited thereto.

[0036] A common wire CL is disposed on a substrate SB, for example. In some embodiments, the common wire CL extends in the same direction as the scan line SL, that is, the common wire CL extends in a first direction d1, but this disclosure is not limited thereto. In this embodiment, the common wire CL, the gate G, and the scan line SL belong to the same metal layer, wherein the common wire CL is partially covered by an insulating layer IL1, but this disclosure is not limited thereto. The common wire CL is electrically connected to a modulation unit AU, for example, to provide a common signal to the modulation unit AU. In this embodiment, the common wire CL can be electrically connected to the modulation unit AU through a through-hole V2 that penetrates the insulating layers IL1 and IL2. Specifically, the through-hole V2 penetrates the insulating layers IL1 and IL2 in the top view direction n of the substrate SB and exposes a portion of the common wire CL, wherein the second electrode C2 is electrically connected to the common wire CL through the through-hole V2, so that the modulation unit AU disposed on the second electrode C2 can be electrically connected to the common wire CL.

[0037] The driving circuit DC is disposed, for example, on the substrate SB. In some embodiments, the driving circuit DC may be disposed on at least one side of the substrate SB. More specifically, the driving circuit DC may be disposed in the peripheral region (not shown) of the substrate SB, but this disclosure is not limited thereto. For example, as shown in FIG1A, the driving circuit DC is disposed at least in the peripheral region located on one side of the substrate SB, but this disclosure is not limited thereto. In some embodiments, the driving circuit DC is disposed by directly disposed on the substrate SB; or the driving circuit DC is disposed by wafer disposed on the substrate SB, and this disclosure is not limited thereto. The driving circuit DC may include, for example, a timing control circuit, a data driving circuit, a voltage supply circuit, a power supply driving circuit, other suitable circuits, or combinations thereof, and this disclosure is not limited thereto. In this embodiment, the driving circuit DC is electrically connected to the scan line SL, the data line DL, and the common line CL (the driving circuit electrically connected to the data line DL is not shown in FIG1A). The driving circuit DC can provide corresponding scan signals and data signals to the transistor TFT through the scan line SL and the data line DL, and the driving circuit DC can also provide corresponding common signals to the modulation unit AU through the common line CL, so that the modulation unit AU can be operated according to the voltage level provided by the transistor TFT and the common line CL, thereby achieving the effect of multi-frequency operation and / or wideband operation.

[0038] The heat dissipation structure TC is disposed, for example, below the substrate SB. Specifically, the heat dissipation structure TC is disposed below the substrate SB in a top-view direction n. The heat dissipation structure TC can, for example, dissipate heat generated by electronic components (e.g., TFTs, modulation units AU, scan lines SL, data lines DL, etc.) disposed above the substrate SB to the outside, thereby reducing the temperature of the modulation device 10a. In some embodiments, the heat dissipation structure TC may include a heat sink having multiple heat dissipation fins to quickly dissipate the aforementioned heat to the outside. In other embodiments, the heat dissipation structure TC may include a vapor chamber having a cavity including microstructures, the cavity including a heat-absorbing end and a heat-releasing end, and a working fluid flowing within the cavity. When the aforementioned heat is conducted to the heat-absorbing end of the cavity, the working fluid absorbs heat and vaporizes. This vaporized working fluid moves to the lower-pressure heat-releasing end due to the increased pressure, and condenses back into liquid at the heat-releasing end, releasing heat, thereby dissipating the aforementioned heat to the outside. The liquid can then return to the heat-absorbing end through capillary action of the microstructures.

[0039] In this embodiment, the impedance of the scan line SL and / or the data line DL during operation can be reduced by setting the heat dissipation structure TC. The scan line SL and / or the data line DL can, for example, conform to the following relationship: R = (ρ*L) / A', where ρ is the resistivity of the scan line SL and / or the data line DL, L is the length of the scan line SL in the first direction d1 and / or the length of the data line DL in the second direction d2, and A' is the cross-sectional area of ​​the scan line SL in the second direction d2 and / or the cross-sectional area of ​​the data line DL in the first direction d1.

[0040] In some embodiments, as shown in FIG1B, the heat dissipation structure TC is disposed below the substrate SB to dissipate the heat generated by the electronic components disposed above the substrate SB to the outside, thereby reducing the temperature of the scan line SL and / or the data line DL and reducing their resistivity, thereby reducing the impedance of the scan line SL and / or the data line DL.

[0041] A conductor layer M is disposed, for example, between a heat dissipation structure TC and a substrate SB. Specifically, the conductor layer M is disposed between the heat dissipation structure TC and the substrate SB in a planar direction n of the substrate SB. The material of the conductor layer M may include, for example, copper, molybdenum, graphite, other suitable conductors, or combinations thereof, and the conductor layer M may include, for example, a single-layer structure or a multi-layer structure; this disclosure is not limited thereto. The conductor layer M may be used, for example, to conduct heat generated by various electronic components (e.g., transistors TFTs, modulation units AU, scan lines SL, data lines DL, etc.) disposed above the substrate SB to the heat dissipation structure TC to reduce the temperature of the modulation device 10a; this disclosure is not limited thereto. In other embodiments, the conductor layer M may be used for electrical conduction. For example, the conductor layer M may include a ground plate, the material of which may include, for example, metal, which may be electrically connected to the modulation unit AU to ground the modulation unit AU. The conductor layer M may, for example, have opaque properties and may be formed entirely beneath the substrate SB or may have openings to shield unwanted electromagnetic waves; this disclosure is not limited thereto.

[0042] Figure 1E is a cross-sectional view of one embodiment cut along section line A2-A2' of Figure 1A, Figure 1F is a cross-sectional view of another embodiment cut along section line A2-A2' of Figure 1A, and Figure 1G is a cross-sectional view of yet another embodiment cut along section line A2-A2' of Figure 1A.

[0043] Referring to FIG1E, this embodiment may further include an insulating layer IL0. The insulating layer IL0 is disposed on the substrate SB, for example, and between the substrate SB and the insulating layer IL1. The material of the insulating layer IL0 may be the same as or similar to the material of the insulating layer IL1, which will not be described in detail here. In addition, the scan line SL and / or data line DL of this embodiment may include auxiliary electrode lines. Specifically, as shown in FIG1E, the scan line SL includes a main electrode line SLa and an auxiliary electrode line SLb, and the data line DL includes a main electrode line DLa and an auxiliary electrode line DLb. The auxiliary electrode lines SLb and DLb are partially covered by the insulating layer IL0. The main electrode lines SLa and DLa are disposed on the insulating layer IL0 and are electrically connected to the auxiliary electrode lines SLb and DLb through through-holes IL0_V1 and IL0_V2 penetrating the insulating layer IL0, respectively.

[0044] Through the aforementioned design, the cross-sectional area of ​​the scan line SL in the second direction d2 and / or the cross-sectional area of ​​the data line DL in the first direction d1 can be increased, thereby reducing the impedance value of the scan line SL and / or the data line DL.

[0045] Additionally, the common wire CL may also include auxiliary electrode wires. Specifically, as shown in Figure 1E, the common wire CL includes a main electrode wire CLa and an auxiliary electrode wire CLb, wherein the auxiliary electrode wire CLb is partially covered by the insulating layer IL0, and the main electrode wire CLa is disposed on the insulating layer IL0 and electrically connected to the auxiliary electrode wire CLb through a through hole IL0_V3 penetrating the insulating layer IL0.

[0046] In some embodiments, the material of the auxiliary electrode lines (e.g., auxiliary electrode lines SLb, DLb, and / or CLb) may be different from the material of the main electrode lines (e.g., main electrode lines SLa, DLa, and / or CLa). Furthermore, the resistivity of the auxiliary electrode lines (e.g., auxiliary electrode lines SLb, DLb, and / or CLb) may be lower than that of the main electrode lines (e.g., main electrode lines SLa, DLa, and / or CLa), but this disclosure is not limited thereto. In other embodiments, the thickness of the auxiliary electrode lines (e.g., auxiliary electrode lines SLb, DLb, and / or CLb) in the top view direction n may be greater than the thickness of the main electrode lines (e.g., main electrode lines SLa, DLa, and / or CLa), but this disclosure is not limited thereto. In other embodiments, in one cross-sectional direction, the thickness of the auxiliary electrode lines (e.g., auxiliary electrode lines SLb, DLb, and / or CLb) may be greater than the thickness of the main electrode lines (e.g., main electrode lines SLa, DLa, and / or CLa), but this disclosure is not limited thereto.

[0047] However, the configuration of the scan line SL and / or data line DL is not limited to the embodiment shown in FIG1E. FIG1F and FIG1G show other configurations of the scan line SL and / or data line DL.

[0048] Please refer to FIG1F, which also shows that the scan line SL and / or data line DL of this embodiment include auxiliary electrode lines. In detail, as shown in FIG1F, the scan line SL includes a main electrode line SLa and an auxiliary electrode line SLb, and the data line DL includes a main electrode line DLa and an auxiliary electrode line DLb. The auxiliary electrode lines SLb and DLb are disposed below the substrate SB, and the main electrode lines SLa and DLa are disposed above the substrate SB and are electrically connected to the auxiliary electrode lines SLb and DLb respectively through through-holes VS and VD penetrating the substrate SB.

[0049] Through the aforementioned design, the cross-sectional area of ​​the scan line SL in the second direction d2 and / or the cross-sectional area of ​​the data line DL in the first direction d1 can be increased, thereby reducing the impedance value of the scan line SL and / or the data line DL.

[0050] Additionally, the common wire CL may also include auxiliary electrode lines. Specifically, as shown in FIG1F, the common wire CL includes a main electrode line CLa and an auxiliary electrode line CLb, wherein the auxiliary electrode line CLb is disposed below the substrate SB, and the main electrode line CLa is disposed above the substrate SB and is electrically connected to the auxiliary electrode line CLb through a through-hole VC penetrating the substrate SB.

[0051] Please refer to Figure 1G, which shows that the scan line SL of this embodiment includes a main electrode line SLa and an auxiliary electrode line SLb. The main electrode line SLa is disposed on the substrate SB, and the auxiliary electrode line SLb is disposed on the insulating layer IL2 and is electrically connected to the main electrode line SLa through a through hole IL2_V1 penetrating the insulating layer IL2 and a through hole IL1_V1 penetrating the insulating layer IL1. The through holes IL2_V1 and IL1_V1 are connected.

[0052] Through the aforementioned design, the cross-sectional area of ​​the scan line SL in the second direction d2 can be increased, thereby reducing the impedance value of the scan line SL.

[0053] However, it should be noted again that the configuration of the scan line SL and / or data line DL is not limited to the embodiments shown in Figures 1E to 1G. For example, the scan line SL and / or data line DL may have a thickness of more than 1 micrometer in the top view direction n of the substrate SB; or the scan line SL and / or data line DL may be composed of a multilayer structure, such that the cross-sectional area of ​​the scan line SL in the second direction d2 and / or the cross-sectional area of ​​the data line DL in the first direction d1 can be relatively increased, thereby reducing the impedance value of the scan line SL and / or data line DL.

[0054] Figure 2A is a partial top view of the modulation apparatus according to the second embodiment of this disclosure, Figure 2B is a cross-sectional view of one embodiment taken along section line B-B' of Figure 2A, and Figure 2C is a cross-sectional view of another embodiment taken along section line B-B' of Figure 2A. It should be noted that the embodiments in Figure 2A may use the component reference numerals and some content of the embodiments in Figure 1A, and the embodiments in Figures 2B and 2C may use the component reference numerals and some content of the embodiments in Figures 1E to 1G, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted.

[0055] Referring to Figure 2A, the main difference between the modulation device 10b of this embodiment and the aforementioned modulation device 10a is that the scan line SL of the modulation device 10b is arranged parallel to the data line DL, that is, the scan line SL of the modulation device 10b extends in the second direction d2. The maximum length of the modulation device 10b in the second direction d2 is less than the maximum length in the first direction d1. Therefore, compared with the arrangement where the scan line SL extends in the first direction d1, the scan line SL of the modulation device 10b has a shorter length.

[0056] With the aforementioned design, the scan line SL can have a relatively short length in the second direction d2, thereby reducing the impedance value of the scan line SL.

[0057] In addition, the common wire CL in this embodiment can also extend in the second direction d2.

[0058] Figures 2B and 2C show some other patterns of the scan line SL.

[0059] Please refer to Figures 2B and 2C, which show that the scan line SL of this embodiment includes an auxiliary electrode line. Specifically, as shown in Figure 2B, the scan line SL includes a main electrode line SLa and an auxiliary electrode line SLb. The main electrode line SLa is disposed on the substrate SB and partially covered by the insulating layer IL1, while the auxiliary electrode line SLb is disposed on the insulating layer IL1 and electrically connected to the main electrode line SLa through a through-hole IL1_V1 penetrating the insulating layer IL1. Furthermore, in this embodiment, the auxiliary electrode line SLb and the data line DL belong to the same metal layer, but this disclosure is not limited thereto. Referring to Figures 2B and 2C, in Figure 2B, the auxiliary electrode line SLb of the scan line SL does not overlap with the common wire CL; while in Figure 2C, the auxiliary electrode line SLb of the scan line SL overlaps with the common wire CL.

[0060] Through the aforementioned design, the cross-sectional area of ​​the scan line SL in the second direction d2 can be increased, thereby reducing the impedance value of the scan line SL.

[0061] Additionally, in the embodiment shown in FIG2B, the common wire CL may also include an auxiliary electrode line. Specifically, as shown in FIG2B, the common wire CL includes a main electrode line CLa and an auxiliary electrode line CLb. The main electrode line CLa is disposed on the substrate SB and partially covered by the insulating layer IL1, and the auxiliary electrode line CLb is disposed on the insulating layer IL1 and electrically connected to the main electrode line CLa through a through-hole IL1_V3 penetrating the insulating layer IL1. Furthermore, in this embodiment, the auxiliary electrode line CLb also belongs to the same metal layer as the data line DL, but this disclosure is not limited thereto.

[0062] Figure 3A is a partial top view of the modulation apparatus according to the third embodiment of this disclosure, and Figure 3B is a cross-sectional view of an embodiment taken along section line C-C' of Figure 3A. It should be noted that the embodiment of Figure 3A may use the component reference numerals and some contents of the embodiment of Figure 2A, wherein the same or similar reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted.

[0063] Please refer to Figures 3A and 3B simultaneously. The main difference between the modulation device 10c in this embodiment and the modulation device 10b described above is that the driving circuit DC of the modulation device 10c is located below the substrate SB, and the driving circuit DC is located approximately in the middle region of the substrate SB.

[0064] In detail, the driving circuit DC is disposed below the substrate SB. In this embodiment, the driving circuit DC is electrically connected to the scan line SL, the data line DL, and the common wire CL through vias VS, VD, and VC, respectively. Vias VS and VC penetrate the substrate SB, and via VD penetrates the insulating layer IL1 and the substrate SB. In some embodiments, the conductor layer M may be disposed between the substrate SB and the driving circuit DC. The driving circuit DC may be electrically connected to the scan line SL, the data line DL, and / or the common wire CL through multiple vias penetrating the substrate SB and the conductor layer M, but this disclosure is not limited thereto.

[0065] Based on this, in the modulation device 10c, the driving circuit DC is disposed below the substrate SB. Therefore, compared with the arrangement in which the driving circuit DC is disposed on at least one side of the substrate SB, the scan line SL and / or data line DL included in the modulation device 10c have shorter lengths.

[0066] With the aforementioned design, the scan line SL and / or the data line DL in the second direction d2 can have relatively short lengths, thereby reducing the impedance values ​​of the scan line SL and / or the data line DL.

[0067] Figure 4 is a partial top view of the modulation apparatus according to the fourth embodiment of this disclosure. It should be noted that the embodiment of Figure 4 may use the component reference numerals and some contents of the embodiment of Figure 1A, wherein the same or similar reference numerals are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0068] Referring to Figure 4, the main difference between the modulation device 10d in this embodiment and the modulation device 10a described above is that one modulation unit AU of the modulation device 10d is operated by two transistors and includes two data lines.

[0069] In detail, the modulation apparatus 10d includes a first transistor TFT1 and a second transistor TFT2 for operating a modulation unit AU, and the data line DL includes a main data line DL1 and an auxiliary data line DL1'. The main data line DL1 may be electrically connected to the first transistor TFT1, for example, and the auxiliary data line DL1' may be electrically connected to the second transistor TFT2, for example, to provide corresponding data signals so that the first transistor TFT1 and the second transistor TFT2 can operate the modulation unit AU, but this disclosure is not limited thereto. In some embodiments, when the voltage or current carried by the main data line DL1 is too large, the auxiliary data line DL1' can be used to share the load, but this disclosure is not limited thereto.

[0070] It is worth noting that the modulation device 10d (or the aforementioned modulation device 10a, modulation device 10b or modulation device 10c) in this embodiment may also include two scan lines (not shown), which include a main scan line and an auxiliary scan line, wherein the main scan line and the auxiliary scan line are each electrically connected to a corresponding transistor, but this disclosure is not limited thereto.

[0071] Figure 5A is a partial top view of the modulation apparatus according to the fifth embodiment of this disclosure; Figure 5B is a cross-sectional view of an embodiment cut along section line D1-D1' of Figure 5A; Figure 5C is a cross-sectional view of an embodiment cut along section line D2-D2' of Figure 5A; and Figure 5D is a cross-sectional view of another embodiment cut along section line D2-D2' of Figure 5A. It should be noted that the embodiment of Figure 5A may use the component reference numerals and some content of the embodiment of Figure 1A; the embodiment of Figure 5B may use the component reference numerals and some content of the embodiment of Figure 1B; and the embodiments of Figures 5C and 5D may each use the component reference numerals and some content of the embodiments of Figures 1E to 1G. The same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted.

[0072] Please refer to Figures 5A and 5B simultaneously. The main difference between the modulation device 10e in this embodiment and the modulation device 10a described above is that the transistor TFT in the modulation device 10e is a top-gate thin-film transistor, and the semiconductor layer SE in the transistor TFT is made of low-temperature polycrystalline silicon.

[0073] In this embodiment, the modulation device 10e further includes a buffer layer BF and an insulating layer IL0.

[0074] A buffer layer BF is disposed, for example, on a substrate SB, and a semiconductor layer SE is disposed, for example, on the buffer layer BF. In this embodiment, the buffer layer BF is disposed between the substrate SB and the semiconductor layer SE, but this disclosure is not limited thereto. The material of the buffer layer BF may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), but this disclosure is not limited thereto. The buffer layer BF may be used, for example, to reduce the entry of impurities from the substrate SB into the semiconductor layer SE, and may be used, for example, to enhance the adhesion between the substrate SB and the semiconductor layer SE, but this disclosure is not limited thereto.

[0075] An insulating layer IL0 is disposed on, for example, the buffer layer BF and partially covers the semiconductor layer SE. The material comprising the insulating layer IL0 may be the same as or similar to the material comprising the insulating layer IL1, and will not be described further here.

[0076] In some embodiments, the semiconductor layer SE may include a source region, a drain region, and a channel region (not shown). The source region contacts the source S, the drain region contacts the drain D, and the channel region overlaps with the gate G in the top view direction n of the substrate SB. Furthermore, the modulation device 10e may also include a light-shielding layer (not shown). The light-shielding layer may, for example, be disposed between the substrate SB and the channel region of the semiconductor layer SE and covered by a buffer layer BF. The light-shielding layer at least partially overlaps with the channel region of the semiconductor layer SE in the top view direction n of the substrate SB, thereby reducing the degradation of the channel region due to external ambient light. In some embodiments, the material of the light-shielding layer may include a material with a transmittance of less than 30%, but this disclosure is not limited thereto.

[0077] Please refer to Figures 5C and 5D. The scan line SL in this embodiment may include auxiliary electrode lines.

[0078] In detail, in one embodiment, as shown in FIG5C, the scan line SL includes a main electrode line SLa and an auxiliary electrode line SLb, wherein the auxiliary electrode line SLb is located on the main electrode line SLa. From another perspective, the modulation device 10e may include a region Area 1 and a region Area 2, which are adjacent to each other in a first direction d1. Region Area 2 is defined as the area in the top view direction n of the substrate SB that does not overlap with the data line DL or the semiconductor layer SE, and region Area 1 is the area other than region Area 2. The main electrode line SLa is distributed, for example, in regions Area 1 and Area 2, and the auxiliary electrode line SLb is distributed, for example, in region Area 2. Based on this, through the aforementioned design, the cross-sectional area of ​​the scan line SL located in region Area 2 in the second direction d2 can be increased, thereby reducing the impedance value of the scan line SL.

[0079] In another embodiment, as shown in FIG5D, the main electrode line SLa of the scan line SL is located on the auxiliary electrode line SLb, wherein the main electrode line SLa is distributed, for example, in regions Area 1 and Area 2, and the auxiliary electrode line SLb is distributed, for example, in region Area 2. Based on this, through the aforementioned design, the cross-sectional area of ​​the scan line SL located in region Area 2 in the second direction d2 can be increased, thereby reducing the impedance value of the scan line SL.

[0080] Figure 6A is a partial top view of the modulation apparatus according to the sixth embodiment of this disclosure, and Figure 6B is a cross-sectional view of an embodiment taken along section line E-E' of Figure 6A. It should be noted that the embodiment of Figure 6A may use the component reference numerals and some content of the embodiment of Figure 5A, and the embodiment of Figure 6B may use the component reference numerals and some content of the embodiment of Figure 5B, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted.

[0081] Please refer to Figures 6A and 6B simultaneously. The main difference between the modulation device 10f in this embodiment and the modulation device 10e described above is that the transistor TFT' in the modulation device 10f is a dual-gate thin-film transistor.

[0082] In detail, in this embodiment, the scan line SL has an opening SL_OP, wherein the opening SL_OP of the scan line SL exposes a portion of the semiconductor layer SE in the top view direction n of the substrate SB, thereby forming a transistor TFT' having dual gates (gate G1 and gate G2) separated from each other.

[0083] Although not shown in Figure 6A, in some embodiments, the opening SL_OP of the scan line SL can extend along the first direction d1 and partially overlap with the data line DL in the top view direction n of the substrate SB, thereby reducing the area of ​​overlap between the scan line SL and the data line DL in the top view direction n of the substrate SB.

[0084] Through the aforementioned design, the area of ​​overlap between the scan line SL and the data line DL in the top view direction n of the substrate SB can be reduced, thereby reducing the capacitive load generated by the scan line SL and the data line DL, which can improve the signal transmission quality of the modulation device 10f.

[0085] Figure 7 is a partial top view schematic diagram showing the arrangement relationship between the scan lines and the common wires in a modulation apparatus according to an embodiment of this disclosure.

[0086] In some embodiments, as shown in FIG7, the common wire CL has an electrical connection segment CL_CS and an extension segment CL_ES. The electrical connection segment CL_CS of the common wire CL is used, for example, for electrical connection with the modulation unit AU. In addition, the extension segment CL_ES of the common wire CL extends, for example, in the extension direction of the common wire CL (the first direction d1 in this embodiment), and its two ends are connected to adjacent electrical connection segments CL_CS. In this embodiment, the electrical connection segment CL_CS of the common wire CL is relatively far away from the scan line SL, that is, the distance DES between the electrical connection segment CL_CS of the common wire CL and the scan line SL in the second direction d2 is greater than the distance DES between the extension segment CL_ES of the common wire CL and the scan line SL in the second direction d2.

[0087] With the aforementioned design, the distance between the common wire CL and the scan line SL in the second direction d2 can be increased, thereby reducing the capacitive load generated by the common wire CL and the scan line SL.

[0088] It is worth noting that in other embodiments, the extension segment CL_ES of the common wire CL can also be made relatively far away from the scan line SL. That is, the distance D_CS between the electrical connection segment CL_CS of the common wire CL and the scan line SL in the second direction d2 is smaller than the distance D_ES between the extension segment CL_ES of the common wire CL and the scan line SL in the second direction d2. However, this disclosure is not limited to this.

[0089] In other embodiments, the distance in the second direction d2 between the common wire CL used to drive a row and the scan line SL used to drive the adjacent row can also be increased, but this disclosure is not limited thereto.

[0090] Figure 8A is a partial top view of the modulation apparatus according to the seventh embodiment of this disclosure, and Figure 8B is a partial top view of the driving circuit of the modulation apparatus according to Figure 8A. It should be noted that the embodiment of Figure 8A may use the component reference numerals and some contents of the embodiment of Figure 3A, and the embodiment of Figure 8B may use the component reference numerals and some contents of the embodiment of Figure 3B, wherein the same or similar reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted.

[0091] Referring to Figure 8A, the main difference between the modulation device 10g in this embodiment and the modulation device 10a described above is that the modulation device 10g includes multiple chip ICs disposed below the substrate SB, and multiple modulation units AU are driven by the multiple chip ICs in partitions.

[0092] In detail, the modulation device 10g of this embodiment divides m*n modulation units AU into a group of modulation unit groups 100, wherein the m*n modulation units AU are arranged in an array, with m modulation units AU arranged in the first direction d1 and n modulation units AU arranged in the second direction d2. Therefore, on the first surface SB_S1 of the substrate SB (the surface on which the modulation units AU are disposed), a group of modulation unit groups 100 includes n scan lines, m data lines, and n common wires, and the group of modulation unit groups 100 is driven by a single chip IC. Taking FIG8A as an example, the modulation device 10g of this embodiment divides 3*2 modulation units AU into a group of modulation unit groups 100 and arranges them in an array. On the first surface SB_S1 of the substrate SB (the surface on which the modulation unit AU is disposed), a group of modulation units 100 includes 2 scan lines (scan line SL1 and scan line SL2), 3 data lines (data line DL1, data line DL2 and data line DL3) and 2 common wires (common wire CL1 and common wire CL2), and the group of modulation units 100 is driven by a chip IC.

[0093] The chip IC may include, for example, timing control circuitry, data driving circuitry, voltage supply circuitry, power supply circuitry, other suitable circuitry, or combinations thereof, and this disclosure is not limited thereto. In this embodiment, the chip can be formed under the substrate SB using a panel-level package (PLP) process, wherein the panel-level package may include a redistribution structure first (RDL first) process or a chip first (CFP) process. Therefore, the substrate SB in this embodiment can have a panel-level size (that is, the area of ​​the substrate SB can be greater than or equal to 50 cm x 50 cm), which can be used to meet high-volume production requirements.

[0094] In addition, in this embodiment, the substrate SB has multiple through holes, through which multiple chip ICs can be electrically connected to the modulation unit AU. Specifically, in a group of modulation units 100, two scan lines (scan lines SL1' and SL2'), three data lines (data lines DL1', DL2', and DL3'), and two common wires (common wire CL1' and CL2') electrically connected to one chip IC are disposed on the second surface SB_S2 (the surface where the chip ICs are disposed). The scan line SL1' is electrically connected to the scan line SL1 through the through hole VS1 of the substrate SB, and the scan line SL2'... The data line DL1' is electrically connected to the scan line SL2 through the through-hole VS2 of the substrate SB, the data line DL2' is electrically connected to the data line DL2 through the through-hole VD1 of the substrate SB, the data line DL3' is electrically connected to the data line DL3 through the through-hole VD3 of the substrate SB, the common wire CL1' is electrically connected to the common wire CL1 through the through-hole VC1 of the substrate SB, and the common wire CL2' is electrically connected to the common wire CL2 through the through-hole VC2 of the substrate SB.

[0095] Through the aforementioned design, in the modulation device 10g, the length of the scan line SL in the first direction d1 and / or the length of the data line DL in the first direction d1 can be reduced, thereby reducing the impedance value of the scan line SL and / or the data line DL.

[0096] Figure 9A is a partial top view of a photosensitive device according to an embodiment of the present disclosure, and Figure 9B is a cross-sectional view of an embodiment taken along section line F-F' of Figure 9A. It should be noted that the embodiment of Figure 9A may use the component reference numerals and some content of the embodiment of Figure 1A, and the embodiment of Figure 9B may use the component reference numerals and some content of the embodiment of Figure 1B, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted.

[0097] Referring to Figure 9A, the main difference between the photosensitive device 20 of this embodiment and the modulation device 10a described above is that the photosensitive device 20 includes a photoelectric unit PS but does not include a modulation unit AU.

[0098] In detail, the photosensitive device 20 includes a photoelectric unit PS, wherein the photoelectric unit PS includes a photodiode PD, an electrode E1, and an electrode E2. The photodiode PD may, for example, include a semiconductor layer PD1, a photosensitive layer PD2, and a semiconductor layer PD3, and the semiconductor layers PD1, PD2, and PD3 are stacked in this order on the substrate SB in the top view direction n. The electrodes E1 and E2 are, for example, electrically connected to the semiconductor layers PD1 and PD3, respectively. The photodiode PD may, for example, include a single-crystal material, a polycrystalline material, or an organic material. For example, the photodiode PD may include an organic photodiode (OPD), but this disclosure is not limited thereto.

[0099] The photoelectric unit PS is electrically connected to the drain D of the transistor TFT'', for example, so that the transistor TFT' can be used to drive the photoelectric unit PS. Specifically, the photoelectric unit PS can convert received photons into carriers (e.g., electrons and / or holes), and these carriers are stored in the photoelectric unit PS when the transistor TFT' is not turned on. When the transistor TFT' is turned on, the carriers stored in the photoelectric unit PS can be read, for example, via a readout line (data line DL) coupled to the transistor TFT', thereby achieving the function of photodetection. In this embodiment, the transistor TFT' is, for example, a dual-gate thin-film transistor (including gate G1 and gate G2), and the material used is, for example, low-temperature polycrystalline silicon, but this disclosure is not limited thereto.

[0100] In some embodiments, the photosensitive device 20 may further include a buffer layer BF, an insulating layer IL3, an insulating layer IL4, and a bias line BL.

[0101] A buffer layer BF is disposed, for example, between the substrate SB and the semiconductor layer SE of the transistor TFT''. The material of the buffer layer BF may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but this disclosure is not limited thereto. The buffer layer BF may be used, for example, to reduce the ingress of impurities from the substrate SB into the semiconductor layer SE, and may be used, for example, to enhance the adhesion between the substrate SB and the semiconductor layer SE, but this disclosure is not limited thereto.

[0102] An insulating layer IL3 is disposed, for example, on an insulating layer IL2. In this embodiment, the insulating layer IL3 covers the transistor TFT'' and partially covers the photoelectric unit PS, wherein the insulating layer IL3 has a through-hole IL3_V that exposes the electrode E2 of the photoelectric unit PS. The material comprising the insulating layer IL3 may be the same as or similar to the material comprising the insulating layer IL1, and will not be described further here.

[0103] An insulating layer IL4 is disposed, for example, on an insulating layer IL3. In this embodiment, the insulating layer IL4 also covers the transistor TFT'' and partially covers the photoelectric unit PS, wherein the insulating layer IL4 has a through-hole IL4_V that exposes the electrode E2 of the photoelectric unit PS, that is, the through-hole IL4_V can communicate with the through-hole IL3_V to expose part of the electrode E2 together. The material comprising the insulating layer IL4 may be the same as or similar to the material comprising the insulating layer IL1, and will not be described in detail here. In some embodiments, the insulating layer IL4 may be used as a planarization layer, but this disclosure is not limited thereto.

[0104] A bias line BL is disposed, for example, on an insulating layer IL4 and electrically connected to a photoelectric unit PS. The bias line BL can be electrically connected to the electrode E2 of the photoelectric unit PS, for example, through interconnected vias IL3_V and IL4_V. The bias line BL can be used, for example, to apply a voltage to the photoelectric unit PS, causing electron-hole pairs in the photoelectric unit PS to separate and generate carriers. In some embodiments, the bias line BL can extend in a second direction d2, but this disclosure is not limited thereto.

[0105] In this embodiment, the design of the scan line SL and / or data line DL used in modulation devices 10a to 10g can also be applied to the photosensitive device 20 to improve the light detection quality of the photosensitive device 20. For example, the capacitive load generated by the scan line SL and data line DL can be reduced by reducing the overlapping area of ​​the scan line SL and data line DL in the top view direction n of the substrate SB; or the impedance value of the scan line SL and / or data line DL can be reduced by making the scan line SL and / or data line DL include a stack of main electrode lines and auxiliary electrode lines, thereby increasing the cross-sectional area of ​​the scan line SL in the second direction d2 and / or the cross-sectional area of ​​the data line DL in the first direction d1. However, this disclosure is not limited to these limitations.

[0106] Figure 10 is a partial top view of the modulation apparatus according to the eighth embodiment of this disclosure. It should be noted that the embodiment of Figure 10 may use the component reference numerals and some contents of the embodiment of Figure 1A, wherein the same or similar reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted.

[0107] Please refer to Figure 10. The main difference between the modulation device 10h in this embodiment and the modulation device 10a described above is that the modulation device 10h includes a modulation unit MEMS but does not include a modulation unit AU.

[0108] In detail, the modulation unit MEMS in the modulation device 10h is, for example, a microelectromechanical unit (MEMS) that includes a common electrode CE and a modulation electrode ME. The common electrode CE is electrically connected, for example, to a common wire CL to receive a signal provided by the common wire CL, and the common electrode CE has, for example, an opening CE_OP, but this disclosure is not limited thereto. The modulation electrode ME is, for example, electrically connected to a transistor TFT to move according to a corresponding signal provided by the transistor TFT. In this embodiment, the modulation electrode ME can rotate and move by receiving a corresponding signal provided by the transistor TFT. For example, a group of modulation units MEMS1 in the first row of the modulation device 10h is in a state where the transistor TFT is not turned on; a group of modulation units MEMS2 in the second row of the modulation device 10h rotates and moves by receiving a first signal provided by the transistor TFT; and a group of modulation units MEMS3 in the third row of the modulation device 10h rotates and moves by receiving a second signal provided by the transistor TFT.

[0109] The capacitance between the common electrode CE and the modulation electrode ME can be changed by rotating and moving the modulation electrode ME, thereby adjusting the operating frequency band; or the effective length of the opening CE_OP of the common electrode CE can be changed, thereby adjusting the resonant frequency of the opening CE_OP, but this disclosure is not limited thereto.

[0110] In this embodiment, the design of the scan line SL and / or data line DL used in modulation devices 10a to 10g can also be applied to modulation device 10h to improve the signal transmission quality of modulation device 10h. For example, the capacitive load generated by the scan line SL and data line DL can be reduced by reducing the overlapping area of ​​the scan line SL and data line DL in the top view direction n of the substrate SB; or the impedance value of the scan line SL and / or data line DL can be reduced by making the scan line SL and / or data line DL include a stack of main electrode lines and auxiliary electrode lines, thereby increasing the cross-sectional area of ​​the scan line SL in the second direction d2 and / or the cross-sectional area of ​​the data line DL in the first direction d1. However, this disclosure is not limited to these limitations.

[0111] Based on the above, some embodiments of this disclosure reduce the impedance of the scan lines and / or data lines by reducing their length, increasing their cross-sectional area, and / or providing a heat dissipation structure in the modulation apparatus. Other embodiments reduce the capacitive load of the scan lines and / or data lines by reducing the permittivity of the insulating layer between the scan lines and data lines, reducing the overlapping area of ​​the scan lines and data lines, and / or increasing the distance between them. Furthermore, still other embodiments of this disclosure may include a combination of the aforementioned modulation apparatus designs, thereby reducing the impedance and capacitive load of the scan lines and / or data lines. Therefore, the modulation apparatus provided by the embodiments of this disclosure can reduce resistive and capacitive loads, and its signal transmission quality and reliability can be improved.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and not to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein. Features between the embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0113] 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h: Modulation device 20: Photosensitive device 100: Modulation unit group A1-A1', A2-A2', B-B', C-C', D1-D1', D2-D2', E-E', F-F': Section lines Area1, Area2: Areas AU, MEMS, MEMS1, MEMS2, MEMS3: Modulation Unit BF: Buffer layer BL: Offset Line C1: First electrode C1_OP, C2_OP, CE_OP, SL_OP: opening C1_SLIT, C2_SLIT: Slot C2: Second electrode CE: Common electrode CL, CL1, CL1', CL2, CL2': Shared wiring CLa, DLa, SLa: Main electrode wires CLb, DLb, SLb: Auxiliary electrode wires CL_CS: Electrical connection segment CL_ES: Extended line segment D: Jiji d1: First direction d2: Second direction DC: Drive circuit DCS, DES: Distance DL, DL1, DL1', DL2, DL2', DL3, DL3': Data lines DL_NOA, SL_NOA: Non-overlapping regions DL_OA, SL_OA: Overlapping region DL_W1: Third width DL_W2: Fourth width E1, E2: Electrodes G, G1, G2: Gate IC: Chip IL0, IL1, IL2, IL3, IL4: Insulating layers IL1_T: Thickness IL0_V1, IL0_V2, IL0_V3, IL1_V1, IL1_V3, IL2_V1, IL3_V, IL4_V, V1, V2, VC, VC1, VC2, VD, VD1, VD2, VD3, VS, VS1, VS2: Through hole M: Conductive layer ME: Modulation electrode n: View from above P: Pitch PAD1, PAD2: Pads PD: Photodiode PD1, PD3: Semiconductor layer PD2: Photosensitive layer PS: Optoelectronic unit S: Source SB:Substrate SB_S1: First surface SB_S2: Second surface SE: Semiconductor layer SL, SL1, SL1', SL2, SL2': Scan lines SLa: Main electrode wire SLb: Auxiliary electrode wire SL_W1: First width SL_W2: Second width TC: Heat dissipation structure TFT, TFT', TFT'': transistor

Claims

1. A modulation device, comprising: substrate; Multiple modulation units are disposed on the substrate; A first signal line is disposed on the substrate and electrically connected to at least one of the plurality of modulation units; And a second signal line, which is disposed on the substrate and arranged parallel to the first signal line in a top view.

2. The modulation apparatus of claim 1, further comprising a driving circuit disposed under the substrate and in a central region of the substrate.

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