Semiconductor device structure and methods of forming the same

Abstract

The embodiments disclosed herein relate to a semiconductor device structure. The structure includes a substrate, an insulating material disposed on the substrate, a first fin structure extending upward from the substrate through the insulating material, and a second fin structure extending upward from the substrate through the insulating material, wherein the first fin structure and the second fin structure extend along a first direction. The structure also includes an isolation trench structure disposed between the first fin structure and the second fin structure, the isolation trench structure extending along a second direction perpendicular to the first direction, wherein the isolation trench structure has a bottom contacting the top surface of the substrate, and the bottom of the isolation trench structure and the top surface of the substrate define a substantially flat interface.

Description

Technical Field

[0001] . Prior Technology

[0002] As the semiconductor industry advances to nanometer technology process nodes in pursuit of higher device density, higher efficiency, and lower cost, challenges from both manufacturing and design issues have spurred the development of multi-gate devices such as FinFETs and gate-all-around (GAA) transistors. To continue providing the required scaling and increased density for multi-gate devices in advanced technology nodes, it is necessary to further reduce gate spacing. Various approaches, such as poly on diffusion edge (PODE) and continuous poly on diffusion edge (CPODE), have been used to reduce gate spacing while preventing leakage current between transistors. However, parasitic fin bipolar transistors have been observed to form during the etching process, leading to the formation of EPI substrate-EPI leakage paths.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Summary of the Invention

[0004] .

[0005] .

[0006] . Simple Explanation of the Diagram

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in this industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1 to 6 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0009] Figures 7A to 10A are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments.

[0010] Figures 7B to 10B are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments.

[0011] Figures 7C to 10C are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments.

[0012] Figures 11A to 11B to 18A to 18B and 21A to 21B to 25A to 25B are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure of Figures 10A and 10B according to some embodiments. Figures 10A and 10B show a plurality of fin structures arranged along the X and Y directions, respectively.

[0013] Figure 18B-1 shows an enlarged view of a portion of the substrate shown in Figure 18B according to some embodiments.

[0014] Figures 19 and 20 illustrate embodiments in which isolation trenches are etched to have a bottom extending to a certain depth in a well region extending into the substrate.

[0015] Figure 19-1 shows an enlarged view of a portion of the substrate shown in Figure 19 according to some embodiments.

[0016] Figures 26 and 27 show cross-sectional views of the semiconductor device structure according to the embodiments shown in Figures 19 and 20, respectively.

[0017] Figure 28 is a top view of a semiconductor element structure shown in Figures 25A and 25B according to some embodiments.

[0018] Figures 29A, 29B, and 29C are cross-sectional views of semiconductor device structures taken along lines DD, EE, and FF of Figure 28, respectively.

[0019] Figures 30 to 36 illustrate alternative embodiments according to some examples, in which a portion of the insulating material is retained within the isolation trench structure and on the top surface of the exposed substrate.

[0020] Figures 37 to 43 illustrate alternative embodiments according to some examples, in which a portion of the insulating material is retained within the isolation trench structure and disposed away from the top surface of the exposed substrate.

[0021] Figures 44A and 44B through 49A and 49B are cross-sectional views of one of the various stages of manufacturing a semiconductor device structure according to some alternative embodiments.

[0022] Figure 50 is an enlarged view of a portion of the substrate shown in Figure 49B according to some embodiments.

[0023] Figure 51 illustrates an embodiment of an isolation trench structure according to some embodiments, having a bottom at substantially the same height as the top surface of the substrate.

[0024] Figure 51-1 shows an enlarged view of a portion of the substrate shown in Figure 51 according to some embodiments.

[0025] Figure 52 shows a cross-sectional view of a semiconductor element structure according to an alternative embodiment.

[0026] Figure 53 shows a cross-sectional view of a semiconductor element structure according to an alternative embodiment.

[0027] Figure 54 shows an enlarged view of a portion of the substrate shown in Figures 52 and 53 according to some embodiments. Implementation

[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and configurations are described below. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "above," "top," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another (one or more) element or feature. In addition to the orientations depicted in the figures, spatially related terms are also intended to encompass different orientations of the apparatus during use or operation. The apparatus may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0030] As integrated circuits shrink, the epitaxial critical dimension (EPI CD, referring to the spacing between epitaxial regions) becomes increasingly smaller. Small EPI CDs make etching trenches for insulating structures without damaging adjacent structures (e.g., epitaxial source / drain features) challenging. Exemplary insulating structures may include a Continuous-Poly-On-Diffusion-Edge (CPODE) structure, which removes a portion or all of a selected fin structure and replaces the selected fin structure with insulating material to form an isolation trench. The CPODE structure prevents leakage current from passing through the epitaxial source / drain features, transistor, and silicon substrate. The embodiments disclosed herein can be applied to other devices that may include CPODE or CMODE structures, such as planar FETs, FinFETs, Horizontal Full-Surround Gate (HGAA) FETs, Vertical Full-Surround Gate (VGAA) FETs, and other suitable devices.

[0031] Figures 1 through 54 illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in Figures 1 through 54, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limiting and is interchangeable.

[0032] Figures 1 to 6 are perspective views of various stages of fabricating a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0033] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurities). Depending on the circuit design, the dopants may be, for example, phosphorus for the n-well regions and boron for the p-well regions.

[0034] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices (e.g., nanostructure channel FETs). In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, while the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, while the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. In some embodiments, the second semiconductor layer 108 may be etched during the manufacturing process and replaced with other materials (e.g., SiO or SiN).

[0035] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of each layer of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0036] The first semiconductor layer 106, or portions thereof, may form one or more nanostructure channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term nanostructure is used herein to refer to any portion of material having nanometer or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions having circular or substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions, including, for example, having cylindrical or substantially rectangular cross-sections. One or more nanostructure channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes surrounding the channels. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0037] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. As shown in FIG1, three first semiconductor layers 106 and three second semiconductor layers 108 are alternately configured, this is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100.

[0038] In Figure 2, fin structures 112 are formed from semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a base portion 116 formed from substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on semiconductor layer stack 104 using a multi-patterning operation including lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam lithography process. The etching process forms trenches 114 by penetrating the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in the unprotected area, thereby leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof. In some embodiments, each fin structure 112 has a longitudinal axis in the X direction.

[0039] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (e.g., chemical mechanical polishing (CMP) and / or etch-back) is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorinated silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be a multilayer dielectric structure. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0040] In Figure 4, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of fin structures 112, such as semiconductor layer stack 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes (e.g., dry etching, wet etching, or a combination thereof). The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from substrate 101.

[0041] In Figure 5, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 can be formed by sequentially depositing uniform-thickness layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more layers of the gate spacers 138 and non-anisotropically etching the one or more layers. In some embodiments, gate spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments two or more sacrificial gate structures 130 may be configured along the X direction.

[0042] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof).

[0043] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor element structure 100.

[0044] In Figure 6, the portion of fin structure 112 not covered by sacrificial gate structure 130 and gate spacer 138 is recessed to a level above, at, or below the top surface of isolation region 120. These recesses of fin structure 112 can be achieved by an etching process (isotropic or anisotropic etching), and this etching process can be selective for one or more crystal planes of substrate 101. The etching process can be dry etching (e.g., RIE, NBE, etc.) or wet etching (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0045] Figures 7A, 7B, and 7C are cross-sectional side views of the semiconductor device structure 100 taken along lines AA, BB, and CC of Figure 6, respectively.

[0046] Figures 8A, 8B, and 8C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of manufacturing a semiconductor device structure 100. As shown in Figure 8A, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. In cases where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant (e.g., but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution).

[0047] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 can be made of a low-k dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), followed by removing the portion of the conformal dielectric layer other than the dielectric spacers 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0048] Figures 9A, 9B, and 9C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of fabricating a semiconductor device structure 100. As shown in Figures 9A and 9C, a source / drain (S / D) region 146 is formed from a substrate portion 116. In some embodiments, the S / D region 146 may be grown vertically and horizontally to form facets that may correspond to crystal planes of the material used for the substrate portion 116. In this disclosure, the source and drain regions may be used interchangeably and have substantially the same structure. Furthermore, (one or more) source / drain regions may individually or jointly refer to a source or drain, depending on the context. The S / D region 146 may be made of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET or one or more layers of Si, SiGe, and Ge for a p-channel FET. For a p-channel FET, a p-type dopant (e.g., boron (B)) may also be included in the S / D region 146. The S / D region 146 can be formed using epitaxial growth methods such as CVD, ALD, or MBE.

[0049] Figures 10A, 10B, and 10C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of fabricating a semiconductor device structure 100. In Figures 10A, 10B, and 10C, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sacrificial gate structure 130, the insulating material 118, and the sidewalls of the S / D region 146. CESL 162 may include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material of ILD layer 164 may include compounds containing Si, O, C and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for ILD layer 164. ILD layer 164 may be deposited by PECVD process or other suitable deposition techniques. In some embodiments, after ILD layer 164 is formed, the semiconductor device structure 100 may be heat-treated to cure ILD layer 164.

[0050] After the formation of the ILD layer 164, a planarization operation (e.g., CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. In some embodiments, after the planarization process, the ILD layer 164 is recessed, and a capping layer 163 is formed on the recessed ILD layer 164. The capping layer 139 may include a nitride (e.g., silicon nitride) to protect the ILD layer 164 during subsequent processes. A second planarization process may be performed to remove portions of the capping layer 163 formed on the sacrificial gate electrode layer 134. After the planarization process, the top surfaces of the capping layer 139, CESL 162, gate spacer 138, and sacrificial gate electrode layer 134 are substantially coplanar.

[0051] Figures 11A to 11B to 18A to 18B and 21A to 21B to 25A to 25B are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100 of Figures 10A and 10B according to some embodiments, showing a plurality of fin structures arranged along the X and Y directions, respectively. In Figures 12A and 12B, a mask structure 1302 is formed on the top surface of the sacrificial gate electrode layer 134, the gate spacer 138, the CESL 162, and the cap layer 139 (or the first ILD layer 164 if the cap layer 139 is not formed). The mask structure 1302 may include a hard mask 1304 and a resist layer 1306. The hard mask 1304 may be any suitable masking material. In some embodiments, the hard mask 1304 is formed of a nitrogen-containing material (e.g., SiN or SiCN). The resist layer 1306 can be a single-layer or three-layer photoresist. An exemplary three-layer photoresist may include a bottom layer 1308, an intermediate layer 1310 disposed above the bottom layer 1308, and a top photoresist layer 1312 disposed above the intermediate layer 1310. The resist layer 1306 can be formed by any suitable process (e.g., spin coating). The bottom layer 1308 may be a bottom anti-reflective coating (BARC). The intermediate layer 1310 may be a silicon-containing inorganic polymer that provides anti-reflective properties and / or hard masking properties for lithography processes. The top photoresist layer 1312 may be a DUV resist (KrF), an argon fluoride (ArF) resist, an EUV resist, an electron beam (e-beam) resist, or an ion beam resist.

[0052] In Figures 13A and 13B, the photoresist top layer 1312 is patterned to form a plurality of photoresist mandrels separated from each other by openings. For ease of illustration, only two openings 1402a and 1402b are shown. The patterned photoresist top layer 1312 serves as a mask to transfer the pattern in the photoresist top layer 1312 (i.e., openings 1402a and 1402b) into the intermediate layer 1310, the bottom layer 1308, and the mask layer 1304. Openings 1402a and 1402b define isolation trenches to be formed in the base portion of the fin structures 102b and 102c. Isolation trenches can be formed between adjacent active regions. The term "active region" refers to the region where a transistor is formed. As will be discussed in more detail below, isolation trenches can be formed by performing a fin dicing (or wafer dicing) process. The isolation trenches are filled with a dielectric to form continuous polysilicon (CPODE) trenches on the diffusion edge. This fin-cutting (or wafer-cutting) process can be referred to as the CPODE process. The term "diffusion edge" is equivalently called the active edge, which is the edge adjacent to an adjacent active region. The CPODE process can be used to reduce gate spacing, thereby increasing the density of multi-gate devices, and thus increasing the device performance required for significantly reduced circuits and devices.

[0053] In Figures 14A and 14B, the pattern (i.e., openings 1402a, 1402b) in the top photoresist layer 1312 (Figures 13A and 13B) is transferred to the mask layer 1304 to form a patterned mask layer 1304'. The bottom layer 1308, the intermediate layer 1310, and the top photoresist layer 1312 are then removed. The formation of the patterned mask layer 1304' can be achieved by one or more lithography processes. As a result of these one or more lithography processes, some portions of the hard mask 1304 are removed, and trench patterns 1402a', 1402b' (collectively referred to as trench patterns 1402') are formed in the patterned mask layer 1304', and a portion of the sacrificial gate electrode layer 134 is exposed. The trench patterns 1402a', 1402b' are elongated openings aligned with the sacrificial gate structure 130. Etching chemicals (such as CF4, CHF3, CH2F2, CHF3, C4F6, etc.) can be used to remove portions of the hard mask 1304 (and the native oxide formed thereon). The patterned mask layer 1304' can then be used to protect the active region during subsequent removal of the exposed sacrificial gate structure and fin cutting (or wafer cutting) processes.

[0054] In Figures 15A and 15B, exposed sacrificial gate structures (e.g., sacrificial gate electrode layer 134) are selectively removed to form openings 1602a and 1602b (collectively referred to as opening 1602). Opening 1602 exposes gate spacer 138 and sacrificial gate dielectric layer 132. The removal of the exposed sacrificial gate structures can be performed by a selective etching process that removes sacrificial gate electrode layer 134 but substantially does not affect gate spacer 138 and sacrificial gate dielectric layer 132. Sacrificial gate dielectric layer 132 protects first semiconductor layer 106 and second semiconductor layer 108 during etch-back processes. In some embodiments, sacrificial gate dielectric layer 132 can also be removed during selective etching processes. In some embodiments, the etching chemicals are selective for the sacrificial gate structures to be etched while minimizing etching of surrounding dielectric layers (e.g., insulating material 118, gate spacer 138, CESL 162, and first ILD layer 164). In some embodiments, the sacrificial gate structure 130 may be removed using chlorine-containing gases (e.g., SiCl4, BCl3, Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. In some embodiments, the sacrificial gate electrode layer 134 has a top flush with the top of the sacrificial gate dielectric layer 132. The following fin cutting or wafer cutting process will remove the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 from the CPODE trench.

[0055] In Figures 16A and 16B, an etching process is performed to remove the sacrificial gate dielectric layer 132. The etching process can be dry etching, wet etching, or a combination thereof. The etching process selectively removes the sacrificial gate dielectric layer 132 without affecting the first semiconductor layer 106, the second semiconductor layer 108, and the sacrificial gate electrode layer 134.

[0056] Figures 17A and 17B through 24A and 24B illustrate the process of extending opening 1602 into the substrate portion for forming isolation trenches in the fin structures 102b, 102c. Specifically, the isolation trenches (and subsequent CPODE structures) are formed such that the exposed substrate 101 has a substantially flat top surface, which prevents the top of the exposed substrate from forming fin structures and becoming parasitic bipolar junction transistors (BJTs). In Figures 17A and 17B, a first semiconductor etching process 141 is performed to remove the first semiconductor layer 106 and the second semiconductor layer 108 (and, in some cases, a small portion of the insulating material 118 exposed due to ion bombardment), thereby forming a first segment of the isolation trench 1802. The first semiconductor etching process 141 is a fin cutting (or wafer cutting) process. A patterned mask layer 1304' is used as an etching mask to perform the first semiconductor etching process 141. The first semiconductor etching process 141 can be dry etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the first semiconductor etching process 141 is an anisotropic etching (directional etching) process. Performing the first semiconductor etching process 141 selectively removes portions of the exposed first semiconductor layer 106, second semiconductor layer 108, and substrate 101 that form the fin structures 102b, 102c. A portion of the insulating material 118 surrounding the fin structures 102b, 102c may also be removed. In some embodiments, a self-aligned CPODE etching process is used to remove portions of the exposed first semiconductor layer 106, second semiconductor layer 108, and substrate 101. The self-aligned CPODE etching process is configured to have high etch selectivity, such that the etching rate of the first semiconductor layer 106 and second semiconductor layer 108 is greater than the etching rate of the internal spacer 144. As a result, the internal spacer 144 remains substantially intact after the fin cutting process.

[0057] As a result of the first semiconductor etching process 141, isolation trenches 1802a and 1802b (collectively referred to as isolation trench 1802) are formed and extended into portions of the fin structures 102b and 102c formed on the substrate 101 (FIG. 17A). In various embodiments, the first semiconductor etching process 141 is performed such that first segments of the isolation trenches 1802a and 1802b are formed with straight and symmetrical sidewall profiles relative to an imaginary line passing through the center of the respective isolation trenches 1802a and 1802b in the depth direction of the isolation trenches 1802a and 1802b. In some embodiments, the isolation trenches 1802a and 1802b may have a first depth D1, defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs1 of the isolation trenches 1802a and 1802b. The first depth D1 can be selected based on the desired level of the narrowest critical dimension (CD). In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is at substantially the same height as the bottom of the epitaxial S / D feature 146. In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is lower than the top surface of the well portion of the substrate 101. In some embodiments, the first depth D1 is substantially equal to the height of the epitaxial S / D feature.

[0058] Self-aligned CPODE etching processes can be achieved using plasma etching with bromine-based (and / or chlorine-based) and oxygen-based chemicals. Exemplary bromine-based etching chemicals may include, but are not limited to, HBr, Br2, BBr3, and combinations thereof. Exemplary chlorine-based etching chemicals may include, but are not limited to, Cl2, CHCl3, CCl4, BCl3, and combinations thereof. Exemplary oxygen-based etching chemicals may include, but are not limited to, O2, CO2, O3, water vapor, and combinations thereof. In some embodiments, plasma etching is performed in a high-density plasma processing chamber using an inductively coupled plasma (ICP) or dipole antenna plasma source. In some embodiments, a resonant antenna plasma source or an electron cyclotron resonance (ECR) plasma source may also be used to achieve low-voltage operation (e.g., about 0.2 ± 0.05 mTorr). The plasma can be driven by an RF power generator using AC currents operating at multiple 13.56 MHz frequencies. The processing chamber can operate at pressures ranging from approximately 0.2 mTorr to approximately 150 mTorr and temperatures ranging from approximately 20°C to approximately 120°C. An RF power generator is operated to provide source power ranging from approximately 100 W to approximately 2500 W. Higher directivity can be achieved by adding bias power to the substrate within the processing chamber. In this case, a DC bias power operating in the range of approximately 0 V to approximately 1000 V (e.g., approximately 50 V to 150 V) can be used. In some cases, pulsed plasma etching can be used. In this case, the output of the power generator can be controlled by a pulse signal with a duty cycle ranging from approximately 5% to 95%. Alternatively, a self-aligned CPODE etching process can enhance etching directivity using only bias power (with zero source power).

[0059] While bromine- or chlorine-based etching chemicals have been discussed, other etching chemicals, such as fluorine-based etching chemicals, may also be used. Exemplary fluorine-containing gases may include, but are not limited to, CF4, SF6, CH2F2, C2H4F2, CHF3, C2F6, NF3, and combinations thereof. Alternatively, the etchant used in the first semiconductor etching process 141 may be a fluorine / chlorine-based etching chemical, a fluorine / bromine-based etching chemical, or any combination thereof.

[0060] In some embodiments, plasma etching can be performed in a plasma etching chamber having the capability to form in-situ ALD of silicon oxide or silicon nitride.

[0061] In Figures 18A and 18B, a second semiconductor etching process 147 is performed to further remove the exposed insulating material 118 and the substrate portion forming the fin structures 102b, 102c. Similarly, the second semiconductor etching process 147 is performed such that the second segments of the isolation trenches 1802a, 1802b are formed with straight and symmetrical sidewall profiles relative to an imaginary line passing through the center of the respective isolation trenches 1802a, 1802b in the depth direction. The isolation trench 1802 is formed with a uniform CD along the depth direction. Specifically, the second semiconductor etching process 147 is performed such that the bottom of the isolation trench 1802 (or in other words, the top surface 101ts of the exposed substrate 101) is flat or substantially flat. The terms "flat" or "substantially flat" as described in this disclosure mean that the surface is substantially planar, with a standard deviation from a flat surface of less than about 5 nm to about 20 nm. The substrate 101 with a flat top surface 101ts does not form a parasitic bipolar junction transistor, which would otherwise be produced in a conventional etch semiconductor process, in which the substrate 101 is etched to form a high aspect ratio fin structure in the well region, resulting in the formation of an EPI-substrate-EPI leakage path.

[0062] The second semiconductor etching process 147 is performed using the same etching chemicals as the first semiconductor etching process 141. The substrate portions of the fin structures 101b and 102c can be removed by the second semiconductor etching process 147 using a plasma etching process including HBr and / or Cl2. In some embodiments, O2 and / or CO2 can be added to the HBr and / or Cl2-based plasma to promote the dissociation of plasma byproducts. In some embodiments, the plasma etching process can be a high-density plasma process using process conditions similar to the first semiconductor etching process 141. The second semiconductor etching process 147 is performed to extend the isolation trenches 1802a and 1802b to a height substantially equal to the interface 137 defined by the substrate 101 and the insulating material 118. The isolation trenches 1802a and 1802b have a second depth D2 measured from the topmost first semiconductor layer 106 to the bottom surface 1802bs2 of the isolation trenches 1802a and 1802b. In other words, the depth of each isolation trench 1802a, 1802b extends from a first depth D1 to a second depth D2. Isolation trenches 1802 with a uniform CD along the depth direction can be obtained through a cyclic process. For example, the processes in Figures 17A and 17B to 18A and 18B can be repeated until the isolation trenches 1802a, 1802b reach a predetermined height.

[0063] One or more etching conditions can be controlled to achieve low-selectivity etching between silicon (e.g., substrate 101) and silicon oxide (e.g., insulating material 118). For example, during the second semiconductor etching process 147, low voltage levels (e.g., chamber pressure below about 50 mTorr) and / or high bias power to the substrate pedestal (e.g., greater than 300 V) can be used to compensate for the etch selectivity required to remove the substrate portions of the insulating material 118 and fin structures 102b, 102c. In some embodiments, the bias power used during the second semiconductor etching process 147 is greater than the bias power used in the first semiconductor etching process 141.

[0064] In some embodiments, boron trichloride (BCl3) and the like can be used to enhance the etch selectivity of silicon oxide, thereby achieving low-selectivity etching between silicon and silicon oxide. In some embodiments, the bottom surface 1802bs2 of the isolation trenches 1802a, 1802b can be located at a height within the well region or accumulation region of the substrate 101. The term "accumulation region" refers to a non-conductive region in the substrate 101 that is below the depletion region (a conductive region located at / near the well region of the substrate 101). In any case, the second depth D2 is sufficient to block the path of leakage current through the epitaxial source / drain features and the silicon substrate. In some embodiments, the second depth D2 can be in the range of about 60 nm and about 200 nm.

[0065] In some embodiments, after the second semiconductor etching process 147, the top surface 101ts of the exposed substrate 101 may have a wave-shaped profile. Figure 18B shows an enlarged view of a portion of the substrate 101 shown in Figure 18B according to some embodiments. It should be understood that the embodiments of Figure 18B-1 can be applied to the embodiments of Figure 18B and any one or more embodiments shown in this disclosure, wherein the bottom of the isolation trench 1802 is at the height of the interface 137 defined by the substrate 101 and the insulating material 118. Therefore, the subsequent CPODE structure has a wave-shaped bottom.

[0066] In some embodiments, a second semiconductor etching process 147 is performed such that the bottom surface of the isolation trench 1802 is at a height below the interface 137 defined by the substrate 101 and the insulating material 118. In some cases, the bottom surface is at a height within the well region of the substrate 101. Figure 19 illustrates an embodiment in which the isolation trench 1802 is etched to have a bottom 1802bs3 extending to a certain depth within the well region of the substrate 101. Such recesses in the substrate 101 can be obtained by controlling one or more etching conditions to achieve low-selectivity etching between silicon (e.g., substrate 101) and silicon oxide (e.g., insulating material 118). For example, during the second semiconductor etching process 147, low pressure ranges (e.g., chamber pressures below about 50 mTorr) and / or high bias power to the substrate base (e.g., greater than 300 V) can be used to compensate for the etch selectivity required to remove the substrate portions of the insulating material 118 and the fin structures 102b, 102c. In some embodiments, the bias power used during the second semiconductor etching process 147 is greater than the bias power used during the first semiconductor etching process 141.

[0067] In some embodiments, a second semiconductor etching process 147 is performed such that a portion of the insulating material 118 is retained and protrudes inward over the sidewalls 134s of the sacrificial gate electrode layer 134, as shown in FIG20. This protrusion 118p of the insulating material 118 can be formed during the second semiconductor etching process 147 under the protection of a patterned masking layer 1304'. Similarly, the isolation trench 1802 is etched to have a bottom with a certain depth extending into the well region of the substrate 101. Therefore, the bottom surface 1802bs4 is at a height below the interface 137 defined by the substrate 101 and the insulating material 118.

[0068] In either of the embodiments of FIG. 19 or FIG. 20, the top surface 101ts of the substrate 101 may have a wave-like profile. FIG. 19-1 shows an enlarged view of a portion of the substrate 101 shown in FIG. 19 according to some embodiments. In some embodiments, the exposed substrate 101 is etched to have a peak 101p and a valley 101v. The peak 101p may have a distance D3 measured from the highest point of the exposed substrate 101's top surface 101ts to the interface 137 (defined by the substrate 101 and the insulating material 118), while the valley 101v may have a distance D4 measured from the lowest point of the exposed substrate 101's top surface 101ts to the interface 137. In some embodiments, the ratio of distance D3 to distance D4 may be from about 1.1 to about 1.5, for example, about 1.3. It should be understood that the embodiment of FIG19-1 can be applied to the embodiment of FIG20 and / or any one or more embodiments disclosed herein, wherein the bottom of the isolation trench 1802 is at a height within the well region of the substrate 101 (i.e., below interface 137). Therefore, the subsequent CPODE structure has a bottom with a wave-like profile.

[0069] In Figures 21A and 21B, the isolation trench 1802 (Figures 18A and 18B) is filled with a dielectric material 2130. In some embodiments, a dielectric liner 2132 may be disposed between the dielectric material 2130 and the exposed surface of the isolation trench 1802. The dielectric material 2130 and dielectric liner 2132 filling the isolation trench 1802 form an isolation trench structure (so-called CPODE trench) 2134. The isolation trench structure 2134 has a substantially flat bottom surface 1802bs2. The bottom surface 1802bs2 of the isolation trench structure 2134 and the top surface 101ts of the substrate 101 define a substantially flat interface. The dielectric material 2130 and dielectric liner 2132 can be made of oxygen-containing materials, such as silicon oxide (SiO2); nitrogen-containing materials, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; low-k dielectric materials; or any suitable dielectric material. The dielectric material 2130 may include chemical materials different from those of the dielectric liner 2132 and can be formed by any suitable process, such as CVD, PECVD, FCVD, or ALD processes.

[0070] In Figures 22A and 22B, once the isolation trench 1802 is filled, a planarization process (e.g., a CMP process) can be performed to remove portions of the dielectric material formed above the patterned mask layer 1304'. The planarization process can be performed until a portion of the cap layer 139 or ILD layer 164 is exposed.

[0071] In Figures 23A and 23B, the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed. Exposed dielectric liner 2132 on the sidewalls of the dielectric material 2130 may also be removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening 166 between the first semiconductor layer 106. The cap layer 139, CESL 162, and the first ILD layer 164 protect the epitaxial source / drain features 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) may be used to selectively remove the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132, but not the gate spacer 138, the isolation trench structure 2134, the first ILD layer 164, and the CESL 162. After the sacrificial gate structure 130 is removed, the first semiconductor layer 106 and the internal spacer 144 are exposed to the opening 166.

[0072] In Figures 24A and 24B, an alternative gate structure 190 is formed. Each alternative gate structure 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interface layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The interface layer 178 may also be formed on the exposed surfaces of the substrate 101, the insulating material 118, and the dielectric layer 2132. The interface layer 178 may include or be made of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride, silicon oxynitride, oxynitride, etc.), and / or dielectric layers (e.g., hafnium silicate) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106. Next, a gate dielectric layer 180 is formed on the exposed surfaces of the semiconductor device structure 100 (e.g., on the sidewalls of the ILD layer 138, the first ILD layer 164, the CESL layer 162, and the top surface of the cap layer 139, if any). The gate dielectric layer 180 may be formed from a different chemical material than the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or be made of a high-k dielectric material. The gate dielectric layer 180 may be a conformal layer formed by a conformal process (e.g., ALD process, PECVD process, molecular beam deposition (MBD) process, or a combination thereof).

[0073] After forming the IL (if any) and gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166 (FIG. 23A) and surrounds a portion of each first semiconductor layer 106. The gate electrode layer 182 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) can be deposited conformally (and sequentially if more than one) between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers may include one or more barrier layers and / or cap layers and one or more work function tuning layers. The one or more barrier layers and / or cap layers may include, for example: tantalum and / or titanium nitrides, silicon nitrides, carbonitrides, and / or aluminum nitrides; tungsten nitrides, carbonitrides, and / or carbides; etc.; or combinations thereof. The one or more work function tuning layers may include, for example: titanium and / or tantalum nitrides, silicon nitrides, carbonitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides; tungsten nitrides, carbonitrides, and / or carbides; cobalt; platinum; etc.; or combinations thereof.

[0074] A portion of the gate electrode layer 182, one or more optional conformal layers (if any), and the gate dielectric layer 180 above the top surface of the first ILD layer 164, CESL 162, cap layer 139 (if any), and gate spacer 138 can be removed by a planarization process (e.g., by a CMP process). After the CMP process, the top surfaces of the isolation trench structure 2134, the first ILD layer 164, CESL 162, gate spacer 138, and gate electrode layer 182 are substantially coplanar.

[0075] In Figures 25A and 25B, the gate electrode layer 182 may optionally undergo one or more metal gate etch-back (MGEB) processes. The MGEB process is performed to recess the top surfaces of the gate electrode layer 182 and the gate dielectric layer 180 to a level below the top surface of the gate spacer 138. In some embodiments, the gate spacer 138 is also recessed to a level below the top surface of the ILD layer 164. A self-aligned contact layer 192 is formed over the gate electrode layer 182. The self-aligned contact layer 192 may be a dielectric material (e.g., SiN) with etch selectivity relative to the ILD layer 164. The self-aligned contact layer 192 protects the gate electrode layer 182 during the formation of contact openings. A silicon layer 184 is then formed on the epitaxial source / drain feature 146, and S / D contacts 186 are formed in the contact openings on the silicon layer 184. Contact 186 may include a conductive material, such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) may be formed on the sidewalls of the contact opening before forming the S / D contact 186. Then, a planarization process (e.g., CMP) is performed to remove excess deposited contact material and expose the top surface of the gate electrode layer 182.

[0076] As can be seen, the isolation trench structure 2134 has a substantially flat bottom surface 1802bs2, which is at the same height as the interface 137 defined by the substrate 101 and the insulating material 118. The bottom surface 1802bs2 extends across the diameter of the isolation trench structure 2134 and contacts the substantially flat top surface of the substrate 101. It has been observed that the lattice mismatch and different thermal expansion characteristics between the substrate 101 and the dielectric material 2130 (of the isolation trench structure 2134) can lead to charge trapping at the interface of the silicon and refilled dielectric heterostructure. Negative trapped charges at the interface of the silicon and refilled dielectric heterostructure may lead to P-type EPI to P-type EPI leakage via parasitic PNP bipolar junction transistors (BJTs), while positive trapped charges at the interface of the silicon and refilled dielectric heterostructure may lead to N-type EPI to N-type EPI leakage via parasitic NPN BJTs. While reducing the depth of the CPODE / CMODE structure can prevent the formation of parasitic finned BJTs beneath the STI (i.e., insulating material 118), insufficient etching can still lead to silicon residue on the STI sidewalls, resulting in current leakage. By forming an isolation trench structure 2134 with a flat bottom surface 1802bs2, a finned structure is not formed on the top of the substrate 101, which would otherwise become a parasitic BJT. As a result, leakage current via epitaxial source / drain features and the silicon substrate is avoided.

[0077] Figures 26 and 27 show cross-sectional views of the semiconductor device structure 100 according to the embodiments shown in Figures 19 and 20, respectively. It can be seen that an isolation trench structure 2134 is formed such that the bottom of the isolation trench structure 2134 extends to a certain depth in the well region of the substrate 101. Specifically, the bottom surfaces 1802bs3 and 1802bs4 of the isolation trench structure 2134 are at a height below the interface 137 defined by the substrate 101 and the insulating material 118. In either case, the isolation trench structure 2134 has sidewalls composed of the insulating material 118 and the substrate 101. In the embodiment of Figure 27, a portion of the insulating material 118 protruding into the isolation trench structure 2134 has a top surface 118t in contact with the dielectric material 2130, and the sidewalls 118s of the insulating material 118 are in contact with the dielectric liner 2132.

[0078] Figure 28 is a top view of the semiconductor device structure 100 shown in Figures 25A and 25B according to some embodiments. For clarity, some components of the semiconductor device structure 100, such as the self-aligned contact layer 192 and CESL 162, are omitted in Figure 28. Figures 29A, 29B, and 29C are cross-sectional views of the semiconductor device structure 100 taken along lines DD, EE, and FF of Figure 28, respectively. As can be seen in Figure 29B, the isolation trench structure 2134 extends through the insulating material 118 (e.g., STI) and into the well region of the substrate 101 to block leakage current between transistors. In addition, the isolation trench structure 2134 with a flat silicon interface also eliminates parasitic fin BJTs in and / or beneath the well region of the substrate 101. Therefore, leakage path 2801 (Figure 28) via EPI-transistor-substrate-EPI is avoided.

[0079] It should be understood that the semiconductor device structure 100 can be further processed using complementary metal-oxide-semiconductor (CMOS) and / or back-end processing (BEOL) to form various features, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structure 100 may also include back-side contacts (not shown) on the back side of the substrate 101, such that the source or drain of the epitaxial S / D feature 146 is connected to a back-side power rail (e.g., a positive voltage VDD or a negative voltage VSS) via the back-side contacts.

[0080] Figures 30 to 36 illustrate alternative embodiments in which a portion of the insulating material 118 is retained within the isolation trench structure and on the top surface 101ts of the exposed substrate 101. In Figure 30, after a first semiconductor etching process 141 removes the first semiconductor layer 106 and the second semiconductor layer 108 (and in some cases a small portion of the insulating material 118), a modified second semiconductor etching process 149 is performed to further remove some portions of the exposed insulating material 118 and the substrate portion forming the fin structures 102b, 102c. The modified second semiconductor etching process 149 is a selective etching process that selectively or preferentially removes silicon (e.g., the substrate portion forming the fin structures 102b, 102c) over silicon oxide (e.g., the insulating material 118). As a result, the insulating material 118 in the form of a plurality of fin structures 118f is retained at the bottom of the isolation trenches 1802a, 1802b (collectively referred to as isolation trench 1802). The top of the fin structure 118f of the insulating material 118 is below the height of the top surface of the insulating material 118 or the interface 142 defined by the insulating material 118 and the sacrificial gate electrode layer 134. In some embodiments, after the modified second semiconductor etching process 149, the top surface 101ts of the exposed substrate 101 may have a flat and curved profile (FIG. 36).

[0081] Directional silicon etching can be achieved by using a plasma etching process with HBr / Cl2-based chemicals containing added O2 and / or CO2 (similar to those used in the second semiconductor etching process 147). Greater directionality can be achieved by adding bias power to the substrate in the processing chamber. The top of the insulating material 118 can have a curved recess due to ion bombardment. In some embodiments, the modified second semiconductor etching process 149 is a two-step process comprising anisotropic etching and isotropic etching. The anisotropic etching process can be plasma etching using bromine-based (e.g., HBr) or chlorine-based (e.g., Cl2) etching chemicals as previously discussed with respect to the first semiconductor etching process 141 (in Figures 17A and 17B). The isotropic etching process can be plasma etching using fluorine-based (e.g., NF3) and / or hydrogen-based (e.g., H2) etching chemicals. In some embodiments, bias power is applied during both the anisotropic and isotropic etching processes. In some embodiments, a bias power is applied during anisotropic etching and an isotropic etching is performed without bias power. Alternatively, the anisotropic etching process may be a dry etching process, while the isotropic etching process may be a wet etching process to achieve highly selective etching between the substrate 101 and the insulating material 118.

[0082] In some embodiments, the modified second semiconductor etching process 149 is a plasma-based atomic layer etching (ALE) process, which is a cyclic etching process involving gas metering and ion bombardment to remove material layer by layer with low damage to the structure. The ALE process facilitates the formation of a flat top surface 101ts of the substrate 101. An exemplary ALE process may include (1) metering the semiconductor device structure 100 disposed in a processing chamber with a halogen-based etching gas (e.g., fluorine-based, chlorine-based, and / or bromine-based chemicals as described above), which is absorbed and chemically reacted with the insulating material 118 and the substrate portions forming the fin structures 102b, 102c; (2) removing residual dosed gas from the processing chamber; (3) bombarding the insulating material 118 and the substrate portions forming the fin structures 102b, 102c with low-energy inert ions (e.g., argon) to remove the reacted surface layer; and (4) removing etching byproducts from the processing chamber. In some embodiments, a radical-based ALE method may be used.

[0083] In some embodiments, the ALE process may use oxygen molecules or free radicals to chemically react with the insulating material 118 and the substrate portion forming the fin structures 102b, 102c, and the reacted layer (e.g., SiO2) may be removed by HF-based chemicals.

[0084] In Figure 31, the isolation trench 1802 (Figure 30) is filled with dielectric material 2130a (e.g., dielectric material 2130). Similarly, a dielectric liner 2132a (e.g., dielectric liner 2132) can be first disposed on the exposed surface of the isolation trench 1802. That is, the dielectric liner 2132a is deposited on the exposed surface of each fin structure 118f of the insulating material 118, the insulating material 118, the substrate 101, the sacrificial gate electrode layer 134, and the sidewalls of the patterned masking layer 1304'. The dielectric material 2130a and dielectric liner 2132a filled within the isolation trench 1802 form an isolation trench structure 2134a. The isolation trench structure 2134a has a plurality of fin-shaped insulating materials 118f on the substantially flat top surface 101ts of the substrate 101.

[0085] In Figure 32, once the isolation trench 1802 is filled, a planarization process can be performed to remove portions of the dielectric material formed on the patterned masking layer 1304', such as those discussed above with respect to Figures 22A and 22B. The planarization process can be performed until a portion of the capping layer 139 or the sacrificial gate electrode layer 134 is exposed.

[0086] In Figure 33, the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed, as discussed above with respect to Figures 23A and 23B.

[0087] In FIG. 34, an alternative gate structure is formed. Each of the alternative gate structures 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interface layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The interface layer 178, the gate dielectric layer 180, and the gate electrode layer 182 may be formed in a manner similar to that discussed above with respect to FIGS. 24A and 24B to FIGS. 25A and 25B.

[0088] A planarization process can be used to remove portions of the gate electrode layer 182 and the gate dielectric layer 180 above the top surfaces of the first ILD layer 164 (not shown), CESL 162 (not shown), cap layer 139 (not shown), and gate spacer 138 (not shown). After the CMP process, the top surfaces of the isolation trench structure 2134a, the first ILD layer 164, CESL 162, gate spacer 138, and gate electrode layer 182 are substantially coplanar.

[0089] In some embodiments, the modified second semiconductor etching process 149 is configured as a highly selective etching process, such that a majority of the insulating material 118 is retained within the isolation trench 1802. Figure 35 shows a cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment, in which the fin-like structures 118f-1 of the insulating material 118 in the isolation trench structure 2134 have a top at substantially the same height as the insulating material 118 below the gate electrode layer 182.

[0090] Figure 36 shows an enlarged view of a portion of the substrate 101 shown in Figures 34 and 35 according to some embodiments. It can be seen that the top surface 101ts of the substrate 101 may include a substantially flat first portion 101ts-1 and a second portion 101ts-2 with a curved profile due to pre-exposure to etching chemicals during a modified second semiconductor etching process 149. The lowest top surface 101ts-2 of the substrate 101 is located below the height of the interface 137 defined by the substrate 101 and the insulating material 118.

[0091] Figures 37 to 43 illustrate an alternative embodiment in which a portion of the insulating material 118 is retained within the isolation trench structure and disposed away from the top surface 101ts of the exposed substrate 101. In Figure 37, after the first semiconductor etching process 141 removes the first semiconductor layer 106 and the second semiconductor layer 108 (and in some cases a small portion of the insulating material 118), a modified second semiconductor etching process 151 is performed to further remove some portions of the exposed insulating material 118, the substrate portions forming the fin structures 102b, 102c, and a portion of the exposed substrate 101. The modified second semiconductor etching process 151 is a selective etching process that selectively removes silicon (e.g., the substrate portions forming the fin structures 102b, 102c and the substrate 101) over silicon oxide (e.g., the insulating material 118). A modified second semiconductor etching process 151 is performed such that the bottom surface 1802bs5 of the isolation trench 1802 is at a height below the interface 137 defined by the substrate 101 and the insulating material 118. As a result, the insulating material 118, in the form of a plurality of fin-like structures 118f-2, is retained within the isolation trench 1802 and separated from the recessed substrate 101 by openings 150. Furthermore, the isolation trench structure 2134a is formed to have a substantially flat bottom surface 1802bs5, as discussed above with respect to Figures 18B, 19, and 20.

[0092] Referring to Figures 28 and 37, the fin-like structures 118f-2 of the insulating material 118 are connected to or supported by the epitaxial source / drain feature 146, which can be positioned along the X-direction (into the plane of the paper). The top of the fin-like structures 118f-2 of the insulating material 118 is at a height below the top surface of the insulating material 118 or at the interface 142 defined by the insulating material 118 and the sacrificial gate electrode layer 134. The bottom of each fin-like structure 118f-2 of the insulating material 118 is at substantially the same height as the interface 137 defined by the substrate 101 and the insulating material 118.

[0093] The modified second semiconductor etching process 151 is similar to the modified second semiconductor etching process 149. In one embodiment, a two-step process including anisotropic etching and isotropic etching is used. The anisotropic etching process is plasma etching using bromine-based (e.g., HBr) etching chemicals, while the isotropic etching process is plasma etching using fluorine-based (e.g., NF3) and / or hydrogen-based (e.g., H2) etching chemicals. To compensate for the etch selectivity required to remove the substrate 101 and the substrate portions forming the fin structures 102b, 102c, a high pressure range (e.g., a chamber pressure greater than about 50 mTorr) and / or a high bias power (e.g., greater than 300 V) on the substrate pedestal can be used. In some embodiments, a high bias power is applied during the anisotropic etching process, while a low bias power is used during the isotropic etching process. Alternatively, the anisotropic etching process can be a dry etching process, while the isotropic etching process can be a wet etching process, to achieve highly selective etching between the substrate 101 and the insulating material 118.

[0094] In Figure 38, the isolation trench 1802 (Figure 37) is filled with dielectric material 2130b (e.g., dielectric material 2130). Similarly, a dielectric liner 2132b (e.g., dielectric liner 2132) can be first disposed on the exposed surface of the isolation trench 1802. That is, the dielectric liner 2132b is deposited on the exposed surface of each fin structure 118f-2 of the insulating material 118, the insulating material 118, the substrate 101, the sacrificial gate electrode layer 134, and the patterned masking layer 1304'. The dielectric material 2130b and the dielectric liner 2132b filled within the isolation trench 1802 form the isolation trench structure 2134b. Each of the plurality of fin structures 118f-2 of the insulating material 118 in the isolation trench structure 2134b is separated from the flat top surface 101ts of the substrate 101 by dielectric material 2130 and dielectric liner 2132.

[0095] In Figure 39, once the isolation trench 1802 is filled, a planarization process can be performed to remove portions of the dielectric material formed on the patterned masking layer 1304', such as those discussed above with respect to Figures 22A and 22B. The planarization process can be performed until a portion of the capping layer 139 or the sacrificial gate electrode layer 134 is exposed.

[0096] In Figure 40, the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed, as discussed above with respect to Figures 23A and 23B.

[0097] In FIG. 41, an alternative gate structure is formed. Each of the alternative gate structures 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interface layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The interface layer 178, the gate dielectric layer 180, and the gate electrode layer 182 may be formed in a manner similar to that discussed above with respect to FIGS. 24A and 24B to FIGS. 25A and 25B. Some portions of the gate electrode layer 182 and the gate dielectric layer 180 above the top surfaces of the first ILD layer 164 (not shown), CESL 162 (not shown), cap layer 139 (not shown), and gate spacer 138 (not shown) may be removed by a planarization process. After the CMP process, the top surfaces of the isolation trench structure 2134a, the first ILD layer 164, the CESL 162, the gate spacer 138, and the gate electrode layer 182 are substantially coplanar.

[0098] In some embodiments, the modified second semiconductor etching process 151 is configured as a highly selective etching process, such that a majority of the insulating material 118 is retained within the isolation trench 1802. Figure 42 shows a cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment. In this embodiment, the fin structures 118f-3 of the insulating material 118 in the isolation trench structure 2134c have a top that is substantially at the same height as the insulating material 118 below the gate electrode layer 182 (or the interface 153 defined by the interface layer 178 and the insulating material 118). The bottom of each fin structure 118f-3 of the insulating material 118 is substantially at the same height as the interface 137 defined by the substrate 101 and the insulating material 118.

[0099] Figure 43 shows an enlarged view of a portion of the substrate 101 shown in Figures 41 and 42 according to some embodiments. It can be seen that the substrate 101 can be etched to have peaks 101p and valleys 101v, thereby producing a CPODE structure with a wavy bottom surface profile.

[0100] While the various embodiments in Figures 10A through 43 describe the first CPODE processing method (i.e., during the front-end-of-line (FEOL) processing prior to metal gate formation), these embodiments are equally applicable to the post-CPODE processing method (or the so-called CMODE process), i.e., during the middle-end-of-line (MEOL) processing after metal gate formation. Figures 44A and 44B through 49A and 49B are cross-sectional views of one of the various stages of fabricating a semiconductor device structure 100 according to some embodiments involving the CMODE process (i.e., after the formation of the metal gate structure). In Figures 44A and 44B, the sacrificial gate structure 130 (Figures 10A and 10B), the sacrificial dielectric layer 132 (Figures 10A and 10B), and the second semiconductor layer 108 (Figures 10A and 10B) have been replaced by an ILD (not shown), a gate dielectric layer 180, and a gate electrode layer 182, as discussed above with respect to Figures 23A and 23B to 24A and 24B. The gate dielectric layer 180 and the gate electrode layer 182 are planarized, for example, by CMP, until the top surface of the ILD layer 164 is exposed. Then, a masking layer 181 is formed on the gate electrode layer 182, the ILD layer 164, the gate spacer 138, and the CESL 162. The masking layer 181 may comprise the same material as the hard mask 1304 described above.

[0101] In Figures 45A and 45B, a mask structure 152 is formed on a mask layer 181. In some embodiments, the mask structure 152 is a three-layer photoresist. For example, the mask structure 152 may include a base layer 154 and an intermediate layer 156 disposed on the base layer 154. The base layer 154 and the intermediate layer 156 are made of different materials such that the optical properties and / or etch properties of the base layer 154 and the intermediate layer 156 are different from each other. In some embodiments, the base layer 154 may be a carbon layer, and the intermediate layer 156 may be a silicon-rich layer designed to provide etch selectivity between the intermediate layer 156 and the base layer 154. The mask structure 152 also includes a photoresist layer 158, which may be a chemically amplified photoresist layer and may be a positive or negative photoresist. The photoresist layer 158 may include a polymer. The photoresist layer 158 may be formed by spin coating. The photoresist layer 158 may be patterned to have openings 159 formed therein.

[0102] In Figures 46A and 46B, opening 159 extends into the intermediate layer 156, the bottom layer 154, and the masking layer 181 to expose at least some portions of the gate electrode layer 182. Then, the masking structure 152 is removed after opening 159 has been extended into the masking layer 181.

[0103] In Figures 47A and 47B, a patterned mask layer 181 is used as a mask to remove portions of the gate electrode layer 182, the gate dielectric layer 180, the first semiconductor layer 106, the insulating material 118, and the substrate portion forming the fin structures 102e and 102f. Layer removal can be achieved using any suitable dry etching, wet etching, or a combination thereof (e.g., those discussed above with respect to Figures 14A through 20). As a result of (one or more) removal processes, an isolation trench 4702 is formed. The isolation trench 4702 is etched to have a bottom 4702bs1 extending to a certain depth into the well region of the substrate 101. Such recesses in the substrate 101 can be obtained by controlling one or more etching conditions to achieve low-selectivity etching between silicon (e.g., substrate 101) and silicon oxide (e.g., insulating material 118). For example, during the removal process, a low pressure range (e.g., a chamber pressure below about 50 millitor) and / or a high bias power to the substrate (e.g., greater than 300 V) can be used to compensate for the etch selectivity required to remove the substrate portions of the insulating material 118 and the fin structures 102e, 102f.

[0104] In some embodiments, the isolation trench 4702 is etched such that the bottom surface 4702bs1 of the isolation trench 4702 (or in other words, the top surface 101ts of the exposed substrate 101) is substantially flat. In one embodiment, the bottom surface 4702bs1 is at a height below the interface 137 defined by the substrate 101 and the insulating material 118. As described above, the substrate 101 with a flat top surface 101ts does not form a parasitic bipolar junction transistor in the well region, which could lead to the formation of an EPI-substrate-EPI leakage path.

[0105] In Figures 48A and 48B, the isolation trench 4702 (Figures 47A and 47B) is filled with a dielectric material 4730 (e.g., dielectric material 2130). Similarly, a dielectric liner 4732 (e.g., dielectric liner 2132) can be first disposed on the exposed surface of the isolation trench 4702. That is, the dielectric liner 4732 is deposited on the exposed surfaces of the insulating material 118, the substrate 101, the gate electrode layer 182, and the patterned masking layer 181. The dielectric material 4730 and the dielectric liner 4732 filling the isolation trench 4702 form an isolation trench structure (so-called CMODE trench) 4734. The isolation trench structure 4734 has a substantially flat bottom surface corresponding to the top surface 101ts of the substrate 101.

[0106] In Figures 49A and 49B, once the isolation trench 4702 is filled, a planarization process can be performed to remove portions of the dielectric material formed on the patterned masking layer 181', such as those discussed above with respect to Figures 22A and 22B. The planarization process can be performed until the ILD layer 164 is exposed. After the planarization process, the top surfaces of the dielectric material 4730, dielectric liner 4732, gate electrode layer 182, ILD layer 164, gate spacer 138, and CESL 162 are substantially coplanar.

[0107] Figure 50 is an enlarged view of a portion of the substrate 101 shown in Figure 49B according to some embodiments. It can be seen that the substrate 101 can be etched to have peaks 101p and valleys 101v, thereby producing a CMODE structure 4734 with a wavy bottom surface profile.

[0108] Figure 51 illustrates an embodiment of an isolation trench structure (CMODE structure) 4734a having a bottom 4702bs2 at substantially the same height as the top surface 101ts of the substrate 101. In this embodiment, the substrate 101 can be etched using any suitable dry etching, wet etching, or a combination thereof (e.g., those discussed above with respect to Figures 14A through 18B).

[0109] Figure 51-1 shows an enlarged view of a portion of the substrate 101 shown in Figure 51 according to some embodiments. It can be seen that the substrate 101 can be etched to have peaks 101p and valleys 101v, thereby producing a CMODE structure with a wavy bottom surface profile.

[0110] Figure 52 shows a cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment. In this embodiment, the isolation trench structure (CMODE structure) 4734b has a substantially flat bottom surface 4702bs3 at a height below the interface 137 defined by the substrate 101 and the insulating material 118. Specifically, a plurality of fin structures 118f-4 of the insulating material 118 are retained in the isolation trench structure 4734b. Although not shown, the fin structures 118f-4 of the insulating material 118 are connected to or supported by the epitaxial source / drain feature 146, which may be disposed in the X direction (into the plane of the paper). Each fin structure in the fin structures 118f-4 of the insulating material 18 has a top at substantially the same height as the interface 155 defined by the insulating material 118 below the gate dielectric layer 180 and the gate electrode layer 182. The fin-like structure 118f-4 of the insulating material 118 can be formed by any suitable process (such as those discussed above with respect to Figures 37 to 43).

[0111] Figure 53 shows a cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment. The embodiment of Figure 53 is substantially the same as that of Figure 52, except that the fin structures 118f-5 of the insulating material 118 in the isolation trench structure 4734b have their tops at a height below the interface 155 defined by the insulating material 118 beneath the gate dielectric layer 180 and the gate dielectric layer 182. The bottom of each fin structure 118f-5 of the insulating material 118 is at substantially the same height as the interface 137 defined by the substrate 101 and the insulating material 118.

[0112] Figure 54 shows an enlarged view of a portion of the substrate 101 shown in Figures 52 and 53 according to some embodiments. It can be seen that the substrate 101 can be etched to have peaks 101p and valleys 101v, thereby producing a CMODE structure with a wavy bottom surface profile.

[0113] The embodiments disclosed herein provide an improved isolation trench structure (e.g., a CPODE / CMODE structure) having a substantially flat bottom surface in contact with the top surface of the substrate. The isolation trench structure with a flat bottom surface prevents the top surface of the substrate from forming fin-like structures and becoming a parasitic bipolar junction transistor (BJT). In some cases, the isolation trench structure may extend into the well region of the substrate to block leakage current via the EPI-transistor-substrate-EPI path.

[0114] A semiconductor device structure is illustrated. The structure includes a substrate, an insulating material disposed on the substrate, a first fin structure extending upward from the substrate through the insulating material, and a second fin structure extending upward from the substrate through the insulating material, wherein the first and second fin structures extend along a first direction. The structure also includes an isolation trench structure disposed between the first and second fin structures, the isolation trench structure extending along a second direction perpendicular to the first direction, wherein the isolation trench structure has a bottom contacting the top surface of the substrate, and the bottom of the isolation trench structure and the top surface of the substrate define a substantially flat interface.

[0115] Another embodiment is a semiconductor device structure. The structure includes a substrate and an insulating material disposed on the substrate, wherein a first portion of the insulating material and the substrate defines a first interface. The structure also includes a first fin structure extending upward from the substrate through the first portion of the insulating material, a second fin structure extending upward from the substrate through a second portion of the insulating material, and an isolation trench structure disposed between the first fin structure and the second fin structure, wherein at least some portions of the isolation trench structure are separated from each other by a third portion of the insulating material.

[0116] Another embodiment is a method for forming a semiconductor device structure. The method includes: forming a first fin structure and a second fin structure from a substrate, each of the first and second fin structures comprising alternately stacked plurality of first semiconductor layers and plurality of second semiconductor layers. The method further includes: forming an insulating material on the substrate; forming a metal gate structure on the insulating material and over a portion of each fin structure in the first and second fin structures; removing a portion of the metal gate structure over the first and second fin structures; removing the first and second fin structures, portions of the insulating material, and the substrate by one or more etching processes to form an isolation trench having a substantially flat bottom surface extending between opposing sidewalls of the isolation trench; and filling the isolation trench with a dielectric material.

[0117] The foregoing outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0118] 100: Semiconductor Component Structure 101: Base 101ts: Top surface 101p: Peak 101ts: Top surface 101ts-1: Part 1 101ts-2: Part Two 101v: Valley 102b, 102c, 102e, 102f: Fin structures 104: Semiconductor layer stacking 106, 108: Semiconductor layer 112: Fin Structure 114: Trench 116: Base portion 118: Insulating materials 118f: Fin-shaped insulating material 118f, 118f-1, 118f-2, 118f-3, 118f-4, 118f-5: Fin-like structures 118p: Highlight 118s: Sidewall 118t: Top surface 120: Isolation Area 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 134s: Sidewall 136: Masking layer 137: Interface 138: Gate spacer 139: Cap Layer 141: First Semiconductor Etching Process 142: Interface 144: Dielectric spacer 146: Source / Drain (S / D) Region, Source / Drain (S / D) Characteristics 147: Second Semiconductor Etching Process 149: Second Semiconductor Etching Process 150: Opening 151: Second Semiconductor Etching Process 152: Masking Structure 154: Bottom Layer 155: Interface 156: Intermediate Layer 158: Photoresist layer 159: Opening 162: Contact Etching Stop Layer (CESL) 163: Cap Layer 164: Interlayer dielectric layer 166: Opening 178: Interface Layer 180: Gate dielectric layer 181, 181': Masking layer 182: Gate electrode layer 184: Silicon layer 186: Contact element 190: Alternative gate structure 192: Self-aligned contact layer 1302: Masking Structure 1304: Hard mask 1304': Mask layer 1306: Resist layer 1308: Bottom Layer 1310: Intermediate Layer 1312: Top layer of photoresist 1402a, 1402b: Opening 1402', 1402a', 1402b': Groove patterns 1602, 1602a, 1602b: Opening 1802, 1802a, 1802b: Isolation trenches 1802bs1, 1802bs2, 1802bs3, 1802bs4, 1802bs5: Bottom surface 1802bs3: Bottom 2130, 2130a, 2130b: Dielectric materials 2132, 2132a, 2132b: Dielectric lining 2134, 2134a, 2134b, 2134c: Isolation trench structure 2801: Leakage Path 4702: Isolation trench 4702bs1, 4702bs3: bottom surface 4702bs1, 4702bs2: Bottom 4730: Dielectric Materials 4732: Dielectric liner 4734, 4734a, 4734b: Isolation trench structure (CMODE structure) D1: First Depth D2: Second Depth D3, D4: Distance

Claims

1. A semiconductor device structure, comprising: One base; An insulating material is disposed on the substrate; A first fin structure extends upward from the substrate through the insulating material; A second fin structure extending upward from the substrate through the insulating material, the first fin structure and the second fin structure extending along a first direction; and an isolation trench structure disposed between the first fin structure and the second fin structure, the isolation trench structure extending along a second direction perpendicular to the first direction; wherein the isolation trench structure has a bottom contacting the top surface of the substrate, and the bottom of the isolation trench structure and the top surface of the substrate define a substantially flat first interface; wherein the isolation trench structure further includes: a plurality of fin-like structures disposed on the substrate.

2. The semiconductor device structure as described in claim 1, wherein, The insulating material and the substrate define a second interface, and the first interface and the second interface are at substantially the same height.

3. The semiconductor device structure as described in claim 1, wherein, The insulating material and the substrate define a second interface, and the first interface is at a height below the second interface.

4. The semiconductor device structure as described in claim 1, wherein, The plurality of fin-like structures and the insulating material are formed from the same material.

5. The semiconductor device structure as described in claim 4, wherein, The top of one or more of the plurality of fin structures is at a height below the top surface of the insulating material.

6. The semiconductor device structure as described in claim 4, wherein, The top of one or more of the plurality of fin structures is at substantially the same height as the top surface of the insulating material.

7. The semiconductor device structure as described in claim 4, wherein, Each of the plurality of fin structures is connected to or supported by an epitaxial source / drain feature.

8. A semiconductor device structure, comprising: One base; An insulating material is disposed on the substrate, and the insulating material and a first portion of the substrate define a first interface; A first fin structure extends upward from the substrate through a first portion of the insulating material; a second fin structure extends upward from the substrate through a second portion of the insulating material; And an isolation trench structure disposed between the first fin structure and the second fin structure, wherein at least some portions of the isolation trench structure are separated from each other by a third portion of the insulating material; wherein the isolation trench structure further includes: a plurality of fin-like structures disposed on the substrate.

9. The semiconductor device structure as described in claim 8, wherein, The third part of the insulating material includes the plurality of fin-like structures.

10. A method for forming a semiconductor device structure, comprising: A first fin structure and a second fin structure are formed from a substrate, each of the first fin structure and the second fin structure comprising an alternately stacked plurality of first semiconductor layers and a plurality of second semiconductor layers; An insulating material is formed on the substrate; a metal gate structure is formed on the insulating material and on a portion of each of the first fin structure and the second fin structure; a portion of the metal gate structure on the first fin structure and the second fin structure is removed; the first fin structure and the second fin structure, a portion of the insulating material, and the substrate are removed by one or more etching processes to form an isolation trench having a substantially flat bottom surface extending between opposite sidewalls of the isolation trench; and the isolation trench is filled with a dielectric material; wherein the one or more etching processes are performed such that a portion of the fin-shaped insulating material remains within the isolation trench.

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