Semiconductor device and methods of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The high-voltage transistor includes a main field plate layer between a gate structure and a drain region of the high-voltage transistor, a barrier layer between the main field plate layer and a substrate layer of the high-voltage transistor, and a patterned field plate structure laterally located between the barrier layer and the drain region. The patterned field plate structure can be formed from the same layer as the gate structure and the associated gate dielectric layer, which minimizes the cost, complexity, and manufacturing resources required to form the patterned field plate structure. The patterned field plate structure serves as a self-aligned mask for forming the barrier layer, the drain region, and / or a metallide layer on the drain region. This allows for closer positioning of the barrier layer and the drain contact window on the drain region, and reduces the lateral dimension of the drain region.

Description

[Previous Technology]

[0001] A high-voltage transistor is a metal-oxide-semiconductor (MOS) transistor that can be configured to operate at a higher drain voltage than a low-voltage transistor. Low-voltage transistors can be used in applications such as logic circuits (e.g., processors), memory (e.g., static random access memory (SRAM)), and / or input / output (I / O) circuits. High-voltage transistors can be used in integrated circuit (IC) drivers, power ICs, image sensors, power management, display driver ICs (DDICs), bipolar-CMOS-DMOS ICs (BCD ICs), and / or image signal processing (ISP) ICs.

Implementation Method

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the apparatus. For instance, the following description of a first feature formed above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at different scales.

[0006] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0007] To operate at higher drain voltages, high-voltage transistors can be manufactured to withstand high breakdown voltages. Breakdown voltage is the voltage at which a transistor will stop operating according to its intended operating principle when it reaches or approaches a certain voltage. In high-voltage transistors, because the high-voltage transistor experiences a high drain voltage, the gate-to-drain voltage may sometimes meet or exceed the breakdown voltage of the high-voltage transistor.

[0008] In some cases, high-voltage transistors can be manufactured with minimal distance between the gate structure and the drain region, enabling them to achieve a specific breakdown voltage (BV). Increasing the distance between the gate structure and the drain region allows for a larger electric field distribution between them, which reduces the peak amplitude of the electric field (and thus increases the breakdown voltage). Furthermore, a field plate layer can be included in the region between the gate structure and the drain region to help control the peak electric field between them.

[0009] The region between the gate structure and the drain region is a keep-out area for metal silicide formation. Therefore, a barrier layer is formed on the substrate of the high-voltage transistor in this region to prevent metal silicide formation when a metal silicide layer is formed on the drain region. A field plate layer can be formed on the barrier layer, and the barrier layer provides additional buffering for the field plate layer to further distribute the electric field between the gate structure and the drain region. However, the barrier layer may be subject to manufacturing rules, such as the minimum spacing between the barrier layer and the drain contact window of the drain region, and / or the minimum overlap between the barrier layer and the drain region (e.g., to ensure that silicide is prevented from forming on the substrate). These manufacturing rules may result in an increase in the lateral occupancy area of ​​the high-voltage transistor. Since the specific on-resistance (Ron, sp) of the high-voltage transistor is a function of the resistance of the high-voltage transistor and the device spacing of the high-voltage transistor, the increased lateral occupancy area due to the manufacturing rules of the barrier layer may result in the high-voltage transistor having a larger specific on-resistance. A larger on-resistance increases power consumption, thereby reducing the operating efficiency of high-voltage transistors. Furthermore, the increased lateral occupancy reduces the density of high-voltage transistors that can be integrated onto a semiconductor device without increasing the lateral occupancy of the semiconductor device itself.

[0010] In some embodiments described herein, a high-voltage transistor includes a main field plate layer between the gate structure and the drain region of the high-voltage transistor, a barrier layer between the main field plate layer and the substrate layer of the high-voltage transistor, and a patterned field plate structure laterally positioned between the barrier layer and the drain region. The patterned field plate structure may be formed from the same layers as the gate structure and the associated gate dielectric layer, which minimizes the cost, complexity, and manufacturing resources required to form the patterned field plate structure.

[0011] The patterned field plate structure acts as a self-aligning mask for forming the barrier layer, thereby allowing precise control over the lateral coverage of the barrier layer on the substrate. Using the patterned field plate structure reduces the spacing between the barrier layer of the high-voltage transistor structure and the drain contact window on the drain region, thus reducing the lateral occupied area of ​​the high-voltage transistor structure. Additionally and / or alternatively, the patterned field plate structure serves as a self-aligning mask for forming the drain region and the associated metal silicate layer on the drain region. The use of the patterned field plate structure eliminates the need for partial overlap between the barrier layer and the drain region, which reduces the lateral width of the drain region. The reduced lateral width of the drain region reduces the lateral occupied area of ​​the high-voltage transistor structure.

[0012] Thus, the reduction in the lateral occupied area of ​​the high-voltage transistor structure enables the high-voltage transistor to achieve a lower specific on-resistance. The reduction in specific on-resistance reduces power consumption, thereby improving the operating efficiency of the high-voltage transistor. In addition, the reduced lateral occupied area allows for an increase in the density of high-voltage transistors integrated onto semiconductor devices without increasing (or minimizing) the peak electric field between the gate structure and drain region of the high-voltage transistor.

[0013] FIG1 is a diagram of an exemplary semiconductor device 100 described herein. Semiconductor device 100 may include a system-on-a-chip (SoC) device, a logic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)), a memory device (e.g., a high-bandwidth memory (HBM) device), a panel driver device, an integrated circuit (IC) driver, a radio frequency (RF) power amplifier, a display driver IC (DDIC), and / or other types of semiconductor devices.

[0014] As shown in FIG1, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 located above the device layer 102 in the z-direction. The device layer 102 may also be referred to as the front-end region or front-end process (FEOL) region of the semiconductor device 100. The interconnect layer 104 may also be referred to as the back-end region or back-end process (BEOL) region of the semiconductor device 100.

[0015] Device layer 102 includes a substrate layer 106. The substrate layer 106 may correspond to a portion of a semiconductor wafer on which the semiconductor device 100 is formed. The substrate layer 106 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate. The substrate layer 106 may extend in the semiconductor device 100 along the x-direction and / or y-direction.

[0016] The integrated circuit device 108 may be included in and / or on the substrate layer 106 of the device layer 102 of the semiconductor device 100. The integrated circuit device 108 includes front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (Fin FET) structures, front-end gate-all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, sensors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices. A front-end semiconductor device refers to a semiconductor device formed in the device layer 102 of the semiconductor device 100 (e.g., in and / or on the substrate layer 106).

[0017] In some embodiments, one or more of the integrated circuit device 108 includes a high-voltage transistor (or a medium-voltage transistor). A "high-voltage transistor" refers to a transistor configured to operate at a higher operating voltage (e.g., a higher gate voltage, a higher source / drain voltage) than a low-voltage transistor. As an example, a high-voltage transistor may be configured to operate in a drain voltage range of about 9 volts to about 36 volts, while a low-voltage transistor may be configured to operate in a drain voltage range of about 0 volts to about 1.8 volts. However, other values ​​within these ranges are also within the scope of this disclosure.

[0018] High-voltage transistors (or medium-voltage transistors) may include laterally diffused (or laterally double-diffused) metal-oxide-semiconductor (LDMOS) transistors with drift regions, wherein charge carriers are laterally diffused to facilitate the distribution of an electric field between the gate structure and the source / drain regions of the high-voltage transistor. The lateral diffusion of charge carriers in the drift regions enables the high-voltage transistor to withstand higher gate and source / drain voltages than the low-voltage transistor (e.g., increasing the breakdown voltage of the high-voltage transistor).

[0019] A dielectric layer 110 is contained above a substrate layer 106. The dielectric layer 110 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or another type of dielectric layer. The dielectric layer 110 includes a dielectric material that allows portions of the substrate layer 106 and / or the integrated circuit devices 108 to be selectively etched or protected from etching, and / or the integrated circuit devices 108 in the electrically isolated device layer 102. The dielectric layer 110 includes silicon nitride (SixNy), oxides (e.g., silicon oxide (SiOx) and / or another oxide material), and / or another type of dielectric material. The dielectric layer 110 may extend in the x-direction and / or y-direction of the semiconductor device 100.

[0020] The interconnect layer 104 in the semiconductor device 100 is located above the substrate layer 106 in the z-direction and above the integrated circuit device 108 in the semiconductor device 100. The integrated circuit device 108 can be electrically coupled to the interconnect layer 104 via a contact window structure 112. In some embodiments, the integrated circuit device 108 can be electrically coupled to a gate contact window and a source / drain contact window. The contact window structure 112 can include contact plugs, vias, posts, contact pads, and / or other types of conductive contact windows. The contact window structure 112 can include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), alloys thereof, metal nitrides containing one or more metals, and / or another electrically conductive material. In some embodiments, a pad is included between the contact window structure 112 and the dielectric layer 110. The gasket may include adhesive gaskets, barrier gaskets and / or another type of gasket, and may include gasket materials such as tantalum (Ta), tantalum nitride (TaN) and / or titanium nitride (TiN).

[0021] The interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in a direction generally perpendicular to the substrate layer 106 (e.g., the z-direction). The dielectric layers may include an ILD layer 114 and an etch stop layer (ESL) 116 arranged alternately in the z-direction. The ILD layer 114 and the ESL 116 may extend in the x-direction and / or y-direction of the semiconductor device 100.

[0022] ILD layers 114 may each comprise oxides (e.g., silicon oxide (SiO₂x) and / or another oxide material), undoped silicate glass (USG), boron-containing silicate glass (BSG), fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS)), hydrosilsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, ILD layers 114 comprise extremely low dielectric constant (ELK) dielectric materials having a dielectric constant of less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO x), amorphous fluorinated carbon (aC xF y), poly(p-xylene), benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous hydrosilsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silicon oxide (SiO x), etc.

[0023] ESL 116 may each comprise silicon nitride (SixNi), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, ILD layer 114 and ESL 116 comprise different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in interconnect layer 104.

[0024] The interconnect layer 104 includes a plurality of conductive structures. One or more of the conductive structures are electrically coupled and / or substantially coupled to one or more of the integrated circuit devices 108 in the device layer 102 (e.g., to the contact window structure 112 of the integrated circuit device 108). The conductive structures provide electrical wiring to enable signals and / or power to be supplied to and / or from the integrated circuit device 108. The conductive structures may include a combination of metallization structures 118 and interconnect structures 120. Metallization structure 118 may include trenches, metallization layers, conductive traces and / or other types of metallization structures. Interconnect structure 120 may include vias, plugs, interconnects and / or other types of interconnect structures. Metallization structure 118 and interconnect structure 120 may be one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, and other examples of electrically conductive materials. In some embodiments, the metallized structure 118 and the interconnect structure 120 include one or more padding layers. The one or more padding layers may include barrier pads, adhesive pads, and / or another type of pad. Examples of materials for the one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0025] In some embodiments, the metallization structures 118 and interconnect structures 120 of the interconnect layer 104 may be arranged in a vertical manner (e.g., in the z-direction). In other words, a plurality of stacked metallization structures 118 and interconnect structures 120 extend between the top of the device layer 102 and the interconnect layer 104 to facilitate the routing of electrical signals and / or power between the device layer 102 and the interconnect structures (not shown) of the semiconductor device 100. The plurality of stacked metallization structures 118 may be arranged in a layer, referred to as an M-layer. For example, a metal-O (MO) layer may be located at the bottom of the interconnect layer 104 and may be directly coupled to the device layer 102 (e.g., coupled to the contact window structure 112 of the integrated circuit device 108 in the device layer 102). A via-1 (V1) layer including one or more interconnect structures 120 may be included above the MO layer. The metal-1 layer (M1) can be located above the V1 layer in the interconnect layer 104, the via-2 layer (V2) can be located above the M1 layer, and the metal-2 layer (M2) can be located above the M1 layer. In addition, the via layer can be included between the vertically arranged M-layers.

[0026] As described above, Figure 1 is provided as an example. Other examples may differ from the description in Figure 1.

[0027] Figures 2A and 2B are diagrams of an embodiment 200 of the integrated circuit device 108 described herein. In embodiment 200, the integrated circuit device 108 includes a high-voltage transistor, such as an LDMOS transistor.

[0028] As shown in Figures 2A and 2B, the integrated circuit device 108 may include a semiconductor device 100 substrate layer 106 or (or may include on the substrate layer 106). The integrated circuit device 108 may include an active region 202 in the substrate layer 106, a bulk region 204 in the substrate layer 106, a source / drain region 206a in the bulk region 204, a source / drain region 206b in the active region 202, and a gate structure 208 on the active region 202.

[0029] The active region 202 may include a region of the substrate layer 106 in which the integrated circuit device 108 operates. The active region 202 may include a doped region of the substrate layer 106, i.e., doped with one or more types of dopants, such as p-type dopants and / or n-type dopants. The active region 202 includes one or more semiconductor materials such that the conductivity of the active region 202 can be selectively controlled using an electric field. Thus, based on the conductivity of the active region 202, current can selectively flow between the source / drain region 206a and the source / drain region 206b. A voltage can be selectively applied to the gate structure 208 to selectively control the conductivity of the active region 202 in the substrate layer 106.

[0030] The source / drain region 206a may be located on a first side of the gate structure 208 (e.g., laterally adjacent to the first side), and the source / drain region 206b may be located on a second side of the gate structure 208 opposite to the first side (e.g., laterally adjacent to the second side). Depending on the context, the source / drain region may refer to a source region, a drain region, or a combination of a source and a drain region. In some embodiments, the source / drain region 206a is the source region of the integrated circuit device 108, and the source / drain region 206b is the drain region of the integrated circuit device 108, which is configured to operate at a relatively high voltage (e.g., up to about 36 volts).

[0031] Source / drain regions 206a and 206b may each include one or more doped regions of the substrate layer 106. In some embodiments, source / drain regions 206a and 206b may include the same type of dopant. For example, source / drain regions 206a and 206b may each include silicon doped with one or more p-type dopants, such as boron (B) and / or gallium (Ga). As another example, source / drain regions 206a and 206b may each include silicon doped with one or more n-type dopants, such as arsenic (As) and / or phosphorus (P). In some embodiments, source / drain regions 206a and 206b include different types of dopant. For example, source / drain region 206a may include silicon doped with one or more p-type dopants, and source / drain region 206b may include silicon doped with one or more n-type dopants.

[0032] The gate structure 208 may be laterally located on the substrate layer 106 between the source / drain regions 206a and 206b. In some embodiments, the gate structure 208 includes a polycrystalline silicon gate. In some embodiments, the gate structure 208 includes a metallic gate and includes one or more metallic materials, such as tungsten (W), titanium (Ti), titanium aluminum (TiAl), and / or other suitable metallic materials.

[0033] The gate dielectric layer 210 may be contained on the base layer 106 between the base layer 106 and the gate structure 208. In some embodiments, a portion of the gate dielectric layer 210 is located on the bulk region 204, and another portion is contained on the active region 202. The gate dielectric layer 210 can provide electrical isolation between the gate structure 208 and the base layer 106, which allows a voltage applied to the gate structure 208 to cause an electric field to be generated in the base layer 106. In some embodiments, the gate dielectric layer 210 may include a low dielectric constant (low k) dielectric material, such as silicon oxide (SiO₂, e.g., SiO₂). Additionally and / or alternatively, the gate dielectric layer 210 may include a high dielectric constant (high k) dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9), such as silicon nitride (Si xN y, e.g. Si 3N 4), hafnium oxide (HfO x, e.g. HfO 2) and / or aluminum oxide (Al xO y, e.g. Al 2O 3).

[0034] One or more sidewall spacers 212 may be included on and / or above the sidewalls of the gate structure 208. The sidewall spacers 212 may include silicon carbide (SiOC), nitrogen-free SiOC, or another suitable dielectric material. Due to the directional (e.g., vertical) etching technique used to form the sidewall spacers 212, the sidewall spacers 212 may have curved or circular outer surfaces.

[0035] The host implantation region 214 may be contained in a bulk region 204 of the substrate layer 106 adjacent to the source / drain region 206a. The host implantation region 214 may be doped with a dopant of the opposite type to that of the source / drain region 206a (e.g., the source / drain region 206a may be doped with an n-type dopant and the host implantation region 214 may be doped with a p-type dopant). An electrical bias is applied to the host implantation region 214 to establish a host bias in the substrate layer 106 to compensate for shifts or changes in the threshold voltage (Vt) of the integrated circuit device 108.

[0036] As shown in Figures 2A and 2B, the drift region 216 may correspond to a portion of the active region 202 between the gate structure 208 and the source / drain region 206b. During operation of the integrated circuit device 108, a depletion region may form in the drift region 216. In the depletion region, the magnitude (or intensity) of the electric field formed in the active region 202 is non-uniform between the gate structure 208 and the source / drain region 206b. The amplitude of the electric field in the depletion region may be highest near the gate structure 208 and may decrease from the gate structure 208 to the source / drain region 206b. If the amplitude of the electric field near the gate structure 208 reaches the critical breakdown electric field of the integrated circuit device 108 (e.g., the maximum electric field at breakdown), it may exceed the breakdown voltage of the integrated circuit device 108.

[0037] To suppress the peak electric field in the drift region 216 and thus achieve a higher breakdown voltage for the integrated circuit device 108, a main field plate layer may be included above the drift region 216 between the gate structure 208 and the source / drain region 206b. The main field plate layer 218 may extend along the substrate layer 106 between the gate structure 208 and the source / drain region 206b, and in some embodiments may extend on the sidewall of the gate structure 208 across a portion of the gate structure 208 and a portion of the sidewall spacer 212.

[0038] The main field substrate layer 218 can be electrically biased to uniformly distribute the amplitude of the electric field across the drift region 216, which reduces the peak amplitude of the electric field in the integrated circuit device 108. The main field substrate layer 218 may include metals such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), tantalum (Ta), ruthenium (Ru), cobalt (Co), and tungsten (Co). Additionally and / or alternatively, the main field substrate layer 218 may include metal nitride materials (e.g., titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), metal oxides (e.g., titanium oxide (TiO2)), and / or another type of metal-containing material.

[0039] Barrier layer 220 may be included between substrate layer 106 (e.g., drift region 216 in substrate layer 106) and main field plate layer 218. Barrier layer 220 may include a resist protective oxide (RPO) layer, which is included to prevent the formation of metal silicides on substrate layer 106, gate structure 208, and / or surface of integrated circuit device 108, except on source / drain regions 206a and / or 206b. Barrier layer 220 may also provide a vertical buffer for main field plate layer 218, which allows the electric field to be further distributed over a larger area for electric field distribution adjustment. Barrier layer 220 may include one or more dielectric materials, such as oxides (e.g., SiO x, such as SiO 2), nitrides (e.g., Si xN y, such as Si 3N 4), carbides, oxynitrides, carbon oxides, and nitride carbides, polymers, and / or other suitable dielectric materials.

[0040] As further shown in Figures 2A and 2B, the patterned field plate structure 222 may be laterally included on the substrate layer 106 between the barrier layer 220 and the source / drain region 206b. The patterned field plate structure 222 may be included as a self-aligned mask for forming the barrier layer 220 and / or for forming a metal silicide layer on the source / drain region 206b. Specifically, the patterned field plate structure 222 may define the lateral position of the end of the barrier layer 220 facing the source / drain region 206b, and / or may define the lateral position of the end of the metal silicide layer on the source / drain region 206b facing the barrier layer 220. Therefore, a first side of the patterned field plate structure 222 may be adjacent to and in direct substantial contact with the end of the barrier layer 220 facing the source / drain region 206b, and a second side of the patterned field plate structure 222 may be adjacent to the source / drain region 206b. In some embodiments, a first side of the patterned field plate structure 222 is spaced apart from the end of the main field plate layer 218 facing the source / drain region 206b. In some embodiments, the first side of the patterned field plate structure 222 is in direct and substantial contact with the end of the main field plate layer 218 facing the source / drain region 206b.

[0041] The patterned field plate structure 222 provides a clear barrier between the barrier layer 220 and the source / drain region 206b, thus allowing for highly controllable parameters (e.g., the distance between the end of the barrier layer and the contact window structure of the source / drain region 206b and / or the formation of the metal silicate layer on the source / drain region 206b).

[0042] In some embodiments, the patterned field plate structure 222 is formed of the same layers as the gate structure 208 and the gate dielectric layer 210 to minimize the impact on the cost, time, and / or complexity of forming the integrated circuit device 108. Therefore, the patterned field plate structure 222 may include a dielectric layer 224 on the substrate layer 106 and a metal layer 226 (or a polysilicon layer) on the dielectric layer 224. The gate dielectric layer 210 and the dielectric layer 224 may be formed of the same dielectric layer, and the gate structure 208 and the metal layer 226 may be formed of the same metal layer (or the same polysilicon layer). Alternatively, the patterned field plate structure 222 may include another material composition, such as a monolithic dielectric structure or a monolithic metal (or polysilicon) structure, etc.

[0043] As further shown in Figures 2A and 2B, the dielectric layer 110 may be included above the integrated circuit device 108. A field plate contact window 228 may extend through the dielectric layer 110 and may be included on the main field plate layer 218. A bias voltage may be applied to the main field plate layer 218 through the field plate contact window 228 to reduce the peak electric field in the drift region 216. The bias voltage increases carrier depletion in the drift region 216, thereby reducing the peak electric field strength in the drift region 216. By manipulating the electric field, the integrated circuit device 108 can achieve a higher breakdown voltage.

[0044] Contact window structure 112a (e.g., gate contact) may be included in one or more dielectric layers and may be electrically connected and / or substantially connected to gate structure 208. As shown in FIG2A, contact window structures 112b and 112c (e.g., source / drain contact windows) may be included in dielectric layer 110 and may be electrically connected and / or substantially connected to source / drain regions 206a and 206b, respectively. Alternatively, as shown in FIG2B, contact window structure 112b may be substantially connected to body implantation region 214. In an embodiment, source / drain region 206a and body implantation region 214 are electrically connected together, and the source body voltage (VSB) is applied to both source / drain region 206a and body implantation region 214 through contact window structure 112b.

[0045] As further shown in Figures 2A and 2B, metal silicate layers 230a and 230b may be included on the source / drain regions 206a and 206b of the integrated circuit device 108, respectively. Metal silicate layers 230a and 230b may each comprise titanium silicate (TiSi), ruthenium silicate (RuSi), and / or another type of metal silicate material. Metal silicate layers 230a and 230b provide a transition between the semiconductor material of the source / drain region 206a and the metal material of the contact window structures 112b and 112c formed on the source / drain regions 206a and 206b, respectively. Metal silicate layers 230a and 230b enable low contact resistance between the contact window structures 112b, 112c and the source / drain regions 206a, 206b.

[0046] As further shown in Figures 2A and 2B, the integrated circuit device 108 may have one or more dimensions. An exemplary dimension D1 may correspond to the lateral distance between the edge of the patterned field plate structure 222 facing the gate structure 208 and the sidewall gap wall 212 on the sidewall of the gate structure 208 facing the source / drain region 206b. Dimension D1 may also correspond to the lateral length of a portion of the barrier layer 220 on the substrate layer 106 between the gate structure 208 and the source / drain region 206b. In some embodiments, dimension D1 is contained in the range of about 200 nanometers to about 500 nanometers. If dimension D1 is less than about 200 nanometers, the integrated circuit device may not achieve a sufficiently high breakdown voltage, and if dimension D1 is greater than about 500 nanometers, the integrated circuit device may not achieve a sufficiently low specific on-resistance. However, other values ​​and ranges besides about 200 nanometers to about 500 nanometers for dimension D1 are also within the scope of this disclosure. In some embodiments, the lateral distance between the patterned field plate structure 222 and the sidewall gap wall 212 is less than the distance between the source / drain region 206b and the gate structure 208 (represented as dimension D2 in Figures 2A and 2B).

[0047] Another example is that dimension D3 may correspond to the lateral length (or width) of the source / drain region 206b. In some embodiments, dimension D3 is contained in the range of about 100 nanometers to about 200 nanometers. If dimension D3 is less than about 100 nanometers, the source / drain region 206b may be susceptible to high process variation, while if dimension D3 is greater than about 200 nanometers, the integrated circuit device may not be able to achieve a sufficiently low specific on-resistance. However, other values ​​and ranges besides about 100 nanometers to about 200 nanometers for dimension D3 are also within the scope of this disclosure.

[0048] Another example is that dimension D4 may correspond to the lateral length (or width) of the patterned field plate structure 222. In some embodiments, dimension D4 is contained in the range of about 50 nanometers to about 200 nanometers. If dimension D3 is less than about 50 nanometers, the likelihood of the barrier layer 220 encroaching on the source / drain region 206b may increase, while if dimension D4 is greater than about 200 nanometers, the integrated circuit device may not be able to achieve a sufficiently low specific on-resistance. However, other values ​​and ranges besides about 100 nanometers to about 200 nanometers for dimension D4 are also within the scope of this disclosure. In some embodiments, the lateral length (dimension D4) of the patterned field plate structure 222 is less than the length of the gate structure 208.

[0049] In another example, dimension D5 may correspond to the vertical thickness (or height) of the patterned field plate structure 222. Since the patterned field plate structure 222 may be formed from the same layers as the gate structure 208 and the gate dielectric layer 210, dimension D5 may correspond to the total vertical thickness (or height) of the gate structure 208 and the gate dielectric layer 210. However, other values ​​and ranges of dimension D5 are also within the scope of this disclosure.

[0050] Another exemplary dimension D6 may correspond to the lateral distance between the edge of the patterned field plate structure 222 facing the source / drain region 206b and the contact window structure 112c on the source / drain region 206b. In some embodiments, dimension D6 is contained in the range of about 20 nanometers to about 100 nanometers. If dimension D6 is less than about 20 nanometers, the lateral width (or length) of the source / drain region 206b may not be large enough to handle the high drain voltage of the integrated circuit device 108, while if dimension D6 is greater than about 100 nanometers, the integrated circuit device may not be able to achieve a sufficiently low specific on-resistance. However, other values ​​and ranges besides about 20 nanometers to about 100 nanometers for dimension D6 are also within the scope of this disclosure.

[0051] Another exemplary dimension D7 may correspond to the lateral distance between the edge of the patterned field plate structure 222 facing the gate structure 208 and the edge of the main field plate layer 218 facing the source / drain region 206b. In some embodiments, dimension D7 is contained in the range of about 0 nanometers to about 100 nanometers. If dimension D7 is greater than about 100 nanometers, the integrated circuit device may not be able to achieve a sufficiently high breakdown voltage. However, other values ​​and ranges besides about 0 nanometers to about 100 nanometers for dimension D7 are also within the scope of this disclosure. In some embodiments, the distance between the patterned field plate structure 222 and the main field plate layer 218 (dimension D7) is smaller than the distance between the patterned field plate structure 222 and the contact window structure 112c (dimension D6).

[0052] Thus, the integrated circuit device 108 includes a barrier layer 220 on a base layer 106 between a gate structure 208 and a source / drain region 206b, a main field plate layer 218 on the barrier layer 220, and a patterned field plate structure 222 on the base layer 106 transversely between the barrier layer 220 and the source / drain region 206b. A first end of the barrier layer 220 may be located above the gate structure 208, and a second end of the barrier layer 220 opposite to the first end may be in substantial contact with the patterned field plate structure 222. The patterned field plate structure 222 can be used as a self-aligned pattern to form the barrier layer 220, thereby enabling precise control of the distance between the barrier layer 220 and the contact window structure 112c of the source / drain region 206b. Furthermore, the patterned field plate structure 222 can be used for self-aligned patterning of the metal silicide layer 230b formed on the source / drain region 206b, thereby enabling precise control over the formation of the metal silicide layer 230b only on the source / drain region 206b. In this way, the patterned field plate structure 222 can compensate for process variations that may occur during the formation of the barrier layer 220 and / or the metal silicide layer 230b, which allows for a reduction in the lateral occupied area of ​​the integrated circuit device 108. The reduction in the lateral occupied area of ​​the integrated circuit device 108 enables the integrated circuit device 108 to achieve a lower specific on-resistance (which improves the operating efficiency of the integrated circuit device 108) and / or to include a higher density of integrated circuit devices 108 in the semiconductor device 100.

[0053] As described above, Figures 2A and 2B are provided as examples. Other examples may differ from those described with respect to Figures 2A and 2B.

[0054] Figures 3A-3R are diagrams of an embodiment 300 forming the integrated circuit device 108 described herein, including a main field substrate layer 218 and a patterned field substrate structure 222. In some embodiments, one or more of the operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, ion implantation tools, planarization tools, and / or other suitable semiconductor processing tools.

[0055] As shown in FIG3A, one or more of the operations in Embodiment 300 may be performed in conjunction with the substrate layer 106 of the semiconductor device 100. The substrate layer 106 may be provided in the form of a semiconductor wafer or other type of substrate.

[0056] As shown in FIG3B, one or more regions in the substrate layer 106 may be doped to form active regions 202 and / or bulk regions 204. An ion implantation tool may be used to implant dopants (e.g., p-type ions, n-type ions) into the substrate layer 106 to form active regions 202 and / or bulk regions 204.

[0057] As shown in FIG3C, a dielectric layer 302 can be formed on the substrate layer 106, and a gate electrode layer 304 can be formed on the dielectric layer 302. The dielectric layer 302 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and / or another suitable deposition technique. In some embodiments, the dielectric layer 302 is formed as portions with different vertical thicknesses. For example, a first portion of the dielectric layer 302 can be formed with a first vertical thickness (denoted as dimension D8 in FIG3C), and a second portion of the dielectric layer 302 can be formed with a second vertical thickness (denoted as dimension D9 in FIG3C), which is greater than the first vertical thickness. In some embodiments, the dielectric layer 302 can be deposited and then etched to form portions with different vertical thicknesses. In some embodiments, portions of the dielectric layer 302 with different vertical thicknesses can be deposited in different deposition operations.

[0058] The gate electrode layer 304 may be formed on and / or above the dielectric layer 302. Deposition tools may be used to deposit the gate structure 208 using PVD, CVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, a planarization tool is used to planarize the dielectric layer 302 and / or the gate electrode layer 304. Chemical mechanical planarization (CMP) and / or another suitable planarization technique may be used to planarize the dielectric layer 302 and / or the gate electrode layer 304.

[0059] As shown in FIG. 3D, a mask layer 306 can be formed on the gate electrode layer 304, and a pattern can be formed in the mask layer 306. In some embodiments, the mask layer 306 is a photoresist layer, and a deposition tool can be used to form the mask layer 306 using spin coating and / or another suitable deposition technique. The pattern can be formed in the mask layer 306 by photolithography, wherein the mask layer 306 can be exposed to a radiation source using an exposure tool to pattern the mask layer 306. A development tool can be used to develop and remove portions of the mask layer 306 to expose the pattern. In some embodiments, the mask layer 306 is a hard mask layer, and an etching tool can be used to etch the mask layer 306 based on the patterned photoresist layer to form the pattern in the mask layer 306.

[0060] As shown in FIG3E, the etching tool can etch the gate electrode layer 304 based on the pattern in the mask layer 306 to define the metal layer 226 of the gate structure 208 and the patterned field plate structure 222. In some embodiments, a dry etching operation is performed to define the metal layer 226 of the gate structure 208 and the patterned field plate structure 222 such that the sidewalls of the metal layer 226 of the gate structure 208 and the patterned field plate structure 222 are substantially perpendicular. The dry etching operation may include a gas-based etching operation, a plasma-based etching operation, and / or another suitable dry etching operation. Additionally and / or alternatively, a wet etching operation may be performed to define the metal layer 226 of the gate structure 208 and the patterned field plate structure 222.

[0061] As shown in FIG3F, the etching tool may etch the dielectric layer 302 based on the pattern in the mask layer 306 and / or based on the gate structure 208 and the metal layer 226 to define the gate dielectric layer 210 and the dielectric layer 224 of the patterned field plate structure 222. As described above, the dielectric layer 302 may include portions with different vertical thicknesses. The dielectric layer 302 may be etched such that the gate dielectric layer 210 includes a portion having a first thickness (size D8) and another portion having a second thickness (size D9) (a larger thickness). Furthermore, the dielectric layer 302 may be etched such that the dielectric layer 224 of the patterned field plate structure 222 has a second thickness (size D9) (a larger thickness).

[0062] As shown in FIG3G, the sidewall spacer 212 can be deposited on the sidewall of the gate structure 208 using CVD, ALD, PVD and / or another type of deposition technique (e.g., using a deposition tool). In some embodiments, the spacer layer is blanket-deposited on the semiconductor device 100 and then etched back to define the sidewall spacer 212.

[0063] As shown in Figure 3H, another dielectric layer 308 may be formed on and / or over a portion of the substrate 106 between the gate structure 208 and the subsequently formed source / drain region 206b. The dielectric layer 308 may also be deposited over the gate structure 208, other portions of the substrate 106, and / or over the patterned field plate structure 222. The dielectric layer 308 may be deposited using CVD, ALD, PVD, and / or another type of deposition technique.

[0064] As shown in FIG3I, an etching tool can be used to subsequently remove portions of the dielectric layer 308 to define a barrier layer 220 between the gate structure 208 and the patterned field plate structure 222. In some embodiments, a dry etching operation is performed to etch the dielectric layer 308 to define the barrier layer 220. The dry etching operation may include a gas-based etching operation, a plasma-based etching operation, and / or another suitable dry etching operation. Removing portions of the barrier layer 220 on the patterned field plate structure 222 and portions of the barrier layer 220 on the substrate layer 106 adjacent to the side of the patterned field plate structure 222 facing away from the gate structure 208, such that the patterned field plate structure 222 defines the end of the barrier layer 220 facing away from the gate structure 208.

[0065] As shown in FIG3J, source / drain regions 206a and 206b can be formed in the substrate layer 106. Furthermore, the main implantation region 214 can be formed in the substrate layer 106 adjacent to the source / drain region 206a. The source / drain region 206a can be formed on a first side of the gate structure 208, and the source / drain region 206b can be formed on a second side of the gate structure 208 opposite to the first side. Therefore, the gate structure 208 is laterally located between the source / drain regions 206a and 206b. This allows the gate structure 208 to selectively control the conductivity of the active region 202 in the substrate layer 106 between the source / drain regions 206a and 206b.

[0066] Furthermore, the source / drain region 206b can be formed such that the patterned field plate structure 222 is laterally located between the source / drain region 206b and the barrier layer 220. The patterned field plate structure 222 provides a clear boundary between the edge of the source / drain region 206b and a portion of the substrate layer 106 below the patterned field plate structure 222, which allows the metal silicate layer 230b to be precisely formed on the source / drain region 206b without forming the metal silicate layer 230b on other portions of the substrate layer 106 located between the gate structure 208 and the source / drain region 206b.

[0067] In some embodiments, source / drain regions 206a and 206b can be formed by doping portions of the substrate layer 106. For example, a first portion of the substrate layer 106 may be doped with one or more dopants (e.g., n-type dopants, p-type dopants) to form source / drain region 206a, and a second portion of the substrate layer 106 may be doped with one or more dopants (e.g., n-type dopants, p-type dopants). An ion implantation tool can be used to implant dopant ions into the first and / or second portions of the substrate layer 106 to form source / drain regions 206a and / or source / drain regions 206b. Alternatively and / or another doping technique (e.g., diffusion) can be used to form source / drain regions 206a and 206b.

[0068] In some embodiments, the source / drain regions 206a and 206b are formed by epitaxially growing the source / drain regions 206a and 206b in a recess in the substrate layer 106. An etching tool can be used to etch the substrate layer 106 to form the recess in the substrate layer 106. The etching operation may be referred to as a strained source / drain (SSD) etching operation, and the recess may be referred to as a strained source / drain recess. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques.

[0069] The deposition tool can be used to form source / drain regions 206a and 206b in the recess. The deposition tool can be used to form source / drain regions 206a and 206b by epitaxial growth, wherein a layer of epitaxial material is deposited in the recess, such that a layer of semiconductor material is formed by epitaxial growth with a specific crystal orientation.

[0070] The materials used to form the source / drain regions 206a and 206b (e.g., silicon (Si), gallium (gas), or another type of semiconductor material) can be doped with p-type dopants (e.g., dopants that include electron acceptor atoms that generate holes in the material), n-type dopants (e.g., dopants that include electron donor atoms that generate mobile electrons in the material), and / or other types of dopants. The material can be doped by adding impurities (e.g., p-type dopants, n-type dopants) to the source gas used during epitaxial operation. Examples of p-type dopants that can be used in epitaxial operation include boron (B) or germanium (Ge). Examples of n-type dopants that can be used in epitaxial operation include phosphorus (P) or arsenic (As).

[0071] Further, as shown in FIG3K, metal silicate layers 230a and 230b can be formed on source / drain regions 206a and 206b, respectively. A self-aligned silicate process can be performed to form metal silicate layers 230a and 230b. The self-aligned silicate process may include depositing a layer of metallic material (e.g., titanium (Ti), cobalt (Co), ruthenium (Ru)) on source / drain regions 206a and 206b using a deposition tool, and then performing an annealing operation to allow the metallic material to diffuse into the top surface of source / drain regions 206a and 206b to form metal silicate layers 230a and 230b. Patterned field plate structure 222 and barrier layer 220 prevent the formation of a layer of metallic material on the substrate layer 106 between gate structure 208 and source / drain region 206b (thereby preventing the formation of metal silicate layer 230b). In some embodiments, another technique is used to form metal silicate layers 230a and 230b.

[0072] As shown in FIG3L, a metal-containing layer 310 may be formed above the integrated circuit device 108. The deposition tool may be used to deposit the metal-containing layer 310 using CVD technology, ALD technology, PVD technology, electroplating technology and / or another type of deposition technology.

[0073] As shown in Figure 3M, the photoresist layer 312 can be formed on and / or above the metal-containing layer 310. A deposition tool is used to deposit the photoresist layer 312 using spin coating and / or other suitable deposition techniques. The photoresist layer 312 can be patterned such that it remains above a portion of the metal-containing layer 310 on the barrier layer 220. An exposure tool can be used to expose the photoresist layer 312 to a radiation source to pattern the photoresist layer 312. A development tool can be used to develop and remove portions of the photoresist layer 312 to expose the pattern.

[0074] As shown in FIG3N, an etching operation can be performed based on the pattern in the photoresist layer 312 to etch the metal-containing layer 310, thereby defining the host substrate layer 218. In some embodiments, the etching operation may include a wet etching operation, a dry etching operation (e.g., a gas-based etching operation, a plasma-based etching operation) and / or another suitable etching operation.

[0075] As shown in FIG30, the remaining portion of the photoresist layer 312 can be removed after the main substrate layer 218 is formed. In some embodiments, the photoresist removal tool uses chemical stripping, plasma ashing and / or other techniques to remove the remaining portion of the photoresist layer 312.

[0076] As shown in FIG3P, after forming the main substrate layer 218, a dielectric layer 110 may be formed on and / or over the integrated circuit device 108. Deposition tools may be used to deposit the dielectric layer 110 using PVD, CVD, ALD, oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool is used to perform a CMP operation to planarize the dielectric layer 110.

[0077] As shown in FIG3Q, a recess 314 can be formed through the dielectric layer 110. For example, the recess 314 can be formed over the source / drain region 206a to expose the metal silicide layer 230a on the source / drain region 206a. As another example, the recess 314 can be formed over the source / drain region 206b to expose the metal silicide layer 230b on the source / drain region 206b. As another example, the recess 314 can be formed over the gate structure 208 to expose the gate structure 208. As another example, the recess 314 can be formed over the main field plate layer 218 to expose the main field plate layer 218.

[0078] In some embodiments, a pattern in the photoresist layer is used to form the recess 314. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer 110. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch through the dielectric layer 110 to form the recess 314. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form the recess 314 based on the pattern.

[0079] As shown in FIG3R, a contact window structure 112a (e.g., a gate contact window) may be formed in a recess 314 above the gate structure 208, such that the contact window structure 112a lands on the gate structure 208. A contact window structure 112b (e.g., a source / drain contact window) may be formed in a recess 314 above the source / drain region 206a, such that the contact window structure 112b lands on the metal silicate layer 230a on the source / drain region 206a. A contact window structure 112c (e.g., a source / drain contact window) may be formed in a recess 314 above the source / drain region 206b, such that the contact window structure 112c lands on the metal silicate layer 230b on the source / drain region 206b. The field plate contact window 228 can be formed in the recess 314 above the main field plate layer 218, so that the field plate contact window 228 lands on the main field plate layer 218.

[0080] The deposition tool can use CVD, PVD, ALD, electroplating, and / or another suitable deposition technique to deposit the contact window structures 112a-112c and the field plate contact window 228. The contact window structures 112a-112c and the field plate contact window 228 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the contact window structures 112a-112c and the field plate contact window 228 are deposited on the seed layer. In some embodiments, a liner is deposited in a recess 314, and the contact window structures 112a-112c and the field plate contact window 228 are deposited on the liner in the recess 314. The liner may include a barrier liner, an adhesive liner, and / or another suitable liner. Examples of liner materials include tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials. In some embodiments, after depositing contact window structures 112a-112c and field plate contact window 228, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the contact window structures 112a-112c and field plate contact window 228.

[0081] As described above, Figures 3A-3R are provided as examples. Other examples may differ from the description of Figures 3A-3R.

[0082] FIG4 is a diagram of an embodiment 400 of the integrated circuit device 108 described herein. In embodiment 400, the integrated circuit device 108 includes a combination and arrangement of layers and structures similar to those of embodiment 200 of the integrated circuit device 108 in FIGS. 2A and 2B. However, as shown in FIG4, in embodiment 400 of the integrated circuit device 108, the patterned field plate structure 222 is electrically short-circuited to the source / drain contact window of the source / drain region 206b, which is the opposite of the electrically floating structure in embodiment 200 of the integrated circuit device 108. Specifically, a fusion contact window structure 402 may be formed and included above the patterned field plate structure 222 and the source / drain region 206b, such that both the patterned field plate structure 222 and the source / drain region 206b are electrically connected to the fusion contact window structure 402.

[0083] As described above, Figure 4 is provided as an example. Other examples may differ from the description in Figure 4.

[0084] FIG5 is a diagram of an embodiment 500 of the integrated circuit device 108 described herein. In embodiment 500, the integrated circuit device 108 includes a combination and arrangement of layers and structures similar to those of embodiment 200 of the integrated circuit device 108 in FIGS. 2A and 2B. However, as shown in FIG5, in embodiment 500 of the integrated circuit device 108, the patterned field plate structure 222 is electrically short-circuited with the contact window structure 112c of the source / drain region 206b, which is the opposite of the electrically floating structure in embodiment 200 of the integrated circuit device 108.

[0085] Specifically, the contact window structure 112c of the patterned field plate structure 222 and the source / drain region 206b can be electrically coupled through one or more metallization structures 118 and / or one or more interconnect structures 120 (not shown) in the interconnect layer 104 of the semiconductor device 100. In some embodiments, the patterned field plate contact window 502 can be included on the patterned field plate structure 222 in the dielectric layer 110, and the patterned field plate contact window 502 can be electrically coupled to the contact window structure 112c through one or more metallization structures 118 and / or one or more interconnect structures 120 in the interconnect layer 104.

[0086] As described above, Figure 5 is provided as an example. Other examples may differ from the description in Figure 5.

[0087] FIG6 is a diagram of an embodiment 600 of the integrated circuit device 108 described herein. In embodiment 600, the integrated circuit device 108 includes a combination and arrangement of layers and structures similar to those of embodiment 200 of the integrated circuit device 108 in FIGS. 2A and 2B. However, as shown in FIG6, in embodiment 600 of the integrated circuit device 108, the patterned field plate structure 222 is electrically short-circuited to the main field plate layer 218, which is the opposite of the electrically floating structure in embodiment 200 of the integrated circuit device 108. Therefore, the edge of the patterned field plate structure 222 facing the gate structure 208 can be in direct and substantial contact with the edge of the main field plate layer 218 facing the source / drain region 206b.

[0088] As described above, Figure 6 is provided as an example. Other examples may differ from the description in Figure 6.

[0089] FIG7 is a flowchart of an exemplary process 700 associated with the semiconductor device described herein. In some embodiments, one or more process blocks in FIG7 are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor processing tools.

[0090] As shown in FIG7, process 700 may include forming a first dielectric layer (block 710) over a substrate layer of a semiconductor device. For example, one or more semiconductor processing tools may be used to form a first dielectric layer (e.g., dielectric layer 302) on a substrate layer (e.g., substrate layer 106) of a semiconductor device (e.g., semiconductor device 100), as described herein.

[0091] As further shown in FIG7, process 700 may include forming a gate electrode layer (block 720) over the first dielectric layer. For example, one or more semiconductor processing tools may be used to form the gate electrode layer (e.g., gate electrode layer 304) on the first dielectric layer, as described herein.

[0092] As further shown in FIG7, process 700 may include etching through the gate electrode layer and the first dielectric layer to form a gate structure and a gate dielectric layer of a transistor structure of a semiconductor device, and to form a patterned field structure (block 730) spaced apart from the gate structure and the gate dielectric layer. For example, one or more semiconductor processing tools may be used to etch the gate electrode layer and the first dielectric layer to form a gate structure (e.g., gate structure 208) and a gate dielectric layer (e.g., gate dielectric layer 210) of a transistor structure of a semiconductor device, and to form a patterned field structure (e.g., patterned field structure 222) spaced apart from the gate structure and the gate dielectric layer, as described herein.

[0093] As further shown in FIG7, process 700 may include forming a second dielectric layer (block 740) over the substrate layer. For example, one or more semiconductor processing tools may be used to form the second dielectric layer (e.g., dielectric layer 308) on the substrate layer, as described herein.

[0094] As further shown in FIG7, process 700 may include etching a second dielectric layer to form a barrier layer (block 750) over a substrate layer between the gate structure and the patterned field plate structure. For example, one or more semiconductor processing tools may be used to etch the second dielectric layer to form a barrier layer (e.g., barrier layer 220) over a substrate layer between the gate structure and the patterned field plate structure, as described herein.

[0095] Process 700 may include other embodiments, such as the embodiments described below and / or any single embodiment or any combination of one or more other processes described elsewhere herein.

[0096] In the first embodiment, etching the second dielectric layer includes using a gate structure and a patterned field plate structure as a self-aligned mask to etch the second dielectric layer.

[0097] In the second embodiment, alone or in combination with the first embodiment, the process 700 includes forming a first source / drain region (e.g., source / drain region 206a) adjacent to the gate structure in the substrate layer, and forming a second source / drain region (e.g., source / drain region 206b) adjacent to the gate structure in the substrate layer.

[0098] In a third embodiment, alone or in combination with one or more first and second embodiments, process 700 includes forming a metal silicate layer (e.g., metal silicate layer 230b) on the second source / drain region, wherein the barrier layer and patterned field plate structure prevent the metal silicate layer from being formed in the substrate layer between the gate structure and the second source / drain region.

[0099] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 700 includes forming a master field plate layer (e.g., master field plate layer 218) on the barrier layer, such that the master field plate layer is spaced apart from the patterned field plate structure.

[0100] Although Figure 7 shows an exemplary block of process 700, in some embodiments, process 700 includes more blocks, fewer blocks, different blocks, or blocks arranged differently than those depicted in Figure 7. Alternatively, two or more blocks of process 700 may be executed in parallel.

[0101] Thus, the high-voltage transistor includes a main field plate layer between the gate structure and the drain region of the high-voltage transistor, a barrier layer between the main field plate layer and the substrate layer of the high-voltage transistor, and a patterned field plate structure laterally located between the barrier layer and the drain region. The patterned field plate structure can be formed from the same layer as the gate structure and the associated gate dielectric layer, which minimizes the cost, complexity, and manufacturing resources required to form the patterned field plate structure. The patterned field plate structure serves as a self-aligned mask for forming the barrier layer, the drain region, and / or the metal silicate layer on the drain region. This allows for closer positioning of the drain contact windows on the barrier layer and the drain region, and reduces the lateral size of the drain region, enabling the high-voltage transistor to achieve a smaller lateral footprint without increasing (or minimally increasing) the peak electric field between the gate structure and the drain region of the high-voltage transistor.

[0102] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a first source / drain region in a substrate layer; a second source / drain region in the substrate layer; a gate structure above the substrate layer and between the first source / drain region and the second source / drain region; a barrier layer on a first portion of the substrate layer, wherein the barrier layer is located between the gate structure and the second source / drain region; a main field plate layer on the barrier layer; and a patterned field plate structure on a second portion of the substrate layer, wherein the patterned field plate structure is laterally located between the barrier layer and the second source / drain region.

[0104] As described in more detail above, some embodiments described herein provide methods. The methods include: forming a first dielectric layer on a substrate layer of a semiconductor device; forming a gate electrode layer on the first dielectric layer; etching the gate electrode layer and the first dielectric layer to form a gate structure and a gate dielectric layer of a transistor structure of the semiconductor device, and to form a patterned field plate structure spaced apart from the gate structure and the gate dielectric layer; forming a second dielectric layer over the substrate layer; and etching the second dielectric layer to form a barrier layer over the substrate layer between the gate structure and the patterned field plate structure.

[0106] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a first source / drain region in a substrate layer; a second source / drain region in the substrate layer; a gate structure above the substrate layer and between the first source / drain region and the second source / drain region; a gate dielectric layer between the gate structure and the substrate layer; a sidewall spacer on a sidewall of the gate structure; a barrier layer on a first portion of the substrate layer, wherein the barrier layer is located between the sidewall spacer and the second source / drain region, and wherein a first end of the barrier layer is located above the gate structure; a main field plate layer on the barrier layer; and a patterned field plate structure on a second portion of the substrate layer, wherein the patterned field plate structure is laterally located between the barrier layer and the second source / drain region, and wherein a second end of the barrier layer opposite the first end is substantially in contact with the patterned field plate structure.

[0108] The terms "about" and "generally" can mean that a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that the terms "about" and "generally" can refer to a percentage of the value of a given quantity disclosed herein.

[0109] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the various embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The following detailed description, taken in conjunction with the accompanying drawings, will provide the best understanding of the nature of this disclosure. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a diagram of an exemplary semiconductor device described herein. Figures 2A and 2B are diagrams of embodiments of the integrated circuit device described herein. Figures 3A-3R are diagrams of embodiments forming the integrated circuit device described herein. Figure 4 is a diagram of an embodiment of the integrated circuit device described herein. Figure 5 is a diagram of an embodiment of the integrated circuit device described herein. Figure 6 is a diagram of an embodiment of the integrated circuit device described herein. Figure 7 is a flowchart of an exemplary process associated with forming the semiconductor device described herein.

Claims

1. A semiconductor device, comprising: The first source / drain region is located in the basal layer; The second source / drain region is located in the substrate layer; A gate structure is located above the substrate layer and between the first source / drain region and the second source / drain region; a barrier layer is located on a first portion of the substrate layer, wherein the barrier layer is located between the gate structure and the second source / drain region; and a main plate layer is located on the barrier layer. The patterned field plate structure is located on the second part of the substrate layer, wherein the patterned field plate structure is laterally located between the barrier layer and the second source / drain region, the patterned field plate structure is spaced apart from the gate structure, and the orthographic projection of the patterned field plate structure on the substrate layer and the orthographic projection of the second source / drain region on the substrate layer do not overlap, and wherein the main field plate layer does not cover the upper surface of the patterned field plate structure, and the main field plate layer is in contact with the sidewall of the patterned field plate structure.

2. The semiconductor device as claimed in claim 1, wherein the patterned field plate structure comprises: A dielectric layer on the second portion of the substrate layer; And a metal layer on the dielectric layer.

3. The semiconductor device of claim 1, wherein the barrier layer is in contact with the patterned field plate structure.

4. A method of forming a semiconductor device, comprising: A first dielectric layer is formed on the substrate layer of the semiconductor device; A gate electrode layer is formed on the first dielectric layer; The gate electrode layer and the first dielectric layer are etched to form the gate structure and gate dielectric layer of the transistor structure of the semiconductor device, and to form a patterned field plate structure spaced apart from the gate structure and the gate dielectric layer; a second source / drain region adjacent to the patterned field plate structure is formed in the substrate layer, wherein the patterned field plate structure is spaced apart from the gate structure, and the orthographic projection of the patterned field plate structure on the substrate layer and the orthographic projection of the second source / drain region on the substrate layer do not overlap; A second dielectric layer is formed above the base layer; The second dielectric layer is etched to form a barrier layer over the base layer between the gate structure and the patterned field plate structure; and a main field plate layer is formed on the barrier layer, wherein the main field plate layer does not cover the upper surface of the patterned field plate structure and contacts the sidewall of the patterned field plate structure.

5. The method of claim 4, wherein etching the second dielectric layer comprises: The gate structure and the patterned field plate structure are used as a self-aligned mask to etch the second dielectric layer.

6. The method as described in claim 4 further includes: A first source / drain region adjacent to the gate structure is formed in the substrate layer.

7. A semiconductor device, comprising: The first source / drain region is located in the basal layer; The second source / drain region is located in the substrate layer; A gate structure is located above the substrate layer and between the first source / drain region and the second source / drain region; a gate dielectric layer is located between the gate structure and the substrate layer; A sidewall gap wall is located on the sidewall of the gate structure; a barrier layer is located on a first portion of the base layer, wherein the barrier layer is situated between the sidewall gap wall and the second source / drain region, and wherein a first end of the barrier layer is located above the gate structure; a main field plate layer is located on the barrier layer; and a patterned field plate structure is located on a second portion of the base layer, wherein the patterned field plate structure is laterally positioned between the barrier layer and the second source / drain region, the patterned field plate structure is spaced apart from the gate structure, and the orthographic projection of the patterned field plate structure onto the base layer and the orthographic projection of the second source / drain region onto the base layer do not overlap, wherein the main field plate layer does not cover the upper surface of the patterned field plate structure, and the main field plate layer contacts the sidewall of the patterned field plate structure, and wherein a second end of the barrier layer opposite the first end is substantially in contact with the patterned field plate structure.

8. The semiconductor device of claim 7, wherein the length of the patterned field plate structure is less than the length of the gate structure.

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