Overlapping image field updates in a display system

Abstract

An illustrative display system includes a pixel array and a frame controller configured to display an image frame by performing a series of successive field updates. The series of successive field updates includes: a first field update, wherein a first write indicator circuit tracks a first traversal across one of the pixel arrays during a first update cycle to update the pixel array from a first image field in the sequence to a second image field; and a second field update, wherein a second write indicator circuit tracks a second traversal across one of the pixel arrays during a second update cycle to update the pixel array from the second image field in the sequence to a third image field. The second update cycle of the second field update overlaps with the first update cycle of the first field update.

Description

Prior Art

[0001] Digitally encoded images can be presented to a viewer using a variety of different types of image displays characterized by various different types of devices. For example, personal computing devices (e.g., laptops, tablets, etc.), mobile devices (e.g., smartphones, e-readers, etc.), wearable devices (e.g., smartwatches, etc.), extended reality devices (e.g., virtual and augmented reality headsets), televisions, and various other devices can each have an image display configured to present images to a user of the device. Summary of the Invention

[0002] Some display systems operate using pulse width modulation (PWM) of pixel emissions to control the brightness of pixels, and by controlling the relative brightness of different primary colors (e.g., red, green, and blue) in each pixel, also control the color emitted by the pixel. For example, some micro light-emitting diode (microLED) displays can operate using these principles. To achieve different brightness levels, the frame controller described herein can direct a pixel array to display an image frame by performing a series of consecutive field updates, with each consecutive field update consuming a finite amount of time (referred to herein as an update period) as a write pointer traverses the array and changes each pixel from one image field to the next. To maximize the dynamic range (e.g., to allow pixels to appear extremely dim without completely turning off), it is desirable for the time period of some image fields (referred to herein as the field duration) to be shorter than the minimum panel update period of a given display system. Thus, by employing multiple write pointers to allow image field updates to overlap (i.e., occur concurrently), the systems and methods described herein allow for extremely short field durations (and thus, allow for extremely high dynamic ranges and flexibility in how field sequences can be configured).

[0003] To this end, one embodiment described herein relates to a display system configured in accordance with the principles described herein. The display system may include a pixel array and a frame controller configured to cause the pixel array to display an image frame by performing a series of consecutive field updates. The series of consecutive field updates may include: 1) a first field update, in which a first write pointer circuit traces a first traversal across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and 2) a second field update, in which a second write pointer circuit traces a second traversal across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence. In this display system, the second update period of the second field update may overlap with the first update period of the first field update.

[0004] Other embodiments described herein may relate to a method performed by a display system such as the one described above. The method may include operations such as causing a pixel array to display an image frame by the display system performing a series of consecutive field updates. The series of consecutive field updates may include: 1) a first field update, in which a first write pointer circuit traces a first traversal across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and 2) a second field update, in which a second write pointer circuit traces a second traversal across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence. In this method, the second update period of the second field update may overlap with the first update period of the first field update.

[0005] Other embodiments described herein may relate to a non-transitory computer-readable medium storing instructions that, when executed, cause a frame controller of a display system to perform a process. For example, the process may include causing a pixel array to display an image frame by performing a series of consecutive field updates. The series of consecutive field updates may include: 1) a first field update, in which a first write pointer circuit traces a first traversal across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and 2) a second field update, in which a second write pointer circuit traces a second traversal across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence. In this process, the second update period of the second field update may overlap with the first update period of the first field update.

[0006] Various additional embodiments are described explicitly herein or can follow the principles described below. It will be understood that each of the examples mentioned above and described below can be implemented in different types of embodiments. For example, each of the various display systems described herein can be implemented in various different types of devices, the methods described herein can be implemented by instructions stored in a non-transitory computer-readable medium, the non-transitory computer-readable medium storing such instructions can be implemented in a display system, and so on.

[0007] Details of these and other embodiments are set forth in the accompanying drawings and the description below. Other features will also become apparent from the following description, the drawings, and the claims. Brief Description of the Drawings

[0008] FIG. 1 shows certain aspects of an illustrative embodiment of overlapping image field updates in a display system according to the principles described herein. FIG. 2 shows a block diagram of an illustrative display system configured to implement overlapping image field updates according to the principles described herein. FIG. 3 shows a block diagram illustrating how a sequencer circuit according to the principles described herein can operate to achieve certain aspects of overlapping image field updates in a display system. FIG. 4 shows an illustrative method for performing overlapping image field updates in a display system according to the principles described herein. FIG. 5 shows certain aspects of how an illustrative display system according to the principles described herein can perform overlapping image field updates based on image field sequence data to present an image frame. FIG. 6 shows certain timing-related aspects of an embodiment of overlapping image field updates in a display system according to the principles described herein. FIG. 7 shows additional aspects of an embodiment of overlapping image field updates in a display system according to the principles described herein. FIG. 8 shows an illustrative device in which a display system configured to perform overlapping image field updates can be implemented according to the principles described herein. FIG. 9 shows an illustrative computing system that can be used to implement various devices and / or systems described herein. Embodiments

[0009] [Related Applications] This application claims priority and the benefit of U.S. Provisional Application No. 63 / 594,817, filed on October 31, 2023, the disclosure of which is hereby incorporated by reference in its entirety.

[0010] Systems and methods for implementing overlapping image field updates in a display system are described herein. As used herein, a pixel array refers to pixels included on a panel of an image display (such as may be included in various types of electronic devices (e.g., augmented reality headsets, mobile devices, smartwatches, computer monitors, televisions, etc.)). A multi-color pixel may be implemented as a composite of at least three pixel elements (such as a red pixel element, a green pixel element, and a blue pixel element). These three primary colors can be used not only together to produce pure red, green, and blue light, but also to produce white light and many other colors. In some instances, other color schemes may be used in addition to this red, green, and blue (RGB) color scheme. As used herein, the pixels included in a pixel array may refer to composite RGB pixels and / or individual pixel elements of such composite pixels (e.g., the red pixel element of a given composite pixel, the green pixel element of a composite pixel, etc.).

[0011] When driving pixels at different luminance levels according to image content, the pixel array can display an image. For example, if there is relatively bright red content in a portion of the image, the red pixels (i.e., the red pixel elements of the composite pixels) in the area of the display associated with that content can be driven at a high intensity (so as to have a high luminance), while the other pixels in that area (e.g., blue and green pixels) may not be driven at all (to produce pure red) or may be driven at a lower intensity (to produce different shades of red, as may be required by the possible image content). As another example, if there is relatively dim red content in another portion of the image, the red pixels in that area of the display can be driven at a lower intensity; if there is green content in another portion of the image, the green pixels in that area of the display can be driven to be brighter than the red and blue pixels; if there is white content in the area, all three RGB colors can be driven according to the luminance of the content; and so on.

[0012] Although some display systems can achieve these various brightness levels by driving pixels with different gray levels (e.g., brighter pixels driven with a larger voltage or current than dimming pixels, etc.), other display systems can achieve the desired brightness levels in other ways. For example, a binary pulse width modulation (PWM) system can be configured to drive each pixel with a single gray level (e.g., a specified voltage or current amount for a pixel that is always driven), and can use time modulation to create the appearance of different brightness values. More specifically, a display system can include a frame controller that causes a pixel array to display each image frame by performing a series of consecutive field updates. The one frame time during which a particular image frame (e.g., a frame of video content, etc.) will be displayed can be subdivided into a number of shorter time periods during which the pixels are driven on and off according to the desired brightness of each pixel. For example, relatively bright pixels (e.g., red pixels in an area of the display that will display bright red content) can be driven in an on state for most or all of the frame time (e.g., many of the subdivided time periods), while relatively dim pixels (e.g., green and blue in that bright red area of the display) can remain in an off state for most or all of the frame time (e.g., many of the subdivided time periods). In other words, in order to display an image frame during the frame time, the frame controller can cause a sequence of image fields to be displayed one after another, thereby collectively producing the effect that the panel displays each pixel at the desired brightness of each pixel throughout the frame time.

[0013] Each different configuration of driving the pixel array during one of these short time periods (the periods into which the total frame time is subdivided) can be referred to herein as an image field or a sub-frame. Thus, rapidly displaying a sequence of such image fields (referred to herein as an image field sequence) during the frame time is equivalent to displaying the image frame corresponding to the image field sequence. In other words, the frame controller described herein is configured to cause the pixel array to display an image frame by performing a series of consecutive field updates among the image fields in a predetermined image field sequence corresponding to the image frame. Rapidly and continuously displaying the entire image field sequence during the frame time is the manner in which the display system described herein can display the image frame corresponding to the image field sequence.

[0014] Accordingly, the frame controller described herein is configured to cause the pixel array to display an image frame by performing a series of consecutive field updates between image fields in an image field sequence corresponding to the image frame, but physical constraints present in the display system may introduce technical problems. For example, one technical problem is the inability to instantaneously perform a field update that causes the pixel array to rapidly change from one image field to the next in the image field sequence. Each field update consumes a certain amount of time from its start to update the first pixel unit (e.g., the first pixel column, etc.) from one image field to the next until it finishes updating the last pixel unit (e.g., the final pixel column). Generally, only one display unit (e.g., one pixel column, a multi-column group, a partial column, etc.) can be updated at a time. Thus, the various display units within a particular pixel display must be updated one at a time until all units have been updated.

[0015] Although any field update will consume non-zero time, the fastest possible field update for a given implementation (regardless of whether the field update is actually performed in this manner by the implementation) will be performed by a single write pointer that tracks the traversal across the entire write to the pixel array without interruption to write to other locations in the pixel array (the other locations are tracked by other write pointers). This shortest amount of time consumed for a single-pointer update in a particular display system may be referred to herein as the minimum panel update period.

[0016] Technical problems arise when the minimum panel update period of a particular display panel is too long to meet dynamic range goals, frame rate goals, power goals, etc. If the minimum panel update period represents the shortest amount of time that any given image field can be displayed during the image field sequence (i.e., the shortest field duration supported by the system), then this minimum panel update period imposes significant constraints on how dim any pixel can be, and thus on the dynamic range that the image display can provide and the frame rate that the image display can support. Unfortunately, most options for shortening the minimum panel update period of a particular system involve increasing its power consumption, increasing complexity and cost, or otherwise compromising design goals.

[0017] As described in detail below, the systems and methods described herein provide a technical solution to this problem by employing overlapping image field updates, which are implemented by using multiple different write pointers that simultaneously traverse the pixel array. For example, the series of consecutive field updates performed by the frame controller described herein may include: 1) a first field update, in which a first write pointer circuit traces a first traverse across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and 2) a second field update, in which a second write pointer circuit traces a second traverse across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence. By overlapping the second update period of the second field update with the first update period of the first field update, the field duration of the second image field can be made extremely short. In one example, for instance, once the first column of pixels is updated from the first image field to the second image field and the first write pointer continues to move to start updating the second column of pixels, the second write pointer can point to the first column and start updating it from the second image field in the image field sequence to the third image field. Thus, for an example display panel with 1000 columns of pixels, the field duration of the second image field will be only the amount of time consumed to update one column, rather than the time consumed to update the entire panel (i.e., 1 / 1000 of the minimum panel update period in this example).

[0018] Accordingly, the technical effects and benefits of this solution are to significantly increase the dynamic range that this type of display system (e.g., a display system that relies on binary PWM or another image field-based display method) can support, while minimizing or having no detrimental effect on the power consumption, frame rate, complexity, or cost of the system. As another beneficial technical effect, this significant reduction in the minimum field duration provided by such overlapping image field updates can also lead to increased design flexibility. For example, flexibility can be increased in terms of how images are encoded into image field sequences and how these sequences are designed. Although outside the scope of this disclosure, it is known that various factors and considerations can be taken into account during this encoding process, such that providing additional flexibility in terms of how image field sequences can be arranged, ordered, configured, etc. can benefit the overall display system in many ways.

[0019] Various embodiments will now be described in more detail with reference to the drawings. It will be understood that the specific embodiments described hereinafter are provided as non-limiting examples and can be applied to various situations. Additionally, it will be understood that other embodiments not explicitly described herein may also fall within the scope of the claims set forth hereinafter. Systems and methods for implementing overlapping image field updates in a display system can produce any or all of the technical benefits mentioned above, as well as various additional and / or alternative technical effects mentioned above, and additional effects and benefits described and / or obvious hereinafter.

[0020] FIG. 1 shows certain aspects of an illustrative embodiment 100 of overlapping image field updates in a display system in accordance with the principles described herein. In FIG. 1, a frame sequence 102 is shown as including a plurality of image frames 104 that are displayed one after another sequentially with respect to time. Time is represented on a time line below the frames 104 to indicate that each frame is presented for a specific frame time. For example, if the frame sequence 102 represents video configured to be presented at 60 frames per second (fps), the frame time during which each of the frames 104 will be presented will be 1 / 60 second, or approximately 16.7 milliseconds.

[0021] Below the time line showing the frames 104 in the frame sequence, FIG. 1 shows a frame time 105 during which a single frame 104 is shown to be presented by image fields (also referred to as sub-frames) of an image field sequence corresponding to the specific frame 104. More specifically, FIG. 1 shows an image field sequence that includes at least image field 106-A, followed by image field 106-B, followed by image field 106-C. The ellipses before and after these image fields indicate that the image field sequence corresponding to this image frame 104 may further include additional image fields before image field 106-A or after image field 106-C.

[0022] Between different image fields in the image field sequence of FIG. 1, a series of field updates are shown, where the labels are related to the letters used for each field sequence. For example, field update 108-AB illustrates where image field 106-A is updated to image field 106-B, and then field update 108-BC shows where image field 106-B is updated to image field 106-C. Other field updates that are not explicitly shown and / or labeled can be performed to continuously move through the image field sequence during the course of one frame time associated with this image frame 104. Specifically, as shown, after image field 106-A has been displayed for a first field duration, field update 108-AB is performed to transition the pixel array from image field 106-A to image field 106-B. Then, after image field 106-B has been displayed for a second field duration (a much shorter duration in this example), field update 108-BC is performed to transition the pixel array from image field 106-B to image field 106-C.

[0023] The image fields in FIG. 1 are shown as having two dimensions. Horizontally, time is represented as indicating how long each image field is displayed (the width dimension along the time axis). However, the vertical direction is to be understood as representing the pixels in each column (or other unit) in the panel. Since updating each column of pixels consumes a finite amount of time (the pixels in the panel cannot change instantaneously), field updates 108-AB and 108-BC are shown as being inclined relative to the horizontal time axis. The slope of these field updates relative to the timeline shows how, at any given point in time, some pixels on the panel (e.g., those that have transitioned to the next image field) can be showing one image field, while other pixels on the panel (e.g., those that have not yet transitioned) may be showing a different image field. In other words, as write pointers 110-1 and / or 110-2 traverse the pixel array to update the pixel array, the write pointer circuitry tracks this traversal by storing an address (e.g., a column number or another address of another suitable pixel unit) in the panel that is currently undergoing a field update. The pixels that have been traversed and updated by the write pointer can show one image field, while the pixels that have not yet been traversed by the write pointer to be updated can show a different image field.

[0024] As used herein, a write pointer refers to a position in a pixel array where a field update is performed at any given time. Since it is not possible to update the entire pixel array simultaneously, the write pointer must traverse the pixel array (e.g., one pixel at a time, one column at a time, etc.) during a finite time period (i.e., the update period) to perform a field update from one image field to another. Although the write pointer itself may be intangible in nature (e.g., a number representing a pixel or column position, etc.), the write pointer can be managed using specific circuitry such as a hardware register, a position storing a pointer in a temporary memory, a custom circuit configured to specifically track the traversal across the pixel array, etc. Thus, as used herein, the write pointer circuitry will be described as tracking the traversal across the pixel array during the update period. Such write pointer circuitry can be configured to store, update, and / or otherwise manage the write pointer and can be implemented in any suitable hardware (e.g., a custom circuit, a dedicated register, a position in a memory, other suitable circuitry, etc.). Although one write pointer circuitry may track only a single position in the pixel array at a time (so as to manage only a single traversal across the pixels at a time), the systems and methods described herein employ a plurality of write pointer circuitries to track multiple positions in the pixel array simultaneously (to allow multiple field updates to be performed simultaneously, such as field updates 108-AB and 108-BC, or to allow the multiple field updates to overlap).

[0025] For illustrative purposes, the first write pointer 110-1 (labeled "1" in FIG. 1) is shown in this example as being used for field update 108-AB. At a time earlier than the snapshot in FIG. 1, write pointer 110-1 may have started at the first column of pixels indicated at the top of image field 106-A and transitioned these pixels to image field 106-B. As time progresses, as each pixel cell transitions from image field 106-A to image field 106-B, write pointer 110-1 will effectively move down along the slope of field update 108-AB. At the snapshot moment in FIG. 1, write pointer 110-1 is shown near the bottom of the slope, indicating that field update 108-AB is nearing completion and write pointer 110-1 will soon be released to track another field update. However, as illustrated by the intersection of vertical line 112 with both field update 108-AB and field update 108-BC, the time for the FIG. 1 snapshot involves two overlapping (parallel) image field updates occurring at once. Although write pointer 110-1 shows that field update 108-AB is still in progress, the field duration of image field 106-B is so short that write pointer 110-2 is shown as having started at the top as part of field update 108-BC to transition from image field 106-B to image field 106-C. As clearly illustrated at the time associated with vertical line 112, the field duration of image field 106-B (i.e., the thinness of the parallelogram representing image field 106-B) is shorter than the minimum panel update period and is thus achieved only by having more than one write pointer work simultaneously.

[0026] Overlapping (parallel) image field updates such as illustrated by field updates 108-AB and 108-BC can produce technical benefits such as shorter field durations that allow for increased dynamic range and other advantages described herein. At the time associated with vertical line 112, for example, some pixel cells (near the top) have undergone both field updates 108-AB and 108-BC such that these pixel cells are displaying image field 106-C. Other pixel cells (in the middle) have undergone field update 108-AB to display image field 106-B but have not yet undergone field update 108-BC (because the traversal tracked by second write pointer 110-2 has not reached these pixel cells). Still other pixel cells (near the bottom) have not undergone either field update 108-BC or field update 108-AB such that these pixel cells are still displaying image field 106-A. Thus, as shown in the figure (and advantageously for the system in the manner described), the field duration of image field 106-B is significantly shorter than the update period of either field update 108-AB or 108-AB.

[0027] After illustrating an implementation of overlapping image field updates executable by a display system in FIG. 1, FIGS. 2 and 3 will now illustrate aspects of a display system including certain system components (data, hardware, and / or instructional components) that interoperate to produce the end result of FIG. 1.

[0028] FIG. 2 shows a block diagram of an illustrative display system 200 configured to implement overlapping image field updates according to the principles described herein. As shown, the display system 200 may be characterized by a frame controller 202 and a memory 204 that stores data for an image frame 206 to be displayed by the display system 200. The frame controller 202 includes a sequencer circuit 208 and a plurality of write pointer circuits 210 to facilitate the display of the image frame 206 according to the principles described herein. By executing the methods described herein, the frame controller 202 may direct a pixel driver circuit 212 to cause a pixel array 214 to present the image frame 206 by continuously displaying a sequence of image fields (such as the image fields 106-A to 106-C illustrated above).

[0029] The pixel array 214 may be arranged in any suitable manner, such as in columns, rows, or in a non-linear arrangement, where the pixels may be grouped into other types of units (e.g., partial columns, interleaved columns, bundles, etc.). Each pixel 214 in the array may be implemented using any suitable technology. For example, the pixel 214 may be implemented as a light-emitting diode (LED), or more particularly, as a microLED that may have an extremely small pixel pitch and high efficiency. The pixel driver circuit array 212 may correspond to the pixel array 214. For example, a circuit for a pixel driver may be included for each individual pixel 214. As mentioned above, the pixel driver circuit may be configured to drive the pixels to turn on and off at a very fast and controlled rate (e.g., in combination with the image field sequence described herein), but may operate in a binary manner such that each pixel is either on or off (and there is no scaling of different analog drive strengths, etc.).

[0030] The memory 204 may represent any suitable buffer hardware that may store all or part of the image frame 206 when presenting the image frame. In some instances, the display system 200 may include sufficient memory 204 to buffer several image frames at a time. The image frame 206 may include data indicating the intensity (e.g., brightness) value of each pixel 214 of the array. However, in order to drive the pixels at their respective intensities using a binary pulse width modulation (PWM) method, the image frame 206 may be converted into a sequence of image fields including a plurality of image fields that, when presented in rapid succession, cause the pixels to exhibit the desired brightness based on the portion of their on and off frame times.

[0031] For further illustration, FIG. 3 shows a block diagram illustrating how a sequencer circuit 208, in accordance with the principles described herein, can operate to achieve certain aspects of overlapping image field updates in a display system. As shown in FIG. 3, when the sequencer circuit 208 drives the pixel driver circuit 212 according to a binary PWM scheme, a sequence instruction 302 (which may also be stored in the memory 204 in some instances) can be executed by the sequencer circuit 208. Specifically, a write pointer vector 308 having a plurality of write pointers 310-1, 310-2, etc. is used to sequence an image field sequence 304 including a plurality of image fields 306-A, 306-B, 306-C, etc. As shown by the ellipse in FIG. 3, any suitable number (including greater than 3) of image fields can be included in the image field sequence 304. Additionally, based on the trade-off principles described below, a suitable plurality of write pointers can be included within the write pointer vector 308.

[0032] The sequencer circuit 208 can be configured to move through the image field sequence 304 by performing a series of consecutive field updates using the write pointer vector 308, causing the pixel array 214 to display an image frame. For example, the sequence instruction 302 can direct the sequencer circuit 208 to perform a series of consecutive field updates. The series can include, for example, a first field update in which a first write pointer circuit associated with the write pointer 310-1 tracks a first pass across the pixel array 214 during a first update period to update the pixel array 214 (with the aid of the pixel driver circuit 212) from the first image field 306-A in the image field sequence 304 to the second image field 306-B in the image field sequence 304. The series of consecutive field updates can further include a second field update in which a second write pointer circuit associated with the write pointer 310-2 tracks a second pass across the pixel array 214 during a second update period to update the pixel array 214 (with the aid of the pixel driver circuit 212) from the second image field 306-B to the third image field 306-C in the image field sequence 304. The series of consecutive field updates can further include additional field updates to reuse the write pointers 310-1 and / or 310-2, as well as to employ other write pointers within the write pointer vector 308 to track additional passes across the pixels to update them to additional image fields within the image field sequence 304. As illustrated above, one benefit of using separate and independent write pointers to perform these field updates is that the second update period of the second field update can overlap with the first update period of the first field update. In other words, even while the first field update using the write pointer 310-1 is still in progress, the second field update using the write pointer 310-2 can begin.

[0033] Figure 4 shows an illustrative method 400 for performing overlapping image field updates in a display system in accordance with the principles described herein. For example, method 400 may be embodied within sequence instructions 302 such that frame controller 202 may use sequencer circuit 208 and a plurality of write pointer circuits 210 to perform method 400 (e.g., to track a write pointer vector such as write pointer vector 308). Although FIG. 4 shows illustrative operations in accordance with a particular embodiment, it will be understood that other embodiments of such methods may omit, add, reorder, and / or modify any of the operations 402-408 explicitly shown in FIG. 4. Additionally, although operations 402-408 are illustrated with arrows indicating a sequential order of operations, it will be understood that some or all of the operations of method 400 may be performed simultaneously (e.g., in parallel) with each other. Each of the operations of method 400 will now be described in more detail as they may be performed by an embodiment of display system 200.

[0034] At operation 402, a display system (e.g., using a frame controller configured to perform binary pulse width modulation) may receive an image frame (e.g., image frame 206) to be displayed by an array of pixels (e.g., pixels 214) of the display system. For example, as illustrated above, the image frame may be one of a sequence of image frames (e.g., a video frame, etc.).

[0035] At operation 404, the display system may cause the pixel array to display the image frame by performing a series of consecutive field updates. For example, the image frame may be converted into a sequence of image fields that, when presented in a rapid sequence according to a binary PWM scheme, causes each pixel in the pixel array to have a desired apparent brightness. As shown within operation 404, two sub-operations 406 and 408 may be performed to cause the pixel array to display the image frame.

[0036] First, at sub-operation 406, a first field update may be performed where a first write pointer circuit tracks a first traversal across the pixel array during a first update period. In this manner, as has been described, the pixel array may be updated from a first image field in the image field sequence to a second image field in the image field sequence.

[0037] Then, at sub-operation 408, a second field update may be performed, where a second write pointer circuit traces a second pass across the pixel array during a second update period to update the pixel array from a second image field to a third image field in an image field sequence. As has been described and as will be illustrated in more detail below, these field updates may be performed simultaneously or at least partially simultaneously. More specifically, while a first update period is still in progress, a second update period of the second field update may overlap with a first update period of the first field update at the start of the second update period.

[0038] In some embodiments, a method (such as method 400) may be embodied as a process in memory. For example, method 400 may be embodied by sequence of instructions 302 and stored in memory 204 or elsewhere. A non-transitory computer-readable medium (e.g., such as implemented by memory 204 in some embodiments) may store instructions that, when executed, cause a processor (e.g., such as sequencer circuit 208) to perform a process embodying method 400. Specifically, when the instructions are executed on the non-transitory computer-readable medium, the processor may: 1) receive an image frame to be displayed by a pixel array of a display system; and 2) cause the pixel array to display the image frame by performing a series of consecutive field updates. The series of consecutive field updates may include: 1) a first field update, where a first write pointer circuit traces a first pass across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and 2) a second field update, where a second write pointer circuit traces a second pass across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence. The second update period of the second field update may overlap with the first update period of the first field update.

[0039] After illustrating embodiments of overlapping image field updates and various details of display systems and methods for achieving such overlapping image field updates, FIGS. 5-7 will now be described to bring these concepts together and illustrate certain timing-related and other details. More specifically, FIG. 5 shows how an illustrative display system may perform overlapping image field updates based on image field sequence data to present certain aspects of an image frame; FIG. 6 highlights various timing-related aspects of embodiments of overlapping image field updates; and FIG. 7 shows additional aspects of embodiments of overlapping image field updates including multiple overlapping updates supported by a set of more than two write pointers.

[0040] FIG. 5 shows a simplified implementation 500 of an implementation of a display system 200 including a frame controller 202 and a pixel array 214. It will be understood that, as described herein, other elements of the display system 200 may also be included, but those elements are not explicitly drawn in FIG. 5. The frame controller 202 is shown as receiving image data 502, which represents data that will be used by the display system 200 to display an image (e.g., an image frame, such as image frame 206). More specifically, the image data 502 is shown as including an image field sequence 304 that corresponds to a particular image frame (e.g., image frame 206), and the pixel array 214 will display the particular image frame when being driven (under the guidance of the frame controller 202) through each image field in the image field sequence 304 during the course of the image frame time.

[0041] Although not explicitly shown in FIG. 5, it will be understood that the display system 200 may further include other components and resources (e.g., processing and memory resources for processing the image data 502, buffering for the image data 502, pixel drivers for driving the pixels 214, etc.). Additionally, although a single image field sequence 304 representing a single image frame (e.g., image frame 206) is shown as the focus of this specification in FIG. 5, additional image field sequences associated with additional image frames are represented in FIG. 5 by similar blocks lined up behind the image field sequence 304 and ellipses, indicating that any number of such image field sequences and image frames may exist (e.g., to present a video sequence, etc.).

[0042] The image field sequence 304 is shown as including a plurality of image fields 306-A through 306-F (the ellipsis indicates that more or fewer image fields may be included in the sequence for a particular implementation). These individual image fields are represented by the boxes labeled "A", "B", "C", etc. in the boxes of the image field sequence 304, and then the dashed arrows show the correlation with some of these representations and another representation of image fields 306-A through 306-C along a timeline similar to the timeline described above with respect to FIG. 1 (the other image fields 306 are not explicitly shown in this latter representation). Although the image field sequence 304 is shown as part of the image data 502 and originating from somewhere outside the display system 200, it will be understood that in some implementations, the display system 200 itself may generate the image field sequence 304 based on the image data 502 received from an internal or external source and not yet configured as an image field sequence. For example, in some implementations, converting the image data to an image field sequence (such as the image field sequence 304) may be a role performed by the sequencer circuit 208. Regardless of where the image data 502 and the image field sequence 304 originate, these may be received by the frame controller 202 and processed according to the principles described herein.

[0043] Similar to the timeline described with respect to FIG. 1, FIG. 5 shows the individual image fields of the image field sequence 304 along a timeline (labeled "Time") near the bottom of the figure. A series of field updates 108 (e.g., a first field update 108-AB, a second field update 108-BC, and other field updates not explicitly shown and / or labeled) may be performed to move continuously through the image field sequence 304 during the course of the frame time associated with an image frame (e.g., image frame 206). Specifically, as shown, after image field 306-A has been displayed for a first field duration, the field update 108-AB is performed to transition the pixel array 214 from image field 306-A to image field 306-B. Then, after image field 306-B has been displayed for a second field duration, the field update 108-BC is performed to transition the pixel array 214 from image field 306-B to image field 306-C.

[0044] As described above with respect to FIG. 1, the image field representation along the timeline in FIG. 5 is shown as having two dimensions, so as to represent not only the duration of each image field being displayed (the width dimension along the timeline), but also the fact that not all pixels 214 in the panel can transition instantaneously (the height dimension orthogonal to the timeline). In other words, the slope of the field update 108 illustrated with respect to the timeline illustrates that at any given time, some pixels 214 can display one image field while other pixels 214 can display a different image field. In other words, when the write pointer circuit traces through the traversal of the pixel array to update the pixel array, the pixels that have been traversed and updated by the write pointer can display one image field, while the pixels that have not been updated by the write pointer traversal can display a different image field.

[0045] As has been described, the display system 200 can be configured to perform overlapping (parallel) image field updates to produce certain technical benefits, such as shorter field durations that allow for increased dynamic range and other advantages. To illustrate this overlap, a particular time 504 is shown in FIG. 5, where the field update 108-AB overlaps with the field update 108-BC (i.e., both occur in parallel or simultaneously). As has been described, this overlap can be achieved by using more than one write pointer circuit to trace more than one traversal across the pixel array, such that both can occur during the same overlap period. At time 504, for example, certain pixels 214 (near the top) have undergone both the field updates 108-AB and 108-BC, such that these pixels are displaying the image field 306-C. Other pixels 214 (in the middle) have undergone the field update 108-AB to display the image field 306-B, but have not yet undergone the field update 108-BC (because the traversal traced by the second write pointer circuit has not yet reached these pixels). Still other pixels 214 (near the bottom) have not undergone either the field update 108-AB or the field update 108-BC, such that these pixel units are still displaying the image field 306-A. Thus, as shown in the figure (and in a manner that is advantageous for the system as has been described), the field duration of the image field 106-B is significantly shorter than the update period of either of the field updates 108-AB or 108-BC.

[0046] The binary PWM technique described herein modulates the brightness of various pixels (and thereby also modulates color when mixing different brightness combinations of primary colors) by rapidly turning pixels on and off according to the image fields within a given sequence of image fields. For example, a given pixel may be turned on for all of the image fields of image field sequence 304 such that the pixel appears at maximum brightness, turned off for all of the image fields of image field sequence 304 such that the pixel appears black, or turned on and off for different image fields to achieve a non-zero brightness that is also less than the maximum. For example, a pixel that is turned on only for image field 306-B will appear very dim (but still on), another pixel that is turned on only for image field 306-A will appear brighter (because the field duration of image field 306-A is longer than the field duration of image field 306-B), and yet another pixel that is turned on for both image fields 306-A and 306-B will be brighter still. By having various image fields with various different field durations for each frame, any given pixel can appear at many different brightness levels based on the combination of image fields for which the pixel is turned on and off.

[0047] In some examples, the image data 502 may define a multi-bit brightness value for each of the pixels 214 in the array. For example, an 8-bit brightness value will correspond to 2^8 = 256 possible different brightness levels (from 0b00000000 to 0b11111111). For an image frame displayed using the binary PWM technique, the array of multi-bit brightness values may be applied to a pixel array corresponding to the pixel array of the image frame. For example, the first image field (e.g., image field 306-A) of an image field sequence (e.g., image field sequence 304) may include a first array of binary values that form the first bit plane of the array of multi-bit brightness values. The second image field (e.g., image field 306-B) in the image field sequence may include a second array of binary values that form the second bit plane of the array of multi-bit brightness values. The third image field (e.g., image field 306-C) in the image field sequence may include a third array of binary values that form the third bit plane of the array of multi-bit brightness values, and so on.

[0048] Thus, for example, an implementation using 8-bit luminance values may use a sequence of image fields with eight image fields of different durations - the longest duration (i.e., the widest image field) for the most significant bit of the multi-bit luminance value, the second longest duration for the second most significant bit of the multi-bit luminance value, and so on until the shortest duration (i.e., the thinnest image field) for the least significant bit of the multi-bit luminance value. Given an arbitrary example, if the 8-bit luminance value of a certain pixel is 0b00110001, then the pixel can be driven to be off for the two longest duration image fields (because its two most significant bits are "0"), driven to be on for the third and fourth longest duration image fields (because its third and fourth most significant bits are "1"), driven to be off for the fifth to seventh longest duration image fields (because these bits are again "0"), and finally, driven to be on for the shortest duration image field (because the eighth least significant bit is "1"). It will be understood that these various image fields need not be presented in any particular order (e.g., from longest to shortest), and in fact, being able to flexibly order the individual image fields in various ways can be advantageous. It will also be understood that this one-to-one mapping of luminance value bits to image fields or sub-frames is given by way of example only, and in implementations having, for example, more than eight different sub-frames, there are other (e.g., more complex) ways to convert luminance data into bit fields.

[0049] In an implementation of this type, each image field in the sequence of image fields (e.g., image fields 306-A to 306-F, etc.) may include an array of binary values corresponding to the pixel array (i.e., binary values representing on or off for each pixel). However, in other types of implementations, for example, for pixels configured to be energized at multiple luminance levels, multi-bit values may be used similarly instead of binary values. Thus, in these examples, each image field in the sequence of image fields may include an array of multi-bit values corresponding to the pixel array.

[0050] As already described, one advantage of using multiple write pointers is that it allows the image field to be shorter than the minimum panel update period (i.e., the length of time consumed to complete an entire field update). As shown in FIG. 5, for example, the duration of image field 306-B is shorter than either of field updates 108-AB or 108-BC. In this way, image field 306-B can be used for a bitplane associated with one of the least significant bits of the multi-bit luminance values assigned to each of the pixels in pixel array 214. At the extreme, the shortest duration image field (i.e., the thinnest image field) that can be provided by a display system with multiple write pointers will be one in which once the first writable unit (referred to herein as a display unit) transitions to one image field and the write pointer moves to a second unit, the first writable unit is rewritten to the next image field using the second write pointer.

[0051] More specifically, given an implementation in which pixel array 214 is arranged on a display panel relative to a plurality of display units (e.g., pixel columns or other addressable groups into which the pixel array is organized), a first write pointer circuit can start tracking the plurality of display units from a first display unit during a first field update (e.g., field update 108-AB) to update each of the plurality of display units, while a second update period of a second field update (e.g., field update 108-BC) can start immediately after the first display unit is updated. For example, the plurality of display units can be implemented as a single column on the display panel such that after completing field update 108-AB for the first column of the panel, field update 108-BC can start immediately on that first column. As another example, the plurality of display units can be implemented as multiple column units on the display panel (e.g., each grouped with two or more columns) such that after completing field update 108-AB for the first multi-column group of the panel, field update 108-BC can start immediately on that multi-column group. As yet another example, the plurality of display units can be implemented as partial columns on the display panel such that after completing field update 108-AB for the first partial column of the panel (e.g., a grouping of one or more pixels on a column), field update 108-BC can start immediately on that first partial column.

[0052] Since these updates are performed on a per-cell basis (e.g., per-column, etc.), it will be understood that such updates can move from the top column to the bottom column (or from the bottom column to the top column) in a sequential order, but this sequential ordering is not necessarily used for every implementation or is ideal for every implementation. More specifically, for some implementations in which the pixel array 214 is arranged in a plurality of columns on the display panel, each traversal across the pixel array 214 can be performed in a sequential update order that starts from the top column among the plurality of columns and proceeds sequentially in consecutive columns until reaching the bottom column among the plurality of columns. However, in other implementations in which the pixel array 214 is arranged in a plurality of columns on the display panel, the traversal can be performed in an unordered manner. For example, each traversal across the pixel array 214 can be performed in a non-sequential update order different from the sequential update order that starts from the top column and proceeds sequentially in consecutive columns until reaching the bottom column. For example, by traversing the display units (e.g., columns, groups of multiple columns, partial columns, etc.) in a random or pseudo-random order, certain unwanted artifacts and effects that would otherwise occur when using sequentially sorted updates can be avoided or mitigated.

[0053] FIG. 6 shows certain timing-related aspects of an embodiment 600 of overlapping image field updates in a display system according to the principles described herein. In FIG. 6, image field 306-A is explicitly shown as representing the first image field in the image field sequence 304, which is displayed when the earlier image frame (“previous frame (P)”) is being replaced. The field update 108-PA is explicitly labeled to show this first transition from the previous image frame (P) to the first image field 306-A of the new image frame. In addition to the field updates 108-AB and 108-BC (described above), FIG. 6 also shows another field update 108-CD to indicate the transition from image field 306-C to image field D (not explicitly shown), which is understood to occur at that point in time.

[0054] Also shown in FIG. 6 are various events labeled “Tn” along the timeline, where n is an integer from 0 to 7 (to distinguish the events from each other). These events are shown as dashed lines that extend to the start and end of the various field updates 108 to indicate the events being called out. Specifically, as shown, event T0 occurs at the start of field update 108-PA, event T1 occurs at the end of field update 108-PA, event T2 occurs at the start of field update 108-AB, event T3 occurs at the start of field update 108-BC, event T4 occurs at the end of field update 108-AB, event T5 occurs at the end of field update 108-BC, event T6 occurs at the start of field update 108-CD, and event T7 occurs at the end of field update 108-CD.

[0055] Extending between such events, FIG. 6 shows the update period 602 of each update 108 and the field duration 604 of each image field 306 (the duration specifically illustrated for the pixels of the last update, but it will be understood that each pixel displays the field timing time of each image field the same as other pixels, even if not in the same time period). More specifically, update period 602-PA shows how long field update 108-PA takes, update period 602-AB shows how long field update 108-AB takes, update period 602-BC shows how long field update 108-BC takes, and update period 602-CD shows how long field update 108-CD takes. In this example, each update period 602 is shown as taking the same amount of time, but these update periods occur at different points on the timeline.

[0056] In contrast, the field durations 604 are shown as being unique in terms of the amount of time they each consume. FIG. 6 shows the field duration 604-A shown by image field 306-A, the field duration 604-B shown by image field 306-B, and the field duration 604-C shown by image field 306-C, with each of these field durations being of a different length. Specifically, as shown, the length of field duration 604-B is relatively short (shorter than any of the other field durations 604 and even shorter than the update period 602). Field duration 604-A is longer than field duration 604-B and the update period 602, and field duration 604-C is even longer.

[0057] In summary, FIGS. 5 and 6 illustrate various principles related to overlapping image field updates and the technical benefits that can be provided thereby.

[0058] As an example, these figures show a display system 200 that includes a pixel array 214 and a frame controller 202 configured to cause the pixel array 214 to display image frames by performing a series of successive field updates 108. The series of successive field updates 108 is shown to include a first field update 108-AB, where a first write pointer circuit traces a first traversal across the pixel array 214 during a first update period 602-AB to update the pixel array from a first image field 306-A in an image field sequence 304 to a second image field 306-B in the image field sequence. The series of successive field updates 108 is further shown to include a second field update 108-BC, where a second write pointer circuit traces a second traversal across the pixel array 214 during a second update period 602-BC to update the pixel array from the second image field 306-B to a third image field 306-C in the image field sequence 304. As shown, the second update period 602-BC of the second field update 108-BC overlaps with the first update period 602-AB of the first field update 108-AB. This allows the field duration 604-B to be even shorter than either of the update periods 602, which would not be possible if the entire pixel array had to be updated before a new update could begin (i.e., if only a single write pointer circuit were used and the update periods 602-AB and 602-BC did not overlap).

[0059] As already mentioned, the minimum panel update period can be defined as the time period in which the frame controller 202 can use a single write pointer circuit to track the traversal across the pixel array to update the pixel array. As mentioned above, the writing to the pixel array is performed at one location (i.e., one display unit) at a time. Thus, an instance using two different write pointers to two separate display units (such as the instances illustrated in FIGS. 5 and 6) will be understood to consume a longer time than the minimum panel update period (because the updates to the pixels at the locations tracked by the two write pointers will be interleaved). Accordingly, the first update period 602-AB and the second update period 602-BC can each be at least twice the minimum panel update period. This allows the second image field 306-B to have a second field duration 604-B shorter than the minimum panel update period, but two short field durations in a column cannot be performed using only these two write pointer circuits. In fact, the cost of using the short field duration 604-B for the image field 306-B is that, as shown, the third image field 306-C has a third field duration 604-C longer than the minimum panel update period, such that the sum of the second field duration 604-B and the third field duration 604-C is at least twice the minimum panel update period. In fact, for an embodiment using two write pointer circuits, the sum of every two consecutive field durations 604 (e.g., field durations 604-A and 604-B, field durations 604-B and 604-C, etc.) on a rolling basis will be at least twice the minimum panel update period.

[0060] It should be noted that even when using fewer than all available write pointers (e.g., at a time when, for example, only one field update is in progress despite two write pointers being available), the speed of the update (reflected by the slope of the field update) can be maintained such that each field duration is consistent across the array (i.e., each pixel will be displayed for the same amount of time for each image field, regardless of its location). In other words, regardless of how many write pointers are actually used at a given moment, the update period can be configured to be the same for each field update (e.g., the slope is determined by the maximum number of write pointers used at any time during the sequence).

[0061] By adding an additional write pointer circuit and an additional parallel traversal across the pixel array, the update period 602 for all field updates 108 will become longer. However, once the rolling window of the continuous field duration 604 is long enough, short field durations (similar to field duration 604-B) can be arranged continuously with respect to each other to provide further flexibility. For example, if the minimum panel update period is again defined as the time period in which the frame controller uses a single write pointer circuit to track the traversal across the pixel array to update the pixel array, then this series of continuous field updates 108 can further include a third field update, in which a third write pointer circuit tracks a third traversal across the pixel array during a third update period to update the pixel array from the third image field to the fourth image field in the image field sequence. In this case, the first update period, the second update period, and the third update period will each be at least three times the minimum panel update period, but two short field durations 604 can be placed continuously in the image field sequence 304. Specifically, in this example, the second image field can be displayed for a second field duration shorter than the minimum panel update period, and the third image field can be displayed for a third field duration shorter than the minimum panel update period, as long as the fourth image field is displayed for a fourth field duration longer than the minimum panel update period, such that the sum of the second field duration, the third field duration, and the fourth field duration is at least three times the minimum panel update period.

[0062] For illustrative purposes, FIG. 7 shows additional aspects of an implementation 700 of overlapping image field updates in a display system in accordance with the principles described herein. Like elements are shown in implementation 700 as shown and described in the other figures above. However, the other examples above included two write pointer circuits that track the traversal across the pixel array, while FIG. 7 shows an example in which a greater plurality of write pointer circuits (e.g., four independent write pointers in this example) allows for even greater design flexibility in a given implementation. More specifically, the two write pointers illustrated in FIGS. 5 and 6 are shown as allowing for one short duration image field 306 (e.g., image field 306-B), as long as the short duration image field is surrounded by longer duration image fields (e.g., image fields 306-A and 306-C), with the limitation that the combined duration of any two consecutive field durations must be at least twice as long as the minimum panel update period. The two-pointer implementation illustrated in FIGS. 5 and 6 will therefore not be able to have two short duration image fields adjacent to each other in the image field sequence.

[0063] As illustrated in FIG. 7, the amount of flexibility that the image field sequence 304 is designed to have may be affected by a trade-off between on the one hand sequencing limitations (e.g., such as how many relatively short-duration image fields can be placed in sequence continuously) and on the other hand the length of the update period 602. More specifically, achieving consecutive (or closely placed) short-duration image fields may require the use of multiple write pointers, which in turn may increase the update period because the update period is proportional to the number of write pointers used (e.g., greater than or equal to the minimum panel update period multiplied by the number of write pointers employed). Thus, if too few write pointers are used, no single image field may have an extremely short duration (the minimum panel update period will present a lower bound), while if too many write pointers are used, the update period for each field update may be so long as to result in unwanted ghosting because different parts of the panel are showing many different sub-frames at any given point in time, and the increase in the update period for any field update lengthens the entire frame time.

[0064] Accordingly, the trade-off can be sensibly managed to select a reasonable number of write pointers to avoid an overly long update period while also having enough write pointers to allow for flexible sequencing of relatively short-duration image fields. A four-pointer implementation showing several short-duration image fields close to each other in an image field sequence is shown in FIG. 7 to illustrate one way in which these trade-offs can be managed.

[0065] Similar to FIGS. 5 and 6 above, FIG. 7 shows an image field sequence 306 labeled with individual letters 'A' through 'F' in this case. In this example, these six image fields are to be understood as representing all of the image fields in a particular image field sequence such that presenting these image fields sequentially is equivalent to presenting a single image frame. As shown in the shaded portions before and after the image field 306, a 'previous frame' represented by the letter 'P' may be before this image frame, and a 'next frame' represented by the letter 'N' may be after it. Thus, a series of consecutive field updates 108 in FIG. 7 includes a field update 108-PA (labeled PA) from the previous frame P to the image field 306-A, a field update 108-AB (labeled AB) from the image field 306-A to the image field 306-B, a field update 108-BC (labeled BC) from the image field 306-B to the image field 306-C, and so on, up to the field updates labeled CD, DE, EF, and FN.

[0066] In this example, as mentioned above, the four write pointers 710-1 to 710-4 can be implemented by four write pointer circuits that track the traversal across the pixels during an update. The field updates managed by each of the write pointers are shown along the timeline, where the arrows span the individual update cycles. Each of these arrows is shown as having the same length because the update cycles for the four-pointer implementation are the same for each of the field updates (including those field updates where the four write pointers can be effectively used during some or all of the field update periods, as described above). However, it will be understood that this update cycle is significantly longer (i.e., the slope of the field update 108 is significantly flatter or less steep) compared to the update cycles in other examples described herein that use fewer write pointers (e.g., the two-pointer implementations of FIGS. 5 and 6). More specifically, this update cycle must be at least four times the minimum panel update cycle, while the update cycles for two-pointer implementations such as those illustrated in FIGS. 5 and 6 can be half that length (i.e., twice the minimum panel update cycle).

[0067] The benefit obtained by accepting this slower update time is demonstrated by the fact that in this example, a number of relatively short-duration image fields 306 can be placed adjacent to each other sequentially. Specifically, the image fields labeled B, C, and D are all shown as having relatively short durations, and they are all close to each other. As shown by the write pointer arrows below the timeline, this sorting flexibility is made possible by the number of write pointers available in this example. Specifically, as shown in the figure, the write pointer 710-1 can first be used for the field update 108-PA ("Pnt1:PàA"), and then again for the field update 108-AB ("Pnt1:AàB"). However, before the field update 108-AB is completed, the field updates 108-BC, 108-CD, and 108-DE start. Since the write pointer 710-1 is busy handling the field update 108-AB, it will not be able to facilitate the field updates 108-BC, 108-CD, or 108-DE as quickly, and the field durations of these image fields will need to be longer. However, since the write pointers 710-2, 710-3, and 710-4 are available in this implementation, FIG. 7 shows that these short-duration image fields B, C, and D can be placed sequentially without problems.

[0068] Specifically, when write pointer 710-1 continues to transform the panel for field update 108-AB ("Pnt1: A→B"), write pointer 710-2 can start transforming the panel for field update 108-BC ("Pnt2: B→C"), write pointer 710-3 can start transforming the panel for field update 108-CD ("Pnt3: C→D"), and write pointer 710-4 can start transforming the panel for field update 108-DE ("Pnt2: D→E"). Thus, there is a time 702 during the frame time period when all four write pointers 710-1 to 710-4 are being used and four different field updates 108 are occurring concurrently. In other words, at time 702, the field durations of five different image fields (A, B, C, D, and E) are shown as overlapping, and four different write pointers (write pointers 710-1 to 710-4) are used to handle the four concurrent field updates. Just before write pointer 710-4 finishes field update 108-DE, write pointer 710-1 is shown as being used to start transforming the panel for field update 108-EF ("Pnt1: E→F"), followed by write pointer 710-1 being used to transform the panel for field update 108-FN ("Pnt1: F→N"). Since the field durations of E and F are significantly longer, there is less overlap in these cases, and write pointer 710-1 (or any other write pointer) may be able to handle two transformations on its own, as shown.

[0069] As mentioned above, the PWM technique can operate using image fields of different lengths within an image field sequence. For example, longer-duration image fields can be used for the higher significant bits of a multi-bit luminance value, while shorter-duration image fields can be used for the lower significant bits of a multi-bit luminance value. This principle is further illustrated in FIG. 7. Specifically, the series of consecutive field updates is shown as being performed such that each image field 306 in the image field sequence is displayed for a unique field duration that is different from the other field durations of the other image fields 306 in the image field sequence. In other words, each of image fields A to F is shown as having a different width - some quite short or thin (e.g., C, B, D, etc.), while others are longer or wider (e.g., A, E, and F).

[0070] A display system according to the principles described herein can be used in a variety of different types of devices to achieve the various benefits and advantages described. For purposes of illustration, FIG. 8 shows an illustrative device 800 including a display system 200 configured to perform overlapping image field updates according to the principles described herein.

[0071] In this example, device 800 is illustrated as being implemented as an extended reality presentation device. More specifically, display system 200 is shown as being integrated into a pair of augmented reality glasses for this implementation. A MicroLED panel, such as may be implemented by display system 200, may be ideally suited for this type of device due to its extremely small size, high brightness, and power efficiency. However, it will be understood that a display system, such as display system 200, may not be limited to extended reality devices such as device 800. Instead, display system 200 may be used for display panels such as smartwatches, mobile devices (e.g., phones, tablets, etc.), laptop computer displays, televisions, appliances, or vehicles, and various other types of devices for specific implementations.

[0072] In almost any of these example devices, the display system implementation may interoperate with other electronic and / or computing resources. Accordingly, device 800 is shown with a processor 802 and a memory 804 implemented within device 800 with display system 200. It will be understood that processor 802 and memory 804 may be implemented as any suitable type of processor and storage resources. Additionally, various other components not shown may be further integrated into a device such as device 800. For example, an audio device for sound detection and playback, a camera device for capturing images, various types of sensors, input / output interfaces, and various other resources may be further included within a device that may be used for a specific implementation.

[0073] As already mentioned, the various methods and processes described herein may be at least partially implemented as instructions embodied in a non-transitory computer-readable medium and executable by one or more computing devices. Generally, a processor (e.g., a microprocessor) receives instructions from a non-transitory computer-readable medium (e.g., a memory, etc.) and executes those instructions, thereby performing one or more operations, such as the operations described herein. Such instructions may be stored and / or transmitted using any of a variety of known computer-readable media.

[0074] A computer-readable medium (also referred to as a processor-readable medium) includes any non-transitory medium that participates in providing data (e.g., instructions) that can be read by a computer (e.g., by a processor of the computer). This medium can take many forms, including but not limited to non-volatile media and / or volatile media. Non-volatile media can include, for example, optical discs or magnetic disks and other persistent memories. Volatile media can include, for example, dynamic random access memory (DRAM), which typically constitutes main memory. Common forms of computer-readable media include, for example, magnetic disks, hard disks, magnetic tapes, any other magnetic media, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), any other optical media, random access memory (RAM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EPROM), flash memory - EEPROM, any other memory chip or cartridge, or any other tangible medium from which a computer can read.

[0075] FIG. 9 shows an illustrative computing system 900 that can be used to implement various devices and / or systems described herein. For example, computing system 900 can include or implement (or partially implement) a display system (e.g., display system 200) or a device (e.g., device 800) described herein, any implementation thereof, any of its components, and / or other devices used therewith.

[0076] As shown in FIG. 9, computing system 900 can include a communication interface 902, a processor 904, a storage device 906, and an input / output (I / O) module 908 communicatively connected via a communication infrastructure 910. Although an illustrative computing system 900 is shown in FIG. 9, the components illustrated in FIG. 9 are not intended to be limiting. Additional or alternative components may be used in other embodiments. The components of computing system 900 shown in FIG. 9 will now be described in more detail.

[0077] Communication interface 902 can be configured to communicate with one or more computing devices. Examples of communication interface 902 include but are not limited to wired network interfaces (such as network interface cards), wireless network interfaces (such as wireless network interface cards), modems, audio / video connections, and any other suitable interfaces.

[0078] Processor 904 generally represents any type or form of processing unit capable of processing data or interpreting, executing, and / or directing the execution of one or more of the instructions, processes, and / or operations described herein. Processor 904 can direct the execution of operations in accordance with one or more application programs 912 or other computer-executable instructions such as those that can be stored in storage device 906 or another computer-readable medium.

[0079] The storage device 906 may include one or more data storage media, devices, or configurations, and may employ any type, form, and combination of data storage media and / or devices. For example, the storage device 906 may include, but is not limited to, hard disk drives, network disk drives, flash disk drives, magnetic disks, optical disks, RAM, dynamic RAM, other non-volatile and / or volatile data storage units, or combinations or sub-combinations thereof. Electronic data (including the data described herein) may be stored temporarily and / or permanently in the storage device 906. For example, data representing one or more executable applications 912 configured to direct the processor 904 to perform any of the operations described herein may be stored within the storage device 906. In some instances, the data may be arranged in one or more databases resident within the storage device 906.

[0080] The I / O module 908 may include one or more I / O modules configured to receive user input and provide user output. One or more I / O modules may be used to receive input for a single virtual experience. The I / O module 908 may include any hardware, firmware, software, or combination thereof that supports input and output capabilities. For example, the I / O module 908 may include hardware and / or software for capturing user input, including but not limited to keyboards or keypads, touch screen components (e.g., touch screen displays), receivers (e.g., RF or infrared receivers), motion sensors, and / or one or more input buttons.

[0081] The I / O module 908 may include one or more devices for presenting output to the user, including but not limited to a graphics engine, a display (e.g., a display screen), one or more output drivers (e.g., a display driver), one or more audio speakers, and one or more audio drivers. In certain embodiments, the I / O module 908 is configured to provide graphics data to the display for presentation to the user. The graphics data may represent one or more graphical user interfaces and / or any other graphical content useful for a particular implementation.

[0082] The following examples describe embodiments of overlapping image field updates in a display system in accordance with the principles described herein.

[0083] Example 1: A display system, comprising: a pixel array; and a frame controller configured to cause the pixel array to display an image frame by performing a series of consecutive field updates, the series of consecutive field updates including: a first field update, wherein a first write pointer circuit traces a first traversal across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and a second field update, wherein a second write pointer circuit traces a second traversal across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence; wherein the second update period of the second field update overlaps with the first update period of the first field update.

[0084] Example 2: The display system according to any one of the preceding examples, wherein: a minimum panel update period is defined as a time period during which the frame controller uses a single write pointer circuit to trace a traversal across the pixel array to update the pixel array; the first update period and the second update period are each at least twice the minimum panel update period; the second image field is displayed for a second field duration shorter than the minimum panel update period; and the third image field is displayed for a third field duration longer than the minimum panel update period, such that the sum of the second field duration and the third field duration is at least twice the minimum panel update period.

[0085] Example 3: The display system according to any one of the preceding examples, wherein: a minimum panel update period is defined as a time period during which the frame controller uses a single write pointer circuit to trace a traversal across the pixel array to update the pixel array; the series of consecutive field updates further includes a third field update, wherein a third write pointer circuit traces a third traversal across the pixel array during a third update period to update the pixel array from the third image field to a fourth image field in the image field sequence; the first update period, the second update period, and the third update period are each at least three times the minimum panel update period; the second image field is displayed for a second field duration shorter than the minimum panel update period; the third image field is displayed for a third field duration shorter than the minimum panel update period; and the fourth image field is displayed for a fourth field duration longer than the minimum panel update period, such that the sum of the second field duration, the third field duration, and the fourth field duration is at least three times the minimum panel update period.

[0086] Example 4: A display system as in any of the foregoing examples, wherein the series of consecutive field updates is performed such that each image field in the sequence of image fields is displayed for a unique field duration that is different from the other field durations of the other image fields in the sequence of image fields.

[0087] Example 5: A display system as in any of the foregoing examples, wherein the first image field in the sequence of image fields includes an array of binary values corresponding to the pixel array.

[0088] Example 6: A display system as in any of the foregoing examples, wherein the first image field in the sequence of image fields includes an array of multi-bit values corresponding to the pixel array.

[0089] Example 7: A display system as in any of the foregoing examples, wherein: the image frame is displayed by applying an array of multi-bit luminance values corresponding to the pixel array of the image frame to the pixel array using a binary pulse width modulation (PWM) technique; the first image field in the sequence of image fields includes a first array of binary values forming a first bit plane of the array of multi-bit luminance values; and the second image field in the sequence of image fields includes a second array of binary values forming a second bit plane of the array of multi-bit luminance values.

[0090] Example 8: A display system as in any of the foregoing examples, wherein: the pixel array is arranged in a plurality of columns on a display panel; and the first traversal and the second traversal across the pixel array are each performed in a sequential update order that starts from a top row of the plurality of columns and proceeds sequentially in consecutive columns until reaching a bottom row of the plurality of columns.

[0091] Example 9: A display system as in any of the foregoing examples, wherein: the pixel array is arranged in a plurality of columns on a display panel; and the first traversal and the second traversal across the pixel array are each performed in a non-sequential update order that is different from a sequential update order that starts from a top row of the plurality of columns and proceeds sequentially in consecutive columns until reaching a bottom row of the plurality of columns.

[0092] Example 10: A display system as in any of the foregoing examples, wherein: the pixel array is arranged on a display panel relative to a plurality of display units; during the first field update period, the first write pointer circuit starts from a first display unit to track the plurality of display units to update each of the plurality of display units; and the second update period of the second field update starts immediately after the first display unit is updated.

[0093] Example 11: A display system as in any of the foregoing examples, wherein the plurality of display units are implemented as a single row on the display panel.

[0094] Example 12: A display system as in any of the foregoing examples, wherein the plurality of display units are implemented as multiple row groups on the display panel.

[0095] Example 13: A display system as in any of the foregoing examples, wherein the plurality of display units are implemented as partial rows on the display panel.

[0096] Example 14: A method, comprising: causing a pixel array to display an image frame by a display system by performing a series of consecutive field updates, the series of consecutive field updates including: a first field update, wherein a first write pointer circuit tracks a first traversal across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and a second field update, wherein a second write pointer circuit tracks a second traversal across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence; wherein the second update period of the second field update overlaps with the first update period of the first field update.

[0097] Example 15: The method as in any one of the foregoing examples, wherein: a minimum panel update period is defined as a time period during which the display system uses a single write pointer circuit to track traversal across the pixel array to update the pixel array; the series of consecutive field updates further includes a third field update, wherein a third write pointer circuit tracks a third traversal across the pixel array during a third update period to update the pixel array from the third image field to a fourth image field in the image field sequence; the first update period, the second update period, and the third update period are each at least three times the minimum panel update period; the second image field is displayed for a second field duration shorter than the minimum panel update period; the third image field is displayed for a third field duration shorter than the minimum panel update period; and the fourth image field is displayed for a fourth field duration longer than the minimum panel update period, such that the sum of the second field duration, the third field duration, and the fourth field duration is at least three times the minimum panel update period.

[0098] Example 16: The method as in any one of the foregoing examples, wherein: the image frame is displayed by applying an array of multi-bit luminance values corresponding to the pixel array of the image frame to the pixel array by using a binary pulse width modulation (PWM) technique; the first image field in the image field sequence includes a first binary value array forming a first bit plane of the array of multi-bit luminance values; and the second image field in the image field sequence includes a second binary value array forming a second bit plane of the array of multi-bit luminance values.

[0099] Example 17: The method as in any one of the foregoing examples, wherein: the pixel array is arranged on a display panel relative to a plurality of display units, the plurality of display units being implemented by one of the following: a single row on the display panel, a plurality of row groups on the display panel, or a partial row on the display panel; during the first field update, the first write pointer circuit starts tracking the plurality of display units from a first display unit to update each of the plurality of display units; and the second update period of the second field update starts immediately after the first display unit is updated.

[0100] Example 18: A non-transitory computer-readable medium storing instructions that, when executed, cause a frame controller of a display system to perform a process, the process including: causing a pixel array to display an image frame by performing a series of consecutive field updates, the series of consecutive field updates including: a first field update in which a first write pointer circuit traces a first traversal across the pixel array during a first update period to update the pixel array from a first image field in an image field sequence to a second image field in the image field sequence, and a second field update in which a second write pointer circuit traces a second traversal across the pixel array during a second update period to update the pixel array from the second image field to a third image field in the image field sequence; wherein the second update period of the second field update overlaps the first update period of the first field update.

[0101] Example 19: The non-transitory computer-readable medium according to any one of the preceding examples, wherein: a minimum panel update period is defined as a time period in which the frame controller uses a single write pointer circuit to trace a traversal across the pixel array to update the pixel array; the series of consecutive field updates further includes a third field update in which a third write pointer circuit traces a third traversal across the pixel array during a third update period to update the pixel array from the third image field to a fourth image field in the image field sequence; the first update period, the second update period, and the third update period are each at least three times the minimum panel update period; the second image field is displayed for a second field duration shorter than the minimum panel update period; the third image field is displayed for a third field duration shorter than the minimum panel update period; and the fourth image field is displayed for a fourth field duration longer than the minimum panel update period, such that the sum of the second field duration, the third field duration, and the fourth field duration is at least three times the minimum panel update period.

[0102] Example 20: The non-transitory computer-readable medium according to any one of the preceding examples, wherein: the pixel array is arranged on a display panel relative to a plurality of display units, the plurality of display units being implemented by one of: a single row on the display panel, a plurality of row groups on the display panel, or a partial row on the display panel; during the first field update, the first write pointer circuit starts tracing the plurality of display units from a first display unit to update each of the plurality of display units; and the second update period of the second field update starts immediately after the first display unit is updated.

[0103] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include embodiments in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be special purpose or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0104] Numerous embodiments have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of this specification and the claims. Additionally, the logical flows depicted in the figures do not necessarily need to show a particular order or sequential order to achieve the desired result. Further, other steps can be provided, or certain steps can be deleted from the described flow, and other components can be added to or deleted from the described system. Accordingly, other embodiments are within the scope of the appended claims.

[0105] For purposes of describing embodiments, the specific structural and functional details disclosed herein are exemplary only. However, example embodiments can be embodied in many alternative forms and should not be construed as limited to the embodiments set forth herein.

[0106] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Without departing from the scope of the embodiments of this disclosure, a first element can be termed a second element, and similarly, a second element can be termed a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0107] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, unless the context clearly dictates otherwise, the singular forms "a / an" and "the" are intended to include the plural forms as well. It will be further understood that the terms "comprises," "comprising," "includes," "including" when used in this specification specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0108] It will be understood that when an element is referred to as being "coupled to", "connected to", or "responsive to" another element or "on another element", it can be directly coupled to, connected to, or responsive to another element or on another element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly coupled to", "directly connected to", or "directly responsive to" another element or "directly on another element", there are no intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0109] For ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the drawings. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation above and below. The device may be otherwise oriented (rotated 130 degrees or at other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0110] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which these concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0111] In addition to the above description, controls may be provided to the user that allow the user to make choices regarding whether and when the collection of user information (e.g., information about the user's social network, social actions or activities, occupation, user preferences, or the user's current location) can be achieved for the systems, programs, or features described herein, and also regarding whether content or communications are sent from the server to the user. Additionally, certain data may be processed in one or more ways before it is stored or used such that personally identifiable information is removed. For example, the user's identity may be processed such that the user's personally identifiable information cannot be determined, or the user's geographical location may be generalized, or location information (such as regarding a city, postal code, or state) may be obtained such that the user's specific location cannot be determined. Thus, the user can control what information about the user is collected, how that information is used, and what information is provided to the user.

[0112] Although certain features of the described embodiments are illustrated as described herein, many modifications, alternatives, variations, and equivalents may occur to those skilled in the art. Accordingly, it is to be understood that the appended claims are intended to cover such modifications and variations that fall within the scope of the embodiments. It is to be understood that it is presented by way of example only and not by way of limitation, and various changes in form and detail may be made. Any part of the devices and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described. Thus, the scope of the present disclosure is not limited to the specific combinations claimed below, but rather extends to cover any combination of the features or example embodiments described herein, regardless of whether that specific combination was specifically recited in the appended claims at that time.

[0113] 100: Embodiment 102: Frame sequence 104: Frame 105: Frame time 106-A: Image field 106-B: Image field 106-C: Image field 108: Field update 108-AB: Field update 108-BC: Field update 108-CD: Field update 108-PA: Field update 110-1: Write pointer 110-2: Write pointer 112: Vertical line 200: Display system 202: Frame controller 204: Memory 206: Image frame 208: Sequencer circuit 210: Write pointer circuit 212: Pixel driver circuit 214: Pixel 302: Serial instruction 304: Image field sequence 306: Image field 306-A: Image field 306-B: Image field 306-C: Image field 308: Write pointer vector 310-1: Write pointer 310-2: Write pointer 400: Method 402: Operation 404: Operation 406: Operation 408: Operation 500: Implementation 502: Image data 504: Specific time 600: Implementation 602: Update period 602-AB: Update period 602-BC: Update period 602-CD: Update period 602-PA: Update period 604: Field duration 604-A: Field duration 604-B: Field duration 604-C: Field duration 700: Implementation 710-1: Write pointer 1 710-2: Write pointer 2 710-3: Write pointer 3 710-4: Write pointer 4 800: Device 802: Processor 804: Memory 900: Computing system 902: Communication Interface 904: Processor 906: Storage Device 908 I / O: Module 910: Communication Infrastructure 912: Application T0: Event T1: Event T2: Event T3: Event T4: Event T5: Event T6: Event T7: Event

Claims

1. A display system comprising: One-pixel array; A frame controller is configured to cause the pixel array to display an image frame by performing a series of successive field updates, the series of successive field updates including: a first update, wherein a first circuit tracks a first traversal across one of the pixel arrays during a first period to update the pixel array from a first image field to a second image field of a sequence; a second update, wherein a second circuit tracks a second traversal across one of the pixel arrays during a second period to update the pixel array from the second image field to a third image field of the sequence; and a third update, wherein a third circuit tracks a third traversal across one of the pixel arrays during a third period to update the pixel array from the third image field to a fourth image field of the sequence; wherein the second period of the second update overlaps with the first period of the first update; and wherein the duration of one of the second image fields and the duration of one of the third image fields are each shorter than a minimum panel update period, the minimum panel update period being defined as the time period during which the frame controller uses a single circuit to track the traversal across the pixel array to update one of the pixel arrays.

2. The display system of claim 1, wherein the first cycle, the second cycle and the third cycle are each at least three times the minimum panel update cycle; and wherein one of the fourth image fields lasts longer than the minimum panel update cycle, such that the second image field, the third image field and the fourth image field are displayed together for at least three times the minimum panel update cycle.

3. A display system as requested in any of requests 1 to 2, wherein the series of consecutive field updates is performed such that each image field in the sequence is displayed for a unique field duration, the unique field duration being different from the other field durations of the other image fields in the sequence.

4. A display system as claimed in any one of claims 1 to 2, wherein the first image field in the sequence includes a binary value array corresponding to the pixel array.

5. A display system as claimed in any one of claims 1 to 2, wherein the first image field in the sequence includes a multi-bit value array corresponding to the pixel array.

6. A display system according to any one of claims 1 to 2, wherein the image frame is displayed by applying a multi-bit luminance value array to the pixel array using a binary pulse width modulation (PWM) technique, the multi-bit luminance value array corresponding to the pixel array of the image frame; wherein the first image field in the sequence includes a first binary value array forming a first bit plane of the multi-bit luminance value array; and wherein the second image field in the sequence includes a second binary value array forming a second bit plane of the multi-bit luminance value array.

7. A display system as claimed in any one of claims 1 to 2, wherein the pixel array is arranged in a plurality of columns on a display panel; and wherein the first traversal and the second traversal across the pixel array are each performed in a sequential update order, the sequential update order starting from one of the top columns of the plurality of columns and continuing sequentially in consecutive columns until one of the bottom columns of the plurality of columns is reached.

8. A display system as claimed in any one of claims 1 to 2, wherein the pixel array is arranged in a plurality of columns on a display panel; and wherein the first traversal and the second traversal across the pixel array are each performed in a non-sequential update order different from a sequential update order, the sequential update order starting from one of the top columns of the plurality of columns and continuing sequentially in consecutive columns until one of the bottom columns of the plurality of columns is reached.

9. A display system as claimed in any one of claims 1 to 2, wherein the pixel array is arranged on a display panel relative to a plurality of display units; wherein during the first update, the first circuit tracks the plurality of display units starting from a first display unit to update each of the plurality of display units; and wherein the second cycle of the second update begins immediately after the first display unit is updated.

10. The display system of claim 9, wherein the plurality of display units are implemented as a single column on the display panel.

11. The display system of claim 9, wherein the plurality of display units are implemented as a multi-column group on the display panel.

12. The display system of claim 9, wherein the plurality of display units are implemented as a portion of the display panel.

13. A method for performing overlapping image field updates, comprising: A display system causes a pixel array to display an image frame by performing a series of successive field updates, the series of successive field updates including: a first update, wherein a first circuit tracks a first traversal across one of the pixel arrays during a first period to update the pixel array from a first image field to a second image field of a sequence; a second update, wherein a second circuit tracks a second traversal across one of the pixel arrays during a second period to update the pixel array from the second image field to a third image field of the sequence; and a third update, wherein a third circuit tracks a third traversal across one of the pixel arrays during a third period to update the pixel array from the third image field to a fourth image field of the sequence; wherein the second period of the second update overlaps with the first period of the first update; and wherein the duration of one of the second image fields and the duration of one of the third image fields are each shorter than a minimum panel update period, the minimum panel update period being defined as the time period during which the display system uses a single circuit to track a traversal across the pixel array to update one of the pixel arrays.

14. The method of claim 13, wherein the first period, the second period and the third period are each at least three times the minimum panel update period; and wherein one of the fourth image fields lasts longer than the minimum panel update period, such that the second image field, the third image field and the fourth image field are displayed together for at least three times the minimum panel update period.

15. The method of any one of claims 13 to 14, wherein the image frame is displayed by applying a multi-bit luminance value array to the pixel array using a binary pulse width modulation (PWM) technique, the multi-bit luminance value array corresponding to the pixel array of the image frame; wherein the first image field in the sequence includes a first binary value array forming a first bit plane of the multi-bit luminance value array; and wherein the second image field in the sequence includes a second binary value array forming a second bit plane of the multi-bit luminance value array.

16. The method of any one of claims 13 to 14, wherein the pixel array is arranged on a display panel relative to a plurality of display units, the plurality of display units being implemented as a single column on the display panel, a group of multiple columns on the display panel, or a partial column on the display panel; wherein during the first update, the first circuitry tracks the plurality of display units starting from a first display unit to update each of the plurality of display units; and wherein the second cycle of the second update begins immediately after the first display unit is updated.

17. A non-transitory computer-readable medium storing instructions, which, when executed, cause a frame controller of a display system to perform a process comprising: A series of successive field updates causes a pixel array to display an image frame, the series of successive field updates including: a first update, wherein a first circuit tracks, during a first period, a first traversal across one of the pixel arrays to update the pixel array from a first image field to a sequence of second image fields; a second update, wherein a second circuit tracks, during a second period, a second traversal across one of the pixel arrays to update the pixel array from the second image field to a sequence of third image fields; and a third update, wherein a third circuit tracks, during a third period, a third traversal across one of the pixel arrays to update the pixel array from the third image field to a sequence of fourth image fields; wherein the second period of the second update overlaps with the first period of the first update; and wherein the duration of one of the second image fields and the duration of one of the third image fields are each shorter than a minimum panel update period, the minimum panel update period being defined as the time period during which the frame controller uses a single circuit to track traversals across the pixel array to update one of the pixel arrays.

18. The non-transitory computer-readable medium of claim 17, wherein the first period, the second period and the third period are each at least three times the minimum panel update period; and wherein one of the fourth image fields lasts longer than the minimum panel update period, such that the second image field, the third image field and the fourth image field are displayed together for at least three times the minimum panel update period.

19. A non-transitory computer-readable medium as claimed in any of claims 17 to 18, wherein the pixel array is arranged on a display panel relative to a plurality of display units, the plurality of display units being implemented as a single column on the display panel, a group of multiple columns on the display panel, or a partial column on the display panel; wherein during the first update, the first circuitry tracks the plurality of display units starting from a first display unit to update each of the plurality of display units; and wherein the second cycle of the second update begins immediately after the first display unit is updated.

Images