Memory circuits with keeper circuits and methods for operating the same

Abstract

This disclosure provides a memory circuit. The memory circuit includes a plurality of memory cells, a precharge circuit, and a holding circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and includes one or more first transistors having a first conductivity type. The holding circuit is coupled to the bit line and includes one or more second transistors having a second conductivity type.

Description

[Technical Field]

[0001] None. [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). The improvement in integrated density is mainly due to the continuous reduction in the size of the smallest feature, which allows more components to be integrated into a given area. [Summary of the Invention]

[0003] None.

Implementation Method

[0005] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatially relative terms (such as "below," "under," "lower part," "above," "upper part," "top," "bottom," and the like) may be used herein to describe the relationship between one element or feature illustrated in the figures and another element (or elements) or feature (or features). In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein may be interpreted similarly.

[0007] Static random-access memory (SRAM) is a type of semiconductor memory commonly used in computing applications requiring high-speed data access. For example, cache memory applications use SRAM to store frequently accessed data, such as data accessed by the central processing unit (CPU). The cell structure and architecture of SRAM enable high-speed data access. An SRAM cell contains a bistable flip-flop structure and a transistor that transmits voltage from bit lines to the flip-flop structure. A typical SRAM architecture includes one or more memory cell arrays and supporting circuitry. The memory cells in each SRAM array are arranged in columns and rows. Access to memory cells in a column is controlled by word lines. Data is passed into (write operations) and out of (read operations) memory cells via bit lines. Each row of memory cells corresponds to at least one bit line. The supporting circuitry includes address circuitry and driver circuitry for accessing each SRAM cell via word lines and bit lines to perform various SRAM operations.

[0008] Generally, SRAM cells are coupled to hold circuits. If a bit line needs to be charged to a certain voltage level, the hold circuit helps the bit line "hold" the charge to that voltage level. For example, when reading logic 0 from an SRAM cell, the hold circuit makes the voltage level on the bit line coupled to the SRAM cell substantially close to the voltage level corresponding to logic 0; and when reading logic 1 from an SRAM cell, the hold circuit makes the voltage level on the bit line coupled to the SRAM cell substantially close to the voltage level corresponding to logic 1. In existing SRAM technology, implementing such hold circuits typically requires a large number of p-type transistors, which may adversely cause unnecessary area overhead. Therefore, existing memory circuits with hold circuits are not entirely satisfactory in certain configurations.

[0009] This disclosure provides various embodiments of memory circuitry including a memory array having a plurality of memory cells, and further including a hold circuit and a precharge circuit coupled to each bit line of the memory array. The hold circuitry is used to hold a voltage level on the bit line when accessing (e.g., reading) a corresponding memory cell, and the precharge circuitry is used to precharge the voltage level on the bit line to a high logic state. In various embodiments, the hold circuitry may include one or more first transistors having a first conductivity type, and the precharge circuitry may include one or more second transistors having a second conductivity type. By employing opposite conductivity types, the area occupied by such peripheral circuitry (e.g., the hold circuitry and the precharge circuitry) can be better utilized, thereby reducing area occupancy.

[0010] Figure 1 illustrates a schematic diagram of a memory system (or circuit) 100 according to various embodiments. The memory system 100 is implemented in the form of an integrated circuit. As illustrated in the example of Figure 1, the memory system 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits, memory cells, memory bits, or bit cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 can be accessed via a plurality of access lines. For example, each memory cell 125 may be connected to at least one corresponding word line WL and a pair of corresponding bit lines BL. Each word line WL and bit line BL may contain any conductive material (e.g., metal). For example, each word line WL and bit line BL may be implemented as one or more metal lines. The memory controller 105 can write data to or read data from the memory array 120 based on electrical signals transmitted via word line WL and bit line BL. In other embodiments, the memory system 100 may include more, fewer, or different components than those shown in Figure 1, but these are still within the scope of this disclosure.

[0011] The memory array 120 is a hardware component for storing data. In various embodiments, the memory array 120 is embodied as a semiconductor memory device. The memory array 120 includes a plurality of storage circuits or memory cells 125. In some embodiments, the memory array 120 includes word lines WL0, WL1, ..., WLJ each extending along a first direction and bit lines BL0, BL1, ..., BLK each extending along a second direction. The word lines WL and bit lines BL may be conductive metal or conductive rails. Each memory cell 125 is connected to one or more corresponding word lines WL and one or more corresponding bit lines BL, and can be operated according to the voltage or current through the corresponding word line WL and the corresponding bit line. Each memory cell 125 may be a static random access memory (SRAM) cell. For example, as shown in Figure 2, the memory cell 125 may be implemented as an eight-transistor (8T) SRAM cell. However, it should be understood that memory cell 125 may be implemented by any of a variety of other memory configurations, but still within the scope of this disclosure. In some embodiments, memory array 120 includes additional lines (e.g., sensing lines, reference lines, reference control lines, power rails, etc.).

[0012] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line controller 112 and a word line controller 114, wherein the bit line controller may further include a precharge circuit 130 and a hold circuit 140. In one configuration, the word line controller 114 is a circuit that provides voltage or current signals via one or more word lines WL of the memory array 120. In one embodiment, the bit line controller 112 is a circuit that provides voltage or current signals via one or more bit lines BL of the memory array 120 and senses voltage or current from the memory array 120 via one or more bit lines BL. In various embodiments, the precharge circuit 130 may utilize a precharge signal to precharge bit line BL to a high logic state (e.g., power supply voltage VDD) during a phase when memory array 120 is not being read or written; and the holding circuit 140 may maintain the voltage level on bit line BL at its assumed voltage level when memory array 120 is being read by supplying a holding current.

[0013] The bit line controller 112 can be connected to the bit line BL of the memory array 120, and the word line controller 114 can be connected to the word line WL of the memory array 120. In one example, in order to write data to the memory cell 125, the word line controller 114 is used to apply a voltage or current signal (sometimes referred to as a WL signal) to the memory cell 125 via the corresponding word line WL connected to the memory cell 125, and the bit line controller 112 is used to apply a voltage or current signal corresponding to the data to be stored to the memory cell 125 via a pair of bit lines BL connected to the memory cell 125. In order to read data from the memory cell 125, the word line controller 114 is used to apply a WL signal to the memory cell 125 via the corresponding word line WL connected to the memory cell 125, and the bit line controller 112 is used to sense the voltage or current corresponding to the data stored by the memory cell 125 via the bit lines connected to the memory cell 125. In some embodiments, the memory controller 105 may include more, fewer, or different components than those shown in Figure 1, but these are still within the scope of this disclosure.

[0014] Figure 2 illustrates a schematic diagram of a memory cell 125 according to a different embodiment, which is implemented as a dual-port SRAM cell having eight transistors. As mentioned above, the memory cell 125 is not limited to this implementation and can be implemented in any other configuration, but is still within the scope of this disclosure.

[0015] In the illustrative example of Figure 2, memory cell 125 includes a pair of cross-coupled inverters 230 and 240, two gate-on transistors 210 and 220, and a read port 250. Inverters 230 and 240 are cross-coupled between nodes n1 and n2 to form a latch. Gate-on transistor 210 is coupled between write bit line wBL and node n1, and gate-on transistor 220 is coupled between complementary write bit line wBLB and node n2, wherein complementary write bit line wBLB is complementary to write bit line wBL. The gates of gate-on transistors 210 and 220 are coupled to the same write word line WWL. Furthermore, gate-on transistors 210 and 220 are n-type transistors. Read port 250 includes transistor 260 and gate-on transistor 270. Transistor 260 is an n-type transistor and is coupled between ground (GND) and the gate-on transistor 270. The gate of transistor 260 is coupled to node n1. The gate-on transistor 270 is coupled between the read bit line rBL and transistor 260. The gate of the gate-on transistor 270 is coupled to the read word line RWL.

[0016] Before accessing memory cell 125, the corresponding read bit line is precharged during precharge. When memory cell 125 is accessed, the corresponding read word line RWL is activated, and data is read by detecting the logic level at the read bit line rBL of the accessed memory cell 125. For example, when a low logic level (e.g., "0") is stored at node n1 of memory cell 125, the transistor 260 of memory cell 125 is turned off (e.g., as an open circuit). Therefore, when memory cell 125 is accessed, a high logic level (e.g., "1") is detected in the read bit line rBL, i.e., the high logic level is read. Conversely, if a high logic level is stored at memory cell 125, the transistor 260 of memory cell 125 will be turned on, and the read bit line rBL will be coupled to ground (GND) via transistor 260 and the gate transistor 270 of memory cell 125. Therefore, when memory cell 125 is accessed, a low logic level will be detected in the read bit line rBL, i.e., a low logic level will be read. In this embodiment, the data in the read bit line rBL is processed to reflect the data stored at the accessed memory cell 125, i.e., the data in the read bit line rBL is complementary to the data stored in the accessed memory cell 125. In some embodiments, the data in the read bit line rBL is the same as the data stored in the accessed memory cell 125.

[0017] Referring also to Figures 1 and 2, the precharge circuit 130 and the hold circuit 140 may be connected together to the read bit line rBL. In some embodiments, the read bit line rBL is coupled to a plurality of memory cells 125, one of which is selected for reading while the others are not selected. During a read operation on the selected memory cell, the precharge circuit 130 may be deactivated while the hold circuit 140 is activated to maintain a voltage level on the read bit line rBL. For example, the hold circuit 140 may provide a hold current Ikpr, the current level of which is between the off current Icell_off of the unselected memory cell and the on current Icell_on of the selected memory cell, to maintain a voltage level on the read bit line rBL substantially close to an assumed voltage level.

[0018] Figure 3 illustrates a schematic diagram of a portion of an example memory circuit according to various embodiments, the example memory circuit including read bit lines rBL coupled to selected memory cells and non-selected memory cells, and the precharge circuit 130 and the hold circuit 140 being implemented as transistors with different conductivity types. Figure 4 illustrates example waveform diagrams of multiple signals during operation of the memory circuit of Figure 3 according to some embodiments.

[0019] As shown in Figure 3, the pre-charge circuit 130 includes a p-type transistor, and the holding circuit 140 includes an n-type transistor. In some embodiments, the first source / drain terminal of the p-type transistor in the pre-charge circuit 130 is connected to the power supply voltage VDD, the second source / drain terminal of the p-type transistor is connected to the read bit line rBL, and the gate terminal of the p-type transistor is connected to the pre-charging (PCH) signal; while the first source / drain terminal of the n-type transistor in the holding circuit 140 is connected to the power supply voltage VDD, the second source / drain terminal of the n-type transistor is connected to the read bit line rBL, and the gate terminal of the n-type transistor is connected to the keep (KPE) signal. When reading the selected memory cell, the PCH signal can be pulled up to logic 1; when reading the selected memory cell, the KPE signal can be pulled up to logic 1. In some embodiments, the PCH signal and the KPE signal can be synchronized, i.e., pulled up / down simultaneously. Therefore, during the read operation, the precharge circuit 130 is deactivated, while the holding circuit 140 is activated to supply the holding current Ikpr, which can be better understood from the waveform diagram in Figure 4.

[0020] As illustrated in Figure 4, when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these reads. On the other hand, during the read, the holding circuit 140 can be activated by the KPE signal. Since the holding circuit 140 is activated during the read of logic 1 or logic 0 to supply the holding current Ikpr, it can be known that the voltage level on the read bit line rBL can be maintained close to the voltage level corresponding to logic 1 or the voltage level corresponding to logic 0.

[0021] In some embodiments, the read bit line rBL is coupled to the output inverter 150, which is composed of an n-type transistor 152 and a p-type transistor 154 connected in series. Specifically, the gate terminals of the n-type transistor 152 and the p-type transistor 154, which together serve as the input terminals of the inverter 150, are connected to the read bit line rBL, and the drain terminals of the n-type transistor 152 and the p-type transistor 154 together serve as the output terminals of the inverter 150. In some embodiments, the size of at least one of the n-type transistor 152 or the p-type transistor 154 may be larger than the size of any transistor forming the memory cell 125.

[0022] Figure 5 illustrates a schematic diagram of a portion of another example memory circuit according to various embodiments. This example memory circuit includes multiple read bit lines, such as read bit lines rBL[0], ..., rBL[N-1], each read bit line coupled to a separate number of memory cells, and implementing a corresponding holding circuit in a manner similar to Figure 3. For example, read bit line rBL[0] is coupled to holding circuit 140[0]; read bit line rBL[N-1] is coupled to holding circuit 140[N-1]; and so on. Each holding circuit 140[0] to 140[N-1] may include an n-type transistor whose gate terminals are connected to a separate control signal KPE. Depending on the selection of memory cells connected to the corresponding read bit line rBL, the holding circuit 140[0] to 140[N-1] may be selectively activated. Furthermore, the memory circuit of Figure 5 may further include a common holding circuit 510 coupled to different holding circuits 140[0] to 140[N-1]. In some embodiments, the common holding circuit 510 may include an n-type transistor that couples the power supply voltage VDD to one of the source / drain terminals of each holding circuit 140[0] to 140[N-1]. Additionally, the gate terminal of the common holding circuit 510 may be bonded to the power supply voltage VDD.

[0023] Figure 6 illustrates a schematic diagram of a portion of another example memory circuit according to various embodiments, this example memory circuit including a precharge circuit 130 and a holding circuit 140 connected to the read bit line rBL. Figure 7 illustrates example waveform diagrams of multiple signals during operation of the memory circuit of Figure 6 according to various embodiments.

[0024] As shown in Figure 6, in addition to the precharge circuit 130 and the holding circuit 140, the controller 610, delay circuit 620, decoder 630, and word line controller 640 are also coupled to the precharge circuit 130 and the holding circuit 140. Such components may be part of the memory controller 105 shown in Figure 1. In some embodiments, the controller 610 may provide an address (ADD) signal to the word line controller 640 to specify the selected memory cell 125. The ADD signal may be provided to the word line controller 640 by the decoder 630. Furthermore, the ADD signal may be provided to the precharge circuit 130 and the holding circuit 140 as the PCH signal and the KPE signal, respectively. In some embodiments, the KPE signal may be delayed after the PCH signal by the delay circuit 620.

[0025] As illustrated in Figure 7, when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these read periods. On the other hand, during the read period, the holding circuit 140 can be activated by the KPE signal, for example, with a slight delay. Since the holding circuit 140 is activated during the period of reading logic 1 or logic 0 by pulling up the KPE signal, it can be known that the voltage level on the read bit line rBL can be maintained close to the voltage level corresponding to logic 1 or the voltage level corresponding to logic 0. Furthermore, since the KPE signal is delayed after the PCH signal, it can be ensured that the signal transition on the read bit line rBL is not too fast (compared to the undelayed KPE signal (shown by dashed lines)).

[0026] Figure 8 illustrates a schematic diagram of a portion of another example memory circuit according to various embodiments, this example memory circuit including a precharge circuit 130 and a holding circuit 140 connected to the read bit line rBL. Figure 9 illustrates example waveform diagrams of multiple signals during operation of the memory circuit of Figure 8 according to various embodiments.

[0027] As shown in Figure 8, in addition to the precharge circuit 130 and the holding circuit 140, the controller 810, logic gate 820, inverter 830, decoder 840, word line controller 850, and several tracking units (with corresponding tracking bit lines and tracking word lines) are also coupled to the precharge circuit 130 and the holding circuit 140. The tracking units are generally used to simulate the behavior of the memory cell 125, and the tracking bit line (TRKBL) is used to simulate the RC behavior of the read bit line rBL. Such components may be part of the memory controller 105 shown in Figure 1. In some embodiments, the controller 810 may provide an address (ADD) signal to the word line controller 850 to specify the selected memory cell 125. The ADD signal may be provided to the word line controller 850 by the decoder 840. While providing the ADD signal, the controller 810 can provide an internal clock (ICLK) signal to start the tracking unit via the tracking word line. Based on the discharge state on the tracking bit line, a KPE signal can be provided to the holding circuit 140, and the precharge circuit 130 can receive the PCH signal based on the ICLK signal. In some embodiments, the KPE signal may be delayed after the signal on the tracking bit line.

[0028] As illustrated in Figure 9, when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these read periods. On the other hand, during the read period, the holding circuit 140 can be activated by the KPE signal, for example, with a slight delay. Since the holding circuit 140 is activated during the period of reading logic 1 or logic 0 by pulling up the KPE signal, it can be known that the voltage level on the read bit line rBL can be maintained close to the voltage level corresponding to logic 1 or the voltage level corresponding to logic 0. Furthermore, since the KPE signal is delayed after the voltage on the tracking bit line (TRKBL), any propagation delay on the read bit line (rBL) can be ensured to be tracked by the TRKBL. Additionally, signal transitions on the read bit line (rBL) will not change too rapidly.

[0029] Figure 10 illustrates a schematic diagram of a portion of another example memory circuit according to various embodiments. This example memory circuit includes read bit lines rBL coupled to selected memory cells and non-selected memory cells, and the precharge circuit 130 and the hold circuit 140 are implemented as transistors with different conductivity types. Figure 11 illustrates example waveform diagrams of multiple signals during operation of the memory circuit of Figure 10 according to various embodiments.

[0030] As shown in Figure 10, the pre-charge circuit 130 includes a p-type transistor, and the holding circuit 140 includes an n-type transistor. In some embodiments, the first source / drain terminal of the p-type transistor in the pre-charge circuit 130 is connected to the power supply voltage VDD, the second source / drain terminal of the p-type transistor is connected to the read bit line rBL, and the gate terminal of the p-type transistor is connected to the pre-charging (PCH) signal; while the first source / drain terminal (KPSRC) of the n-type transistor in the holding circuit 140 is coupled to the read bit line rBL via inverters 150 and 1010, the second source / drain terminal of the n-type transistor is connected to the read bit line rBL, and the gate terminal of the n-type transistor is connected to the keep (KPE) signal. In some embodiments, the PCH signal and the KPE signal can be synchronized with each other, i.e., simultaneously pulled up / pull down. Therefore, during a read operation, the precharge circuit 130 is deactivated, while the holding circuit 140 is activated to supply a holding current Ikpr. Because the source / drain terminal (KPSRC) is coupled to the read bit line rBL, the holding current Ikpr provided by the holding circuit 140 can be adjusted according to the logic state of the selected memory cell being read.

[0031] As illustrated in Figure 11, when reading logic 1 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up; when reading logic 0 from the selected memory cell, the signal applied to the read word line RWL is asserted (e.g., pulled up), and the PCH signal is also pulled up. Therefore, the precharge circuit 130 can be deactivated during these reads. On the other hand, during the read, the holding circuit 140 can be activated by the KPE signal. Since the holding circuit 140 is activated during the read of logic 1 or logic 0 to supply the holding current Ikpr, it can be known that the voltage level on the read bit line rBL can be maintained close to the voltage level corresponding to logic 1 or the voltage level corresponding to logic 0. Furthermore, when reading logic 0 from the memory cell, the voltage at the source / drain terminal (KPSRC) of the holding circuit 140 can be pulled down (e.g., from the dashed line), thereby reducing the holding current Ikpr. Therefore, the voltage level on the read bit line rBL can be kept at a low level.

[0032] Figure 12 illustrates a flowchart of an example method 1200 for forming a memory circuit according to various embodiments. For example, at least some operations (or steps) in method 1200 may be used to form the memory circuit described above. It should be noted that method 1200 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that additional operations may be provided before, during, and / or after method 1200 in Figure 12, and some other operations may only be briefly described herein.

[0033] Method 1200 begins with operation 1210. In operation 1210, a plurality of memory cells are formed along the main surface of the substrate. In some embodiments, the memory cells may each be formed with a separate number of transistors, for example, a 6T SRAM cell, an 8T SRAM cell, etc. The operation of forming such transistors along the main surface is generally referred to as part of a front-end-of-line (FEOL) network or process.

[0034] The substrate may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AllnAs, AlGaAs, GainAs, GainP, and / or GainAsP; or combinations thereof.

[0035] Method 1200 continues to operation 1220. In operation 1220, a plurality of metallization layers are formed above the main surface, wherein at least one metallization layer contains bit lines commonly coupled to memory cells formed along the main surface. The operation of forming such metallization layers above the main surface is generally referred to as part of a back-end-of-line (BEOL) network or process.

[0036] Method 1200 continues to operation 1230. In operation 1230, a pre-charge circuit is formed along the main surface of the substrate, wherein the pre-charge circuit includes a p-type transistor. In some embodiments, the pre-charge circuit is used to pre-charge the bit line to a high logic state. For example, the p-type transistor of the pre-charge circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail for providing a power supply voltage (e.g., power supply voltage VDD) and the bit line, respectively. In some embodiments, the p-type transistor of the pre-charge circuit may have a gate terminal for receiving a pre-charge (PCH) signal.

[0037] Method 1200 continues to operation 1240. In operation 1240, a holding circuit is formed along the main surface of the substrate, wherein the holding circuit includes an n-type transistor. In some embodiments, when at least one of the memory cells storing a high logic state corresponding to a first voltage level is read, the holding circuit is used to maintain a voltage level on the bit line substantially close to the first voltage level; and when at least one memory cell storing a low logic state corresponding to a second voltage level is read, the holding circuit is used to maintain a voltage level on the bit line substantially close to the second voltage level. For example, the n-type transistor of the holding circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail for providing a power supply voltage (e.g., power supply voltage VDD) and a bit line, respectively. In some embodiments, the n-type transistor of the holding circuit may have a gate terminal for receiving a keep (KPE) signal.

[0038] Figure 13 illustrates a flowchart of an example method 1300 for operating a memory circuit according to various embodiments. It should be noted that method 1300 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that additional operations may be provided before, during, and / or after method 1300 of Figure 13, and some other operations may only be briefly described herein.

[0039] Method 1300 begins with operation 1310. In operation 1310, bit lines coupled to a plurality of memory cells are precharged to a first logic state. In some embodiments, a precharge circuit of the memory circuit (e.g., precharge circuit 130) may precharge the bit lines to a high logic state, which corresponds to a power supply voltage (e.g., power supply voltage VDD). The precharge circuit may include a p-type transistor formed along a major surface of a substrate. For example, the p-type transistor of the precharge circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail for providing the power supply voltage and the bit lines, respectively. In some embodiments, the p-type transistor of the precharge circuit may have a gate terminal for receiving a pre-charge (PCH) signal.

[0040] Method 1300 continues to operation 1320. In operation 1320, when at least a first memory cell storing a first logic state corresponding to a first voltage level is read, the voltage level on the holding bit line is substantially close to the first voltage level; and when a second memory cell storing a second logic state corresponding to a second voltage level is read, the voltage level on the holding bit line is substantially close to the second voltage level. In some embodiments, a holding circuit (e.g., holding circuit 140) of the memory circuit can hold the voltage level on the bit line. The holding circuit may include an n-type transistor formed along a major surface of a substrate. For example, the n-type transistor of the holding circuit may have a first source / drain terminal and a second source / drain terminal coupled to a power rail for providing a power supply voltage (e.g., power supply voltage VDD) and the bit line, respectively. In some embodiments, the n-type transistor of the holding circuit may have a gate terminal for receiving a hold (KPE) signal.

[0041] In one embodiment of this disclosure, a memory circuit is provided. The memory circuit includes a plurality of memory cells, a precharge circuit, and a holding circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and includes one or more first transistors having a first conductivity type. The holding circuit is coupled to the bit line and includes one or more second transistors having a second conductivity type.

[0042] In another embodiment of this disclosure, a memory circuit is provided. The memory circuit includes a plurality of memory cells, a precharge circuit, and a holding circuit. The plurality of memory cells are commonly coupled to a bit line. The precharge circuit is coupled to the bit line and is used to precharge the bit line to a high logic state when none of the plurality of memory cells are read or written. The precharge circuit includes at least one p-type transistor. The holding circuit is coupled to the bit line and is used to: hold the voltage level on the bit line substantially close to the first voltage level when at least one of the plurality of memory cells storing a high logic state corresponding to a first voltage level is read; and hold the voltage level on the bit line substantially close to the second voltage level when at least one of the plurality of memory cells storing a low logic state corresponding to a second voltage level is read. The holding circuit includes at least one n-type transistor.

[0043] In another embodiment of this disclosure, an operating method is provided for a memory circuit. The operating method includes the following steps: precharging bit lines coupled to a plurality of memory cells to a first logic state by a precharge circuit; when at least one of the plurality of memory cells storing the first logic state corresponding to a first voltage level is read, holding the voltage level on the bit lines at a substantially close to the first voltage level by a holding circuit; and when a second of the plurality of memory cells storing a second logic state corresponding to a second voltage level is read, holding the voltage level on the bit lines at a substantially close to the second voltage level by a holding circuit.

[0044] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node relating to the subject semiconductor device. Based on a particular technology node, the term “about” may indicate the value of a given quantity that varies from, for example, 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0045] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can at any time design or modify other programs and structures based on the content of this disclosure to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation. Figure 1 illustrates a block diagram of a memory circuit according to some embodiments; Figure 2 illustrates a schematic diagram of a portion of the memory circuit of Figure 1 according to some embodiments; Figure 3 illustrates another schematic diagram of a portion of the memory circuit of Figure 1 according to some embodiments; Figure 4 illustrates waveform diagrams of various signals when operating the memory circuit of Figure 3 according to some embodiments; Figure 5 illustrates yet another schematic diagram of a portion of the memory circuit of Figure 1 according to some embodiments; Figure 6 illustrates yet another schematic diagram of a portion of the memory circuit of Figure 1 according to some embodiments; Figure 7 illustrates waveform diagrams of various signals when operating the memory circuit of Figure 6 according to some embodiments; Figure 8 illustrates yet another schematic diagram of a portion of the memory circuit of Figure 1 according to some embodiments; Figure 9 illustrates waveform diagrams of various signals when operating the memory circuit of Figure 8 according to some embodiments; Figure 10 illustrates yet another schematic diagram of a portion of the memory circuit of Figure 1 according to some embodiments. Figure 11 illustrates waveforms of various signals during operation of the memory circuit of Figure 10 according to some embodiments; Figure 12 illustrates a flowchart of a method for forming a memory circuit according to some embodiments; and Figure 13 illustrates a flowchart of an operation method of the memory circuit according to some embodiments. [Biomaterial Storage]

[0047] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A memory circuit comprising: a plurality of memory cells commonly coupled to a bit line; a precharge circuit coupled to the bit line and including one or more first transistors having a first conductivity type, wherein the one or more first transistors include a p-type transistor that couples a power supply voltage to the bit line; and a holding circuit coupled to the bit line and including one or more second transistors having a second conductivity type, wherein the one or more second transistors include an n-type transistor that couples the power supply voltage to the bit line.

2. The memory circuit as claimed in claim 1, wherein the precharge circuit is configured to precharge the bit line to a high logic state when none of the plurality of memory cells have been read or written.

3. The memory circuit as claimed in claim 1, wherein the holding circuit is configured to: hold a voltage level on the bit line substantially close to the first voltage level when at least one of the plurality of memory cells storing a high logic state corresponding to a first voltage level is read; and hold the voltage level on the bit line substantially close to the second voltage level when at least another of the plurality of memory cells storing a low logic state corresponding to a second voltage level is read.

4. The memory circuit as claimed in claim 1, wherein the drain terminal of the n-type transistor of the holding circuit is connected to a signal on the bit line.

5. The memory circuit as claimed in claim 4, wherein a gate terminal of the p-type transistor in the precharge circuit is connected to a precharge signal, and a gate terminal of the n-type transistor in the holding circuit is connected to a holding signal.

6. The memory circuit as claimed in claim 1, further comprising: an inverter coupled to the bit line and including a third transistor and a fourth transistor connected in series; wherein a dimension of the third transistor or the fourth transistor is larger than a dimension of any one of the one or more second transistors.

7. The memory circuit as claimed in claim 5, further comprising: a plurality of tracking units connected to a tracking bit line, the plurality of tracking units simulating the plurality of memory cells; wherein the hold signal is delayed after a signal on the tracking bit line.

8. The memory circuit as claimed in claim 4, wherein a drain terminal of the n-type transistor of the holding circuit is connected to a signal on the bit line.

9. A memory circuit comprising: a plurality of memory cells commonly coupled to a bit line; a precharge circuit coupled to the bit line for precharging the bit line to a high logic state when none of the plurality of memory cells are read or written, wherein the precharge circuit includes at least one p-type transistor; and a holding circuit coupled to the bit line for: holding a voltage level on the bit line substantially close to the first voltage level when at least one of the plurality of memory cells storing a high logic state corresponding to a first voltage level is read; and holding the voltage level on the bit line substantially close to the second voltage level when at least one of the plurality of memory cells storing a low logic state corresponding to a second voltage level is read, wherein the holding circuit includes at least one n-type transistor.

10. An operating method for a memory circuit, comprising the steps of: precharging a bit line coupled to a plurality of memory cells to a first logic state via a precharge circuit; when at least one of the plurality of memory cells storing the first logic state corresponding to a first voltage level is read, holding a voltage level on the bit line at substantially close to the first voltage level via a holding circuit; and when a second of the plurality of memory cells storing a second logic state corresponding to a second voltage level is read, holding the voltage level on the bit line at substantially close to the second voltage level via the holding circuit.

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