Translation barrier instruction

Abstract

An apparatus may include a processor circuit that can be configured to execute a translation barrier instruction. To execute the translation barrier instruction, the processor circuit may be configured to prevent address translation of instructions occurring sequentially after the translation barrier instruction until the translation barrier instruction has been completed. The processor circuit may be further configured to complete the translation barrier instruction based on the completion of all address translations of instructions occurring sequentially before the translation barrier instruction.

Description

Translation barrier instructions Embodiments described herein relate to computer systems, including system-on-a-chip (SOC) and multi-die packages. More specifically, the disclosed embodiments are directed to methods for synchronizing address translation in out-of-order processors. Computer systems, such as system-on-a-chip (SOC), typically include one or more processors that serve as the system's central processing unit (CPU), along with various other components, such as memory controllers and peripherals. Some processors execute instructions sequentially, where the first instruction completes before the next instruction is allowed to complete. Certain long-lead operations, such as memory fetches, can require multiple clock cycles to complete, causing the in-order processor to stall while the instructions following the memory fetch complete. These processor stalls can negatively impact processor performance. To mitigate processor stalls, some processors are configured to allow out-of-order processing, allowing subsequent instructions to execute if they do not depend on the results of the long preceding instruction. Out-of-order processing allows the processor to avoid idleness while waiting for long-lead instructions to complete, thereby improving efficiency. In addition to out-of-order processing, some processors may use virtual-to-physical address mapping, for example, to support the relocation of program code into available memory space. For example, applications can be written using virtual address references to support a wide variety of computing devices. For a given device, such an application can be stored in a first available portion of non-volatile memory space, then copied to and executed from a different portion of volatile memory space. Virtual-to-physical address mapping can be performed when code is stored or copied. When the code is executed, virtual addresses referenced in the code are translated into physical addresses corresponding to the portion of the address space where the code and associated information are currently stored. none Cross-reference to related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 616,008, filed on December 29, 2023, entitled “Translation Barrier Instruction,” the disclosure of which is incorporated herein by reference in its entirety. Several problems may arise during the operation of a computer system using out-of-order processing. For example, due to out-of-order processing, two or more program threads may become out of sync with the program order, with one thread fetching multiple instructions before another thread. At some point, the thread that is executing ahead may become dependent on events that occur in the thread that is lagging behind. Such events may include address translations, memory permission determinations, and modifications to system registers. With respect to address translation, the activation of different applications may result in the generation of new address translation tables. In addition, the currently active application may branch to a program that was not previously loaded into volatile execution memory, resulting in different program code being loaded and causing additions to the existing address translation table. Therefore, instructions executed out of order may need to be synchronized with changes to the address translation table to prevent, for example, an earlier instruction from incorrectly using an address translation that was not valid until after the earlier instruction was executed. To synchronize operations within the processor to a common point in program order, out-of-order processors may utilize barrier instructions. Barrier instructions can be used to stall a program thread that is executing ahead of a slower program thread, allowing the slower thread to "catch up" and bringing all associated program threads to a common point in program order. Mechanisms that can be employed by barrier instructions include, for example, preventing speculative operations, flushing the instruction pipeline, re-fetching instructions, and the like. However, using this type of barrier instruction mechanism can negatively impact performance. Speculative operations are often used to pre-fetch instructions and data to reduce latency associated with memory accesses. Clearing the execution pipeline of instructions that have already been fetched, decoded, and ready to issue results in all the processing used to fetch and decode these instructions being wasted. New fetch and decode operations are then performed to refill the cleared pipeline. Therefore, a new barrier instruction is contemplated for address translation, avoiding pipeline flushes and allowing some speculative operations to proceed. Such a barrier instruction may also be applied to changes to system registers associated with the translation lookaside buffer (TLB). Such a barrier instruction may prevent the barrier from completing until all program-ordered translations preceding the barrier have completed. Translations occurring after the barrier in program order cannot be executed until the contemplated barrier instruction completes. In some embodiments, such a barrier instruction may also be applied to changes to registers that affect address translations or permissions in the TLB. For example, the barrier instruction may not complete until all program-ordered changes to these translation registers preceding the barrier have completed. Furthermore, program-ordered changes to these registers after the barrier may be prevented until the barrier instruction completes. Examples of such translation registers include registers that store the base address of tables (such as paging tables or permission tables), or registers that control other aspects of translations and / or permissions. In other embodiments, the barrier instruction may be applied to all system registers, rather than simply to system registers that control address translation or permissions. As used herein, a "completed" instruction refers to an instruction that has progressed through the instruction pipeline to the point where the instruction is ready to be retired. In various embodiments, it is contemplated that completion may refer to the point at which an instruction is retired or the point at which an instruction waits for an earlier instruction to complete in order to be retired. Disclosed embodiments address systems and methods for implementing translation barrier instructions. For example, the disclosed embodiments include processor circuitry configured to execute a translation barrier instruction. The processor circuitry may prevent address translations for instructions that occur after the translation barrier instruction in program order until after the translation barrier instruction completes. The processor circuitry may also complete the translation barrier instruction based on completing all address translations for instructions that occur before the translation barrier instruction in program order. FIG1 illustrates a block diagram of an embodiment of a processor circuit, such as may be included on a system-on-chip (SOC). As shown, processor circuit 100 includes decode circuitry 140 coupled to an instruction cache (ICache) 120 and address circuitry 110. Instruction cache 120 is shown with instructions (instr) 145a-145d and a translation barrier instruction 142. Address circuitry 110 includes translation circuitry 112, access permission circuitry 114, and registers 116. Processor circuit 100 may be included in whole or in part in a computing system, such as a desktop or laptop computer, a smartphone, a tablet, a wearable smart device, or the like. In some embodiments, processor circuit 100 is included in a single IC, such as a SOC, or in a multi-die chiplet system. As shown, processor circuit 100 may include one or more execution pipelines for processing instructions stored in instruction cache 120. In other embodiments, processor circuit 100 may include two or more cores included in the same processor complex. Processor circuit 100 may be configured to implement any suitable instruction set architecture (ISA), such as ARM ™ 、PowerPC ® 、Blackfin ® , or x86 ISA, or a combination thereof. As shown, processor circuit 100 is further configured to implement at least one additional instruction, including a translation barrier instruction (e.g., translation barrier instruction 142). Processor circuit 100 may fetch program instructions from one or more coupled memory circuits and store the fetched instructions, including instruction 145 and translation barrier instruction 142, in instruction cache 120. In terms of program order, earlier instructions are depicted at the top of the five illustrated instructions, and later instructions are depicted at the bottom. However, the actual location within instruction cache 120 may be based on the cache line corresponding to the fetch address used to retrieve the instruction. As shown, decode circuitry 140 is configured to receive and decode instructions from instruction cache 120. As part of the instruction decoding operation, decode circuitry 140 may also be configured to identify operands included in the received instruction, such as instruction 145. In some examples, the operand may be a pointer or address indicating a memory location where operand data is stored. In such examples, decode circuitry 140 may be configured to determine a virtual address for the operand data and use address circuitry 110 to determine a physical address corresponding to the virtual address. As shown, the address circuitry 110 is configured to receive translation requests for specific virtual addresses. The address circuitry 110 may include circuitry associated with converting virtual addresses into physical addresses. For example, the translation circuitry 112 may include one or more address translation tables and one or more translation lookup buffers. The access permission circuitry 114 may include various circuits for determining whether the current processing thread has permission to access a specific address or address range. The registers 116 may include registers associated with the translation tables, such as a base address register, and registers associated with defining specific address ranges and their associated access permissions. In various embodiments, the circuitry of the address circuitry 110 may be included in a single circuit block or may be distributed throughout the processor circuitry 100, such as within a plurality of memory management units. In some embodiments, transaction requests may be associated with data reads and writes generated in response to the execution of code in the processor circuitry 100. The transaction requests may be included in an instruction fetch or prefetch operation. Program code can use virtual addresses (rather than explicit physical addresses) to access memory locations in a computer system. This virtual addressing allows the code to be executed by a variety of hardware systems that may have different physical memory mappings. Virtual addressing also allows the code to be executed alongside various other programs without requiring the code to access similar addresses as other programs. Decode circuitry 140 retrieves instructions from instruction cache 120 and identifies the type of instruction and initiates decoding of any included operands, including the source and / or destination addresses of data consumed and / or produced by the instruction. As illustrated, decode circuitry 140 retrieves instructions 145a-145c and initiates translation of the respective addresses associated with these instructions. As depicted, address circuitry 110 has initiated address translations 147a-147c associated with instructions 145a-145c, respectively. As shown, processor circuit 100 is configured to execute translation barrier instruction 142. For example, decode circuit 140 retrieves translation barrier instruction 142 from instruction cache 120, then decodes and issues the barrier instruction. Processor circuit 100 is configured to, upon issuance of translation barrier instruction 142, prevent address translation of instructions occurring after translation barrier instruction 142 in program order until after translation barrier instruction 142 completes. In this example, decode circuit 140 may retrieve and decode instruction 145d after translation barrier instruction 142 has been issued but before translation barrier instruction 142 has completed. Upon issuance of translation barrier instruction 142, if instruction 145d requires address translation, address translation is not performed while execution of translation barrier instruction 142 is in effect. However, if instruction 145d does not require address translation, instruction 145d may be issued and executed. As shown, processor circuit 100 may also be configured to complete translation barrier instruction 142 upon completion of all address translations for instructions that occurred before translation barrier instruction 142 in program order. Address translations 147a and 147b associated with instructions 145a and 145b may be allowed to proceed because these instructions precede translation barrier instruction 142 in program order. In some embodiments, decode circuitry 140 may actively monitor for such incomplete translation operations, for example, by polling status associated with the in-progress translation operations. In other embodiments, decode circuitry 140 may receive an indication from address circuitry 110 for each in-progress address translation 147a and 147b when the respective translation result is available. Based at least in part on the determination that outstanding address translations 147a and 147b are complete, processor circuit 100 may be further configured to retire translation barrier instruction 142. Address translation by processor circuit 100 is now synchronized with translation barrier instruction 142 and may proceed with address translation of later instructions, such as instructions 145c and 145d. As shown, address translation 147c may be in progress when translation barrier instruction 142 is issued. Because instruction 145c is later than translation barrier instruction 142, instruction 145c is not allowed to proceed. In some embodiments, address translation 147c may be stalled in address circuitry 110, or may be allowed to proceed, but the result of the translation may be prevented from being used and / or cached. In other embodiments, address translation 147c may be canceled, and a new address translation request for instruction 145c issued from decode circuitry 140 after translation barrier instruction 142 is completed. In some embodiments, processor circuit 100 may further include a set of one or more system registers associated with TLB 105. The set of system registers may include base addresses for tables (e.g., paging tables or permission tables), or other registers that control address translation and / or permissions to access secure addresses. Some of the registers in the set may be included in address circuitry 110 and / or other circuitry within processor circuit 100. In addition to preventing address translation for instructions that are later than translation barrier instruction 142, processor circuit 100 also prevents changes to the set of system registers from occurring in program order after translation barrier instruction 142 until translation barrier instruction 142 completes. For example, instruction 140d may modify a value in one of the set of system registers. Processor circuit 100 may prevent instruction 140d from modifying the associated system register in one or more of a variety of ways. In some embodiments, decode circuitry 140 may not issue instruction 140d while execution of translation barrier instruction 142 is active. In other embodiments, instruction 140d may be allowed to issue and execute, but the new value may be buffered until translation barrier instruction 142 completes. After translation barrier instruction 142 completes, the buffered value may be moved to an associated system register. Processor circuit 100 may further be configured to complete translation barrier instruction 142 based on the completion of all changes to the set of system registers that occurred in program order before translation barrier instruction 142. For example, instruction 145b may include an instruction to store a new base address to a register in a translation table. If instruction 145b has not yet completed when translation barrier instruction 142 is issued, processor circuit 100 allows the storage of the new base address to be performed before completing translation barrier instruction 142. Generally, processor circuitry 100 does not stall execution of instructions, but rather prevents later address translations from proceeding. However, in some cases, processor circuitry 100 may be further configured to stall one or more instructions to allow sufficient time for earlier address translations to complete. For example, where later instructions depend on blocked address translations that are prevented from proceeding until translation barrier instruction 142 completes, the decode circuitry may stall instructions issued later than translation barrier instruction 142. In some embodiments, processor circuit 100 may be configured to issue speculative translation requests for instructions that occur after translation barrier instruction 142 in program order before issuing translation barrier instruction 142. For example, processor circuit 100 may issue a speculative address translation request associated with instruction 145d that occurs after translation barrier instruction 142 in program order to address circuitry 110. Instruction 145d may, for example, be a conditional branch instruction for which branch prediction circuitry in processor circuit 100 predicts a taken branch, thereby triggering a prefetch operation for the virtual address indicated by instruction 145d. The speculative translation request may be generated to determine the physical address that maps to the virtual address to be used in the prefetch operation. After issuing translation barrier instruction 142 (but before completion), processor circuit 100 may be configured to prevent the results of the speculative translation request from being cached in the associated TLB. Because instruction 145d follows translation barrier instruction 142 in program order, processor circuit 100 may be configured to block translation results for speculative branch addresses from being stored and thus available for prefetch operations. As described above, the processor circuit 100 may further include a set of one or more system registers related to the operation of the processor circuit 100. Such registers may include system configuration registers, which, for example, affect system permissions and / or security permissions for some or all processing circuits in the IC that includes the processor circuit 100. In some embodiments, the set of system registers may include all system registers. In other embodiments, the set of system registers may include all registers that affect address translation. In another embodiment, the set of system registers may include all registers that affect address permissions. In some embodiments, the set of system registers may include all registers that affect address translation and / or address permissions. One such system register may include a base address register that stores a base address of a paging table or a permission table. Note that in various embodiments, processor circuit 100 may be configured to determine whether all incomplete translation operations and changes to the set of system registers that occurred before translation barrier instruction 142 are complete before retiring translation barrier instruction 142. Furthermore, under some conditions, processor circuit 100 may stall translation operations and system register changes that occurred after translation barrier instruction 142. Furthermore, processor circuit 100 may prevent caching of speculative translations that were initiated before translation barrier instruction 142 was issued but that occurred after the translation barrier instruction. The translation barrier instruction 142 can be used, for example, to synchronize translation operations with the point in the program where the translation barrier instruction 142 is placed. The synchronization of the translation operations can be performed before modifying the address translation table. Therefore, based at least in part on the determination that the incomplete translation operation is complete, the processor circuit 100 can be further configured to determine that the condition for the translation barrier instruction 142 has been met. After determining that the condition has been met, the processor circuit 100 can perform one or more operations to modify the translation table. For example, instructions 145c and / or 145d can change the base address and / or translation permissions in the address translation table, which in turn can change the way virtual addresses are mapped to physical addresses in subsequent translation operations. This synchronization can prevent the address translation table from being incorrectly accessed by an earlier address translation operation after the address translation table is modified by an instruction that occurs after the later address translation in program order. Similarly, later address translations that execute before the address translation table is modified but occur later in program order can be prevented from incorrectly accessing pre-modified information in the address translation table. It should be noted that the processor circuit 100 shown in FIG1 is merely an example. The diagram in FIG1 has been simplified to highlight features of the present disclosure. Various embodiments may include circuit elements of different configurations. For example, three elements of the processor circuit 100 are shown. In other embodiments, other circuit elements may be included, such as one or more address translation tables and translation lookaside buffers, one or more execution units, load / store units, data caches, branch prediction circuits, and the like. In addition, the instruction cache 120 in the illustrated processor circuit has five instructions. In other embodiments, the instruction cache may include any appropriate number of instructions. In various embodiments, the processor circuit 100 may be implemented using any appropriate combination of sequential logic circuits and combinational logic circuits. Additionally, registers and / or memory circuits (such as SRAM) may be used in such circuits to temporarily store information such as instructions, data, address values, and the like. Figure 1 illustrates the use of translation barrier instructions to synchronize address translation operations in a processor circuit. The processor circuit can be implemented in a variety of ways. Figure 2 illustrates another example of a processor circuit. FIG2 shows a block diagram of an embodiment of processor circuitry for implementing translation barrier instructions. In some embodiments, processor circuitry 200 may correspond to processor circuitry 100 in FIG1 . Processor circuitry 200 includes fetch circuitry 210, instruction cache (ICache) circuitry 220, an instruction memory management unit (IMMU) 230, decode circuitry 240, an execution unit 250, a data cache (DCache) circuitry 260, a data memory management unit (DMMU) 270, and a memory management unit (MMU) 280. IMMU 230 includes a translation lookaside buffer (TLB) 234 and registers 236. Execution unit 250 includes a plurality of execution circuits, including an integer unit 252, a floating point unit 254, and a load / store unit 256. DMMU 270 includes a translation lookaside buffer (TLB) 274 and a register 276. Similarly, MMU 280 includes a translation lookaside buffer (TLB) 284 and a register 286. In some embodiments, fetch circuit 210, ICache circuit 220, decode circuit 240, execution unit 250, and DCache circuit 260 may be referred to as an instruction pipeline circuit of processor circuit 200. As shown, the fetch circuit 210 can be configured to issue fetch requests to retrieve a group of one or more instructions based on the current program counter value and the presence of any flow control instructions (e.g., branch instructions, call instructions, return instructions, and the like). These fetch requests are transmitted to the ICache circuit 220 and the IMMU 230. If the fetch group is already cached in the ICache circuit 220, the IMMU 230 can respond to the fetch request without doing anything. Otherwise, the IMMU 230 can issue one or more memory transactions to retrieve the instructions for the requested fetch group. These memory transactions can utilize address translation to convert the virtual addresses used by the fetch circuit 210 into physical addresses that can be used by the IMMU 230 to generate one or more memory transactions. The IMMU 230 is configured to use the TLB 234 to cache the most recently completed address translations. As shown, memory transactions issued by IMMU 230 may be passed to MMU 280 for fulfillment. In some cases, TLB 234 may not include an entry corresponding to the requested fetch address. In such cases, a virtual address may be used in the memory transaction passed to MMU 280. Upon receiving a memory transaction without an address translation, MMU 280 may be configured to access TLB 284 to determine whether an entry corresponding to the virtual address included in the received memory transaction exists. If so, this entry may be used to determine the physical address of the memory transaction. Otherwise, MMU 280 may access a translation table to determine the physical address. The result of the translation table access may be stored in TLB 284 for subsequent use. After the physical address has been determined, MMU 280 may forward the memory transaction to one or more memory circuits (e.g., a higher-level cache, system memory circuits, non-volatile storage circuits, and the like) to fulfill the memory transaction. As shown, decode circuitry 240 is configured to receive and decode instructions from ICache circuitry 220. As part of the instruction decoding operation, decode circuitry 240 may be further configured to identify operands included in the received instruction. In some examples, the operand may be a pointer or address indicating a memory location where operand data is stored. In such examples, decode circuitry 240 may be configured to determine the virtual address of the operand and issue a memory request to DCache circuitry 260 to determine whether the operand at the virtual address is cached. If the virtual address does not hit in DCache circuitry 260, DMMU 270 may issue one or more memory transactions to MMU 280. In a manner similar to IMMU 230, DMMU 270 may access TLB 274 to determine whether the virtual address of the desired operand has an entry corresponding to the physical address translation. If so, the physical address may be used in the memory transaction sent to MMU 280. If the virtual address misses in TLB 274, MMU 280 may access TLB 284 to find the physical address translation. As described above, another miss may cause the translation table to be accessed to receive the virtual-to-physical mapping of the operand address. As shown, processor circuit 200 may configure TLBs 234, 274, and 284 for a first address space. For example, the first address space may correspond to a specific application code assigned to processor circuit 200 for execution. Execution of the specific application code may include allocating a specific amount of system memory to store instructions and data associated with the specific application code. Prior to startup, the code for the specific application may be stored in non-volatile storage memory (e.g., flash memory or a hard drive). After allocating the first address space for the specific application, the stored code and associated data (or portions thereof) may then be copied to the first address space based on virtual-to-physical address translations included in a translation table. As execution of the specific application progresses, the translation table is referenced to perform translations of virtual addresses used in the code for the specific application into physical addresses in the first address space to which the virtual addresses have been mapped. Such translations may then be cached into one or more of TLBs 234, 274, and 284 to reduce the time to perform subsequent translations of the virtual addresses of these previous translations. For example, processor circuit 200 using decode circuit 240 may be configured to execute translation barrier instruction 242. For example, TLBs 234, 274, and 284 may be smaller than the translation table. As execution of a particular application progresses to different portions of the program code, translations of previously untranslated virtual addresses may result. If an entry in one of TLBs 234, 274, and 284 is not available to cache the most recent translation result, an older entry may be selected, and the currently stored translation may be evicted and replaced with the newer translation. To update the selected TLB entry, processor circuit 200 receives and executes translation barrier instruction 242 before making any changes to the selected TLB entry. Based at least in part on the execution of translation barrier instruction 242, processor circuit 200 may block translation operations that are pending in processor circuit 200 and occur in program order after translation barrier instruction 242. Processor circuit 200 may also be configured to determine the progress of incomplete translation operations that occur in program order before translation barrier instruction 242 in processor circuit 200. However, instructions that do not depend on translation operations may continue, including instructions that have been issued later than translation barrier instruction 242. Based at least in part on determining that a translation has been received for an incomplete translation operation, processor circuit 200 may continue to execute one or more instructions capable of modifying the configuration of TLBs 234, 274, and 284 for a second address space that is different from the first address space. For example, one or more TLB entries may be evicted and replaced with more recent translation results. As shown, registers 236, 276, and 286 are associated with the configurations of TLBs 234, 274, and 284, respectively. Processor circuit 200 may further be configured to, based at least in part on the execution of translation barrier instruction 242, block changes to one or more of registers 236, 276, and 286 that occurred after translation barrier instruction 242 in program order. Furthermore, processor circuit 200 may be configured to determine whether pending changes to one or more of registers 236, 276, and 286 that occurred before translation barrier instruction 242 in program order are complete. Based at least in part on the determination that the pending changes to one or more of registers 236, 276, and 286 are complete, processor circuit 200 may continue to execute one or more instructions that can modify the configurations of TLBs 234, 274, and 284. As shown, processor circuit 200 may be further configured to, before executing translation barrier instruction 242, issue speculative translation requests for instructions that occur after translation barrier instruction 242 in program order. After executing translation barrier instruction 242, processor circuit 200 may be configured to prevent the results of speculative translation requests from being cached in any of TLBs 234, 274, and 284. After completion of translation barrier instruction 242, if the translation remains valid, e.g., the translation of the virtual address has not changed between the start and end of execution of translation barrier instruction 242, the results of the speculative translation requests may be cached. However, if the address space including the virtual address is updated during or immediately after execution of translation barrier instruction 242, processor circuit 200 may discard the results of the speculative translation requests and reissue the request. Processor circuit 200 may also include one or more system registers related to the operation of processor circuit 200, such as registers associated with execution unit 250, fetch circuit 210, decode circuit 240, and the like. In a manner similar to that described above with respect to registers 236, 276, and 286, processor circuit 200 may be further configured to, based at least in part on the execution of translation barrier instruction 242, stall changes to one or more system registers that occurred after translation barrier instruction 242 in program order, and determine whether pending changes to one or more system registers that occurred before translation barrier instruction 242 in program order are complete. Based at least in part on determining that the pending changes are complete, processor circuit 200 may be further configured to continue executing one or more instructions that are capable of modifying the configuration of TLBs 234, 274, and 284. In some embodiments, processor circuit 200 may be further configured to allow blocked translation operations to continue in processor circuit 200 based, at least in part, on determining that execution of one or more instructions that can modify the configuration of TLBs 234, 274, and 284 has occurred. Additionally, if the translation remains valid, e.g., the translation of the virtual address has not changed between the start and end of execution of translation barrier instruction 242, the result of the speculative translation request may be cached. However, if the address space includes an update of the virtual address during execution of one or more instructions, processor circuit 200 may discard the result of the speculative translation request and reissue the request. It should be noted that the embodiment of FIG. 2 is an example of how processor circuitry supporting translation barrier instructions may be implemented. Similar to FIG. 1 , FIG. 2 includes limited components for clarity. In other embodiments, the processor circuitry may also include additional components, such as branch prediction circuitry, co-processors, and the like. In various embodiments, the circuitry of processor circuit 200 may be implemented using any suitable combination of sequential and combinational logic circuitry. Additionally, registers and / or memory circuitry (such as SRAM) may be used within such circuitry to temporarily store information such as instructions, data, address values, and the like. In summary, various embodiments of an apparatus may include processor circuitry that is configurable to execute a translation barrier instruction. To execute the translation barrier instruction, the processor circuitry may be configured to prevent address translations for instructions that occur after the translation barrier instruction in program order until after the translation barrier instruction completes. The processor circuitry may further be configured to complete the translation barrier instruction based on completion of all address translations for instructions that occur before the translation barrier instruction in program order. In a further example, the apparatus may further include a set of system registers. To execute the translation barrier instruction, the processor circuit may be further configured to: prevent changes to the set of system registers that occur after the translation barrier instruction in program order until after the translation barrier instruction completes; and complete the translation barrier instruction based on completing all changes to the set of system registers that occurred before the translation barrier instruction in program order. In some examples, the set of system registers may include all system registers. In other examples, the set of system registers may include all registers that affect address translation. In a further example, the set of system registers may include all registers that affect address permissions. In another example, the set of system registers may include all registers that affect address translation or address permissions. In a further embodiment, the set of system registers includes a base address register that stores a base address of a paging table or a permission table. In one example, the apparatus may further include one or more translation lookaside buffers (TLBs) configured to store virtual-to-physical address mappings. To execute the translation barrier instruction, the processor circuitry may be configured to prevent caching of address translations in the one or more TLBs for speculatively executed instructions that occur after the translation barrier instruction in program order until after the translation barrier instruction completes. In another example, to prevent address translations for instructions that occur after the translation barrier instruction, the processor circuitry may be configured to stall the issuance of one or more instructions that occur after the translation barrier instruction in program order. The circuits and techniques described above with respect to Figures 1 and 2 can be used in various ways to execute specific instructions. Several methods associated with executing translation barrier instructions are described below in conjunction with Figures 3 through 6. In some embodiments, the operations of the disclosed methods can be performed using instructions included in a non-transitory computer-readable memory having program instructions, which can be executed by processor circuitry in a system to cause the operations described with respect to Figures 3 through 6 to occur. Turning to FIG3 , a flow chart of an embodiment of a method for executing a translation barrier instruction by a processor circuit is shown. Method 300 may be executed by a processor circuit such as processor circuits 100 and 200 of FIG1 and FIG2 , respectively. In some embodiments, the operations of method 300 , or portions thereof, may be performed by execution circuits in the system that execute instructions stored in non-volatile memory, such as hard-coded microcode in the system. As an example, method 300 is described below using processor circuit 100 of FIG1 . References to elements in FIG1 are included as non-limiting examples. Method 300 begins at block 310, where processor circuit 100 issues a translation barrier instruction 142. For example, translation barrier instruction 142 may be issued after a translation table associated with address circuitry 110 is populated with entries defining an address space associated with at least a portion of an active application. In preparation for a change to an address space (e.g., a change to a different address space, or a change in access permissions to an address space), processor circuit 100 may issue translation barrier instruction 142 before modifying the translation table. At block 320, method 300 continues by causing processor circuit 100 to prevent pending address translations of instructions that occur after translation barrier instruction 142 in program order until after the translation barrier instruction completes. As described above, translation barrier instruction 142 may cause processor circuit 100 to stall translation operations until translation barrier instruction 142 completes. In some embodiments, address circuitry 110 may stall ongoing address translations of instructions that are later than translation barrier instruction 142, and / or decode circuitry 140 may not issue address translation requests for instructions that are later than the translation barrier instruction. At block 330, method 300 may continue by processor circuit 100 completing translation barrier instruction 142 based on completing all address translations of instructions that occur in program order before translation barrier instruction 142. In some embodiments, translation barrier instruction 142 is not completed until all earlier translation operations are completed. Thus, processor circuit 100 may retire translation barrier instruction 142 after all conditions associated with translation barrier instruction 142 have been completed. Note that the method of FIG. 3 includes blocks 310 through 330. Method 300 may terminate at block 330 or may repeat some or all of the method's blocks. For example, method 300 may repeat block 320 for instructions added to instruction cache 120 while translation barrier instruction 142 remains active. Method 300 may be executed concurrently with different instances of the method. For example, a system including processor circuit 100 may include other processor circuits, each of which may independently execute a respective instance of the translation barrier instruction at different points in time, but with overlapping processing. Turning now to FIG. 4 , a flowchart illustrating an embodiment of a different method for executing a translation barrier instruction by a processor circuit is shown. In a manner similar to method 300 , method 400 may be performed by a processor circuit, such as processor circuits 100 and 200 of FIG. 1 and FIG. 2 . Also similar to method 300 , some or all of the operations of method 400 may be performed by execution circuits in a system that execute instructions stored in non-volatile memory, such as microcode. As an example, method 400 is described below using processor circuit 200 of FIG. References to elements in FIG. 2 are included as non-limiting examples. Method 400 begins at block 410, where processor circuit 200 issues a translation barrier instruction 142. For example, translation barrier instruction 142 may be issued after one or more of TLBs 234, 274, and / or 284 have been populated with entries and registers 236, 276, and 286 have been set based on an address space associated with at least a portion of an active application. In preparation for making changes to one or more of registers 236, 276, and 286, processor circuit 200 (e.g., decode circuit 240) may issue translation barrier instruction 242 before modifying any of registers 236, 276, and 286. At block 420, the method 400 continues by preventing changes to the set of system registers that occur after the translation barrier instruction 142 in program order until after the translation barrier instruction 142 completes. As previously disclosed, execution of the translation barrier instruction 142 may block changes to specific registers in the set of system registers, including, for example, one or more of registers 236, 276, and 286, based on store instructions that occur later than the translation barrier instruction 142. However, store instructions that occur earlier than the translation barrier instruction 142 may be allowed to proceed before the translation barrier instruction 142 completes. At block 430, the method 400 continues by the processor circuit 200 completing the translation barrier instruction 142 based on completing all changes to the set of system registers that occurred in program order before the translation barrier instruction 142. The condition of the translation barrier instruction 142 may be satisfied after all outstanding writes to the associated system registers (e.g., one or more of registers 236, 276, and 286) associated with instructions earlier than the translation barrier instruction 142 have been completed. Based on the condition of the translation barrier instruction 142 being satisfied, the processor circuit 100 may continue to execute subsequent instructions later than the translation barrier instruction 142. Note that the method of FIG. 4 includes blocks 410 through 430. Method 400 may terminate at block 430 or may repeat some or all of the operations. For example, method 400 may repeat in response to another instance receiving a translation barrier instruction. Similar to method 300, method 400 may be executed concurrently with different instances of method 400. Methods 300 and 400 may be executed in combination based on the issuance of translation barrier instruction 142. Turning now to FIG. 5 , a flow chart illustrating an embodiment of a method for stalling instruction issuance by a processor circuit based on an active translation barrier instruction 142 is shown. In a manner similar to methods 300 and 400 , method 500 may be performed by a processor circuit, such as processor circuits 100 and 200 of FIG. 1 and FIG. 2 . As an example, method 500 is described below using processor circuit 100 of FIG. 1 . References to elements in FIG. 1 are included as non-limiting examples. Method 500 may be performed concurrently with one or more operations of method 300 , such as after block 310 and concurrently with blocks 320-330. At block 510, method 500 begins with processor circuitry issuing an instruction later than the active translation barrier instruction based on a later instruction that does not depend on an address translation operation. For example, processor circuitry 100 may execute instruction 145c while translation barrier instruction 142 is active based on a determination that instruction 145c does not depend on a pending address translation. Many instructions may perform logical or arithmetic operations using operands previously stored in one or more registers in a register file of processor circuitry 100. Therefore, any pending changes to an address table or registers associated with an address translation may not affect values ​​currently stored in the register file. At block 520, method 500 continues with a determination by processor circuitry that remaining decoded instructions depend on outstanding address translations. With instructions allowed to proceed, later instructions may be fetched and / or decoded. At some point, all decoded instructions may depend on pending address translations that have been blocked from proceeding due to active translation barrier instruction 142. At block 530, method 500 continues by causing processor circuit 100 to stall the issuance of one or more instructions that occur after the translation barrier instruction in program order based at least in part on the determination. For example, a pending instruction may be prevented from issuing due to a pending address translation. Once the supply of ready-to-issue instructions has been issued, instruction execution may be stalled until the translation barrier instruction 142 completes. Note that the method of FIG. 5 includes blocks 510 through 530. Method 500 may terminate at block 530 or may repeat some or all of the operations. For example, method 500 may repeat in response to another instance receiving instructions. Similar to methods 300 and 400, method 500 may be executed concurrently with different instances of methods 300, 400, and / or 500. Referring now to FIG6 , a flow chart of an embodiment of a method for handling speculative translation requests by a processor circuit in conjunction with a translation barrier instruction is illustrated. In a manner similar to methods 300 through 500 , method 600 may be performed by a system such as processor circuits 100 and 200 of FIG1 and FIG2 . As an example, method 600 is described below using processor circuit 100 of FIG1 . References to elements in FIG1 are included as non-limiting examples. Method 600 may be performed concurrently with one or more operations of method 300 , such as after block 310 and concurrently with blocks 320 through 330 . At block 610, method 600 begins with processor circuit 100, prior to issuing translation barrier instruction 142, issuing a speculative translation request for an instruction that occurs after translation barrier instruction 142 in program order (e.g., instruction 145d). As previously disclosed, processor circuit 100 may support out-of-order processing. Thus, processor circuit 100 may issue an address translation request for instruction 145d before issuing translation barrier instruction 142 and before the earlier of instructions 145 is issued. Because the virtual address associated with instruction 145d does not have a corresponding entry in the TLB in address circuitry 110, the speculative translation request may be transmitted to a translation table (e.g., included in or coupled to address circuitry 110). Requesting a speculative translation may help avoid delaying the issuance of instruction 145d due to waiting for an address translation at a later point in time. Method 600 continues at block 620 where processor circuit 100 issues a translation barrier instruction. After speculative address translation has been requested, but before the translation result is received, processor circuit 100 may issue translation barrier instruction 142 to prevent requesting address translation of a later instruction. However, a speculative translation request for instruction 145d is already in progress and may allow the virtual address to be translated into a physical address based on the current value in the translation table. At block 630, method 600 continues with processor circuit 100 preventing the result of the speculative translation request from being cached in the TLB after issuing translation barrier instruction 142. For example, although processor circuit 100 has issued a speculative translation request for instruction 145d to address circuitry 110, the result of the speculative translation may be received after issuing translation barrier instruction 142. Based on at least issuing translation barrier instruction 142, processor circuit 100 prevents the result of the speculative translation from being cached in the TLB. Because processor circuit 100 may execute one or more instructions that modify the translation tables, the result of the speculative translation may be invalid when instruction 145d is to be executed in program order. By blocking the result of the speculative translation from being cached, invalid translations may be avoided. Note that the method of FIG6 includes blocks 610 through 630. Method 600 may terminate at block 630 or may repeat some or all of the operations. For example, method 600 may repeat in response to issuing more than one speculative translation request before issuing translation barrier instruction 142. Similar to method 500, method 600 may be executed concurrently with different instances of any disclosed method. Figures 1 through 6 illustrate circuits and methods for a system (e.g., a system-on-a-chip) including an execution pipeline capable of executing translation barrier instructions. Any embodiment of the disclosed system may be included in one or more of various computer systems, such as desktop computers, laptop computers, smartphones, tablets, wearable devices, and the like. In some embodiments, the circuits described above may be implemented on a system-on-a-chip (SOC) or other type of integrated circuit (including a multi-die package). A block diagram illustrating an embodiment of system 700 is shown in Figure 7. In some embodiments, system 700 may include any disclosed embodiment of the systems disclosed herein, such as processor circuits 100 and 200 shown in Figures 1 and 2. In the illustrated embodiment, system 700 includes at least one instance of a system-on-a-chip (SOC) 706, which may include various types of processor circuits, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise include a communication mesh architecture and interfaces to memory and input / output devices. SOC 706 may correspond to an instance of a processor circuit and / or system disclosed herein. In various embodiments, SOC 706 is coupled to external memory circuits 702, peripheral devices 704, and a power supply 708. A power supply 708 is also provided that supplies a supply voltage to the SOC 706 and one or more supply voltages to the external memory circuit 702 and / or the peripheral device 704. In various embodiments, the power supply 708 represents a battery pack (e.g., a rechargeable battery pack in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SOC 706 is included (and more than one external memory circuit 702 is also included). External memory circuit 702 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM (such as mDDR3) and / or low-power versions of SDRAM (such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. In some embodiments, external memory circuit 702 may include non-volatile memory, such as flash memory, ferroelectric random-access memory (FRAM), or magnetoresistive RAM (MRAM). One or more memory devices may be coupled to a circuit board to form a memory module (such as a single inline memory module (SIMM) or a dual inline memory module (DIMM)). Alternatively, the device may be mounted in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration along with an SOC or an integrated circuit. Depending on the type of system 700, peripheral devices 704 may include any desired circuitry. For example, in one embodiment, peripheral devices 704 include devices for various types of wireless communications (such as WiFi, Bluetooth, cellular, GPS, etc.). In some embodiments, peripheral devices 704 also include additional storage, including RAM, solid-state storage, or disk storage. Peripheral devices 704 may include user interface devices, such as a display (including a touchscreen or multi-touchscreen display), a keyboard or other input device, a microphone, a speaker, etc. As shown, system 700 is shown to have applications across a wide range of fields. For example, system 700 can be used as part of the chips, circuitry, components, etc., of a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a television 750 (or a set-top box coupled to a television). Also shown are a smartwatch and a health monitoring device 760. In some embodiments, the smartwatch can include a variety of general computing-related functions. For example, the smartwatch can provide email, phone services, a user's calendar, and so on. In various embodiments, the health monitoring device can be a dedicated medical device or otherwise include dedicated health-related functionality. In various embodiments, the smartwatches mentioned above may or may not include some or all of the health monitoring-related functions. Other wearable devices 760 are also contemplated, such as devices worn around the neck, devices attached to hats or other headwear, devices implantable in the human body, glasses designed to provide augmented and / or virtual reality experiences, and so on. System 700 can further be used as part of cloud-based service(s) 770. For example, the aforementioned devices and / or other devices can access computing resources (i.e., remotely located hardware and / or software resources) in the cloud. Furthermore, system 700 can be used in one or more devices in a home 780 other than those mentioned above. For example, appliances within a home can monitor and detect conditions of concern. Various devices within a home (e.g., refrigerator, air conditioning system, etc.) can monitor their status and provide alerts to the homeowner (or, for example, repair facilities) when specific events are detected. Alternatively, a thermostat can monitor the temperature within a home and automatically adjust the heating / cooling system based on the homeowner's historical responses to various conditions. FIG7 also illustrates the application of system 700 to various modes of transportation 790. For example, system 700 can be used in control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, surface vessels ranging from private boats to cruise ships, and motorcycles (for rental or personal use). In various cases, system 700 may be used to provide automated guidance (eg, self-driving vehicles), general system control, and other aspects. It should be noted that a wide variety of potential applications for system 700 may include various performance, cost, and power consumption requirements. Therefore, a scalable solution that can use one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption may be beneficial. These and many other embodiments are possible and contemplated. It should be noted that the devices and applications depicted in FIG7 are illustrative only and are not intended to be limiting. Other devices are possible and contemplated. As disclosed with respect to Figure 7, system 700 may include one or more integrated circuits included in a personal computer, smartphone, tablet computer, or other type of computing device. A process for designing and producing an integrated circuit using design information is presented below in Figure 8. FIG8 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. The embodiment of FIG8 may be used in a process for designing and manufacturing integrated circuits, such as those including one or more instances of the processor circuits 100 and 200 (or portions thereof) described above. In the illustrated embodiment, a semiconductor manufacturing system 820 is configured to process design information 815 stored on a non-transitory computer-readable storage medium 810 and to manufacture an integrated circuit 830 based on the design information 815. Non-transitory computer-readable storage medium 810 may include any of various suitable types of memory devices or storage devices. Non-transitory computer-readable storage medium 810 may be installation media (e.g., a CD-ROM, floppy disk, or magnetic tape device); computer system memory or random access memory (e.g., DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.); non-volatile memory (e.g., flash memory, magnetic media (e.g., a hard drive), or optical storage); registers or other similar types of memory devices. Non-transitory computer-readable storage medium 810 may also include other types of non-transitory memory or a combination thereof. Non-transitory computer-readable storage medium 810 may include two or more memory media that may reside in different locations (e.g., in different computer systems connected via a network). Design information 815 may be specified using any of a variety of suitable computer languages ​​(including hardware description languages), such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. Design information 815 may be used by semiconductor manufacturing system 820 to manufacture at least a portion of integrated circuit 830. For example, the format of design information 815 may be recognizable by at least one semiconductor manufacturing system, such as semiconductor manufacturing system 820. In some embodiments, design information 815 may include wiring tables specifying the elements of a circuit cell library and their connectivity. One or more circuit cell libraries used during logic synthesis of circuits included in integrated circuit 830 may also be included in design information 815. Such circuit cell libraries may include device or transistor-level wiring tables, mask design data, characterization data, and the like, indicating circuit elements included in the circuit cell library. In various embodiments, integrated circuit 830 may include one or more custom macrocells (such as memory, analog or mixed-signal circuits, and the like). In such cases, design information 815 may include information related to the included macrocells. Such information may include, without limitation, schematic capture databases, mask design data, behavioral models, and device or transistor-level wiring lookup tables. As used herein, mask design data may be formatted according to the Graphics Data System II (GDSII) or any other suitable format. Semiconductor manufacturing system 820 may include any of a variety of suitable components configured to manufacture integrated circuits. For example, this may include components for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet light treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 820 may also be configured to perform various tests on the manufactured circuits for proper operation. In various embodiments, integrated circuit 830 is configured to operate according to the circuit design specified by design information 815, which may include performing any of the functionality described herein. For example, integrated circuit 830 may include any of the various components shown or described herein. Furthermore, integrated circuit 830 may be configured to perform the various functions described herein in conjunction with other components. As used herein, phrases of the form "design information that specifies a design of a circuit configured to ..." do not imply that the circuit in question must be manufactured to satisfy the specified requirement. Rather, the phrase indicates that the circuit described by the design information, once manufactured, will be configured to perform the specified action or will include specified components.*** This disclosure includes references to an "embodiment" or groups of "embodiments" (e.g., "some embodiment" or "various embodiments"). Embodiments are different implementations or instances of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," and the like do not necessarily refer to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications and alternatives within the spirit and scope of this disclosure. This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments will necessarily exhibit any or all of the potential advantages. Whether or not an advantage is achieved for a particular embodiment depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular embodiment may include additional circuitry (in combination with one of the disclosed embodiments) outside the scope of this disclosure, thereby negating or reducing one or more of the disclosed advantages. Furthermore, suboptimal design implementation of a particular embodiment (e.g., implementation techniques or tools) may also negate or reduce the disclosed advantages. Even assuming a skilled implementation, the realization of an advantage may still depend on other factors, such as the environmental conditions in which the embodiment is deployed. For example, inputs supplied to a particular embodiment may prevent one or more of the problems addressed in this disclosure from occurring in a particular instance, and as a result, the benefits of its solutions may not be realized. Given the existence of possible factors external to this disclosure, it is expressly intended that any potential advantages described herein not be construed as requiring compliance with the claim limitations in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the type of improvement(s) available to designers having the benefit of this disclosure. Describing such advantages permissibly (e.g., stating that a particular advantage "may result") is not intended to convey doubt as to whether such advantages can actually be achieved, but rather to recognize that the technical reality of achieving such advantages often depends on additional factors. Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims drafted based on this disclosure, even if only a single example of a particular feature is described. The disclosed embodiments are intended to be illustrative, not restrictive, and nothing to the contrary is stated in this disclosure. Therefore, it is intended that the claims cover the disclosed embodiments as well as such alternatives, modifications, and equivalents as would be apparent to one of ordinary skill in the art having the benefit of this disclosure. For example, the features of this application may be combined in any suitable manner. Accordingly, new claims may be formulated during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. Specifically, by reference to the accompanying claims, features from independent claims may be combined with features from other independent claims, including, where appropriate, claims that are dependent upon other dependent claims. Similarly, features from separate dependent claims may be combined, where appropriate. Accordingly, although the accompanying dependent claims may be drafted so that each is dependent on a single other claim, additional dependencies are also contemplated. Any combination of features of the dependent claims consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the accompanying claims. It is also contemplated that claims drafted in one format or legal type (e.g., apparatus) may be intended to support corresponding claims in another format or legal type (e.g., method), where appropriate.*** Because this disclosure is a legal document, its terms and phrases are subject to administrative and judicial interpretation. The definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret the claims drafted based on this disclosure. Unless the context clearly dictates otherwise, a reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, a reference in a claim to "an item" does not exclude additional instances of that item in the absence of accompanying context. A "plurality" item refers to a collection of two or more items. As used herein, the word “may” is used herein in a permissive sense (ie, having the potential to, being able to), and not in a mandatory sense (ie, must). The terms “comprising” and “including” and their forms are open ended and mean “including, but not limited to.” When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement "x or y" is equivalent to "x or y, or both," thus: 1) x is included but y is not included; 2) y is included but not x; and 3) both x and y are included. On the other hand, phrases such as "either x or y, but not both" clearly indicate that "or" is used in an exclusive sense. The statement "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to encompass all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases encompass any single element (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements of the set. Thus, the phrase "at least one of ... w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase is not to be construed as requiring at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z. In this disclosure, various "designations" may be placed before nouns or noun phrases. Unless the context indicates otherwise, different designations applied to a feature (e.g., "first circuit," "second circuit," "specific circuit," "given circuit," etc.) refer to different instances of that feature. Additionally, unless otherwise specified, the designations "first," "second," and "third" when applied to a feature do not imply any type of order (e.g., spatial, temporal, logical, etc.). The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on specific factors, or on those specific factors and other unspecified factors. Consider the term "determine A based on B." This term indicates that B is a factor used to determine A, or that B influences the determination of A. This term does not exclude that A may also be determined based on some other factor, such as C. This term is also intended to encompass an embodiment in which A is determined based solely on B. As used herein, the term "based on" is synonymous with the term "based at least in part on." The phrase "in response to" or "response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, an effect may be in response to those factors alone, or may be in response to those specified factors and other unspecified factors. Consider the phrase "perform A in response to B." This phrase specifies that B is the factor that triggers the performance of A or triggers a specific result of A. This phrase does not exclude that A may also be performed in response to some other factor, such as C. This phrase also does not exclude that A may be performed in response to both B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to." Similarly, the phrase "in response to" is synonymous with the phrase "at least in part in response to." In this disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This notation ("an entity" is configured to "perform one or more tasks") is used herein to refer to a structure (i.e., a physical thing). Specifically, this notation is used to indicate that the structure is configured to perform the one or more tasks during operation. A structure may be said to be "configured to" perform a task even if it is not currently being operated. Thus, an entity described or described as "configured to" perform a task refers to a physical thing, such as a device, a circuit, a system having a processing unit, a memory storing program instructions executable to perform the task, etc. This phrase is not used herein to refer to an intangible thing. In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform these tasks / operations even if not specifically mentioned. The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function. However, this unprogrammed FPGA could be "configurable to" perform that function. After being appropriately programmed, the FPGA could then be said to be "configured to" perform a specific function. For purposes of U.S. patent applications based on the present disclosure, describing a structure in a claim as "configured to" perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) to interpret the claimed elements. If applicants intend to invoke § 112(f) during prosecution of a U.S. patent application based on the present disclosure, the claimed elements will be recited using the construct "means for 'performing a function'." *** Various "circuits" may be described in this disclosure. These circuits or "circuitry" constitute hardware that includes various types of circuit elements, such as combinational logic, timed storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuitry can be custom designed or taken from a standard library. In various embodiments, the circuitry may include digital components, analog components, or a combination of both, as needed. Certain types of circuits are generally referred to as "units" (e.g., decode units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry. Thus, the disclosed circuits / units / components and other elements shown in the drawings and disclosed herein include hardware elements, such as those described in the preceding paragraphs. In many instances, the internal configuration of hardware elements within a particular circuit can be specified by describing the functionality of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode of an instruction and routing that instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform this function. The description of this function is sufficient to indicate to a person of ordinary skill in the art of computer science a set of possible structures for the circuit. In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other components can be defined by the functions or operations they are configured to perform. This configuration and the manner in which such circuits / units / components interact with each other form a microarchitectural definition of the hardware, which is ultimately fabricated into an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microhierarchical definition is a structure recognized by those skilled in the art as one from which many physical implementations can be derived, all of which fall within the broad structure described by the microhierarchical definition. That is, it is proposed that, based on the microhierarchical definition provided by the present disclosure, one skilled in the art can, without undue experimentation and applying conventional techniques, implement the structure by encoding a description of the circuits / units / components in a hardware description language (HDL) such as Verilog or VHDL. HDL descriptions are often expressed in a functionally tangible manner. However, for those skilled in the art, this HDL description is used to translate the structure of a circuit, cell, or component into the next level of implementation details. This HDL description can take the form of behavioral code (which is generally not synthesizable), register transfer language (RTL) code (which is generally synthesizable, in contrast to behavioral code), or structural code (e.g., a wiring lookup table specifying logic gates and their connectivity). The HDL description can then be synthesized from a component library designed for a given IC fabrication technology and modified for timing, power, and other reasons to produce a final design library, which is then transferred to the fabrication facility for mask fabrication and, ultimately, the IC. Some hardware circuits, or portions thereof, can also be customized in a schematic editor and transferred to the IC design along with the synthesized circuitry. The IC may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, and inductors) and the interconnects between the transistors and the circuit elements. Some embodiments may implement multiple integrated circuits that are coupled together to implement a hardware circuit, and / or in some embodiments, discrete components may be used. Alternatively, the HDL design may be synthesized into a programmable logic array, such as a field programmable gate array (FPGA), and implemented in the FPGA. The decoupling between the design of this group of circuits and the subsequent lower-level implementation of these circuits often leads to situations where the circuit or logic designer never specifies a specific set of structures for the lower-level implementation beyond a description of the actions the circuits are configured to perform when this process is performed at a different stage in the circuit implementation process. In fact, many different underlying combinations of circuit elements can be used to implement the same circuit, resulting in a large number of equivalent structures for that circuit. As mentioned, these underlying circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the component libraries available for a particular project, and so on. In many cases, the choice of different design tools or methodologies to generate these different implementations can be arbitrary. Furthermore, it's common for a single implementation of a circuit's specific functional specifications to include a large number of devices (e.g., millions of transistors) for a given implementation. Consequently, the sheer volume of this information makes it impractical to provide a complete description of the underlying structure used to implement a single implementation, let alone a large array of equivalently feasible implementations. For this reason, this disclosure describes circuit structures using functional shorthand commonly used in the industry. 100: Processor Circuit 110: Address Circuitry 112: Translation Circuit 114: Access Permission Circuit 116: Register 120: Instruction Cache (ICache) 140: Decoding Circuit 142: Translation Barrier Instruction 145a: Instruction 145b: Instruction 145c: Instruction 145d: Instruction 147a: Address Translation 147b: Address Translation 147c: Address Translation 200: Processor Circuit 210: Fetch Circuit 220: Instruction Cache (ICache) Circuit 230: Instruction Memory Management Unit (IMMU) 234: Translation Lookaside Buffer (TLB) 236: Register 240: Decoding Circuit 242: Translation Barrier Instruction 250: Execution Unit 252: Integer Unit 254: Floating Point Unit (FPU) 256: Load / Store Unit (LSU) 260: Data cache (DCache) circuit 270: Data memory management unit (DMMU) 274: Translation lookaside buffer (TLB) 276: Register 280: Memory management unit (MMU) 284: Translation lookaside buffer (TLB) 286: Register 310: Block 320: Block 330: Block 410: Block 420: Block 430: Block 510: Block 520: Block 530: Block 610: Block 620: Block 630: Block 700: System 702: External memory circuit 704: Peripheral device 706: System on chip (SOC) 708: Power supply 710: Desktop computer 720: Laptop computer 730: Tablet computer 740: Cellular or mobile phone 750: Television 760: Smart watch and health monitoring device 770: Cloud-based service 780: Home 790: Transport mode 810: Non-transitory computer-readable media 815: Design information 820: Semiconductor manufacturing system 830: Integrated circuit The following embodiments will refer to the accompanying drawings, which are briefly described below. [FIG. 1] illustrates a block diagram of an embodiment of a processor circuit that supports a translation barrier instruction. [FIG. 2] illustrates a block diagram of an embodiment of a processor circuit that can be implemented in the system of FIG. 1. [FIG. 3] illustrates a flow chart of an embodiment of a method for executing a translation barrier instruction. [FIG. 4] illustrates a flow chart of another embodiment of a method for executing a translation barrier instruction. [FIG. 5] illustrates a flow chart of an embodiment of a method for stalling instructions in response to execution of a translation barrier instruction. [FIG. 6] illustrates a flow chart of an embodiment of a method for executing a speculative translation request in conjunction with execution of a translation barrier instruction. [FIG. 7] illustrates various embodiments of a system including coupled integrated circuits. [FIG. 8] illustrates a block diagram of an example computer-readable medium according to some embodiments. While the embodiments described in this disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and detailed description are not intended to limit the embodiments to the precise forms disclosed, but are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. 100: Processor circuit 110: Address circuit system 112: Translation Circuit 114: Access authority circuit 116: register 120: Instruction Cache (ICache) 140: decoding circuit 142:Translation barrier instruction 145a: Instructions 145b: Instructions 145c: Instructions 145d: Instructions 147a: Address Translation 147b: Address Translation 147c: Address Translation

Claims

1. An apparatus for executing a translation barrier instruction, comprising: a processor circuit configured to execute the translation barrier instruction, wherein, in order to execute the translation barrier instruction, the processor circuit is configured to: prevent address translation of operands of fetched instructions occurring sequentially after the translation barrier instruction until the translation barrier instruction is completed; execute fetched instructions occurring sequentially after the translation barrier instruction and independent of a pending address translation; and complete the translation barrier instruction based on the completion of all address translations of operands of fetched instructions occurring sequentially before the translation barrier instruction.

2. The device of claim 1, further comprising: a set of system registers; wherein, in order to execute the translation barrier instruction, the processor circuitry is configured to: prevent changes to the set of system registers after the translation barrier instruction in program order until the translation barrier instruction is completed; and complete the translation barrier instruction based on the completion of all changes to the set of system registers that occurred in program order before the translation barrier instruction.

3. The device as requested in item 2, wherein the group of system registers is all system registers.

4. The device as requested in item 2, wherein the group of system registers comprises all registers that affect address translation.

5. The device as requested in item 2, wherein the group of system registers comprises all registers that affect address permissions.

6. The device as requested in item 2, wherein the group of system registers comprises all registers that affect address translation or address permissions.

7. The device as claimed in claim 6, wherein the set of system registers includes a base address register storing a base address of a paging table or a permission table.

8. The device of claim 1, further comprising: one or more translation back buffers (TLBs) configured to store virtual-to-physical address mappings; wherein, in order to execute the translation barrier instruction, the processor circuitry is configured to: prevent caching of address translations in the one or more TLBs for speculative execution instructions occurring sequentially after the translation barrier instruction, until the translation barrier instruction is completed.

9. The device of claim 1, wherein, in order to prevent address translation for instructions occurring after the translation barrier instruction, the processor circuitry is configured to pause the issuance of one or more instructions occurring sequentially after the translation barrier instruction.

10. A method for executing a translation barrier instruction, comprising: responding to a translation barrier instruction issued by a processor circuit: the processor circuit preventing the translation of pending address translations for operands of fetched instructions occurring sequentially after the translation barrier instruction until the translation barrier instruction is completed; completing fetched instructions occurring sequentially after the translation barrier instruction and independent of a pending address translation; and the processor circuit completing the translation barrier instruction based on completing all address translations for operands of fetched instructions occurring sequentially before the translation barrier instruction.

11. The method of claim 10, further comprising responding to the issuance of the translation barrier instruction by: the processor circuitry preventing changes to a set of system registers in program order after the translation barrier instruction until the translation barrier instruction is completed; and the processor circuitry also completing the translation barrier instruction based on the completion of all changes to the set of system registers in program order before the translation barrier instruction.

12. The method of request item 11, wherein the group of system registers is all system registers.

13. The method of request item 11, wherein the group of system registers are all registers that affect address translation.

14. The method of request item 11, wherein the group of system registers comprises all registers that affect address translation or address permissions.

15. The method of claim 10, wherein the prevention includes halting the issuance of one or more instructions that occur sequentially after the translation barrier instruction.

16. The method of claim 10, further comprising responding to the issuance of the translation barrier instruction by: preventing cache of address translation in one or more translation back buffers (TLBs) for speculative execution instructions that occur sequentially after the translation barrier instruction, until the translation barrier instruction is completed, wherein the one or more TLBs are configured to store virtual to physical address mappings.

17. An apparatus for executing a translation barrier instruction, comprising: a processor circuit including an instruction pipeline configured to execute the translation barrier instruction, wherein, in order to execute the translation barrier instruction, the instruction pipeline is configured to: perform address translation for operands of fetched instructions earlier than the translation barrier instruction in the instruction pipeline; prevent address translation for operands of fetched instructions later than the translation barrier instruction in the instruction pipeline; execute one or more fetched instructions later than the translation barrier instruction and independent of a pending address translation; and complete the translation barrier instruction based on completing the address translation for operands of all such fetched instructions earlier than the translation barrier instruction in the instruction pipeline.

18. The apparatus of claim 17, further comprising a set of system registers, wherein the instruction pipeline circuitry is further configured to: prevent changes to the set of system registers by instructions in the instruction pipeline circuitry that are later than the translation barrier instruction; allow changes to the set of system registers by instructions in the instruction pipeline circuitry that are earlier than the translation barrier instruction; and complete the translation barrier instruction based on the completion of such changes to the set of system registers by instructions in the instruction pipeline circuitry that are earlier than the translation barrier instruction.

19. The device as requested in item 18, wherein the group of system registers includes registers that affect address translation or address permissions.

20. The device of claim 19, further comprising: one or more translation back buffers (TLBs) configured to store virtual-to-physical address mappings; wherein, in order to execute the translation barrier instruction, the instruction pipeline circuitry is further configured to: prevent caching of address translations in the one or more TLBs for speculative execution instructions later than the translation barrier instruction until after the translation barrier instruction has been completed.

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