Transparent display device

Abstract

A transparent display device is disclosed that reduces edge artifacts by optimizing the arrangement of four color emitting regions. The transparent display device may include multiple pixel regions having a non-transmissive region and a transmissive region, and a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially in a first direction within the non-transmissive region of the multiple pixel regions. One of the second and third sub-pixels may be a green sub-pixel, and the other may be a white sub-pixel. When the second sub-pixel is a green sub-pixel, the first sub-pixel is a red sub-pixel, or when the third sub-pixel is a green sub-pixel, the fourth sub-pixel is a red sub-pixel.

Description

Transparent display device This disclosure relates to a transparent display device that can improve image quality by reducing edge artifacts. A transparent display device may include a non-transmissive area and a transmissive area. The non-transmissive area may display full color using four-color sub-pixels including white, red, green, and blue light-emitting areas. In a four-color transparent display device, the spacing between the light-emitting sub-pixels can be increased to display a specific color, or the spacing between the light-emitting sub-pixels may deviate. Therefore, four-color transparent display devices may exhibit edge artifacts, which are perceived as white lines, black lines, or color edges at the edges where there are brightness differences between adjacent pixels, resulting in a decrease in image quality. Therefore, this disclosure aims to provide a transparent display device that substantially overcomes the problems caused by one or more limitations and disadvantages in the related art. One aspect of this disclosure provides a transparent display device that can reduce edge artifacts by optimizing the layout of the four-color emitting areas. To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a transparent display device may include a display area having a non-transparent region and a transmissive region, comprising a plurality of pixel regions, and a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in this order in the non-transparent region of the plurality of pixel regions in a first direction. Specifically, each pixel region may have a non-transparent region and a transmissive region, and a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in the non-transparent region of the pixel region in a first direction. One of the second and third sub-pixels may be a green sub-pixel, and the other may be a white sub-pixel. If the second sub-pixel is a green sub-pixel, then the first sub-pixel may be a red sub-pixel; if the third sub-pixel is a green sub-pixel, then the fourth sub-pixel may be a red sub-pixel. The first to fourth sub-pixels can be red sub-pixels, green sub-pixels, white sub-pixels, and blue sub-pixels arranged sequentially in the first direction. The first to fourth sub-pixels can be blue sub-pixels, white sub-pixels, green sub-pixels, and red sub-pixels arranged sequentially in the first direction. According to another aspect of this disclosure, the transparent display device may include a display area having a non-transmissive region and a transmissive region, having a plurality of pixel regions, and red sub-pixels, green sub-pixels, white sub-pixels and blue sub-pixels, which are arranged in the non-transmissive region of the plurality of pixel regions in a vertical direction in this order. According to another aspect of this disclosure, a transparent display device may include a display area having a non-transparent region and a transmissive region, comprising a plurality of pixel regions; and blue sub-pixels, white sub-pixels, green sub-pixels, and red sub-pixels arranged sequentially in the vertical direction within the non-transparent region of the plurality of pixel regions. Specifically, each pixel region may have a non-transparent region and a transmissive region; and blue sub-pixels, white sub-pixels, green sub-pixels, and red sub-pixels arranged sequentially in the vertical direction within the non-transparent region of the plurality of pixel regions. One or more of these aspects may include one or more of the following features: The transmissive region can be provided to the left or right of the non-transmissive region in multiple pixel regions, or on both sides of the left and right of the non-transmissive region. Each pixel region of a multi-pixel region can have both a non-transmissive region and a transmissive region. In each pixel region, the green and white sub-pixels of the four sub-pixels in the non-transparent region can be set at the center of the non-transparent region, and the red and green sub-pixels can be set adjacent to each other. The first direction can be vertical. The first direction can also be the direction of the data lines in the transparent display device and / or the pixel area. The emission regions of the first, second, third, and fourth sub-pixels of the pixel region can be arranged side by side in the first direction. The transmittance of a pixel region can be greater than 45%. The transmittance of a pixel region can be at least 55%. The aperture ratio of the blue subpixel and the aperture ratio of the red subpixel can be greater than the aperture ratio of the white subpixel and the aperture ratio of the green subpixel. The aperture ratio of the first subpixel and the aperture ratio of the fourth subpixel can be greater than the aperture ratio of the second subpixel and the aperture ratio of the third subpixel. In this document, unless otherwise stated, such as expressly indicated or implicitly disclosed, the terms "region" and "area" are used interchangeably. In this document, the terms "transmissive region" and "transmissive area" are used interchangeably; in this document, the terms "non-transmissive region" and "non-transmissive area" are used interchangeably; in this document, the terms "pixel region" and "pixel area" are used interchangeably. Each of the multiple pixel regions may include an emitting region and a transmissive region. The emitting region contains multiple sub-pixels for displaying image data, while the transmissive region is used for light transmission. The emitting region may be represented as a non-transmissive region, and the transmissive region may be represented as a transparent region. The non-transmissive region may include the emitting region. In each pixel region, the transmissive region (or transmissive area) may be adjacent to the non-transmissive region in a second direction. The second direction may be horizontal. The second direction may be the direction of the gate line of the pixel region and / or the transparent display device. The second direction may be left-right. The second direction may be perpendicular to the first direction. The non-transmissive region (or non-transmissive area) may include the first to fourth emission regions of the first to fourth sub-pixels arranged side-by-side in the first direction. The non-transmissive region (or non-transmissive area) may include a black matrix surrounding the emission region. Each sub-pixel (or the non-transmissive area of ​​each sub-pixel) may contain an emission region and a black matrix surrounding the emission region. In this document, a transparent display device is defined as a display device comprising a plurality of pixel regions, each having a transmissive region. The non-transmissive area can be configured to display full color using four-color subpixels containing white, red, green, and blue emitting areas. It should be understood that the foregoing general description and the following detailed description of this disclosure are merely illustrative examples intended to provide further explanation of the requested disclosure. The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following aspects described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the aspects described herein. Rather, these aspects are intended to make this disclosure complete and thorough, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, the scope of protection of this disclosure is defined by the claims of the patent application and their equivalents. The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings, which are used to describe various aspects of this disclosure, are merely exemplary and therefore the disclosure is not limited to the details shown. The same symbols denote the same elements throughout the specification. In the following description, detailed descriptions of known functions or constructions are omitted where such description would unnecessarily obscure the gist of the disclosure. The terms "comprising," "having," and "including" are used in this specification and may be incorporated unless a more restrictive term such as "only" is used. Singular terms may include plural forms, and vice versa, unless the contrary is stated. When interpreting components, even if not explicitly described, the components should be interpreted as including a range of error. When describing positional relationships, for example, when the positional relationship between two components is "on," "above," "below," and "beside," one or more other components may be placed between the two components, unless more restrictive terms such as "only" or "directly" are used. When describing temporal relationships, such as when describing the order of time as "after," "following," "next," and "before," discontinuous situations may be included unless more restrictive terms such as "only," "immediately," or "directly" are used. It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. In describing the elements of this disclosure, terms such as "first," "second," "A," "B," "(a)," and "(b)" may be used. These terms are intended only to identify the corresponding element from other elements and are not intended to define or limit the basis, order, sequence, or number of the corresponding elements. As in describing an element or layer as "connected," "coupled," or "attached" to another element or layer, the element or layer may be directly connected or attached to another element or layer, or indirectly connected or attached through one or more intermediary elements or layers "disposed" between the elements or layers, unless otherwise stated. The term "at least one" should be understood to include any and all related combinations of one or more of the listed elements. For example, "at least one or more first elements, second elements and third elements" means all combinations of two or more of the first element, second element and third element, as well as the first element, second element or third element. The features of this disclosure may be combined or integrated with each other in whole or in part, and may operate and be driven in various ways internally and technically, so as to be fully understood by one of ordinary skill in the art. The various aspects of this disclosure may be carried out independently or together and may be interdependent. The aspects of this disclosure will now be described with reference to the accompanying drawings. Since the proportions of the elements shown in the drawings may differ from actual proportions for ease of explanation, this disclosure is not limited to the proportions shown. Furthermore, all components of each display device according to all aspects of this disclosure are operatively coupled and configured. Figures 1 and 2 are block diagrams illustrating configuration examples of transparent display devices according to one or more embodiments of the present disclosure. Figures 3A to 3C and 4A to 4C are diagrams illustrating example pixel structures according to one or more embodiments of the present disclosure. According to one or more embodiments, the display devices 1000 and 1000A may be liquid crystal display devices, electroluminescent display devices using self-emissive elements, or microluminescent diode display devices using microluminescent diodes. The electroluminescent display device may be an organic light-emitting diode (OLED) display device, a quantum-dot light-emitting diode (QLED) display device, or an inorganic light-emitting diode (ILED) display device. According to one or more embodiments, as shown in Figures 1 and 2, the transparent display devices 1000 and 1000A may include a display panel 100, a gate driver 300, a data driver 400, a timing controller 600, a gamma voltage generator 700, and power management circuits 800 and 800A, etc. The gate driver 300 and the data driver 400 may be represented by a panel driver 200 that drives the display panel 100. The gate driver 300, the data driver 400, the timing controller 600, and the gamma voltage generator 700 may be represented by a display driver 500. According to one or more embodiments, as shown in FIG2, the transparent display device 1000A may further include a light shield 1100 disposed on the back side of the display panel 100 and overlapping the display panel 100, and a light shield driver 1200 for driving the light shield 1100. As shown in Figures 1 and 2, the display panel 100 can be a rigid display panel or a deformable flexible display panel, such as a foldable, bendable, rollable, or stretchable display panel. Display panel 100 is a transparent display panel, allowing the background behind display panel 100 to be viewed through display panel 100. Display panel 100 may include a display area AA and a border area surrounding display area AA, wherein a plurality of pixel areas PX are arranged in a matrix in display area AA for displaying images. According to one or more embodiments, display panel 100 may be a panel with an embedded or attached touch sensor screen superimposed on display area AA. Each of the multiple pixel regions PX may include an emitting region EA that sets multiple subpixels to display an image on the screen, and a transmissive region (transmissive area TA) that transmits light. The emitting region EA may be represented as a non-transmissive region, while the transmissive region (transmissive area TA) may be represented as a transparent region. As shown in Figures 3A to 4C, according to various embodiments, each pixel region PX11, PX12, PX13, PX21, PX22, and PX23 may include a non-transmissive region NTA having a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4 arranged side-by-side in a first direction Y (vertical direction), and a transmissive region TA adjacent to the non-transmissive region NTA in a second direction X (horizontal direction). The non-transmissive region NTA may include a first emitting region EA1, a second emitting region EA2, a third emitting region EA3, and a fourth emitting region EA4 arranged side-by-side in the first direction Y (vertical direction), and a black matrix BM surrounding these emitting regions EA1, EA2, EA3, and EA4. The structure of a first type pixel region PX11 according to one or more embodiments and a second type pixel region PX21 according to one or more embodiments may be such that a non-transmissive region NTA is disposed on the left and a transmissive region TA is disposed on the right. The structure of a first type pixel region PX12 according to one or more embodiments and a second type pixel region PX22 according to one or more embodiments may be such that a non-transmissive region NTA is disposed on the right side and a transmissive region TA is disposed on the left side. The structure of the first type pixel region PX13 according to one or more embodiments and the second type pixel region PX23 according to one or more embodiments may be such that the non-transparent region NTA is disposed in the center and the transmissive region TA is disposed to the left and right of the non-transparent region NTA. The first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 can be respectively set on the first column line RL1, the second column line RL2, the third column line RL3, and the fourth column line RL4 arranged side by side in the first direction Y. As shown in Figures 3A to 3C, the first type of pixel regions PX11, PX12 and PX13 may include blue (hereinafter referred to as B), white (hereinafter referred to as W), green (hereinafter referred to as G) and red (hereinafter referred to as R) sub-pixels SP1, SP2, SP3 and SP4, which are arranged sequentially in the non-transmissive region NTA in the first direction Y. As shown in Figures 4A to 4C, the second type of pixel regions PX21, PX22 and PX23 may include red (R), green (G), white (W) and blue (B) sub-pixels SP1, SP2, SP3 and SP4, which are arranged sequentially in the non-transmissive region NTA in the first direction Y. As shown in Figures 3A to 4C, in the pixel regions PX11, PX12, PX13, PX21, PX22, and PX23 according to various embodiments, the green sub-pixels and white sub-pixels can be concentrated in the center of the non-transmissive region NTA in the first direction Y. This avoids or reduces edge artifacts such as white and black lines at the edges of the image pattern that can occur due to the separation or differences in the separation distance between the green and white sub-pixels. As shown in Figures 3A to 4C, in each pixel region PX11, PX12, PX13, PX21, PX22, and PX23 according to various embodiments, the red sub-pixel can be configured to be adjacent to the green sub-pixel in the first direction Y. Therefore, color stripe artifacts that may occur at the edge of the image pattern due to the separation distance between the red and green sub-pixels can be prevented or reduced. As shown in Figures 3A to 4C, in the pixel regions PX11, PX12, PX13, PX21, PX22, and PX23 according to various embodiments, one of the second sub-pixel SP2 and the third sub-pixel SP3 centered in the first direction Y can be a green sub-pixel and the other can be a white sub-pixel. As shown in Figures 4A to 4C, if the second sub-pixel SP2 is a green sub-pixel, then the first sub-pixel SP1 can be a red sub-pixel, the third sub-pixel SP3 can be a white sub-pixel, and the fourth sub-pixel SP4 can be a blue sub-pixel. As shown in Figures 3A to 3C, if the third sub-pixel SP3 is a green sub-pixel, then the fourth sub-pixel SP4 is a red sub-pixel, the first sub-pixel SP1 is a blue sub-pixel, and the second sub-pixel SP2 is a white sub-pixel. Each of the multiple sub-pixels SP1 to SP4 may include a light-emitting element and a pixel circuit that independently drives the light-emitting element. The light-emitting element may be an organic light-emitting diode, a quantum dot light-emitting diode, or an inorganic light-emitting diode. The pixel circuit may include various configurations of thin-film transistors (TFTs), including driving TFTs that drive the light-emitting element, switching TFTs that transmit data signals to the driving TFTs, and storage capacitors that store the driving voltage of the driving TFTs. The pixel circuit may be electrically connected to signal lines configured in the display panel 100, including gate lines, data lines, power lines, etc. The power management circuits 800 and 800A can utilize externally supplied input voltage to generate and output various driving voltages for the operation of all configurations of the transparent display device, namely the display panel 100 and the display driver 500. The power management circuit 800A can further supply driving voltage to drive the light shield 1100 and the light shield driver 1200. The gate driver 300 can be controlled according to multiple gate control signals supplied by the timing controller 600 and can independently drive the gate lines of the display panel 100. The gate driver 300 can provide a scan signal of the gate on voltage to the corresponding gate line during the driving period of each gate line, and can provide a gate off voltage to the corresponding gate line during the non-driving period of each gate line. The gate driver 300 can be formed by a thin-film transistor in the display area AA and embedded in the bezel area of ​​the display panel 100 in the form of a gate in panel (GIP). According to one or more embodiments, the gate driver 300 embedded in the display panel 100 can receive multiple gate control signals from the timing controller 600 via a level offsetter. The level offsetter can receive control signals from the timing controller 600 and perform level offsetting or logic processing on them to generate multiple gate control signals and supply them to the gate driver 300. The gamma voltage generator 700 generates multiple reference gamma voltages with different gamma voltage levels and supplies them to the data driver 400. The gamma voltage generator 700 can generate multiple reference gamma voltages corresponding to the gamma characteristics of the display device according to the control of the timing controller 600 and supply them to the data driver 400. The gamma voltage generator 700 can adjust the reference gamma voltage levels according to the gamma data received from the timing controller 600 and output them to the data driver 400. The gamma voltage generator 700 can adjust the high-potential power supply voltage (as the maximum gamma voltage) according to the peak brightness control of the timing controller 600, and can adjust the multiple reference gamma voltages according to the adjusted high-potential power supply voltage and output them to the data driver 400. The data driver 400 can be controlled according to the data control signal supplied by the timing controller 600, and can convert digital data from the timing controller 600 into analog data signals using a digital-to-analog conversion circuit. The data driver 400 can subdivide multiple reference gamma voltages from the gamma voltage generator 700 into gradient voltages, and use the subdivided gradient voltages to convert the digital data into analog data signals. The data driver 400 can supply the converted data signals to the data lines of the display panel 100. Furthermore, the data driver 400, under the control of the timing controller 600, can supply a reference voltage to the reference line of the display panel 100. The data driver 400, under the control of the timing controller 600, can also supply a reference voltage for display and sensing purposes. Under the control of the timing controller 600, the data driver 400 uses a sensing unit to sense signals reflecting the driving characteristics of each sub-pixel SP1, SP2, SP3 and SP4 via a reference line through a voltage sensing method or a current sensing method. The timing controller 600 can receive source image data and timing control signals from the host system. The host system can be a system on a mobile device such as a computer, television system, set-top box, tablet, or mobile phone, or a system in a vehicle. The timing control signals may include dot clock, data enable signal, vertical synchronization signal, horizontal synchronization signal, etc. The timing controller 600 can control the gate driver 300 and the data driver 400 using timing control signals from the host system and internally stored timing setting information. The timing controller 600 can generate multiple gate control signals to control the drive timing of the gate driver 300 and supply them to the gate driver 300. The timing controller 600 can also generate multiple data control signals to control the drive timing of the data driver 400 and supply them to the data driver 400. The timing controller 600 can perform various image processing operations on input image data from the host system, including image quality correction, down-level correction, and brightness correction to reduce power consumption, and supply the processed image data to the data driver 400. The timing controller 600 can be represented as an image processing unit. In one or more embodiments, the timing controller 600 may use a peak luminance control (PLC) method to control the peak luminance based on the image data. The timing controller 600 may determine the average picture level (APL) of the image data, and the higher the average picture level, the lower the peak luminance can be set to reduce power consumption. In one or more embodiments, the timing controller 600 can cause the display device 1000 to operate in a sensing mode. In the sensing mode, the timing controller 600 can receive sensing data of the electrical characteristics of the display panel 100 through sensing circuits embedded in the data driver 400 and power management circuits 800, 800A. In one or more embodiments, the timing controller 600 may accumulate image data and predict a reduced-order region in the display panel 100 based on the accumulated data to determine the sensing region. In sensing mode, the timing controller 600 may supply sensing data, which utilizes the data driver 400 or power management circuits 800, 800A to sense the electrical characteristics of the sensing region of the display panel 100. Based on sensing data, the timing controller 600 can calculate the changes in the electrical characteristics (such as critical voltage offset values) of the driving transistors and / or light-emitting elements of each sub-pixel SP1, SP2, SP3, SP4, and can calculate and store compensation values ​​for these changes in memory. The timing controller 600 can compensate for image data by applying the compensation values ​​stored in memory to compensate for brightness deviations caused by deviations in the characteristics of each sub-pixel SP1, SP2, SP3, SP4, or to compensate for image retention caused by downsampling. According to one or more embodiments, the sensing mode of the display devices 1000 and 1000A can be executed according to the instructions of the host system, can be executed by the user through the request of the host system, or can be executed according to the driving sequence determined by the timing controller 600. According to one or more embodiments, as shown in FIG2, the transparent display device 1000A can operate in a screen key mode and a perspective key mode by controlling the light transmittance of the light-shielding plate 1100. The screen key mode may include a normal mode for displaying television images, etc. The perspective key mode may include a transparent mode. The timing controller 600 can determine whether the input video is in screen key mode or perspective key mode based on its type. In screen key mode, the timing controller 600 operates in normal mode, and under its control, the light-shielding driver 1200 can operate the light-shielding plate 1100 in a black-displaying light-shielding mode. Therefore, the display panel 100 can utilize the pixel area PX on the black background of the light-shielding plate 1100, visible through the transmission area TA, to display the screen image, thereby improving the visibility of the screen image. When in perspective key mode, under the control of timing controller 600, light shield driver 1200 can drive light shield 1100 in perspective mode. Therefore, the viewer can see the screen image displayed by pixel area PA, and the background behind is visible through light shield 1100 and the transmissive area TA of display panel 100. Figure 5 is an equivalent circuit diagram of an example configuration of each sub-pixel according to one or more embodiments of the present disclosure. As shown in Figure 5, each sub-pixel 10A includes a light-emitting element EL connected between a first power line VDDL providing a high-potential driving voltage ELVDD (first power supply voltage) and a second power line VSSL providing a low-potential driving voltage ELVSS (second power supply voltage), a pixel circuit containing first and second switching thin-film transistors ST1 and ST2 and a driving thin-film transistor DT, and a storage capacitor Cst for independently driving the light-emitting element EL. The light-emitting element EL may have an anode connected to the source node N2 of the driving thin-film transistor DT, a cathode connected to the second electric field line VSSL, and an organic light-emitting layer located between the anode and the cathode. The anode of each sub-pixel may be independent, but the cathode may be a common electrode shared by all sub-pixels. When the driving current is supplied by the driving thin-film transistor DT, the light-emitting element EL can generate light with a brightness proportional to the value of the driving current by injecting electrons from the cathode into the organic light-emitting layer and injecting holes from the anode into the organic light-emitting layer, and emit fluorescent or phosphorescent materials through the recombination of electrons and holes in the organic light-emitting layer. The first switching thin-film transistor ST1 is driven by the scan signal SCAN supplied to the gate line GL by the gate driver 300, and the data voltage Vdata supplied to the data line DL from the data driver 400 can be supplied to the gate node N1 that drives the thin-film transistor DT. The second switching thin-film transistor ST2 can be driven by a scan signal SCAN supplied from the gate driver 300 to the gate line GL, and a reference voltage Vref supplied from the data driver 400 to the reference line RL can be supplied to the source node N2 of the driving thin-film transistor DT. On the other hand, in sensing mode, the second switching thin-film transistor ST2 can provide a current reflecting the characteristics of the driving thin-film transistor DT or the characteristics of the light-emitting element EL to the reference line RL. The first switching thin-film transistor ST1 and the second switching thin-film transistor ST2 can be controlled by the same gate line, or as shown in Figure 5, they can be controlled by different gate lines. The storage capacitor Cst connected between the gate node N1 and the source node N2 of the driving thin-film transistor DT charges the driving voltage (Vgs) of the driving thin-film transistor DT to the differential voltage of the data voltage Vdata and the reference voltage Vref supplied to the gate node N1 and the source node N2, respectively, through the first switching thin-film transistor ST1 and the second switching thin-film transistor ST2. The charged driving voltage Vgs is maintained during the period when the first switching thin-film transistor ST1 and the second switching thin-film transistor ST2 are turned off. The driving thin-film transistor DT can control the luminous intensity of the light-emitting element EL by controlling the current Ids flowing to the light-emitting element EL according to the driving voltage Vgs charged in the storage capacitor Cst. In Figure 5, the gate line GL can be driven by the gate driver 300, receiving the data voltage Vdata and reference voltage Vref from the data driver 400, as well as the high-potential drive voltage ELVDD and low-potential drive voltage ELVSS from the power management circuits 800 and 800A. Figure 6 is an equivalent circuit diagram of an example configuration of each sub-pixel according to one or more embodiments of the present disclosure. As shown in Figure 6, each sub-pixel 10B may include a light-emitting element EL and a pixel circuit. The pixel circuit includes a driving thin-film transistor DT that supplies current to the light-emitting element EL, multiple thin-film transistors T1 to T6, and a storage capacitor Cst. The thin-film transistors in each pixel circuit may be made of polycrystalline silicon semiconductor, amorphous silicon semiconductor, or oxide semiconductor. For example, the driving thin-film transistor DT and thin-film transistors T1 to T6 may include polysilicon thin-film transistors having P-type channels utilizing polysilicon with fast mobility. On the other hand, the driving thin-film transistor DT and thin-film transistors T1 to T3, T5 to T6 can be constructed from polysilicon thin-film transistors with P-type channels, while the compensation thin-film transistor T4, which connects the driving thin-film transistor DT to the diode structure, can be constructed from an oxide thin-film transistor with N-type channels utilizing an oxide semiconductor having a smaller leakage current compared to polysilicon. The fourth switching thin-film transistor T4 can block leakage current to prevent flickering during low-speed operation with a relatively low screen refresh rate. The light-emitting element EL may include an anode connected to the drain electrode of the driving thin-film transistor DT via a light-emitting control thin-film transistor T5, a cathode connected to a second power line 110 providing a second power supply voltage ELVSS, and an organic light-emitting layer between the anode and the cathode. The light-emitting element EL can produce light with a brightness proportional to the value of the driving current supplied from the driving thin-film transistor DT. The compensating thin-film transistor T4 can be controlled by the first gate line 104 and can be connected to the second node N2, which is connected to the gate electrode of the driving thin-film transistor DT, and the third node N3, which is connected to the drain electrode of the driving thin-film transistor DT. The compensating thin-film transistor T4 can be turned on by the gate conduction voltage of the first gate signal SC1[n] supplied by the first gate line 104, connecting the gate electrode and drain electrode of the driving thin-film transistor DT, thereby connecting the driving thin-film transistor DT into a diode structure. The first gate line 104 can be arranged on two columns, namely the (n-1)th column line and the nth column line (where n is an integer greater than or equal to 2), which can reduce the size of the gate driver 300 embedded in the bezel area of ​​the display panel 100 and the size of the bezel. The switching thin-film transistor T1 is controlled by the second gate line 105 and can connect the data line 102 to the first node N1 connected to the source electrode of the driving thin-film transistor DT. The switching thin-film transistor T1 can be turned on by the gate conduction voltage of the second gate signal SC2[n] supplied by the second gate line 105, and can supply the data voltage Vdata supplied by the data line 102 to the source electrode of the driving thin-film transistor DT. The operation control thin-film transistor T2 is controlled by the light emission control line 111 and can connect the first power line 103 to the first node N1 connected to the source electrode of the driving thin-film transistor DT. The operation control thin-film transistor T2 can be turned on by the gate conduction voltage of the light emission control signal EM[n] supplied by the light emission control line 111, and supply the first power supply voltage ELVDD supplied by the first power line 103 to the source electrode of the driving thin-film transistor DT. The light-emitting control thin-film transistor T5 is controlled by the light-emitting control line 111 and can connect the third node N3, which is connected to the drain electrode of the driving thin-film transistor DT, to the fourth node N4, which is connected to the anode electrode of the light-emitting element EL. The light-emitting control thin-film transistor T5 can be turned on by the gate conduction voltage of the light-emitting control signal EM[n] supplied by the light-emitting control line 111, and can connect the drain electrode of the driving thin-film transistor DT to the anode electrode of the light-emitting element EL. The first initialization thin-film transistor T3 is controlled by the third gate line 106 and can connect the third node N3, which is connected to the drain electrode of the driving thin-film transistor DT, to the first initialization line 108. The first initialization thin-film transistor T3 can be turned on by the gate turn-on voltage of the third gate signal SC3[n] supplied by the third gate line 106, and can supply the first initialization voltage Vini, which is supplied via the first initialization line 108, to the third node N3, which is connected to the drain electrode of the driving thin-film transistor DT. The second initialization thin-film transistor T6 is controlled by the fourth gate line 107 and can be connected to the second initialization line 109 via the fourth node N4 connected to the anode of the light-emitting element EL. The second initialization thin-film transistor T6 can be turned on by the gate turn-on voltage of the fourth gate signal SC3[n+1] provided through the fourth gate line 107, and can be supplied with the second initialization voltage (VAR, anode reset voltage) provided by the second initialization line 109 to the fourth node N4 connected to the anode of the light-emitting element LED. The fourth gate line 107 can share the third gate line that supplies the third gate signal on the (n+1)th column line. A storage capacitor Cst can be connected between the first power line 103 and the second node N2, which is connected to the gate electrode of the driving thin-film transistor DT. The storage capacitor Cst can be charged by the voltage difference between the first power supply voltage ELVDD supplied by the first power line 103 and the data voltage Vdata supplied to the second node N2. The data voltage Vdata can be supplied from the data line 102 to the second node N2 by operating the control thin-film transistor T2, driving the thin-film transistor DT, and switching the thin-film transistor T1. While driving the thin-film transistor DT is connected to the diode structure through the compensation thin-film transistor T4, the storage capacitor Cst can sample and store the critical voltage Vth of driving the thin-film transistor DT, and can provide the data voltage (Vdata+Vth) compensated by the critical voltage Vth to the gate electrode of driving the thin-film transistor DT. Therefore, the storage capacitor Cst can be charged to a target voltage, which is the voltage difference between the first power supply voltage ELVDD and the data voltage (Vdata) compensated by the threshold voltage Vth of the driving thin-film transistor DT, and the target charging voltage can be used as the driving voltage Vgs between the gate and source electrodes of the driving thin-film transistor DT. In this way, the characteristic deviation of the driving thin-film transistor DT between sub-pixels can be compensated. The driving thin-film transistor DT can control the luminous intensity of the light-emitting element EL by controlling the current Ids flowing to the light-emitting element EL according to the driving voltage charged in the storage capacitor Cst. In Figure 6, gate lines 104, 105, 106, and 107 can be driven by gate driver 300, and light-emitting control line 111 can be driven by light-emitting control driver embedded in gate driver 300 and disposed in the bezel area of ​​display panel 100. Data voltage Vdata can be supplied from data driver 400. First power supply voltage ELVDD, second power supply voltage ELVSS, first initialization voltage Vini, and second initialization voltage VAR can be supplied from power management circuits 800 and 800A. Figure 7 is an example diagram illustrating the regions of each pixel according to one or more embodiments of the present disclosure, and Figures 8A to 8C are graphs illustrating the transmittance of a transparent display device in a comparative example and a transparent display device according to one or more embodiments of the present disclosure. According to one or more embodiments, as shown in FIG7, the pixel region PX may include a non-transmissive region NTA disposed at the center of the second direction X, and transmissive regions TA disposed on both sides of the non-transmissive region NTA in the second direction X. The non-transmissive region NTA may include emission regions EA1, EA2, EA3, and EA4 of red (R) sub-pixels SP1, green (G) sub-pixels SP2, white (W) sub-pixels SP3, and blue (B) sub-pixels SP4 arranged sequentially and side by side in the first direction Y. The pixel circuits of the red (R) sub-pixels SP1, green (G) sub-pixels SP2, white (W) sub-pixels SP3, and blue (B) sub-pixels SP4 may be disposed below and overlap with the light emission regions EA1, EA2, EA3, and EA4. The red (R) sub-pixel SP1, green (G) sub-pixel SP2, white (W) sub-pixel SP3, and blue (B) sub-pixel SP4 can be respectively connected to the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4, which extend from the left side of the non-transmissive region NTA along the first direction Y and are arranged side-by-side in the second direction X. The red (R) sub-pixel SP1, green (G) sub-pixel SP2, white (W) sub-pixel SP3, and blue (B) sub-pixel SP4 can share connections to the first electric field line VDDL, the reference line RL, and the second electric field line VSSL, which extend from the right side of the non-transmissive region NTA along the first direction Y and are arranged side-by-side in the second direction X. The red (R) sub-pixel SP1, green (G) sub-pixel SP2, white (W) sub-pixel SP3, and blue (B) sub-pixel SP4 can share a connection to the gate line GL extending in the second direction X. As shown in Figures 8A to 8C, according to one embodiment, the transmittance (55%) of a pixel region (PX) having a vertical array structure in which multiple light-emitting regions EA of four-color (red R, green G, white W, and blue B) sub-pixels are arranged side by side in the vertical direction is improved compared to the transmittance (45%) of a comparative example shown in Figures 8A and 8B, which has light-emitting regions EA of four-color (red R, green G, white W, and blue B) sub-pixels arranged in a matrix. Figure 9 is a diagram illustrating color edge phenomena based on the arrangement order of three-color subpixels according to a comparative example. Figures 10A to 11C are diagrams illustrating examples of edge artifact phenomena in a transparent display device according to a comparative example. Figures 12A to 12C are diagrams illustrating examples of edge artifact mitigation effects in a transparent display device according to one or more embodiments of the present disclosure. Figures 13A to 15B are diagrams illustrating examples of edge artifacts in a transparent display device according to a comparative example. Figures 16A and 16B are diagrams illustrating examples of edge artifact mitigation effects in a transparent display device according to one or more embodiments of the present disclosure. As shown in Figure 9, in the basic structure of stripes using three-color (red R, green G, blue B) subpixels, a RGB array structure with the green subpixels centered can display white lines without color edges. On the other hand, when displaying white lines using a GBR array structure with the green subpixels skewed to the left, a red edge appears at the right edge of the white line; conversely, when displaying white lines using a BRG array structure with the green subpixels skewed to the right, a blue edge appears at the left edge of the white line. When the red and green subpixels are separated by another subpixel (B), as in the GBR array structure, the color edges become more pronounced. As shown in Figures 10A to 10C, 13A, and 13B, it can be seen that the green sub-pixel G in pixel region PXa is not placed in the center, and the red sub-pixel R and the green sub-pixel G are separated from each other by the white sub-pixel W and the blue sub-pixel B. As shown in Figures 10A and 13A, for the display device according to the comparative example, using the pixel region PXa according to the comparative example, the red sub-pixel R / white sub-pixel W / blue sub-pixel B / green sub-pixel G are arranged in the vertical direction in sequence. Therefore, as shown in Figure 10B, it can be seen that the display device according to the comparative example has black lines (BL) and white lines (WL) on the edges of the green G and D patterns displayed on the white background, or as shown in Figure 10C, red stripes on the edges of the yellow line patterns, or as shown in Figure 13B, edge artifacts such as white lines, black lines, and colored stripes on the edges of the various colored box patterns. As shown in Figures 11A to 11C, 14, and 14B, in the display device of the comparison example utilizing the pixel region PXb, the red subpixel R, green subpixel G, blue subpixel B, and white subpixel W are arranged vertically in the order shown in Figures 11A and 14A, with the white subpixel W not placed in the center of the pixel region PXb. Therefore, as shown in Figure 11B, the display device of the comparison example can exhibit black lines (BL) and white lines (WL) at the edges of the G and D patterns displayed on a green background, or as shown in Figure 14B, artifacts such as white lines and black lines at the edges of various color patterns. However, as shown in Figure 10C, due to the adjacent placement of the red subpixel R and the green subpixel G in the pixel region PXb, the display device of the comparison example does not produce color edge artifacts in the yellow line pattern. As shown in Figures 12A to 12C, 16A, and 16B, in a display device utilizing a pixel region PX according to one or more embodiments, as shown in Figures 12A and 16A, the red subpixel R, green subpixel G, white subpixel W, and blue subpixel B are arranged vertically in sequence. The green subpixel G and white subpixel W are located at the center of the pixel region PX, and the red subpixel R and green subpixel G are adjacent. Therefore, as shown in Figure 12B, the display device according to one or more embodiments does not produce black or white line artifacts at the edges of the G and D patterns displayed on a white background in green. As shown in Figure 12C, no color edge artifacts are produced for the yellow line pattern. And as shown in Figure 16B, no edge defects such as white lines, dark lines, and color edge artifacts are produced at the edges of the various color patterns. As shown in Figures 15A and 15B, in the display device utilizing the pixel region PXc according to the comparison example, as shown in Figure 15A, the red sub-pixel R, white sub-pixel W, green sub-pixel G, and blue sub-pixel B are arranged vertically in sequence, with the red sub-pixel R and green sub-pixel G separated by the white sub-pixel W within the pixel region PXc. Therefore, as shown in Figure 15B, the display device according to the comparison example can produce edge defects such as color stripes at the edges of various color patterns. As described above, the transparent display device according to one or more embodiments can improve image quality by placing a green subpixel and a white subpixel in the center of the non-transparent area of ​​the four color subpixels in the non-transparent area of ​​each pixel area, and setting the red subpixel and the green subpixel adjacent to each other. A transparent display device according to one or more embodiments may include red / green / white / blue or blue / white / green / red subpixels arranged side by side in the non-transmissive area of ​​each pixel area in the vertical direction to improve image quality by reducing edge defects such as white lines, black lines and color stripes, and may achieve low power consumption by increasing the transmissive area to improve transmittance. A transparent display device according to one or more embodiments may include a plurality of pixel regions comprising a non-transmissive region and a transmissive region, wherein the non-transmissive region of each pixel region includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially in a first direction. One of the second and third sub-pixels may be a green sub-pixel, and the other may be a white sub-pixel. When the second sub-pixel is a green sub-pixel, the first sub-pixel may be a red sub-pixel; when the third sub-pixel is a green sub-pixel, the fourth sub-pixel may be a red sub-pixel. In a transparent display device according to one or more embodiments, the first to fourth sub-pixels may be red sub-pixels, green sub-pixels, white sub-pixels and blue sub-pixels arranged sequentially in a first direction. In a transparent display device according to one embodiment, the first to fourth sub-pixels may be blue sub-pixels, white sub-pixels, green sub-pixels and red sub-pixels arranged sequentially in a first direction. In each pixel region of the transparent display device according to one or more embodiments, the transmissive region may be disposed in the region to the left or right of the non-transmissive region, or may be disposed in the regions on the left and right sides of the non-transmissive region. A transparent display device according to one or more embodiments may include a plurality of pixel regions containing a non-transmissive region and a transmissive region, wherein the non-transmissive region of each pixel region may include red sub-pixels, green sub-pixels, white sub-pixels and blue sub-pixels arranged sequentially in the vertical direction. A transparent display device according to one or more embodiments may include a plurality of pixel regions containing a non-transmissive region and a transmissive region, wherein the non-transmissive region of each pixel region may include blue sub-pixels, white sub-pixels, green sub-pixels and red sub-pixels arranged sequentially in the vertical direction. The transparent display device according to one or more embodiments of this disclosure can be applied to a variety of electronic devices. For example, the transparent display device according to one or more embodiments of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, navigation devices, in-vehicle navigation devices, in-vehicle display devices, televisions, wallpaper display devices, signage devices, and home appliances. The features, structures, and effects described above are included in at least one or more embodiments of this disclosure, but are not limited to only one or more embodiments. Furthermore, the features, structures, and effects described in at least one embodiment of this disclosure can be implemented by those skilled in the art through combination or modification of other embodiments. Therefore, content related to combination and modification should be considered to fall within the scope of this disclosure. Various substitutions, modifications, and alterations are readily apparent to those skilled in the art within the scope of this disclosure without departing from the spirit and scope of the invention. Therefore, the scope of this disclosure is defined by the following claims, and all alterations or modifications derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of this invention. 100: Display panel; 102: Data line; 103: First power line; 104, 105, 106, 107: Gate line; 108: First initialization line; 109: Second initialization line; 110: Second power line; 111: Light emission control line; 200: Panel driver; 300: Gate driver; 400: Data driver; 500: Display driver; 600: Timing controller; 700: Gamma voltage generator; 800, 800A: Power management circuit; 1000, 1000A: Display device; 1100: Light shield; 1200: Light shield driver; 10A, 10B: Subpixel; AA: Display area; B: Blue subpixel; BL: Black line; BM: Black matrix; BR G: Blue, Red, Green; Cst: Storage Capacitor; DL, DL1, DL2, DL3, DL4: Data Line; DT: Driving Thin Film Transistor; EA, EA1, EA2, EA3, EA4: Emitting Region; EL: Light Emitting Element; ELVDD, ELVSS: Voltage; EM[n]: Light Emitting Control Signal; G: Green Subpixel; GBR: Green, Blue, Red; GL: Gate Line; N1, N2, N3, N4: Node; PX, PX11, PX12, PX13, PX21, PX22, PX23, PXa, PXb, PXc: Pixel Region; R: Red Subpixel; RL, RL1, RL2, RL3, RL4: Line; RGB: Red, Green, Blue; SC1[n] SC2[n], SC3[n], SC3[n+1]: Gate signal; SCAN: Scan signal; SP1, SP2, SP3, SP4: Sub-pixel; ST1, ST2: Switch; TA: Transmission region; T1, T2, T3, T4, T5, T6: Thin film transistor; W: White sub-pixel; WL: White line. The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. These drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Figure 1 is a block diagram illustrating a configuration example of a transparent display device according to one or more embodiments of the present disclosure. Figure 2 is a block diagram illustrating a configuration example of a transparent display device according to one or more embodiments of the present disclosure. Figures 3A to 3C are illustrations of exemplary pixel structures according to one or more embodiments of the present disclosure. Figures 4A to 4C are illustrations of exemplary pixel structures according to one or more embodiments of the present disclosure. Figure 5 is an equivalent circuit diagram of an example configuration of each sub-pixel according to one or more embodiments of the present disclosure. Figure 6 is an equivalent circuit diagram of an example configuration of each sub-pixel according to one or more embodiments of the present disclosure. Figure 7 is an example diagram illustrating the regions of each pixel according to one or more embodiments of the present disclosure. Figures 8A to 8C are graphs illustrating the transmittance of a transparent display device in a comparative example and a transparent display device according to one or more embodiments of the present disclosure. Figure 9 is a diagram illustrating the color edge phenomenon based on the arrangement order of the three-color sub-pixels according to the comparative example. Figures 10A to 10C and Figures 11A to 11C are examples of edge artifacts in transparent display devices illustrated according to comparative examples. Figures 12A to 12C are illustrations of examples of edge artifact mitigation effects of transparent display devices according to one or more embodiments of the present disclosure. Figures 13A, 13B, 14A, 14B, 15A, and 15B are examples of edge artifacts in a transparent display device illustrated according to a comparative example. Figures 16A and 16B are illustrations of examples of edge artifact mitigation effects of a transparent display device according to one or more embodiments of the present disclosure. 100: Display panel 200: Panel driver 300: Gate Driver 400: Data Drive 500: Display driver 600: Timing Controller 700: Gamma Voltage Generator 800: Power Management Circuit 1000: Display device AA: Display area EA: Launch Area PX: Pixel area TA: Transmission area

Claims

1. A transparent display device, comprising: a display area having a plurality of pixel areas, the pixel areas having a non-transparent area and a transmissive area; a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, arranged sequentially in the non-transparent area of ​​each of the pixel areas in a vertical direction; and a black matrix surrounding the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel in the non-transparent area, but not surrounding the transmissive area, wherein one of the second sub-pixel and the third sub-pixel is a green sub-pixel, and the first sub-pixel... The second sub-pixel and the third sub-pixel are white sub-pixels, and the first sub-pixel is a red sub-pixel when the second sub-pixel is a green sub-pixel, or the fourth sub-pixel is a red sub-pixel when the third sub-pixel is a green sub-pixel, wherein the aperture ratio of each of the red light-emitting regions of the red sub-pixel and the blue light-emitting regions of the blue sub-pixel is greater than the aperture ratio of each of the green light-emitting regions of the green sub-pixel and the white light-emitting regions of the white sub-pixel; and wherein the aperture ratio of the green light-emitting region is the same as the aperture ratio of the white light-emitting region.

2. The transparent display device as claimed in claim 1, wherein the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are red sub-pixels, green sub-pixels, white sub-pixels and blue sub-pixels arranged sequentially in the vertical direction.

3. The transparent display device as described in claim 1, wherein the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are blue sub-pixels, white sub-pixels, green sub-pixels and red sub-pixels arranged sequentially in the vertical direction.

4. The transparent display device as claimed in claim 1, wherein the transmissive region is disposed to the left or right of the non-transmissive region in the pixel regions, or disposed to the left and right of the non-transmissive region.

5. The transparent display device as described in claim 2 or 3, wherein: The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are respectively connected to a first data line, a second data line, a third data line, and a fourth data line. The first data line to the fourth data line are located on the left side of the non-transmissive region and extend along the vertical direction. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are connected to each of a first power line, a reference line, and a second power line. The first power line, the reference line, and the second power line are located on the right side of the non-transmissive region and extend along the vertical direction. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are connected to a gate line. The gate line is located between the second sub-pixel and the third sub-pixel and extends along a horizontal direction.

6. The transparent display device as described in claim 5, wherein: The red emitting area of ​​the red sub-pixel, the green emitting area of ​​the green sub-pixel, and the blue emitting area of ​​the blue sub-pixel overlap with the second data line, the third data line, and the fourth data line on the left side of the non-transparent area, and overlap with the first power line and the reference line on the right side of the non-transparent area, but do not overlap with the first data line and the second power line. The white emitting area of ​​the white sub-pixel overlaps with the first data line, the second data line, the third data line, and the fourth data line on the left side of the non-transparent area, and overlaps with the first power line, the reference line, and the second power line on the right side of the non-transparent area.

Images