Package structures and methods of forming the same

Abstract

The embodiments disclosed herein relate to a method for forming a package structure. The method includes: depositing a first layer on the front side of a wafer and depositing a second layer on the back side of the wafer; depositing a third layer on the first layer and a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to packaging structures and methods for forming the same. [Previous Technology]

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured as follows: various insulating or dielectric layers, conductive layers, and semiconductor layers of material are sequentially deposited on a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit elements and components thereon. The semiconductor devices on the substrate are combined into individual wafers to achieve the designed function. In some cases, two or more substrates with different devices can be combined to form a complex substrate, wherein each individual die comprises two or more dies. For example, a substrate with logic devices can be combined with a substrate with an image sensor, such that the logic devices are connected to the image sensor, and each individual wafer may include a logic wafer and an image sensor wafer. The individual wafers are individualized by dicing the integrated circuit along scribe lines. For example, the individual wafers are then individually packaged into multi-wafer modules or other types of packages.

[0003] The semiconductor industry is increasing the integration density of various electronic components by continuously shrinking the minimum feature size, which allows more components to be integrated into a given area. In some applications, these smaller electronic components require packaging systems that are smaller and more advanced than those of the past. Furthermore, as more and more metal layers are added to the back end of line (BEOL) process, the warpage of the single-chip system (SOC) substrate is becoming increasingly high, which greatly reduces the chip-on-substrate process window of the system-on-chip (SoIC) and leads to low bonding yields.

[0004] Therefore, an improved packaging structure is necessary. [Summary of the Invention]

[0005] Some embodiments of this disclosure provide a method comprising: depositing a first layer on a front side of a wafer and depositing a second layer on a back side of the wafer; depositing a third layer on the first layer and depositing a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and depositing a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

[0006] Some other embodiments of this disclosure provide a method comprising: providing a first device structure, wherein the first device structure has a first surface and a second surface opposite to the first surface, and the second surface has a first cross-sectional profile; depositing a first structure on the first surface, wherein the first structure causes the second surface to have a second cross-sectional profile different from the first cross-sectional profile; and incorporating the first device structure into a second device structure.

[0007] Some further embodiments of this disclosure provide a method comprising: bonding an intercalation substrate to one or more dies; removing a portion of the intercalation substrate to expose one or more vias; depositing a structure on the intercalation substrate and the vias, comprising: depositing a first protective layer on the intercalation substrate and the vias; depositing a first buffer layer on the first protective layer; depositing a second protective layer on the first buffer layer; and depositing a second buffer layer on the second protective layer; removing the structure; depositing a dielectric material on the intercalation substrate and the vias; and forming one or more electrical connectors in the dielectric material.

Implementation Method

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference digits and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, spatially related terms (e.g., "below," "below," "lower than," "higher than," "above," "above," "top," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0017] Embodiments of this disclosure relate to methods for processing and bonding substrates to manufacture integrated circuit wafers. The substrate may include semiconductor devices formed on the front side of the substrate and may be referred to as a device substrate. Specifically, embodiments of this disclosure provide a method for depositing a backside structure to protect devices on the substrate and / or adjust substrate warpage during bonding and packaging processes. In some embodiments, the backside structure is deposited in a batch processing chamber, wherein layers of the backside structure are formed on both the front and back sides of the substrate. Layers formed on the back side of the substrate can reduce cavity defects.

[0018] Figures 1A, 1B, 1C, 1D, 1E, and 1F are schematic cross-sectional views of a package structure 100 manufactured according to embodiments of the present disclosure. As shown in Figure 1A, front and back layers 104F and 104B are deposited on the front and back layers 102F and 102B of wafer 102, respectively, and front and back layers 106F and 106B are deposited on the front and back layers 104F and 104B, respectively. In some embodiments, wafer 102 is a blank wafer made of the following: elemental semiconductors, such as crystalline silicon or crystalline germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), combinations thereof, or other suitable materials. In some embodiments, wafer 102 includes multilayer semiconductors, semiconductor-on-insulator (SOI), such as silicon-on-insulator or germanium-on-insulator.

[0019] In some embodiments, the front layer 104F and the back layer 104B are formed simultaneously and have substantially the same properties, such as composition and thickness. For example, the front layer 104F and the back layer 104B are deposited simultaneously in a process chamber, wherein both the front layer 102F and the back layer 102B of wafer 102 are exposed to the processing environment. The front layer and the back layer 104F, 104B may include any suitable dielectric material, such as oxides, such as SiO, SiO2, SiNO, SiONC, etc. In some embodiments, the front layer and the back layer 104F, 104B may include semiconductors, such as SiGe, SiP, etc. In some embodiments, when wafer 102 is a silicon wafer, the front dielectric layer 104F and the back dielectric layer 104B are made of or include silicon oxide. In some embodiments, the front layer and the back layer 104F, 104B may be deposited by any suitable process. In some embodiments, the front and back layers 104F, 104B are formed by introducing oxide precursors into the process chamber. In some embodiments, one or more cleaning processes may be performed prior to the formation of the front and back layers 104F, 104B to remove native oxides and / or contaminants from the wafer 102.

[0020] The front layer 104F is sometimes referred to as a backing layer for subsequent patterning processes. In some embodiments, the front layer 104F and the back layer 104B have the same or different thicknesses T1. In some embodiments, the thickness T1 ranges from about 20 angstroms to about 2000 angstroms, for example from about 20 angstroms to about 60 angstroms.

[0021] In some embodiments, the front layer 106F and the back layer 106B are formed simultaneously and have substantially the same characteristics, such as composition and thickness. For example, the front layer 106F and the back layer 106B are formed simultaneously in a process chamber, wherein both the front dielectric layer 104F and the back dielectric layer 104B are exposed to the processing environment. In some embodiments, dielectric layers 104F, 104B, 106F, and 106B are deposited in the same process chamber.

[0022] The front and back layers 106F and 106B may comprise any suitable dielectric or semiconductor material, such as nitrides, like SiN, SiNO, Si3N4, SiNC, SiONC, etc. In some embodiments, the front and back layers 106F and 106B may comprise semiconductors, such as SiGe, SiP, etc. The materials of the front and back layers 106F and 106B are different from the materials of the front and back layers 104F and 104B. In some embodiments, the front layer 106F and the back layer 106B are made of or comprise nitrides, such as silicon nitride. The front and back layers 106F and 106B can be deposited by any suitable process. In some embodiments, the front and back layers 106F and 106B are formed by flowing a nitrogen-containing precursor and a semiconductor-containing precursor into a process chamber. The front layer 106F and the back layer 106B have the same or different thicknesses T2. In some embodiments, the thickness T2 ranges between about 100 angstroms and about 600 angstroms. The front layer 106F can be used as a hard mask layer during subsequent patterning processes. In some embodiments, the thickness T2 of the front layer 106F is greater than the thickness T1 of the front layer 104F. In some embodiments, the ratio R1 of the thickness T1 of the front layer 104F to the thickness T2 of the front layer 106F is between about 1:1 and about 1:18, for example, between about 1:9 and about 1:10.

[0023] While forming the front layer 104F and front layer 106F to enable subsequent FEOL processes, the back layer 104B and back layer 106B remain on the back side 102B of the wafer 102 during wafer processing and can provide protection for the wafer 102. However, during certain processes, such as combined processes and wet cleaning processes, the back layers 104B and 106B, formed simultaneously with the front layers 104F and 106F respectively, cannot provide sufficient protection for the wafer 102, resulting in cracks or cavity defects in the wafer 102. The embodiments disclosed herein provide an improved back side structure to prevent damage to the wafer 102 during wafer processing.

[0024] As shown in FIG1B, an etch stop layer 108 is deposited on the front layer 106F. The etch stop layer 108 may be made of or comprise any suitable material having an etch selectivity different from that of the front layer 106F. In some embodiments, the etch stop layer 108 comprises the same material as the front layer 104F. The etch stop layer 108 may have a thickness T3. In some embodiments, the thickness T3 ranges from about 50 angstroms to about 1000 angstroms.

[0025] In some embodiments, an etch stop layer 108 is formed in a process chamber on the back side of the package structure 100 where it is not exposed to the processing environment. Therefore, no material is formed on the back side layer 106B during the formation of the etch stop layer 108. The etch stop layer 108 can be formed by any suitable process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

[0026] As shown in FIG1C, a front layer 110F and a back layer 110B are formed on the etch stop layer 108 and the back layer 106B, respectively. Similar to the front and back layers 104F, 104B and the front and back layers 106F, 106B, the front layer 110F and the back layer 110B are formed simultaneously and have substantially the same characteristics, such as composition and thickness. The front layer 110F and the back layer 110B are formed simultaneously in a processing chamber where both the etch stop layer 108 and the back layer 106B are exposed to the processing environment.

[0027] The back layer 110B has a thickness T4. In some embodiments, the thickness T4 ranges between about 100 angstroms and about 1600 angstroms. In some embodiments, the back layer 110B comprises the same material as the back layer 106B, and the back layer 110B and the back dielectric layer 106B have a combined thickness T5. In some embodiments, the thickness T5 ranges from about 200 angstroms to about 20000 angstroms. The back layers 106B and 110B having a thickness T5 can improve cavity defects during the bonding process. Furthermore, in embodiments where the back layers 106B and 110B are made of silicon nitride, silicon nitride can cause greater stress and affect the warpage of the package structure 100. In some embodiments, the ratio R2 of the thickness T1 of the back layer 104B to the combined thickness T5 of the back layers 106F and 110F is between about 1:20 and about 1:60. A smaller ratio R2 compared to ratio R1 (i.e., a larger thickness T5 compared to thickness T2) can improve cavity defects, stress, and warpage adjustment in the package structure 100.

[0028] As shown in FIG1C, back layer 110B, back layer 106B, and back layer 104B form back structure 112. Back structure 112 can be retained on wafer 102 during wafer processing to protect the back side 102B of wafer 102. In some embodiments, back structure 112 can also be used as a stress adjustment or warpage adjustment structure to achieve a certain warpage in package structure 100.

[0029] As shown in FIG1D, the front layer 110F is removed while the back layer 110B is retained. In some embodiments, the package structure 100 is placed in a process chamber where the back layer 110B is not exposed to the processing environment. The process chamber may be a dry etching chamber, such as a plasma etching chamber. In some embodiments, the front layer 110F is removed by a plasma etching process utilizing a plasma source and an etchant. The plasma source may be an inductively coupled plasma (ICP) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, a capacitor coupled plasma (CCP) source, etc. In some embodiments, the etchant may include tetrafluoromethane (CF4), difluoromethylene (CH2F2), or hexafluoroethane (C2F6), and oxygen and / or nitrogen may be selectively added to control the etching rate and etching selectivity. In some embodiments, the etchant has higher etching selectivity for the front layer 110F relative to the etch stop layer 108. The etch stop layer 108 allows the removal of the front layer 110F without damaging the front layer 106F.

[0030] As shown in FIG1E, the etch stop layer 108 is removed. The etch stop layer 108 can be removed by any process that does not substantially affect the front layer 106F. In some embodiments, a wet etching process is performed to remove the etch stop layer 108, while the front layer 106F is substantially unaffected by the wet etching process. In some embodiments, the wet etching process includes immersion in diluted HF.

[0031] In some embodiments, the package structure 100 includes a wafer 102, front layers 104F and 106F disposed on the front side 102F of the wafer 102, and back layers 104B, 106B, and 110B disposed on the back side 102B of the wafer 102. In some embodiments, the front layer 104F and the back layer 104B each comprise silicon oxide, and the front layer 106F and the back layers 106B and 110B each comprise silicon nitride. The front layers 104F and 106F can be used as mask structures during the patterning process. The back layer 104B can be used as a transition layer because the material of the back layer 104B has better lattice matching with the material of the wafer 102 compared to the material of the back layer 106B. Back layers 106B and 110B can be used as protective layers to protect wafer 102, for example, by preventing cracks or cavities from appearing on the back side 102B of wafer 102 due to the characteristics of back layers 106B and 110B and their combined thickness T5. If back layers 106B and 110B are formed directly on the back side 102B of wafer 102 without back layer 104B, then back layers 106B and 110B may be easily peeled off from the back side 102B of wafer 102.

[0032] After removing the etch stop layer 108, a FEOL process is performed on wafer 102 to form a plurality of devices (not shown), and a back-end (BEOL) process can be performed to form an interconnect structure 120 on wafer 102, as shown in FIG1F. In some embodiments, the plurality of devices include a plurality of application-specific integrated circuit (ASIC) devices. In some embodiments, the plurality of devices constitute logic circuits, storage circuits, sensor circuits, etc. In some embodiments, the plurality of devices constitute control circuitry for sensor circuits. In some embodiments, the plurality of devices include transistors, capacitors, diodes, resistors, etc. In some embodiments, the devices are transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, PFETs / NFETs, or other suitable transistors. The transistor can be a planar field-effect transistor (FET), a FinFET, a nanostructure transistor, or other suitable transistor. Nanostructured transistors may include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor with gate electrodes surrounding the channel.

[0033] The interconnect structure 120 can be formed using BEOL fabrication technology. BEOL includes the formation and patterning of dielectric layers and conductive metal layers. The interconnect structure 120 includes a plurality of conductive features 118, such as conductive lines and conductive vias, embedded in the dielectric structure 116.

[0034] As shown in FIG1F, the package structure 100 further includes a structure 150 bonded to the interconnect structure 120. In some embodiments, the structure 150 includes a CMOS image sensor (CIS) device. In some embodiments, the CIS device is a back-illuminated (BSI) CIS device. For example, in some embodiments, the structure 150 includes an interconnect structure 151 and a wafer 158 disposed on the interconnect structure 151. The interconnect structure 151 includes a dielectric layer 152 and conductive features 154 embedded in the dielectric layer 152. In some embodiments, the top surface of the interconnect structure 120 is configured to be bonded to the top surface of the interconnect structure 151 of the structure 150. A microlens array 156 may be formed on the wafer 158. Thus, in some embodiments, the wafer 102 is a logic circuit wafer including logic circuitry, and the structure 150 is a sensor wafer having BSI sensing integrated circuitry. The logic circuit wafer and the sensor wafer are bonded to form a three-dimensional integrated circuit (3DIC).

[0035] The logic circuit wafer and the sensor wafer are bonded through any suitable process, such as direct bonding, hybrid bonding, etc. Pressure may be applied to the package structure 100 during the bonding process. The back cover structure 112 protects the back cover 102B of the wafer 102 during the bonding process. Furthermore, the back cover structure 112 protects the wafer 102 from damage by processing chemicals during the wet etching process.

[0036] Figures 2A, 2B, 3A, 3B, 4A, and 4B are schematic side views of two device structures 200 and 202 to be combined according to some embodiments. As shown in Figure 2A, device structure 200 and device structure 202 will be combined. In some embodiments, device structures 200 and 202 are wafers having devices and interconnect structures formed thereon. For example, device structure 200 may include wafer 102 of FIG. 1F, a plurality of devices, and interconnect structures 120, and device structure 202 may include interconnect structure 151 of FIG. 1F, wafer 158, and microlens array 156. In some embodiments, device structure 200 is a die, and device structure 202 is a die. As shown in Figure 2A, device structure 200 has a bonding surface 204 that will be bonded to bonding surface 206 of device structure 200. Bonding surface 204 may be the top surface of the topmost layer of device structure 200. For example, mating surface 204 may be the top surface of interconnect structure 120 (FIG. 1F). Mating surface 206 may be the top surface of the topmost layer of device structure 202. For example, mating surface 206 may be the top surface of interconnect structure 151 (FIG. 1F). In some embodiments, the cross-sectional profile of mating surface 204 does not match the cross-sectional profile of mating surface 206. For example, as shown in FIG. 2A, mating surface 204 is substantially flat, while mating surface 206 is curved, for example, having a concave cross-sectional profile.

[0037] In some embodiments, to alter the cross-sectional profile of the bonding surface 204, a back structure 210 is formed on the back surface 208 of the device structure 200, as shown in FIG2B. The back structure 210 includes at least one protective layer 212 and at least one buffer layer 214. In some embodiments, the protective layer 212 comprises the same material as the back layer 104B, and the buffer layer 214 comprises the same material as the back layer 106B. In some embodiments, two or more protective layers 212 and two or more buffer layers 214 are stacked alternately, as shown in FIG2B. As described above, the material of the protective layer 212 and the material of the wafer 102 have better lattice matching than the material of the buffer layer 214. Furthermore, the protective layer 212 tends to cause concave (smile-shaped) warpage, while the buffer layer 214 tends to cause convex (frowning) warpage. Therefore, in some embodiments, the thickness of the buffer layer 214 is much greater than the thickness of the protective layer 212 to cause concave warpage. As shown in Figure 2B, after the back structure 210 is formed on the back surface 208 of the device structure 200, the device structure 200 has a convex warp, and the mating surface 204 has a convex cross-sectional profile. The convex cross-sectional profile of the mating surface 204 matches the concave cross-sectional profile of the mating surface 206. Therefore, the mating process for mating the device structure 200 and the device structure 202 is improved.

[0038] In some embodiments, as shown in FIG3A, device structure 200 includes a curved (e.g., having a convex cross-sectional profile) mating surface 204, and device structure 202 includes a curved (e.g., having a convex cross-sectional profile) mating surface 206. In some embodiments, the cross-sectional profile of mating surface 204 is altered by forming a back structure 210 on the back surface 208 of device structure 200, as shown in FIG3B. As described above, back structure 210 includes alternating protective layers 212 and buffer layers 214. In some embodiments, the thickness of protective layer 212 is greater than the thickness of buffer layer 214 because protective layer 212 tends to cause concave warping. Therefore, with the back structure 210 having a thicker protective layer 212, the cross-sectional profile of mating surface 204 changes from convex to concave, as shown in FIG3B. The concave profile of mating surface 204 matches the convex profile of mating surface 206, as shown in FIG3B.

[0039] In some embodiments, as shown in FIG4A, device structure 200 includes a curved (e.g., having a convex cross-sectional profile) mating surface 204, and device structure 202 includes a curved (e.g., having a convex cross-sectional profile) mating surface 206. In some embodiments, the cross-sectional profiles of both mating surfaces 204 and 206 are altered by forming a back structure 210 on the back surface 208 of device structure 200 and the back surface 216 of device structure 202, as shown in FIG4B. As described above, the back structure 210 includes alternating protective layers 212 and buffer layers 214. In some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214 because the protective layer 212 tends to cause concave warping. Therefore, with the back structure 210 having a thicker protective layer 212, the cross-sectional profile of mating surface 204 changes from convex to concave, as shown in FIG4B. In some embodiments, the convex mating surface 206 of device structure 202 does not match the concave mating surface 204 of device structure 200. Therefore, a back surface structure 210 is formed on the back surface 216 of device structure 200 to change the curvature of mating surface 206 of device structure 200. In some embodiments, mating surface 206 becomes more convex due to the addition of back surface structure 210, which includes a protective layer 212 that is thicker than the buffer layer 214. In some embodiments, mating surface 206 becomes less convex due to the addition of back surface structure 210, which includes a buffer layer 214 that is thicker than the protective layer 212. By changing the cross-sectional profile of mating surface 204 from convex to concave, and by changing the cross-sectional profile of mating surface 206 from convex to more convex or less convex, the matching of mating surfaces 204 and 206 is improved.

[0040] The backside structure 210 shown in Figures 2B, 3B, and 4B alters the warpage of the device structure 200 (and device structure 202 in Figure 4B) to change the cross-sectional profile of the bonding surface 204 (and bonding surface 206 in Figure 4B), so that bonding surfaces 204 and 206 match. Furthermore, the backside structure 210 protects the back surface 208 of the device structure 200 (and the back surface 216 of the device structure 202) during the bonding process, similar to the backside structure 112 of the protective wafer 102 in Figure 1F.

[0041] Device structures 200 and 202 can be any suitable structure. In some embodiments, device structure 200 is a logic wafer, device structure 202 is another logic wafer, and the combination of device structures 200 and 202 is a wafer-to-wafer combination. In some embodiments, device structure 200 is a die, device structure 202 is a die, and the combination of device structures 200 and 202 is a die-to-die combination. In some embodiments, device structure 200 is a wafer, device structure 202 is a die, and the combination of device structures 200 and 202 is a die-to-wafer combination. The combination of device structures 200 and 202 can form other types of packages, such as chip-on-wafer-on-substrate (CoWoS) packages, integrated system-on-chip (SoIC) packages, stacked memory device packages, etc.

[0042] Figures 5A and 5B are schematic side views of a back structure 210 according to some embodiments. In some embodiments, the back structure 210 includes alternating protective layers 212 and buffer layers 214, as shown in Figure 5A. The number of protective layers 212 can range from 1 to 50, and the number of buffer layers 214 can range from 1 to 50. In some embodiments, the thickness of the protective layers 212 is substantially fixed, and the thickness of the buffer layers 214 is substantially fixed. In some embodiments, the thickness of the protective layers 212 is substantially the same as the thickness of the buffer layers 214. In some embodiments, the thickness of the protective layers 212 is significantly different from the thickness of the buffer layers 214. As described above, in some embodiments, the thickness of the protective layers 212 is greater than the thickness of the buffer layers 214 to cause concave warping. In some embodiments, the thickness of the buffer layers 214 is greater than the thickness of the protective layers 212 to cause convex warping.

[0043] In some embodiments, the thickness of the buffer layer 214 is not fixed, as shown in FIG5B. For example, the backside structure 210 includes a protective layer 212 and buffer layers 214a-c. Buffer layer 214a is closest to the backside of the wafer (or die) on which the backside structure 210 is formed, and buffer layer 214c is furthest from the backside of the wafer (or die). In some embodiments, the thickness of buffer layers 214a-c increases in the direction away from the wafer. For example, buffer layer 214a has a first thickness, buffer layer 214b has a second thickness greater than the first thickness, and buffer layer 214c has a third thickness greater than the second thickness. As described above, a protective layer 212 is formed between the buffer layer 214 and the wafer due to the lattice mismatch between the buffer layer 214 and the wafer. In some embodiments, the thickness of the buffer layer 214 is increased to induce convex warping of the wafer. If the thickness of the buffer layer 214 is greater than a threshold, the buffer layer 214 may be easily peeled off. Therefore, to accommodate the thicker buffer layer 214, an additional protective layer 212 is formed in the backside structure 210 to separate the thicker buffer layer 214. As the buffer layer 214 moves further away from the wafer, the risk of stripping decreases. Therefore, the thickness of the buffer layer 214 increases as it moves further away from the wafer. Although Figure 5B shows three protective layers 212 and three buffer layers 214a-c, other numbers of protective layers 212 and buffer layers 214a-c may also be used. In some embodiments, the backside structure 210 includes alternating protective layers 212 and buffer layers 214, and the thickness of the buffer layer 214 increases in the direction away from the wafer (or grain) on which the backside structure 210 is formed. The thickness of the protective layer 212 may remain substantially constant.

[0044] In some embodiments, the thickness of the protective layer 212 increases in the direction away from the wafer, while the thickness of the buffer layer 214 remains constant. In some embodiments, the buffer layer 214 provides protection for the wafer, and the protective layer 212 is softer than the buffer layer 214 and can provide cushioning when the wafer is held by a substrate holder.

[0045] Figures 6A and 6B are schematic side views of a device structure 200 manufactured according to some embodiments. In some embodiments, as shown in Figure 6A, the device structure 200 is placed in a process chamber, wherein both the front and back sides of the device structure 200 are exposed to the processing environment. Next, a back structure 210 is formed on the back side of the device structure 200, and a front structure 250 is formed on the front side of the device structure 200. In some embodiments, the back structure 210 and the front structure 250 are formed simultaneously. The layers of the back structure 210 are formed sequentially, and the layers of the front structure 250 are formed simultaneously with the corresponding layers of the back structure 210. Since the front structure 250 and the back structure 210 are formed simultaneously on the device structure 200, the warping of the device structure 200 is not affected, because the front structure 250 and the back structure 210 are formed on the front and back sides of the device structure 200, respectively.

[0046] Next, as shown in FIG6B, the front structure 250 is removed. The device structure 200 having the front structure 250 and the back structure 210 can be placed in an etching chamber, wherein the back structure 210 is not exposed to the processing environment. The layers of the front structure 250 can be removed by one or more etching processes. The etching process can be a dry etching process, a wet etching process, or a combination thereof. After the front structure 250 is removed, the warpage (or no warpage) of the device structure 200 is adjusted to better match the warpage of another device structure (e.g., device structure 202) to which the device structure 200 will be bonded.

[0047] In some embodiments, the device structure 200 is a blank wafer or a blank carrier wafer. The backside structure 210 can adjust the warpage of the blank wafer so that, after components are formed or bonded to the blank wafer, the warpage can match the warpage of the device of the elements to be bonded to the blank wafer.

[0048] In some embodiments, the back structure 210 is formed in a process chamber in which the back of the device structure 200 is exposed to the processing environment, while the front of the device structure 200 is not exposed to the processing environment. The back structure 210 is then formed on the back of the device structure 200, and the front structure 250 is not formed on the front of the device structure 200.

[0049] Figures 7A, 7B, 7C, 7D, and 7E are schematic side views of a package structure 100 manufactured according to some embodiments. In some embodiments, as shown in Figure 7A, the package structure 100 is a CoWoS package. The package structure 100 includes a carrier 302, an adhesive layer 304 disposed on the carrier 302, and a plurality of dies 308 disposed on the adhesive layer 304. The dies 308 can be any suitable die, such as an integrated circuit die. The dies 308 can be separated by a dielectric material 306. The dielectric material 306 can be any suitable dielectric material. In some embodiments, the dielectric material 306 is a molding material for encapsulating the dies 308. An interconnect structure 310 is disposed on the dies 308. The interconnect structure 310 includes conductive features 312 formed in one or more dielectric layers. The interconnect structure 310 is bonded to an interconnect structure 314. Interconnect structure 314 may include conductive features that electrically connect to conductive features 312 of interconnect structure 310. Interconnect structures 310 and 314 can be bonded by any suitable process, such as direct bonding or hybrid bonding. An interposer substrate 320 is disposed on interconnect structure 314, and a plurality of vias 318 are formed in the interposer substrate 320. In some embodiments, the vias 318 are through-holes penetrating the substrate. Interposer substrate 320 and interconnect structure 314 may be formed separately from die 308 and interconnect structure 310. Similarly, die 308 and interconnect structure 310 may be formed on carrier 302 before being bonded to interconnect structure 314 and interposer substrate 320.

[0050] As shown in FIG. 7B, the intercalator substrate 320 is thinned to expose the via 318. The intercalator substrate 320 can be thinned by grinding, polishing, etching, sintering, other suitable processes, or combinations thereof. Next, as shown in FIG. 7C, a backside structure 210 is formed on the intercalator substrate 320. The backside structure 210 may include alternating protective layers 212 and buffer layers 214, as shown in FIG. 7C. In some embodiments, the intercalator substrate 320 is a silicon substrate, and the protective layer 212 is formed on the intercalator substrate 320 due to better lattice matching. As mentioned above, the thickness of the buffer layer 214 may vary, for example, increasing in the direction away from the intercalator substrate 320. In some embodiments, the thickness of the buffer layer 214 is greater than the thickness of the protective layer 212 to cause a convex warping of the intercalator substrate 320. In some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214 to cause a concave warping of the intercalator substrate 320.

[0051] In some embodiments, as shown in FIG7D, the backside structure 210 is removed, while the interfacing substrate 320 retains the warpage resulting from the presence of the backside structure 210. In other words, once the backside structure 210 forms warpage on the interfacing substrate 320, removing the backside structure 210 will not affect the warpage. A dielectric material 322 is deposited on the interfacing substrate 320, and an electrical connector 324 is formed in the dielectric material 322. The dielectric material 322 may include any suitable dielectric material. In some embodiments, the dielectric material 322 includes a polymer, such as polyimide. The electrical connector 324 electrically connects to the corresponding via 318. The electrical connector 324 may be a solder ball, metal pillar, controlled collapse wafer connection (C4) bump, microbump, bump formed by electroless nickel-palladium-immersion gold (ENEPIG) technology, etc. The electrical connector 324 may be formed by common methods such as vapor deposition, electroplating, printing, solder transfer, balling, etc.

[0052] In some embodiments, the back structure 210 is not removed, and the electrical connector 324 is formed in the back structure 210. For example, the electrical connector 324 extends through the protective layer 212 and the buffer layer 214 of the back structure 210 to electrically connect to the through hole 318.

[0053] As shown in FIG. 7E, the package structure 100 is flipped and attached to the printed circuit board (PCB) 330, and the carrier 302 is removed. The carrier 302 can be removed by any suitable process. In some embodiments, a release film (not shown) is used to remove the carrier 302. In some embodiments, the adhesive layer 304 remains on the die 308, as shown in FIG. 7E. The electrical connector 324 is electrically connected to the PCB 330. In some embodiments, the intermediary substrate 320 has a concave warp due to the backside structure 210 formed thereon. The concave warp of the intermediary substrate 320 improves the contact between the electrical connector 324 and the PCB 330.

[0054] Figures 8A, 8B, and 8C schematically illustrate warpage adjustment according to some embodiments. As shown in Figure 8A, a first die 402 is bonded to a second die 410. In some embodiments, each first die 402 includes a circuit layer 404 electrically isolated by an isolation layer 406. In some embodiments, the circuit layer 404 includes multiple devices, such as those described in Figure 1F. The isolation layer 406 may include any suitable dielectric material. Multiple electrical connectors 408 are disposed above the circuit layer 404, as shown in Figure 1F. An interconnect structure 409 may be disposed below the circuit layer 404 and the isolation layer 406. The interconnect structure 409 is placed on a carrier 411, and a back face structure 210 is formed on the back face of the carrier 411, as shown in Figure 8A. The back face structure 210 may form warpage on the carrier 411 and the material disposed thereon. In some embodiments, a concave warpage is formed, which allows the electrical connectors 408 to better connect to the second die 410.

[0055] As shown in FIG8A, the second die 410 includes a circuit layer 412 electrically isolated by an isolation layer 414. An intermediary substrate 416 is disposed below the circuit layer 412 and the isolation layer 414, and a plurality of vias 418 are formed in the intermediary substrate 416. The vias 418 can be electrically connected to the corresponding circuit layer 412. The first die 402 and the second die 410 are combined such that the electrical connector 408 is electrically connected to the corresponding vias 418.

[0056] As shown in FIG8B, instead of using an electrical connector 408, dielectric layers 452 and 456, each including conductive features 450 and 454, are used to bond the first die 402 to the second die 410. In some embodiments, the dielectric layer 452 is formed on each of the first dies 402, and the conductive features 450 are formed in the dielectric layer 452. The backside structure 210 can provide a curved top surface of the dielectric layer 452, so that the top surface of the dielectric layer 452 can better match the bottom surface of the dielectric layer 456. The dielectric layer 456 and the conductive features 454 are disposed under the intercalating substrate 416. In some embodiments, each via 418 is electrically connected to the corresponding conductive feature 454, as shown in FIG8B. The backside structure 210 can be used in a manner similar to the backside structure 210 described in FIG2B and FIG3B.

[0057] In some embodiments, the cross-sectional profile of the bottom surface of the dielectric layer 456 can be altered by the backside structure 210, as shown in FIG8C. In some embodiments, a carrier 460 is formed over the circuit layer 412 and the isolation layer 414, and the backside structure 210 is formed on the carrier 460. The backside structure 210 can alter the cross-sectional profile of the bottom surface of the dielectric layer 456 so that the bottom surface of the dielectric layer 456 can better match the top surface of the dielectric layer 452 of the first die 402 (FIG. 8B). The backside structure 210 and the carrier 460 can be removed after the first die 402 is bonded to the second die 410. The backside structure 210 can be used in a manner similar to the backside structure 210 described in FIG. 4B.

[0058] The packages shown in Figures 8A to 8C can be System-on-Chip (SoIC) packages. The backside structure 210 forms warpage (or alters the cross-sectional profile of the top and / or bottom surfaces to be bonded) in one or more dies to improve the bonding process and die bonding. The backside structure 210 can be used for other types of packages.

[0059] This disclosure provides methods for forming an encapsulation structure 100 in various embodiments. In some embodiments, the method includes forming a back surface structure 210 on the back surface of the device structure 200. The back surface structure 210 includes alternating protective layers 212 and buffer layers 214. Some embodiments may achieve advantages. For example, the protective layer 212 tends to cause concave warpage on the device structure 200, and the buffer layer 214 tends to cause convex warpage on the device structure 200. By adjusting the warpage of the device structure 200, the bonding of the device structure 200 with another device structure is improved.

[0060] One embodiment is a method. The method includes: depositing a first layer on the front side of a wafer and depositing a second layer on the back side of the wafer; depositing a third layer on the first layer and depositing a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and depositing a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

[0061] Another embodiment is a method. The method includes providing a first device structure having a first surface and a second surface opposite to the first surface, and the second surface having a first cross-sectional profile. The method further includes depositing a first structure on the first surface, and the first structure causing the second surface to have a second cross-sectional profile different from the first cross-sectional profile. The method further includes incorporating the first device structure into a second device structure.

[0062] Another embodiment is a method. The method includes: bonding an intercalation substrate to one or more dies; removing a portion of the intercalation substrate to expose one or more vias; and depositing a structure on the intercalation substrate and the vias. Depositing the structure includes: depositing a first protective layer on the intercalation substrate and the vias, depositing a first buffer layer on the first protective layer, depositing a second protective layer on the first buffer layer, and depositing a second buffer layer on the second protective layer. The method further includes: removing the structure; depositing a dielectric material on the intercalation substrate and the vias; and forming one or more electrical connectors in the dielectric material.

[0063] The features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0008] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0009] Figures 1A, 1B, 1C, 1D, 1E and 1F are schematic cross-sectional views of a package structure manufactured according to some embodiments.

[0010] Figures 2A, 2B, 3A, 3B, 4A and 4B are schematic side views of two device structures to be combined according to some embodiments.

[0011] Figures 5A and 5B are schematic side views of the rear structure according to some embodiments.

[0012] Figures 6A and 6B are schematic side views of the device structure manufactured according to some embodiments.

[0013] Figures 7A, 7B, 7C, 7D and 7E are schematic side views of a package structure manufactured according to some embodiments.

[0014] Figures 8A, 8B and 8C schematically illustrate warp modulation according to some embodiments.

Claims

1. A method of forming a semiconductor structure, comprising: depositing a first layer on a front side of a wafer and depositing a second layer on a back side of the wafer; depositing a third layer on the first layer and a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

2. The method according to request item 1, wherein, The first layer and the second layer each contain an oxide, and the third layer and the fourth layer each contain a nitride.

3. The method according to request item 2, wherein, The sixth layer contains the same material as the fourth layer.

4. The method according to request item 3, wherein, The first layer has a first thickness, the second layer has a second thickness, the third layer has a third thickness, and the fourth and sixth layers together have a fourth thickness.

5. The method according to request item 4, wherein, The fourth thickness is greater than the second thickness.

6. The method according to claim 4, wherein, The first ratio of the first thickness to the third thickness is less than the second ratio of the second thickness to the fourth thickness.

7. The method according to request item 6, wherein, The first ratio is between 1:1 and 1:18, and the second ratio is between 1:20 and 1:

60.

8. The method according to request item 1, wherein, The first process is a dry etching process.

9. A method of forming a semiconductor structure, comprising: providing a first device structure, wherein, The first device structure has a first surface and a second surface opposite to the first surface, and the second surface has a first cross-sectional profile; a first structure is deposited on the first surface, wherein the first structure causes the second surface to have a second cross-sectional profile different from the first cross-sectional profile; and the first device structure is combined with a second device structure; wherein the first structure includes an alternating plurality of protective layers and a plurality of buffer layers.

10. A method of forming a semiconductor structure, comprising: bonding an interposer substrate to one or more dies; removing a portion of the interposer substrate to expose one or more vias; depositing a structure on the interposer substrate and the vias, comprising: depositing a first protective layer on the interposer substrate and the vias; depositing a first buffer layer on the first protective layer; depositing a second protective layer on the first buffer layer; and depositing a second buffer layer on the second protective layer; removing the structure; depositing a dielectric material on the interposer substrate and the vias; and forming one or more electrical connectors in the dielectric material.

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