Layered structures, semiconductor devices, and methods for manufacturing semiconductor devices

Abstract

A stacked structure capable of suppressing bending, a semiconductor device, and a method for manufacturing a semiconductor device are provided. The stacked structure of this embodiment comprises: a first wafer including a first semiconductor element layer and a first substrate on which the first semiconductor element layer is disposed; a second semiconductor element layer directly bonded to one side of the first wafer; and a third semiconductor element layer directly bonded to the other side of the first wafer. The second and third semiconductor element layers comprise the same type of semiconductor element, and are configured to sandwich the first wafer between them.

Description

[Technical Field]

[0001] The present invention relates to a stacked structure, a semiconductor device, and a method for manufacturing a semiconductor device. [Previous Technology]

[0002] Because the wafer is stacked in multiple segments and then stacked in multiple layers, there is a possibility that the curvature of the stacked body will increase. [Summary of the Invention]

[0003] A stacked structure capable of suppressing bending, a semiconductor device, and a method for manufacturing a semiconductor device are provided.

[0004] The stacked structure of this embodiment includes: a first wafer including a first semiconductor element layer and a first substrate on which the first semiconductor element layer is disposed; a second semiconductor element layer directly bonded to one side of the first wafer; and a third semiconductor element layer directly bonded to the other side of the first wafer. The second and third semiconductor element layers include the same type of semiconductor element, and the second and third semiconductor element layers are configured to sandwich the first wafer between them.

[0005] The semiconductor device of this embodiment includes: a first wafer having a first semiconductor element layer; a second semiconductor element layer directly bonded to one side of the first wafer; and a third semiconductor element layer directly bonded to the other side of the first wafer: the second semiconductor element layer and the third semiconductor element layer include the same type of semiconductor element, and the second semiconductor element layer and the third semiconductor element layer are configured to sandwich the first wafer between them and face each other.

[0006] The method for manufacturing a semiconductor device according to this embodiment includes: bonding a first wafer and a second wafer such that a first surface and a second surface face each other, wherein the first wafer has a first semiconductor element layer formed on its first surface and is bent such that the first surface forms a convex shape, the second wafer has a second semiconductor element layer formed on its second surface and is bent such that the second surface forms a convex shape, and bonding a third wafer such that a third surface faces a first back surface opposite to the first surface of the first wafer, wherein the third wafer has a third semiconductor element layer formed on its third surface and is bent such that the third surface forms a convex shape.

Implementation Method

[0008] Hereinafter, embodiments of the present invention will be described with reference to drawings.

[0009] This embodiment is not intended to limit the inventors. The drawings are schematic or conceptual, and the proportions of the parts may not be the same as in reality. In the specification and drawings, the same symbols are used for the same elements as in the aforementioned drawings, and detailed descriptions are omitted where appropriate.

[0010] (First Embodiment) FIG1 is a diagram showing one example of the configuration of the stacked structure 1 according to the first embodiment. In addition, FIG1 also shows one semiconductor device 2 after the stacked structure 1 is monolithically divided into a plurality of semiconductor devices 2.

[0011] The stacked structure 1 is a stacked structure consisting of three wafers W1, W2, and W3.

[0012] Wafer W1 is, for example, a logic wafer. Wafer W1 has a surface F11 and a surface F12 opposite to surface F12. Wafer W1 has: a device layer containing semiconductor element E1; and a semiconductor substrate S1 on which semiconductor element E1 is disposed. In the example shown in FIG1, semiconductor element E1 is disposed on the surface F11 side. Semiconductor substrate S1 is disposed on the surface F12 side. Semiconductor element E1 is, for example, a readout circuit. In the example shown in FIG1, semiconductor element E1 of wafer W1 is, for example, a controller for controlling the memory cell array described later. The controller is, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit.

[0013] Wafer W2 is, for example, a memory array wafer. Wafer W2 is disposed on one side (e.g., side F11) of wafer W1. Wafer W2 has: a device layer containing semiconductor element E2; and a semiconductor substrate S2 on which semiconductor element E2 is disposed. Alternatively, as shown in the example in FIG1, semiconductor substrate S2 may not be provided. Semiconductor element E2 is, for example, a memory element. In the example shown in FIG1, semiconductor element E2 of wafer W2 is, for example, a memory array. The memory array may also be a three-dimensional memory array in which a plurality of memory cells are arranged in three dimensions. The memory array is, for example, a 3D type NAND memory, but may also be a DRAM (Dynamic Random Access Memory) array, etc.

[0014] Wafer W3 is, for example, a memory array wafer. Wafer W3 is disposed on the other side (e.g., side F12) of wafer W1. Wafer W3 has: a device layer containing semiconductor element E3; and a semiconductor substrate S3 on which semiconductor element E3 is disposed. Semiconductor element E3 is, for example, a memory element. In the example shown in FIG1, the semiconductor element E3 of wafer W3 is a memory array. The memory array can also be a three-dimensional memory array in which a plurality of memory cells are arranged in three dimensions. The memory array is, for example, a 3D type NAND memory, but can also be a DRAM (Dynamic Random Access Memory) array, etc.

[0015] Wafer W2 and W3 are the same type of wafer. That is, semiconductor device E2 and E3 are the same type of device.

[0016] When a semiconductor device has a transistor, the semiconductor substrate may need to have a certain thickness to facilitate the operation of the semiconductor device, depending on the semiconductor device. The semiconductor substrate S1 has a thickness corresponding to the operating limit of the semiconductor device E1 in the CMOS circuit. The thickness of the semiconductor substrate S1 is, for example, 5 μm or more. The thickness of the first semiconductor substrate S1 may also be smaller than the thickness of one or both of the second semiconductor substrate S2 and the third semiconductor substrate S3.

[0017] Semiconductor device 2 is a stacked chip CH1, CH2, CH3.

[0018] Chip CH1 is, for example, a logic chip. Chip CH1 is one chip after the wafer W1 contained in the stacked structure 1 is monolithically divided into multiple chips. Chip CH1 has a semiconductor element E1 and a semiconductor substrate S1.

[0019] Chip CH2 is, for example, a memory chip. Chip CH2 is one of a plurality of chips after the wafer W2 contained in the stacked structure 1 is monolithically divided. Chip CH2 has a semiconductor element E2 and a semiconductor substrate S2.

[0020] Chip CH3 is, for example, a memory chip. Chip CH3 is one chip after the wafer W3 contained in the stacked structure 1 is monolithically divided into multiple chips. Chip CH3 has a semiconductor element E3 and a semiconductor substrate S3.

[0021] Chip CH2 and CH3 are the same type of chip.

[0022] Here, wafers W1, W2, and W3 are bent. The bending of the wafer is caused, for example, by the difference in the coefficient of thermal expansion between the material of the semiconductor substrate (e.g., silicon (Si)) and the material of the laminated film (semiconductor device) formed at a film-forming temperature of several hundred degrees Celsius.

[0023] Therefore, wafers W2 and W3 are configured to sandwich wafer W1 between them. More specifically, wafers W2 and W3 are configured to sandwich wafer W1 between them and face to face (together). That is, wafers W2 and W3 are arranged in a vertically reversed configuration. In addition, in the example shown in Figure 1, the "Array" of semiconductor elements E2 and E3 is described as vertically reversed.

[0024] By configuring identical wafers W2 and W3 to sandwich wafer W1, bending of wafers W2 and W3 can be eliminated (counteracted). As a result, bending of the stacked structure 1 and the semiconductor device 2 can be suppressed.

[0025] Figures 2A and 2B are cross-sectional views showing one example of the structure of the laminated structure 1 in the first embodiment. Figures 2A and 2B are cross-sectional views of the laminated structure 1 shown in Figure 1.

[0026] Wafer W1 and wafer W2 are bonded together with bonding surface S. Similarly, wafer W1 and wafer W3 are bonded together with bonding surface S.

[0027] Semiconductor element E1 is, for example, a transistor disposed on semiconductor substrate S1.

[0028] Semiconductor element E2 includes, for example, a memory lattice array. The bit line BL of semiconductor element E2 is located on the underside of wafer W2, that is, on the wafer W1 side of wafer W2.

[0029] Semiconductor element E3 includes, for example, a memory lattice array. The bit line BL of semiconductor element E3 is located on the upper side of wafer W3, that is, on the wafer W1 side of wafer W3. The through electrode pads through semiconductor substrate S1 are directly bonded (attached) to the electrode pads formed on the surface of semiconductor element E3 (the upper side of wafer W3). The electrode pads formed on the surface of semiconductor element E1 (the upper side of wafer W1) are directly bonded (attached) to the electrode pads formed on the surface of semiconductor element E2 (the lower side of wafer W2). Semiconductor element E2 and semiconductor element E3 are directly electrically connected without passing through the transistors of semiconductor element E1.

[0030] Therefore, as shown in Figures 2A and 2B, wafers W2 and W3 are arranged in an inverted configuration. Additionally, bonding pads for external connections are formed on the side of wafer W3, for example. In this case, the semiconductor substrate S3 can be at least partially or completely removed. Alternatively, bonding pads for external connections can be formed on the side of wafer W2. In this case, the semiconductor substrate S2 can also be at least partially or completely removed. The semiconductor substrate is removed by grinding, lapping, etching, or the like.

[0031] In addition, in FIG2A, the semiconductor substrate S2 of the wafer W2 is shown, but as shown in FIG1, the semiconductor substrate S2 may also be omitted.

[0032] In Figure 2A, the stepped portion of the memory lattice array contained in semiconductor element E2 is formed as a staircase running from the upper left to the lower right. In Figure 2A, the stepped portion of the memory lattice array contained in semiconductor element E3 is formed as a staircase running from the lower right to the upper left. That is, the stepped portion of the memory lattice array contained in semiconductor element E2 and the stepped portion of the memory lattice array contained in semiconductor element E3 are point-symmetric.

[0033] In Figure 2B, the stepped portion of the memory lattice array contained in semiconductor element E2 is formed as a staircase running from the upper left to the lower right. In Figure 2B, the stepped portion of the memory lattice array contained in semiconductor element E3 is formed as a staircase running from the lower left to the upper right. That is, the stepped portion of the memory lattice array contained in semiconductor element E2 and the stepped portion of the memory lattice array contained in semiconductor element E3 are linearly symmetrical.

[0034] Next, the manufacturing method of the stacked structure 1 will be explained.

[0035] Figures 3A to 3E are figures showing an example of a manufacturing method of the stacked structure 1 of the first embodiment.

[0036] First, as shown in Figure 3A, wafers W1 and W2 are prepared. Each of wafers W1 and W2 has a semiconductor substrate S1 and S2, respectively. Since semiconductor elements E1 and E2 are thin films, it is difficult to handle individual semiconductor elements E1 and E2 without the semiconductor substrates S1 and S2. By using the semiconductor substrates S1 and S2 that support semiconductor elements E1 and E2, wafers W1 and W2 can be easily processed.

[0037] The wafers W1 and W2 shown in Figure 3A each have a convex curvature. More specifically, the logic wafer W1 has a curvature with convexity a. The memory array wafer W2 has a curvature with convexity b. That is, the curvature of wafers W1 and W2 is different. The magnitude of the curvature is convexity a < convexity b.

[0038] Next, as shown in Figure 3B, wafer W1 and wafer W2 are bonded together. The semiconductor element E1 side of wafer W1 and the semiconductor element E2 side of wafer W2 will be bonded together.

[0039] Next, as shown in FIG3C, the stacked structure of wafers W1 and W2 is flipped vertically to remove at least a portion of the semiconductor substrate S1, thereby thinning it. Additionally, wafer W3 shown in FIG3C is prepared simultaneously with wafer W2, for example, in the process shown in FIG3A. Alternatively, the entire semiconductor substrate S1 can be removed. This can be done by grinding, lapping, etching, or similar methods.

[0040] The stacked structure of wafers W1 and W2 shown in Figure 3C has a convex curvature. More specifically, the stacked structure of wafers W1 and W2 has a curvature caused by concave a and convex b after the convex a is reversed vertically. As mentioned above, since convex a < convex b, the stacked structure of wafers W1 and W2 has a convex curvature.

[0041] Next, as shown in FIG3D, the stacked structure of wafers W1 and W2 is bonded to wafer W3. The semiconductor substrate S1 side of wafer W1 is bonded to the semiconductor element E3 side of wafer W3.

[0042] Next, as shown in FIG3E, wafers W1, W2, and W3 are flipped vertically to thin the semiconductor substrate S2. In the example shown in FIG3E, the semiconductor substrate S2 is removed. In this way, the stacked structure 1 shown in FIG1 is completed.

[0043] Furthermore, even if semiconductor substrate S2 is removed, semiconductor substrates S1 and S3 will remain, so the stacked structure of wafers W1, W2, and W3 is still easy to process. Therefore, the thickness of the second semiconductor substrate S2 can also be different from the thickness of the third semiconductor substrate S3. In the example shown in FIG3E, the thickness of the second semiconductor substrate S2 is 0 μm.

[0044] The stacked structure of wafers W1, W2, and W3 shown in Figure 3E has a convex bend. More specifically, the stacked structure of wafers W1, W2, and W3 has a bend caused by a concave b resulting from the inversion of convex a and convex b, and by convex b itself. Since concave b and convex b are eliminated, the stacked structure of wafers W1, W2, and W3 has a bend with convex a.

[0045] Then, by monolithizing the stacked structure 1, the semiconductor device 2 is completed. Alternatively, the semiconductor substrate S3 can be removed before completing the semiconductor device 2. The bonding pads connecting to the outside can be formed after removing the semiconductor substrate S3, or they can be formed on the semiconductor substrate S3 without removing the semiconductor substrate S3. The bonding pads connecting to the outside can also be formed on the side of the semiconductor substrate S2.

[0046] As described above, according to the first embodiment, wafers W2 and W3 are configured to sandwich wafer W1 between them. This eliminates bending of wafers W2 and W3. As a result, bending of the stacked structure 1 and the semiconductor device 2 can be suppressed.

[0047] Furthermore, the bending of the semiconductor substrate itself can sometimes affect the bending of the stacked structure 1 and the semiconductor device 2. If the bending of wafers W1 and W3 is eliminated and can be ignored, the bending of the stacked structure 1 is almost entirely caused by the bending of wafer W1. The bending of the wafer depends on stress and thickness. In the example shown in FIG3E, semiconductor element E1 has an upward convex bending, semiconductor substrate S1 has a downward convex bending, and wafer W1 has an upward convex convex a bending all over. The greater the thickness of semiconductor substrate S1, the greater the downward convex bending of semiconductor substrate S1. Therefore, the thickness of semiconductor substrate S1 can also be adjusted so that the bending of semiconductor element E1 is balanced with that of semiconductor substrate S1. In this way, the bending of the stacked structure 1 and the semiconductor device 2 can be further suppressed.

[0048] Furthermore, for example, when semiconductor elements E2 and E3 each have a vertically symmetrical structure internally, even if wafers W2 and W3 are reversed vertically, the curvature of wafers W2 and W3 will not change. In this case, wafers W2 and W3 do not need to be arranged opposite each other. That is, wafers W2 and W3 can also be arranged in the same direction without being reversed vertically.

[0049] (Comparative Example) Figure 4 is a diagram showing one example of the configuration of the stacked structure 1a in the comparative example. In the comparative example, compared with the first embodiment, the arrangement of the stacked wafers is different. In addition, in Figure 4, a portion of the semiconductor substrate is omitted.

[0050] The stacked structure 1a comprises three stacked wafers W1a, W2a, and W3a. Wafer W1a is, for example, a logic wafer. Wafers W2a and W3a are, for example, memory array wafers.

[0051] FIG5 is a cross-sectional view showing one example of the configuration of the comparative example of the laminated structure 1a. FIG5 is a cross-sectional view of the laminated structure 1 shown in FIG4.

[0052] The wafers W1a and W3a sandwiched between wafer W2a are dissimilar wafers. Wafers W2a and W3a are arranged in the same orientation.

[0053] Figures 6A to 6C are diagrams illustrating one example of a manufacturing method for the comparative example of the stacked structure 1a. The processes shown in Figures 6A to 6C are performed after the same processes shown in Figures 3A and 3B. In addition, the wafers W1 and W2 shown in Figures 3A and 3B are the same as wafers W1a and W2a.

[0054] After wafers W1a and W2a are bonded together (see Figure 3B), the semiconductor substrate S2 is thinned as shown in Figure 6A. In the example shown in Figure 6A, the semiconductor substrate S2 is removed. Furthermore, wafer W3a shown in Figure 6A is prepared simultaneously with wafer W2a, for example, in the process shown in Figure 3A.

[0055] The stacked structure of wafers W1a and W2a shown in Figure 6A has a concave curvature. More specifically, the stacked structure of wafers W1a and W2a has a curvature caused by the concave b resulting from the reversal of convex a and convex b. As mentioned above, since convex a < convex b, the stacked structure of wafers W1a and W2a has a concave curvature.

[0056] Next, as shown in Figure 6B, the stacked structure of wafers W1a and W2a is bonded to wafer W3a.

[0057] Next, as shown in FIG6C, the semiconductor substrate S3 is thinned. In the example shown in FIG6C, the semiconductor substrate S3 is removed.

[0058] The stacked structure of wafers W1a, W2a, and W3a shown in Figure 6C has a concave curvature. More specifically, the stacked structure of wafers W1a, W2a, and W3a has a curvature caused by a convex a and two concave bs after the inversion of two convex bs. As mentioned above, since convex a < convex b, the stacked structure of wafers W1a, W2a, and W3a has a concave curvature.

[0059] In the process shown in Figure 6C, the bending of the two concave b of the memory array wafers W2a and W3a becomes stronger due to the overlapping bending. As a result, the bending of the stacked structure 1a increases.

[0060] In this respect, in the first embodiment, wafers W2 and W3 of the same type are configured to sandwich wafer W1. This eliminates bending of wafers W2 and W3. As a result, bending of the stacked structure 1 and the semiconductor device 2 can be suppressed.

[0061] (Second Embodiment) FIG7 is a diagram showing an example of the configuration of the stacked structure 1 according to the second embodiment. The second embodiment differs from the first embodiment in that the wafers W2 and W3 are arranged in an up-down reverse configuration. In addition, the semiconductor substrate is omitted in FIG7.

[0062] Compared with FIG. 1 of the first embodiment, wafers W2 and W3 are reversed in orientation. In this case, wafers W2 and W3 are also configured to sandwich wafer W1 between them. Therefore, bending of wafers W2 and W3 can be eliminated.

[0063] In addition, detailed description of the semiconductor device 2 having wafers CH1, CH2, and CH3 after wafers W1, W2, and W3 are monolithized is omitted.

[0064] As in the second embodiment, wafers W2 and W3 can also be arranged in an upside-down configuration. The stacked structure 1 according to the second embodiment can achieve the same effect as the first embodiment.

[0065] (Third Embodiment) Figure 8 is a diagram showing an example of the structure of the stacked structure 1 in the third embodiment. The third embodiment differs from the first embodiment in that the wafer W1 is arranged in an inverted configuration. In addition, in Figure 8, the semiconductor substrates S1, S2, and S3 are omitted.

[0066] Compared with FIG. 1 of the first embodiment, wafer W1 is reversed vertically. In this case, wafers W2 and W3 are also configured to sandwich wafer W1 between them. Therefore, bending of wafers W2 and W3 can be eliminated.

[0067] In addition, detailed description of the semiconductor device 2 having wafers CH1, CH2, and CH3 after wafers W1, W2, and W3 are monolithized is omitted.

[0068] As in the third embodiment, the wafer W1 can also be arranged in an upside-down configuration. The stacked structure 1 according to the third embodiment can achieve the same effect as the first embodiment.

[0069] (Fourth Embodiment) Figure 9 is a diagram showing an example of the configuration of the stacked structure 1 according to the fourth embodiment. The fourth embodiment is different from the first embodiment, where two logic wafers sandwich a memory array wafer. In addition, the semiconductor substrate is omitted in Figure 9.

[0070] Wafer W1 is, for example, a memory array wafer. Wafers W2 and W3 are, for example, logic wafers.

[0071] In this case, wafers W2 and W3 are also configured to sandwich wafer W1 between them and face each other. Therefore, bending of wafers W2 and W3 can be eliminated.

[0072] In addition, detailed description of the semiconductor device 2 having wafers CH1, CH2, and CH3 after wafers W1, W2, and W3 are monolithized is omitted.

[0073] As in the fourth embodiment, it can also be configured as two logic wafers sandwiching a memory array wafer. The stacked structure 1 according to the fourth embodiment can achieve the same effect as the first embodiment. Furthermore, at least one of the second embodiment and the third embodiment can be combined in the stacked structure 1 according to the second embodiment. That is, both wafers W2 and W3 can be arranged in a top-bottom reversible configuration, and wafer W1 can also be arranged in a top-bottom reversible configuration.

[0074] (Fifth Embodiment) FIG10 is a diagram showing an example of the configuration of the stacked structure 1 according to the fifth embodiment. The fifth embodiment is a configuration of four stacked wafers, which differs from the first embodiment. In addition, the semiconductor substrate is omitted in FIG10.

[0075] The stacked structure 1 is more equipped with wafer W4.

[0076] Wafer W4 is a logic wafer. Wafer W4 is disposed between one side (e.g., side F11) of wafer W1 and wafer W2. Wafer W4 has: a device layer containing semiconductor device E4; and a semiconductor substrate S4 on which semiconductor device E4 is disposed. In Figure 10, semiconductor substrate S4 is omitted.

[0077] Wafer W4 is bonded to wafer W1 using the lower bonding surface. Similarly, wafer W4 is bonded to wafer W2 using the upper bonding surface.

[0078] Wafer W1 and W4 are the same type of wafer. That is, semiconductor device E1 and E4 are the same type of device.

[0079] Wafer W4 is configured to be opposite to wafer W1. That is, wafers W1 and W4 are arranged in an inverted configuration. This eliminates bending of wafers W1 and W4. As a result, bending of the stacked structure 1 and the semiconductor device 2 can be suppressed.

[0080] In addition, the wafers W1 and W4 can also be configured to be reversed.

[0081] Wafers W2 and W3 are configured to sandwich two wafers W1 and W4. Wafers W2 and W3 are configured to sandwich two wafers W1 and W4 and face each other. In this way, bending of wafers W2 and W3 can be eliminated. As a result, bending of the stacked structure 1 and the semiconductor device 2 can be suppressed.

[0082] In addition, detailed description of the semiconductor device 2 having wafers CH1, CH2, CH3, and CH4 after wafers W1, W2, W3, and W4 are omitted.

[0083] Alternatively, more than five wafers may be stacked. In this case, wafers W2 and W3 are also configured to sandwich three or more wafers between them.

[0084] As in the fifth embodiment, four wafers can also be stacked. The stacked structure 1 according to the fifth embodiment can achieve the same effect as the first embodiment. Furthermore, the second embodiment can also be combined in the stacked structure 1 according to the fifth embodiment. That is, the wafers W2 and W3 can also be arranged in reverse order.

[0085] (Sixth Embodiment) Figure 11 is a diagram showing one example of the configuration of the stacked structure 1 according to the sixth embodiment. The sixth embodiment is different from the fifth embodiment, where two logic wafers sandwich two memory array wafers. That is, the sixth embodiment can also be a combination of the fourth and fifth embodiments. Furthermore, the semiconductor substrate is omitted in Figure 11.

[0086] Wafer W1 and W4 are, for example, memory array wafers. Wafer W2 and W3 are, for example, logic wafers.

[0087] Similar to the fifth embodiment, wafer W4 is configured to be opposite to wafer W1. This eliminates bending of wafers W1 and W4.

[0088] Similar to the fifth embodiment, wafers W2 and W3 are configured to sandwich two wafers W1 and W4 between them and face each other. This eliminates bending of wafers W2 and W3.

[0089] In addition, detailed description of the semiconductor device 2 having wafers CH1, CH2, CH3, and CH4 after wafers W1, W2, W3, and W4 are omitted.

[0090] As in the sixth embodiment, the two logic wafers can also be configured to sandwich two memory array wafers. The stacked structure 1 according to the sixth embodiment can achieve the same effect as the fifth embodiment.

[0091] In this embodiment, wafer W1 is a logic wafer, and wafers W2 and W3 are examples of memory array wafers, but are not limited thereto. For example, the combination of wafers W1, W2 and W3 can be components formed on the wafer such as passive components such as logic and capacitors, pixel sensors or power semiconductors, and any combination is acceptable as long as it can mitigate the bending of the wafer.

[0092] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit and scope of the invention. These embodiments or variations thereof are included within the scope and spirit of the present invention and within the scope of the claims and their equivalents. [Simplified Explanation of the Diagram]

[0007] [Fig. 1] is a diagram showing an example of the structure of the laminated structure according to the first embodiment. [Fig. 2A] is a cross-sectional view showing an example of the structure of the laminated structure according to the first embodiment. [Fig. 2B] is a cross-sectional view showing an example of the structure of the laminated structure according to the first embodiment. [Fig. 3A] is a diagram showing an example of a manufacturing method of the laminated structure according to the first embodiment. [Fig. 3B] is a diagram following Fig. 3A showing an example of a manufacturing method of the laminated structure. [Fig. 3C] is a diagram following Fig. 3B showing an example of a manufacturing method of the laminated structure. [Fig. 3D] is a diagram following Fig. 3C showing an example of a manufacturing method of the laminated structure. [Fig. 3E] is a diagram following Fig. 3D showing an example of a manufacturing method of the laminated structure. [Fig. 4] is a diagram showing an example of the structure of the laminated structure of a comparative example. [Fig. 5] is a cross-sectional view showing an example of the structure of the laminated structure of a comparative example. [Fig. 6A] is a diagram showing one example of a manufacturing method of a composite structure according to a comparative example. [Fig. 6B] is a diagram following Fig. 3A, showing one example of a manufacturing method of a composite structure. [Fig. 6C] is a diagram following Fig. 3B, showing one example of a manufacturing method of a composite structure. [Fig. 7] is a diagram showing one example of the structure of a composite structure according to a second embodiment. [Fig. 8] is a diagram showing one example of the structure of a composite structure according to a third embodiment. [Fig. 9] is a diagram showing one example of the structure of a composite structure according to a fourth embodiment. [Fig. 10] is a diagram showing one example of the structure of a composite structure according to a fifth embodiment. [Fig. 11] is a diagram showing one example of the structure of a composite structure according to a sixth embodiment.

Claims

1. A laminated structure, characterized by comprising: a first wafer including a first semiconductor element layer and a first substrate on which the first semiconductor element layer is disposed; a second semiconductor element layer directly bonded to one side of the first wafer; and a third semiconductor element layer directly bonded to the other side of the first wafer, wherein the second and third semiconductor element layers comprise the same type of semiconductor element, the second and third semiconductor element layers are configured to sandwich the first wafer between them and face each other, and the second and third semiconductor element layers are configured in such a way that the bending generated by the second semiconductor element layer and the bending generated by the third semiconductor element layer cancel each other out.

2. As described in claim 1, the layered structure, wherein, It also includes a fourth semiconductor element layer that is directly bonded between the first wafer and the second semiconductor element layer, wherein the second semiconductor element layer and the third semiconductor element layer are configured to sandwich the first wafer and the fourth semiconductor element layer therebetween.

3. The layered structure as described in claim 2, wherein, The aforementioned first semiconductor element layer and the aforementioned fourth semiconductor element layer include the same type of semiconductor element.

4. As described in claim 1, the layered structure, wherein, The aforementioned second semiconductor element layer and the aforementioned third semiconductor element layer have memory grid arrays, and the aforementioned first semiconductor element layer has a CMOS control circuit for controlling the aforementioned memory grid array.

5. A stacked structure as described in any of claims 1 to 4, wherein, It conforms to at least one of a second substrate having the aforementioned second semiconductor element layer or a third substrate having the aforementioned third semiconductor element layer.

6. The layered structure as described in claim 5, wherein, The thickness of the second substrate is different from that of the third substrate.

7. The layered structure as described in claim 6, wherein, The thickness of the first substrate is smaller than the thickness of one or both of the second and third substrates.

8. A semiconductor device, characterized by comprising: a first wafer having a first semiconductor element layer; a second semiconductor element layer directly bonded to one side of the first wafer; and a third semiconductor element layer directly bonded to the other side of the first wafer: the second and third semiconductor element layers comprise the same type of semiconductor element; the second and third semiconductor element layers are configured to sandwich the first wafer between them and face each other; and the second and third semiconductor element layers are configured in such a way that the bending generated by the second semiconductor element layer and the bending generated by the third semiconductor element layer cancel each other out.

9. The semiconductor device as described in claim 8, wherein, It further includes a fourth semiconductor element layer that is directly bonded between the first wafer and the second semiconductor element layer. The second and third semiconductor element layers are configured to sandwich the first wafer and the fourth semiconductor element layer therebetween. The first and fourth semiconductor element layers include the same type of semiconductor element.

10. The semiconductor device as described in claim 9, wherein, The aforementioned second semiconductor element layer and the aforementioned third semiconductor element layer have memory grid arrays, and the aforementioned first semiconductor element layer has a CMOS control circuit for controlling the aforementioned memory grid array.

11. The semiconductor device as described in any one of claims 8 to 10, wherein, It conforms to at least one of a second substrate having the aforementioned second semiconductor element layer or a third substrate having the aforementioned third semiconductor element layer.

12. A method for manufacturing a semiconductor device, characterized by comprising: A first wafer and a second wafer are bonded together with their first and second surfaces facing each other. The first wafer has a first semiconductor element layer formed on its first surface and is bent to form a convex surface. The second wafer has a second semiconductor element layer formed on its second surface and is bent to form a convex surface. A third wafer is bonded together with its third surface facing the first back surface of the opposite side of the first surface of the first wafer. The third wafer has a third semiconductor element layer formed on its third surface and is bent to form a convex surface. The second and third wafers are bonded together in such a way that the bending of the second wafer and the bending of the third wafer cancel each other out.

13. A method for manufacturing a semiconductor device as described in claim 12, wherein, It further includes: after bonding the aforementioned first surface and the aforementioned second surface together so that they are opposite each other, removing at least a portion of the aforementioned first back surface.

14. A method for manufacturing a semiconductor device as described in claim 12, wherein, It further includes: forming external connection pads on the second back side of the surface opposite to the second surface of the aforementioned second wafer, or forming external connection pads on the third back side of the surface opposite to the third surface of the aforementioned third wafer.

15. A method for manufacturing a semiconductor device as described in claim 14, wherein, It further includes: removing at least a portion of the second wafer from the second back side or removing at least a portion of the third wafer from the third back side before forming the aforementioned external connection pads.

16. A method for manufacturing a semiconductor device as described in any of claims 12 to 15, wherein, The aforementioned first semiconductor element layer includes a CMOS control circuit, and the aforementioned second and third semiconductor element layers include memory grid arrays controlled by the aforementioned CMOS control circuit.

17. A method for manufacturing a semiconductor device as described in any of claims 12 to 15, wherein, The bending size of the first wafer is smaller than that of the second wafer.

Images