Semiconductor devices and semiconductor memory devices

Abstract

One embodiment provides a semiconductor device and a semiconductor memory device capable of manufacturing high-quality semiconductor devices. The semiconductor device of this embodiment includes: a gate electrode extending in a first direction; an oxide semiconductor extending in a vertical direction intersecting the first direction and penetrating the gate electrode; a first electrode connected to a first lower end of the oxide semiconductor; a second electrode connected to a first upper end of the oxide semiconductor; and a first insulating film comprising an upper gate film covering the upper surface of the gate electrode, a lower gate film covering the lower surface of the gate electrode, and a gate insulating film covering a first surface of the gate electrode facing the oxide semiconductor, and formed of a first insulating material.

Description

Technical Field

[0001] [References to related applications] This application enjoys priority to Japanese Patent Application No. 2024-044156 (filed on March 19, 2024). This application includes all contents of the basic application by reference to that basic application.

[0002] This embodiment relates to a semiconductor device and a semiconductor memory device. Prior Technology

[0003] In semiconductor devices, metal oxides containing indium and tin are sometimes used in the electrodes. Summary of the Invention

[0004] In the manufacturing process of semiconductor devices that use metal oxides in electrodes, a technique is required to produce high-quality semiconductor devices.

[0005] The problem to be solved by the present invention is to provide a semiconductor device and a semiconductor memory device capable of manufacturing high-quality semiconductor devices.

[0006] An embodiment of the semiconductor device includes: a gate electrode formed extending in a first direction; an oxide semiconductor formed extending in a vertical direction intersecting the first direction and penetrating the gate electrode; a first electrode connected to a first lower end of the oxide semiconductor; a second electrode connected to a first upper end of the oxide semiconductor; and a first insulating film comprising an upper gate film covering the upper surface of the gate electrode, a lower gate film covering the lower surface of the gate electrode, and a gate insulating film covering a first surface of the gate electrode facing the oxide semiconductor, and formed of a first insulating material.

[0007] The semiconductor device of one embodiment includes: a first oxide semiconductor extending in a vertical direction; a first interlayer insulating film extending along a plane parallel to a direction intersecting the vertical direction and penetrated by the first oxide semiconductor; a first electrode containing oxygen, indium, and tin; a first film disposed between the first oxide semiconductor and the first electrode, electrically connected to the first oxide semiconductor and the first electrode, and formed of a semiconductor or conductor; and a gate electrode separating the gate insulating film and facing the first oxide semiconductor, wherein the first film contains atoms with a binding energy greater than that between oxygen atoms and indium atoms in the first electrode.

[0008] An embodiment of the semiconductor memory device includes: the semiconductor device; a first capacitor electrode connected to the first electrode; a second capacitor electrode facing the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode. Simple Explanation of the Diagram

[0009] Figure 1 is a circuit diagram illustrating an example of the circuit structure of the memory cell array in the first embodiment. Figure 2 is a cross-sectional schematic diagram illustrating a structural example of a semiconductor memory device in the first embodiment, showing a cross-sectional view parallel to the ZX plane. Figure 3 is a cross-sectional schematic diagram illustrating a structural example of a semiconductor device in the first embodiment, showing a cross-sectional view of the semiconductor device parallel to the ZX plane. Figure 4 is a cross-sectional schematic diagram illustrating a structural example of a semiconductor device in the first embodiment, showing a cross-sectional view of the semiconductor device parallel to the YZ plane. Figure 5 is a cross-sectional view of the cut line VV shown in Figures 3 and 4. Figure 6 is a cross-sectional schematic diagram illustrating a structural example near the word line contact of the semiconductor device in the first embodiment, showing a cross-sectional view of the semiconductor device parallel to the YZ plane. Figure 7 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 8 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 9 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 10 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 11 is a cross-sectional view of the cut line XI-XI shown in Figures 9 and 10. Figure 12 is a cross-sectional view parallel to the YZ plane showing the manufacturing process near the word line contact of the semiconductor device in the first embodiment. Figure 13 is a cross-sectional view parallel to the YZ plane showing the manufacturing process near the word line contact of the semiconductor device in the first embodiment. Figure 14 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 15 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 16 is a cross-sectional view parallel to the YZ plane showing the manufacturing process near the word line contact of the semiconductor device in the first embodiment. Figure 17 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 18 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 19 is a cross-sectional view parallel to the YZ plane showing the manufacturing process near the word line contact of the semiconductor device in the first embodiment. Figure 20 is a cross-sectional view parallel to the YZ plane showing the manufacturing process near the word line contact of the semiconductor device in the first embodiment. Figure 21 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 22 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 23 is a cross-sectional view of the cut line XXIII-XXIII shown in Figures 21 and 22. Figure 24 is a cross-sectional view parallel to the YZ plane showing the manufacturing process near the word line contact of the semiconductor device in the first embodiment. Figure 25 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 26 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 27 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 28 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 29 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 30 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 31 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 32 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 33 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 34 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 35 is a cross-sectional view of the cut line XXXV-XXXV shown in Figures 33 and 34. Figure 36 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 37 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 38 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 39 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 40 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 41 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 42 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 43 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 44 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 45 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 46 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 47 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 48 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 49 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 50 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 51 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the first embodiment. Figure 52 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device of the comparative example. Figure 53 is a cross-sectional schematic diagram illustrating a structural example of a semiconductor device in the second embodiment, showing a cross-sectional view of the semiconductor device parallel to the YZ plane. Figure 54 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 55 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 56 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 57 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 58 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 59 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 60 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 61 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 62 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 63 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Figure 64 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device in the second embodiment. Implementation

[0010] The present embodiment will now be described with reference to the accompanying drawings. To facilitate understanding, the same symbols will be used to label the same components in each drawing as much as possible, and repeated descriptions will be omitted.

[0011] [First Implementation Form] The structure of the semiconductor memory device according to the first embodiment will be described. In various figures, the X-axis, Y-axis, and Z-axis are sometimes shown. The X-axis, Y-axis, and Z-axis form a right-handed three-dimensional orthogonal coordinate system. Hereinafter, the direction of the arrow on the X-axis is sometimes referred to as the X-axis+ direction, and the direction opposite to the arrow is sometimes referred to as the X-axis- direction; the same applies to the other axes. Furthermore, the Z-axis+ direction and the Z-axis- direction are sometimes referred to as "above" and "below," respectively. Additionally, the planes orthogonal to the X-axis, Y-axis, or Z-axis are sometimes referred to as the YZ plane, ZX plane, or XY plane, respectively. Furthermore, the Z-axis direction is sometimes referred to as the "vertical direction." "Above," "below," and "vertical direction" are merely terms indicating relative positional relationships within the figures and are not terms defining orientations based on the vertical direction.

[0012] In addition, except where specifically described, the dimensions of the constituent components shown in the figures are sometimes shown differently from the actual dimensions in order to facilitate understanding of the explanation.

[0013] In this specification, "connection" includes not only physical connection but also electrical connection, and unless otherwise specified, "connection" includes not only direct connection but also indirect connection.

[0014] In this specification, "formed above" includes not only the case where it is formed in contact with the ground above, but also the case where it is formed above, separated from other objects, unless otherwise specified. The same applies to cases such as "formed below".

[0015] The semiconductor memory device 101 in the first embodiment is an oxide semiconductor-random access memory (OS-RAM) including an array of memory cells.

[0016] As shown in Figure 1, the memory cell array includes: multiple memory cells MC, multiple word lines WL, and multiple bit lines BL.

[0017] In Figure 1, as an example of multiple character lines WL, character lines WL n, WL n+1, and WL n+2 are shown (where n is a positive integer). Additionally, in Figure 1, as an example of bit lines BL, bit lines BL m, BL m+1, and BL m+2 are shown (where m is a positive integer). Furthermore, the number of memory cells MC is not limited to the number shown in Figure 1.

[0018] Multiple memory cells (MCs) can be arranged in a matrix to form a memory cell array. A memory cell (MC) includes a memory transistor (MTR) that is a field-effect transistor (FET) and a memory capacitor (MCP).

[0019] A series of memory cells MC arranged along the column direction are connected to the word line WL (e.g., word line WL n) corresponding to their respective column (e.g., the nth column). A series of memory cells MC arranged along the row direction are connected to the bit line BL (e.g., bit line BL m+2) corresponding to their respective row (e.g., the (m+2)th row).

[0020] In detail, the gate of the memory transistor MTR contained in the memory cell MC is connected to the word line WL corresponding to the column to which the memory cell MC belongs. One of the sources or drains of the memory transistor MTR is connected to the bit line BL corresponding to the row to which the memory cell MC belongs.

[0021] One electrode of the memory capacitor MCP contained in the memory cell MC is connected to either the source or the drain of the memory transistor MTR contained in the memory cell MC. The other electrode of the memory cell MC is connected to a power supply line (not shown) that supplies a specific potential.

[0022] The memory cell MC is configured such that, by switching the memory transistor MTR based on the potential of the corresponding word line WL, data can be retained by accumulating charge in the memory capacitor MCP caused by the current flowing through the corresponding bit line BL.

[0023] As shown in Figure 2, the semiconductor memory device 101 includes: a semiconductor substrate 10, a circuit 11 (an example of a "semiconductor circuit"), a capacitor 20, a semiconductor device 30, a conductor 33, an insulating layer 34, an insulating layer 35, and an insulating layer 63.

[0024] The capacitor 20 includes: a conductor 21, an insulating film 22 (an example of a "dielectric film"), a conductor 23, a capacitor electrode 24 (an example of a "first capacitor electrode"), and a capacitor electrode 25 (an example of a "second capacitor electrode").

[0025] The semiconductor device 30 includes: a field-effect transistor 40 (an example of a "semiconductor element"), an upper electrode 50 (an example of a "second electrode") disposed above the field-effect transistor 40, and a lower electrode 32 (an example of a "first electrode") disposed below the field-effect transistor 40.

[0026] The field-effect transistor 40 includes: an oxide semiconductor layer 70 (an example of "oxide semiconductor" and "first oxide semiconductor"), a gate insulating film 43, a conductive layer 42 (an example of "gate electrode"), and an insulating layer 45.

[0027] An oxide semiconductor layer 70 is formed in the insulating layer 45, having an upper end 70a (an example of a "first upper end") and a lower end 70b (an example of a "first lower end"). The oxide semiconductor layer 70 is a columnar body extending in the Z-axis+ direction from the lower end 70b toward the upper end 70a. The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40, and the oxide semiconductor layer 70 has an amorphous structure.

[0028] The conductive layer 42 is separated from the gate insulating film 43 and faces the oxide semiconductor layer 70. Specifically, the conductive layer 42 functions as the gate electrode of the field-effect transistor 40, and the gate insulating film 43 surrounds the oxide semiconductor layer 70 between the upper end 70a and the lower end 70b. The conductive layer 42 may contain, for example, tungsten (W).

[0029] The gate insulating film 43 may include, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen.

[0030] The upper electrode 50 is formed in the Z-axis+ direction relative to the oxide semiconductor layer 70 and is connected to the upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes: a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0031] The metal film 50c contains tungsten. A metal oxide layer 50a is formed between the metal film 50c and the upper end 70a of the oxide semiconductor layer 70, and contains a metal oxide. The metal oxide may contain, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium tin oxide (ITO).

[0032] The barrier metal layer 50b comprises titanium and nitrogen and is formed between the metal oxide layer 50a and the metal film 50c. In this embodiment, the barrier metal layer 50b is formed, for example, of titanium nitride (TiN).

[0033] The lower electrode 32 is connected to the lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 comprises a metal oxide. Specifically, the lower electrode 32 comprises, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin oxide (ITO).

[0034] Furthermore, the lower electrode 32 is not limited to ITO, but can also be a structure containing at least one element selected from indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten and iron.

[0035] Circuit 11 comprises a decoder for selecting a plurality of memory cells MC in the semiconductor memory device 101, namely capacitor 20 and a specified memory cell MC in field-effect transistor 40, a sense amplifier connected to bit line BL, and peripheral circuitry including a register containing static random access memory (SRAM). Circuit 11 may also include CMOS circuitry of field-effect transistors having P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs) formed by complementary metal-oxide-semiconductor (CMOS) processes.

[0036] The field-effect transistor of circuit 11 can be formed using a semiconductor substrate 10, such as a single-crystal silicon substrate. P-FET and N-FET are so-called transverse field-effect transistors that have a channel region, a source region, and a drain region on the semiconductor substrate 10, and have channels in a region close to the surface of the semiconductor substrate 10 for allowing carriers to flow in the X-axis or Y-axis direction, which is substantially parallel to the surface of the semiconductor substrate 10. Furthermore, the semiconductor substrate 10 may also have P-type or N-type conductivity. For convenience, FIG2 illustrates an example of the field-effect transistor of circuit 11.

[0037] Capacitor 20 is the memory capacitor MCP contained in the memory cell MC (see Figure 1). Figure 2 shows four capacitors 20, but the number of capacitors 20 is not limited to four.

[0038] In this embodiment, capacitor 20 is disposed above semiconductor substrate 10. Capacitor electrode 24 in capacitor 20 is connected to conductor 21 and lower electrode 32. Capacitor electrode 25 faces capacitor electrode 24. Insulating film 22 is disposed between capacitor electrode 24 and capacitor electrode 25.

[0039] Capacitor 20 is a three-dimensional capacitor such as a cylindrical capacitor. Furthermore, other capacitors, including those with structures capable of storing charge, may also be used as the capacitor in this embodiment.

[0040] Capacitor electrode 24 is located below lower electrode 32. Capacitor electrode 24 has an upper end facing the lower end face of the dielectric conductor 21, and a columnar shape extending downward from this upper end. Conductor 21 is formed to cover both lower electrode 32 and capacitor electrode 24. Insulating film 22 is formed to cover conductor 21. Capacitor electrode 25 surrounds a portion below the insulating film 22 and has a lower end abutting against the upper end face of conductor 23.

[0041] The capacitor electrode 24 may contain materials such as SiGe, which contains silicon and germanium. The insulating film 22 may contain materials such as ZrAlO, which contains zirconium, aluminum, and oxygen. The conductor 21 may contain materials such as titanium nitride, which contains nitrogen and titanium. The conductor 23 and the capacitor electrode 25 may contain materials such as tungsten and titanium nitride.

[0042] Conductor 33 includes wiring that electrically connects circuit 11 to semiconductor device 30. Conductor 33 may include through-hole wiring, for example, as shown in FIG2, having through-hole wiring extending in the Z-axis direction and connecting character line WL to circuit 11 disposed on semiconductor substrate 10. Conductor 33 may contain copper, for example.

[0043] An insulating layer 34 is disposed between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0044] An insulating layer 35 is disposed above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0045] Semiconductor device 30 is disposed above capacitor 20. Field-effect transistor 40 in semiconductor device 30 corresponds to memory transistor MTR of memory cell MC (see Figure 1).

[0046] In the semiconductor device 30, a field-effect transistor 40 is disposed above the lower electrode 32. Specifically, the oxide semiconductor layer 70 of the field-effect transistor 40 is located above the lower electrode 32 in a direction away from the semiconductor substrate 10.

[0047] The upper electrode 50 is located above the oxide semiconductor layer 70 in a direction away from the semiconductor substrate 10. With this structure, the field-effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (vertical direction) that is substantially perpendicular to the surface of the semiconductor substrate 10.

[0048] Furthermore, the oxide semiconductor layer 70 is an oxygen-deficient semiconductor that serves as a donor, and the metal elements include indium (In), zinc (Zn), and gallium (Ga). Specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, namely indium gallium zinc oxide (IGZO) (InGaZnO). Moreover, the oxide semiconductor layer 70 can also be other types of oxide semiconductors.

[0049] Figure 3 shows a cross-sectional view of the semiconductor device 30 when observed in a section 70ZX parallel to the ZX plane and within the oxide semiconductor layer 70. Figure 4 shows a cross-sectional view of the semiconductor device 30 when observed in a section 70YZ parallel to the YZ plane and within the oxide semiconductor layer 70. Figure 5 is a cross-sectional view at the cut line VV shown in Figures 3 and 4.

[0050] As shown in Figures 3-5, compared to the semiconductor device 30 shown in Figure 2, the semiconductor device 30 includes an insulating film 321 (an example of a "first insulating film") instead of a gate insulating film 43, and further includes a spacer film 311 (an example of a "third insulating film"). The insulating layer 45 includes: an insulating film 45a, an insulating film 45b (an example of a "fourth insulating film" and a "first interlayer insulating film"), and an insulating film 45c (an example of a "second insulating film").

[0051] Multiple conductive layers 42 are repeatedly disposed in the X-axis direction (an example of the "second direction"). Multiple oxide semiconductor layers 70 are arranged in two dimensions. That is, a portion of the multiple oxide semiconductor layers 70 is repeatedly disposed along the Y-axis direction (an example of the "first direction"). In addition, another portion of the multiple oxide semiconductor layers 70 is repeatedly disposed along the X-axis+ direction.

[0052] The conductive layer 42 is formed of a first conductive material. In this embodiment, the conductive layer 42 comprises tungsten. Alternatively, the conductive layer 42 may also be a structure containing other elements.

[0053] The conductive layer 42 extends along the Y-axis. Specifically, the conductive layer 42 includes: a surrounding portion 42b surrounding the oxide semiconductor layer 70; and a connecting portion 42c connecting the two surrounding portions 42b.

[0054] The surrounding portion 42b in the conductive layer 42 has a hole 405 extending in the vertical direction. The oxide semiconductor layer 70 passes through the hole 405.

[0055] When the conductive layer 42 is viewed from above, the width of the connecting portion 42c in the X-axis direction is narrower than the width of the surrounding portion 42b in the X-axis direction.

[0056] The insulating film 321 is formed of a first insulating material. The first insulating material contains silicon and nitrogen. In this embodiment, the insulating film 321 is a silicon nitride. Alternatively, the insulating film 321 may also be an oxide of silicon, an oxide of hafnium, or an oxide of aluminum, etc.

[0057] The insulating film 321 includes: an upper gate film portion 321a, a lower gate film portion 321b, and a gate insulating film portion 321c.

[0058] The upper gate film portion 321a covers the upper surface 42d of the conductive layer 42. The lower gate film portion 321b covers the lower surface 42e of the conductive layer 42.

[0059] The gate insulating film portion 321c covers the first surface of the conductive layer 42 facing the oxide semiconductor layer 70. In this embodiment, the gate insulating film portion 321c covers the inner wall surface 405b of the hole portion 405. The gate insulating film portion 321c is in contact with the oxide semiconductor layer 70 and surrounds the center portion of the oxide semiconductor layer 70 away from the upper end 70a and the lower end 70b.

[0060] The upper gate film portion 321a, the lower gate film portion 321b, and the gate insulating film portion 321c are integrally formed. That is, the composition of each element in the upper gate film portion 321a, the lower gate film portion 321b, and the gate insulating film portion 321c is substantially the same.

[0061] The conductive layer 42 has a side surface 42f with the X-axis direction as its normal direction. The side surface 42f is not covered by the insulating film 321 and is in contact with the insulating film 45c.

[0062] The insulating film 45c is formed, for example, of a second insulating material different from the first insulating material. In this embodiment, the insulating film 45c is an oxide of silicon.

[0063] The spacer film 311 (an example of a "third insulating film") is formed of a third insulating material different from the first insulating material. The oxygen permeability of the first insulating material is lower than that of the third insulating material. In this embodiment, the spacer film 311 is, for example, an oxide of silicon.

[0064] The spacer film 311 has a hole 401 (an example of a "first hole") and is disposed above the gate upper film portion 321a. The hole 401 extends in the vertical direction and is penetrated and connected to the oxide semiconductor layer 70.

[0065] In detail, the spacer membrane 311 includes a cylindrical portion 311a and a plate-shaped portion 311b. The cylindrical portion 311a is disposed above the surrounding portion 42b in the conductive layer 42, separating the upper membrane portion 321a of the gate, and extends substantially parallel to the Z-axis.

[0066] The cylindrical portion 311a has a hole 401. The lower end of the cylindrical portion 311a forms an annular surface that contacts the upper gate film portion 321a. The inner wall surface 401b of the hole 401 contacts the oxide semiconductor layer 70 and surrounds a portion of the upper part of the oxide semiconductor layer 70 around its entire circumference. The plate-shaped portion 311b is disposed above the connecting portion 42c in the conductive layer 42, separating the upper gate film portion 321a, and extends along a plane substantially parallel to the XY plane.

[0067] An insulating film 45a is disposed above the plate-shaped portion 311b. The insulating film 45a is, for example, an oxide of silicon.

[0068] The insulating film 45b is formed of a fourth insulating material, which is different from the first insulating material. The oxygen permeability of the first insulating material is lower than that of the fourth insulating film. In this embodiment, the insulating film 45b is, for example, an oxide of silicon.

[0069] An insulating film 45b has a hole 403 (an example of a "third hole") and is disposed below the lower gate film portion 321b. The hole 403 extends in the vertical direction and is penetrated and connected to the oxide semiconductor layer 70. The inner wall surface 403b of the hole 403 is in contact with the oxide semiconductor layer 70 and surrounds a portion of the lower part of the oxide semiconductor layer 70 around its entire circumference.

[0070] The insulating film 45c will break between two adjacent conductive layers 42 in the X-axis direction. Specifically, the insulating film 45c is located between the two adjacent conductive layers 42 in the X-axis direction and extends substantially parallel to the Y-axis.

[0071] The upper end of the insulating film 45c is connected to the lower surface of the insulating film 45a. The lower part of the insulating film 45c is embedded in the insulating film 45b. In this embodiment, the insulating film 45a and the insulating film 45c are integrally formed.

[0072] Figure 6 shows a cross-sectional view of the semiconductor device 30 near the word line contact when viewed in a cross-section 70YZ parallel to the YZ plane and within the oxide semiconductor layer 70.

[0073] As shown in Figure 6, the semiconductor device 30 further includes a through-hole electrode 270. The through-hole electrode 270 is formed of a first conductive material. That is, the through-hole electrode 270 contains tungsten.

[0074] The through-hole electrode 270 is formed in the insulating layer 45 and has an upper end 270a (an example of a "second upper end") and a lower end 270b (an example of a "second lower end"). The through-hole electrode 270 is a columnar body extending in the Z-axis+ direction from the lower end 270b toward the upper end 270a.

[0075] The through-hole electrode 270 is electrically connected to the conductive layer 42. In this embodiment, the through-hole electrode 270 penetrates the conductive layer 42. Alternatively, the through-hole electrode 270 may not penetrate the conductive layer 42.

[0076] The spacer membrane 311 then forms a pore 402 (an example of a "second pore"), which extends in the vertical direction and is penetrated by a portion above the through-hole electrode 270.

[0077] In detail, the spacer membrane 311 further includes a cylindrical portion 311c. The cylindrical portion 311c is disposed above the conductive layer 42, separating the upper membrane portion 321a of the gate, and extends substantially parallel to the Z-axis.

[0078] The cylindrical portion 311c has a hole 402. The lower end of the cylindrical portion 311c forms an annular surface that connects with the upper gate membrane portion 321a in the insulating membrane 321.

[0079] The insulating film 45b then forms a hole 404 (an example of a "fourth hole"), which extends in the vertical direction and is penetrated by the through-hole electrode 270.

[0080] The insulating film 321 further includes an upper membrane portion 321d and a lower membrane portion 321e of the through hole. The upper membrane portion 321d and the lower membrane portion 321e of the through hole respectively cover the inner wall surface 402b of the hole portion 402 and the inner wall surface 404b of the hole portion 404.

[0081] In detail, the upper membrane portion 321d of the through hole has a generally cylindrical shape. The outer peripheral surface of the upper membrane portion 321d of the through hole is in full contact with the inner wall surface 402b of the hole portion 402. In other words, the inner wall surface 402b surrounds the upper membrane portion 321d of the through hole around its entire circumference.

[0082] The inner circumferential surface of the upper membrane portion 321d of the through hole is in full contact with the upper portion of the through hole electrode 270. That is, the upper membrane portion 321d of the through hole surrounds the upper portion of the through hole electrode 270 around its entire circumference. In other words, the upper membrane portion 321d of the through hole covers the upper portion of the through hole electrode 270 between the cylindrical portion 311c and the upper portion of the through hole electrode 270.

[0083] The lower membrane portion 321e of the through hole has a generally cylindrical shape. The outer peripheral surface of the lower membrane portion 321e is in full contact with the inner wall surface 404b of the hole portion 404. In other words, the inner wall surface 404b surrounds the lower membrane portion 321e of the through hole around its entire circumference.

[0084] The inner circumferential surface of the lower portion of the via-hole film 321e is in full contact with the lower portion of the via-hole electrode 270. That is, the lower portion of the via-hole film 321e surrounds the lower portion of the via-hole electrode 270 around its entire circumference. In other words, the lower portion of the via-hole film 321e covers the lower portion of the via-hole electrode 270 between the insulating film 45b and the lower portion of the via-hole electrode 270.

[0085] [Semiconductor device manufacturing method] Hereinafter, as an example of a method for manufacturing a semiconductor device according to a first embodiment, the method for manufacturing a semiconductor device 30 will be described.

[0086] First, as shown in Figures 7 and 8, insulating films 45b, 142, and 45ba are sequentially disposed above insulating layer 35. Insulating films 45b, 142, and 45ba extend along a plane substantially parallel to the XY plane. Insulating film 142 is, for example, a silicon nitride. A transistor hole TH is formed, extending substantially parallel to the Z-axis and penetrating insulating films 45ba, 142, and 45b, and then cleaned. At the bottom of transistor hole TH, the lower electrode 32 is exposed.

[0087] Next, as shown in Figures 9-12, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30. Herein, the transistor hole TH is filled by the sacrificial amorphous silicon layer 170.

[0088] Next, as shown in Figure 13, a mask is formed on the surface of the semiconductor device 30 by photolithography, including film deposition, resist coating, exposure, development, and stripping. Then, a via VH extending substantially parallel to the Z-axis is formed on the semiconductor device 30 by etching. In this embodiment, the via VH penetrates to the conductor 33 through insulating films 45ba, 142, and 45b. Below the via VH is a hole 404 formed in the insulating film 45b.

[0089] Next, as shown in Figures 14-16, the insulating film 142 inside the via VH and the insulating film 142 between the insulating films 45ba and 45b are removed by etching with phosphoric acid solution, forming a cavity 242.

[0090] Next, as shown in Figures 17-19, an insulating film 321 is formed, for example, by atomic layer deposition. Specifically, an upper gate film portion 321a and a lower gate film portion 321b are formed on the surface below the insulating film 45ba and the surface above the insulating film 45b, respectively. A gate insulating film portion 321c is formed around the sacrificial amorphous silicon layer 170 exposed in the void 242. An upper via film portion 321d and a lower via film portion 321e are formed on the inner wall surface 402b of the hole 402 and the inner wall surface 404b of the hole 404, respectively.

[0091] Next, as shown in Figure 20, the top of the semiconductor device 30 is etched back by reactive ion etching to expose the conductor 33 at the bottom of the via VH.

[0092] Next, as shown in Figures 21-24, tungsten is filled into the voids 242 by physical vapor deposition to form a conductive layer 42. Herein, the conductive layer 42 is electrically connected to the conductor 33.

[0093] Next, as shown in Figures 25 and 26, the sacrificial amorphous silicon layer 170 is etched back, thereby removing a portion of the upper part of the sacrificial amorphous silicon layer 170 to expose the upper surface of the insulating film 45ba. At this time, the upper end of the sacrificial amorphous silicon layer 170 is located above the conductive layer 42, for example, inside the transistor hole TH.

[0094] Next, as shown in Figures 27 and 28, the insulating film 45ba is removed by etching. This exposes the upper gate film portion 321a.

[0095] Next, as shown in Figures 29 and 30, a spacer film 311 is formed above the semiconductor device 30. Thereby, the sacrificial amorphous silicon layer 170 exposed above the gate upper film portion 321a and the surface above the gate upper film portion 321a are covered by the spacer film 311.

[0096] Next, as shown in Figures 31 and 32, a mask layer 145 with a groove 145a extending substantially parallel to the Y-axis is formed by photolithography on the surface of the semiconductor device 30, including film formation, resist coating, exposure, development and stripping.

[0097] Next, as shown in Figures 33-35, a groove 45ca extending through the insulating film 45b and substantially parallel to the Y-axis is formed in the semiconductor device 30 by etching. This separates the spacer film 311 into a cylindrical portion 311a and a plate-like portion 311b. Furthermore, the conductive layer 42 is separated into a plurality of electrodes extending substantially parallel to the Y-axis and repeatedly disposed in the X-axis+ direction. These electrodes correspond to the character line WL (see Figure 1).

[0098] Furthermore, the surrounding portion 42b in the conductive layer 42 is formed by a self-aligning process. In detail, even if the mask formation position based on the photolithography is off, since the cylindrical portion 311a of the spacer film 311 located on the side of the sacrificial amorphous silicon layer 170 functions as a mask, the surrounding portion 42b is also formed in a self-aligned manner around the transistor hole TH.

[0099] Next, as shown in Figures 36 and 37, insulating films 45c and 45a are integrally formed on the surface of the semiconductor device 30. Then, chemical mechanical polishing is performed on the surface above the semiconductor device 30, thereby exposing the surface above the sacrificial amorphous silicon layer 170 from the insulating film 45a.

[0100] Next, as shown in Figures 38 and 39, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0101] Next, as shown in Figures 40 and 41, an oxide semiconductor layer 70 is formed inside the transistor hole TH. Then, the surface above the semiconductor device 30 is chemically mechanically polished.

[0102] Next, as shown in Figures 42 and 43, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the surface above the semiconductor device 30. Then, an LPHM (Landing Pad Hard Mask) film 50e, for example containing silicon oxide, is formed on top of the metal film 50c.

[0103] Next, as shown in Figures 44 and 45, a mask is formed on the surface of the semiconductor device 30 by photolithography, including film deposition, resist coating, exposure, development, and stripping. Then, an upper electrode 50, which functions as a landing pad, is formed on the semiconductor device 30 by etching. The upper electrode 50 includes a barrier metal layer 51a, a barrier metal layer 50b, and a metal film 50c.

[0104] Next, as shown in Figures 46 and 47, an LP substrate 50d, for example, comprising silicon oxide, is formed on the surface above the semiconductor device 30. An insulating layer 63 is formed above the LP substrate 50d to fill the gaps formed by the LP substrate 50d. The insulating layer 63, for example, comprises silicon oxide. Then, the surface above the semiconductor device 30 is chemically mechanically polished.

[0105] Next, as shown in Figures 48 and 49, a barrier metal layer 51a, a conductive layer 51b, and a barrier metal layer 51c are formed from bottom to top on the surface above the semiconductor device 30. The barrier metal layers 51a and 51c may contain, for example, titanium nitride. The conductive layer 51b may contain, for example, tungsten.

[0106] Then, on the surface above the barrier metal layer 51c, BLHM (Bit Line Hard Mask) films 66a and 66b are formed from bottom to top. BLHM films 66a and 66b may contain, for example, silicon nitride and silicon oxide, respectively.

[0107] Next, as shown in Figures 50 and 51, a mask is formed on the surface of the semiconductor device 30 by photolithography, including film deposition, resist coating, exposure, development, and stripping. Then, a trench 66ca is formed on the semiconductor device 30 by etching, penetrating the insulating layer 63 and the metal film 50c and extending substantially parallel to the X-axis. Here, the barrier metal layer 51a, conductive layer 51b, and barrier metal layer 51c are separated into electrodes extending substantially parallel to the X-axis and repeatedly disposed in the Y-axis+ direction. These electrodes correspond to bit lines BL (see Figure 1).

[0108] Next, as shown in Figures 3 and 4, an insulating film 66c is formed above the semiconductor device 30 for the buried trench portion 66ca. The insulating film 66c may contain, for example, silicon oxide.

[0109] (Effect) As shown in Figure 52, in the comparative example of the semiconductor device 90, a gate insulating film 43 is sometimes provided on the inner surface of the transistor hole TH instead of the insulating film 321.

[0110] For example, in a process where the bottom of the gate insulating film 43 is etched back using reactive ion etching to expose the lower electrode 32, sometimes the bottom of the gate insulating film 43 cannot be completely removed, leaving a portion remaining. This situation is more likely to occur when the dielectric constant of the gate insulating film 43 is high.

[0111] In this situation, sufficient conduction current cannot be obtained. In addition, the contact area between the oxide semiconductor layer 70 and the lower electrode 32 deviates, or gate leakage increases, resulting in decreased reliability.

[0112] Furthermore, when the gate insulating film 43 is formed in the transistor hole TH, the film is formed with the lower electrode 32 exposed. Therefore, when the temperature is increased by heating, the ITO on the lower electrode 32 may sometimes disappear due to the temperature rise.

[0113] In contrast, in the semiconductor device 30, since the process of etching back the bottom of the gate insulating film 43 by reactive ion etching is not performed, a portion of the bottom of the gate insulating film 43 can be prevented from remaining.

[0114] Furthermore, since the insulating film 321 is formed while the lower electrode 32 is prevented from being exposed by using the sacrificial amorphous silicon layer 170, the disappearance of the lower electrode 32 can be suppressed.

[0115] Furthermore, by having the gate upper film portion 321a surround the central portion of the oxide semiconductor layer 70 away from the upper end 70a and the lower end 70b, and the spacer film 311 and the insulating film 45b respectively surround the upper part (hereinafter, sometimes referred to as the upper semiconductor portion) and the lower part (hereinafter, sometimes referred to as the lower semiconductor portion) of the oxide semiconductor layer 70, the situation where the oxygen permeability of the upper semiconductor portion and the lower semiconductor portion is significantly different can be suppressed.

[0116] This allows the oxygen content in the upper and lower parts of the semiconductor to be nearly symmetrical, thus making the resistance value of the upper part of the semiconductor similar to that of the lower part. Therefore, even if the source and drain are reversed, a symmetrical conduction current can still be obtained.

[0117] Furthermore, since the dielectric constant of the material between the conductive layer 42 and the upper part of the semiconductor can be made close to that of the material between the conductive layer 42 and the lower part of the semiconductor, the situation where the edge electric field between the conductive layer 42 and the upper part of the semiconductor is significantly different from that between the conductive layer 42 and the lower part of the semiconductor can be suppressed.

[0118] [Second Implementation Form] The semiconductor device 30B according to the second embodiment will be described. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same effects resulting from the same structure will not be mentioned sequentially for each embodiment.

[0119] Figure 53 shows a cross-sectional view of the semiconductor device 30B when observed in a cross-section 70YZ parallel to the YZ plane and within the oxide semiconductor layer 70.

[0120] As shown in FIG53, the semiconductor device 30B of the second embodiment, compared with the semiconductor device 30 shown in FIG3 to FIG5, includes a gate insulating film 43 instead of an insulating film 321, and further includes an interface film 501 (an example of the "first film").

[0121] The gate insulating film 43 is cylindrical with a hole 43a extending in the vertical direction, and penetrates the insulating film 45a, the conductive layer 42, and the insulating film 45b. The outer peripheral surface of the gate insulating film 43 is in full contact with the inner wall surface of the transistor hole TH. In other words, the inner wall surface of the transistor hole TH surrounds the gate insulating film 43 around its entire circumference.

[0122] The inner circumferential surface of the gate insulating film 43 is in full contact with the side surface of the oxide semiconductor layer 70. That is, the gate insulating film 43 surrounds the side surface of the oxide semiconductor layer 70 around its entire circumference.

[0123] An interface film 501 is disposed between the oxide semiconductor layer 70 and the lower electrode 32, and is electrically connected to both the oxide semiconductor layer 70 and the lower electrode 32. In this embodiment, the interface film 501 is disposed between the oxide semiconductor layer 70, the insulating film 45b, and the lower electrode 32.

[0124] Specifically, in the insulating layer 35 (an example of a "second interlayer insulating film"), a hole 35a (an example of a "fifth hole") extending in the vertical direction is formed. An interface film 501 is disposed inside the hole 35a and is flat and columnar. The interface film 501 is exposed from the insulating layer 35. Specifically, the upper surface 501a of the interface film 501 is exposed from the opening 35c of the hole 35a and is in contact with the lower end 70b of the oxide semiconductor layer 70, the lower end 43c of the gate insulating film 43, and the lower surface of the insulating film 45b.

[0125] The lower electrode 32 has a cross-section with approximately the same shape as the interface film 501 and is a flattened columnar shape. The lower electrode 32 is disposed inside the insulating layer 35 and does not protrude from the insulating layer 35. Specifically, the lower electrode 32 is disposed inside the hole portion 35a and does not protrude from the opening portion 35c. In this embodiment, the lower electrode 32 is disposed below the interface film 501 and is in contact with the lower surface 501b of the interface film 501. The lower electrode 32, through the dielectric conductor 21, faces the capacitor electrode 24 disposed below it.

[0126] The contact area between the lower surface 501b of the interface film 501 and the lower electrode 32 (hereinafter, sometimes referred to as the lower contact area) is larger than the contact area between the lower end 70b of the oxide semiconductor layer 70 and the upper surface 501a of the interface film 501 (hereinafter, sometimes referred to as the upper contact area).

[0127] The sides of the interface film 501, the lower electrode 32, and the capacitor electrode 24 are surrounded by the conductor 21. The insulating film 22 surrounds the conductor 21. The upper outer peripheral surface of the insulating film 22 is in full contact with the inner wall surface 35b of the hole 35a.

[0128] The interface film 501 is formed of a semiconductor or conductor and contains atoms with a binding energy greater than that between oxygen atoms and indium atoms in the lower electrode 32.

[0129] In this embodiment, the interface film 501 includes, for example, gallium. The interface film 501 is, for example, an oxide semiconductor (an example of a "second oxide semiconductor"). Specifically, the interface film 501 includes indium, gallium, zinc, and oxygen. More specifically, the interface film 501 is IGZO. Furthermore, the interface film 501 may also be indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), InO, ZnO, GaO, and SnO, etc.

[0130] The composition ratio of indium, gallium and zinc in the oxide semiconductor layer 70 is different from that in the interface film 501.

[0131] [Semiconductor device manufacturing method] The following describes a method for manufacturing a semiconductor device 30B as an example of a method for manufacturing a semiconductor device according to a second embodiment.

[0132] First, as shown in FIG54, a hole 35a is formed in the insulating layer 35. An insulating film 22, a conductor 21, and a capacitor electrode 24 are formed inside the hole 35a.

[0133] Next, as shown in FIG55, a conductor 21 is further formed above the semiconductor device 30B. The conductor 21 functions, for example, as a barrier film.

[0134] Next, as shown in FIG56, a lower electrode 32 is formed above the semiconductor device 30B.

[0135] Next, as shown in FIG57, the upper surface of the semiconductor device 30B is chemically mechanically polished to expose the lower electrode 32 from the opening 35c.

[0136] Next, as shown in FIG58, the upper surface of the lower electrode 32 is lowered by wet etching so that the lower electrode 32 is not exposed from the opening 35c.

[0137] Next, as shown in FIG59, an interface film 501 is formed above the semiconductor device 30B.

[0138] Next, as shown in FIG60, the surface above the semiconductor device 30B is chemically mechanically polished, thereby exposing the upper surface 501a of the interface film 501 from the opening 35c of the hole 35a.

[0139] Next, as shown in Figure 61, an insulating film 45b, a conductive layer 42, and an insulating film 45a are sequentially disposed above the insulating layer 35. A transistor hole TH is formed, extending approximately parallel to the Z-axis and penetrating the insulating film 45b, the conductive layer 42, and the insulating film 45a, followed by cleaning. A gate insulating film 43 is formed on the inner surface of the transistor hole TH. At this time, since the gate insulating film 43 is formed by heating, the ITO of the lower electrode 32 disappears due to the temperature rise.

[0140] Next, as shown in Figure 62, the bottom of the gate insulating film 43 is etched back by reactive ion etching, exposing the interface film 501 at the bottom of the transistor hole TH.

[0141] Next, as shown in Figure 53, an oxide semiconductor layer 70 is formed inside the transistor hole TH. Then, the surface above the semiconductor device 30B is chemically mechanically polished.

[0142] Furthermore, in the semiconductor device 30B shown in FIG. 56, the conductor 21 is not limited to the interior of the hole 35a, but is formed by extending from the opening 35c to the exterior of the hole 35a. On the other hand, as shown in FIG. 63, when the conductor 21 is formed to extend into the interior of the hole 35a, the chemical mechanical polishing step shown in FIG. 57 and the wet etching step shown in FIG. 58 can be omitted, and an interface film 501 is formed on the top of the semiconductor device 30B as shown in FIG. 64.

[0143] (Effect) For example, if the indium concentration in the interface film 501 is greater than the indium concentration in the oxide semiconductor layer 70, the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32 can be reduced.

[0144] Even when the zinc concentration in the interface film 501 is higher than the zinc concentration in the oxide semiconductor layer 70, the contact resistance can still be reduced. Similarly, even when the gallium concentration in the interface film 501 is lower than the gallium concentration in the oxide semiconductor layer 70, the contact resistance can still be reduced. Furthermore, when the indium concentration in the interface film 501 is higher than the indium concentration in the oxide semiconductor layer 70, the contact resistance can be effectively reduced.

[0145] Furthermore, even when the gallium concentration of the interface film 501 is low and the zinc concentration of the interface film 501 is high compared to the oxide semiconductor layer 70, the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32 can still be reduced.

[0146] Furthermore, assuming that the lower electrode 32 is exposed without the interface film 501, the ITO on the lower electrode 32 may sometimes disappear due to the temperature rise during the formation of the gate insulating film 43 by heating.

[0147] The binding energy with oxygen decreases in the order of gallium, indium, and zinc. By providing a structure with an interface film 501 containing gallium, the interface film 501 can function as a robust cap. This helps to suppress the disappearance of the lower electrode 32 during the formation of the gate insulating film 43.

[0148] That is, when the gallium concentration in the interface film 501 is greater than the gallium concentration in the lower electrode 32, the disappearance of the lower electrode 32 during the formation of the gate insulating film 43 can be suppressed because the binding energy between gallium and oxygen is greater.

[0149] In addition, by using a structure where the lower contact area is larger than the upper contact area, the contact area between ITO and IGZO can be increased, thereby reducing the contact resistance with the lower electrode 32.

[0150] Furthermore, in the semiconductor device 30, the structure in which the lower electrode 32 is physically connected to the oxide semiconductor layer 70 has been described, but it is not limited to this. If the lower electrode 32 is electrically connected to the oxide semiconductor layer 70, it can also be a structure in which the lower electrode 32 is not physically connected to the oxide semiconductor layer 70.

[0151] Furthermore, in the semiconductor device 30, the structure in which the upper electrode 50 is physically connected to the oxide semiconductor layer 70 has been described, but it is not limited to this. If the upper electrode 50 is electrically connected to the oxide semiconductor layer 70, it may also be a structure in which the upper electrode 50 is not physically connected to the oxide semiconductor layer 70.

[0152] Furthermore, in the semiconductor device 30B, the structure in which the interface film 501 is physically connected to the oxide semiconductor layer 70 has been described, but it is not limited to this. If the structure is an electrical connection between the interface film 501 and the oxide semiconductor layer 70, it may also be a structure in which the interface film 501 is not physically connected to the oxide semiconductor layer 70.

[0153] Furthermore, in the semiconductor device 30B, a structure in which the interface film 501 is physically connected to the lower electrode 32 has been described, but it is not limited to this. If the interface film 501 is electrically connected to the lower electrode 32, then it may also be a structure in which the interface film 501 is not physically connected to the lower electrode 32.

[0154] The present embodiment has been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Any design modifications made by those skilled in the art to these specific examples that possess the features of this disclosure are also included within the scope of this disclosure. The components included in each specific example, as well as their configuration, conditions, shapes, etc., are not limited to those illustrated and can be appropriately modified. The combinations of the components included in each specific example can be appropriately changed as long as no technical contradiction arises.

[0155] 10: Semiconductor substrate 11: Circuit 20: Capacitor 21, 23: Conductors 22, 45a, 45b, 45ba, 45c, 66c, 142, 321: Insulating film 24, 25: Capacitor electrodes 30, 30B, 90: Semiconductor devices 32: Lower electrode 33: Conductor 34, 35, 45, 63: Insulation layer 35a, 43a, 401, 402, 403, 404, 405: Hole section 35b, 401b, 402b, 403b, 404b, 405b: inner wall surface 35c: Opening 40: Field-effect transistor 42, 51b: Conductive layer 42b: Enclosure 42c: Connecting part 42d, 501a: Upper surface 42e, 501b: Lower surface 42f: Side view 43: Gate insulating film 43c: End 45ca, 66ca, 145a: Groove section 50: Upper electrode 50a: Metal oxide layer 50b, 51a, 51c: Barrier metal layer 50c: Metallic film 50d:LP liner 50e:LPHM membrane 66a, 66b: BLHM membrane 70: Oxide semiconductor layer 70a, 270a: Upper end 70b, 270b: Lower end 70YZ, 70ZX: Sections 101: Semiconductor memory device 145: Masking layer 170: Sacrificial amorphous silicon layer 242: Void 270: Through-hole electrode 311: Spacer membrane 311a, 311c: Cylindrical section 311b: plate-shaped part 321a: Upper membrane part of gate 321b: Lower gate membrane section 321c: Gate insulating film section 321d: Upper membrane portion of the through-hole 321e: Lower part of the membrane section of the through-hole 501: Interface film BL, BL m, BL m+1, BL m+2: Bit lines MC: Memory Unit MCP: Memory Capacitor MTR: Memory Transistor TH: Transistor aperture VV, XI-XI, XXIII-XXIII, XXXV-XXXV: Cut wire VH: Through hole WL, WL n, WL n+1, WL n+2: Character lines X, Y, Z: Axes

Claims

1. A semiconductor device, comprising: The gate electrode extends in the first direction; An oxide semiconductor extends in a vertical direction intersecting the first direction and penetrates the gate electrode; A first electrode is connected to a first lower end of the oxide semiconductor; a second electrode is connected to a first upper end of the oxide semiconductor; and a first insulating film includes an upper gate film covering the upper surface of the gate electrode, a lower gate film covering the lower surface of the gate electrode, and a gate insulating film covering a first surface of the gate electrode facing the oxide semiconductor, and is formed of a first insulating material. The semiconductor device further includes a second insulating film, the second insulating film comprising a second insulating material different from the first insulating material, the gate electrode having a side surface with a second direction intersecting the vertical direction and the first direction as a normal direction, and the second insulating film being in contact with the side surface.

2. The semiconductor device of claim 1, wherein the first insulating material comprises silicon and nitrogen.

3. The semiconductor device as claimed in claim 1, wherein the semiconductor device further comprises: A via electrode has a second upper end and a second lower end, and extends in the vertical direction; a third insulating film is respectively penetrated by the oxide semiconductor and the via electrode, and is disposed above the upper gate film portion; and a fourth insulating film is respectively penetrated by the oxide semiconductor and the via electrode, and is disposed below the lower gate film portion. The second lower end of the via electrode is electrically connected to the semiconductor circuit. The first insulating film further includes: an upper via film portion covering the via electrode between the third insulating film and the via electrode; and a lower via film portion covering the via electrode between the fourth insulating film and the via electrode. The gate electrode includes a first conductive material, and the via electrode includes the first conductive material and is electrically connected to the gate electrode.

4. The semiconductor device as claimed in claim 1, wherein the semiconductor device further comprises: The third insulating film is formed of a third insulating material that is different from the first insulating material; The third insulating film is formed of a fourth insulating material different from the first insulating material. The third insulating film is penetrated by and connected to the oxide semiconductor and is disposed above the upper part of the gate film. The fourth insulating film is penetrated by and connected to the oxide semiconductor and is disposed below the lower part of the gate film.

5. The semiconductor device of claim 4, wherein the oxygen permeability of the first insulating material is less than that of the third insulating material.

6. The semiconductor device of claim 4, wherein the oxygen permeability of the first insulating material is less than that of the fourth insulating material.

7. The semiconductor device of claim 1, wherein the first electrode comprises a metal oxide.

8. A semiconductor device, comprising: The first oxide semiconductor extends in the vertical direction; A first interlayer insulating film extends along a plane parallel to a direction intersecting the vertical direction and is penetrated by the first oxide semiconductor; a first electrode contains oxygen, indium, and tin; a first film is disposed between the first oxide semiconductor and the first electrode, electrically connected to the first oxide semiconductor and the first electrode, and is formed of a semiconductor or conductor; and a gate electrode is separated from the gate insulating film and faces the first oxide semiconductor, the first film containing atoms with a binding energy greater than the binding energy between oxygen atoms and indium atoms in the first electrode.

9. The semiconductor device of claim 8, wherein the first film is disposed between the first oxide semiconductor and the first interlayer insulating film and the first electrode.

10. The semiconductor device of claim 8, wherein the gate insulating film penetrates the first interlayer insulating film and surrounds the first oxide semiconductor, and the first film is in contact with the first interlayer insulating film, the gate insulating film and the first oxide semiconductor.

11. The semiconductor device of claim 8, wherein the semiconductor device further includes a second interlayer insulating film, the second interlayer insulating film being disposed such that the first interlayer insulating film is located between the second interlayer insulating film and the gate electrode, the first film being exposed from the second interlayer insulating film, and the first electrode being disposed inside the second interlayer insulating film and not exposed from the second interlayer insulating film.

12. The semiconductor device as claimed in claim 8, wherein the first film is a second oxide semiconductor.

13. The semiconductor device of claim 12, wherein the first oxide semiconductor and the second oxide semiconductor respectively comprise indium, gallium, zinc and oxygen, and the composition ratio of indium, gallium and zinc in the first oxide semiconductor is different from the composition ratio of indium, gallium and zinc in the second oxide semiconductor.

14. The semiconductor device of claim 8, wherein the first film comprises gallium.

15. The semiconductor device of claim 12, wherein the first film is in contact with the first electrode and the first oxide semiconductor, and the contact area between the first film and the first electrode is larger than the contact area between the first film and the first oxide semiconductor.

16. A semiconductor memory device, comprising: The semiconductor device as described in claim 1 or 8; The first capacitor electrode is connected to the first electrode; The second capacitor electrode faces the first capacitor electrode; And a dielectric film, disposed between the first capacitor electrode and the second capacitor electrode.

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