Memory circuit and method for operating the same

Abstract

A memory circuit includes: a memory array comprising a plurality of first memory cells, each of the first memory cells being used to store a data bit; a trace row comprising at least one second memory cell and a third memory cell, wherein the second memory cell is coupled to a first trace bit line, a second trace bit line and a trace word line, and the third memory cell is coupled to the first trace bit line; and a word line auxiliary circuit coupled to the memory array and the trace row. The word line auxiliary circuit can receive a control signal present on a control line coupled to the third memory cell; and increase a voltage level applied to an operating voltage of a word line in response to a change in the control signal.

Description

[Technical Field]

[0001] None. [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Primarily, this improvement in integration density has come from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. [Summary of the Invention]

[0003] None.

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify the embodiments of this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0007] Many modern electronic devices and systems include substantial computing power for controlling and managing a wide range of functions and useful applications. This computing power is typically provided by one or more processor cores. These processor cores operate as digital computers, thereby typically fetching executable instructions from memory, performing arithmetic and logical operations on the digital data fetched from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting data processed by the processor cores are executed as appropriate. Considering the large amounts of digital data typically involved in performing the complex functions of these modern devices, significant solid-state memory capabilities are usually implemented in the electronic circuitry for these systems.

[0008] Static random access memory (SRAM) has become the memory technology of choice for most of the solid-state data storage requirements of these modern power-conscious electronic systems. SRAM is a type of volatile semiconductor memory that uses bistable circuitry to store data bits without requiring new bistable circuitry. SRAM devices typically include one or more memory arrays, each array comprising a plurality of SRAM cells. SRAM cells are commonly referred to as memory cells (or bit cells) because they store one bit of information represented by the logic state of two cross-coupled inverters. Each memory array includes a plurality of bit cells configured in columns and rows. Each bit cell in the memory array includes connections to a power supply voltage and a reference voltage. Logic signals on the bit lines control reading from and writing to the bit cells, wherein word lines control the connections of the bit lines to inverters, which are otherwise floating. Word lines can be coupled to a plurality of bit cells along a column of the memory array, wherein different word lines are provided for different columns.

[0009] With the trend of rapid scaling, existing SRAM devices typically face increasing demands for reduced power consumption and increased speed. For example, in system-on-chip (SoC) applications, to reduce power consumption, the operating voltage of logic circuits can be reduced or turned off when in sleep or low-power mode to save power. However, in such SoC applications, processors (e.g., central computing unit (CPU), mobile accelerated processing unit (APU), etc.) may remain in sleep mode and require access to Level 1 (L1) cache memory (e.g., L1 data cache, L1 instruction cache). Therefore, the operating voltage of the SRAM device in the L1 cache SRAM device can affect the processor's operating voltage and overall power consumption. However, reducing the operating voltage of the SRAM device can lead to SRAM cell stability concerns, such as degraded write margin.

[0010] In this regard, word line (WL) auxiliary circuitry has been proposed. Typically, existing WL auxiliary circuitry is coupled to one or more word lines of the memory array and can boost the voltage (WL voltage) present on one of the asserted word lines. For example, the WL voltage can initially be provided equal to the supply voltage (VDD), and the WL voltage can be boosted to a higher voltage level by the activation of a corresponding charger or boost circuit. However, the timing associated with the activation time of the boost circuit is not well defined according to the actual operation of the corresponding memory array. For example, if the boost circuit is activated too early, data corruption occurs on the memory array. In another instance, if the boost circuit is activated too late, the performance of the memory array is degraded. Therefore, existing SRAM devices with WL auxiliary circuitry are not entirely satisfactory in certain configurations.

[0011] This disclosure provides various embodiments of a memory circuit including a memory array and word line auxiliary circuitry. In various embodiments, the WL auxiliary circuitry can be accurately activated based on a tracking signal simulating a propagation delay present in the memory array. For example, the memory array may include a plurality of nominal memory cells, and the memory circuitry may further include a tracking row physically and operatively coupled to the memory array. This tracking row may be integrated into the memory array. The tracking row may include various types of tracking cells. For example, a first tracking cell may simulate a propagation (or signal routing) delay on a nominal bit line of the memory array as a tracking signal present on the tracking bit line, a second tracking cell may simulate a load on the nominal bit line, and a third tracking cell may change a control signal in response to detecting a change in the tracking signal. As disclosed herein, the memory circuitry may use the change in the control signal to activate the WL auxiliary circuitry, which is used to boost the WL voltage. In various embodiments of this disclosure, a third tracking unit, essentially acting as an inverter, is coupled between the tracking bit line and the control wiring representing the control signal. Therefore, the WL auxiliary circuit is not activated until the tracking signal (present on the tracking bit line) changes. In this way, the WL voltage boost can be precisely controlled. For example, the WL voltage is boosted after a sufficiently large voltage difference between the nominal bit line BL and the nominal bit line BLB is set. Therefore, the disclosed memory circuit is protected from data corruption and can operate at high speeds.

[0012] Figure 1 illustrates a block diagram of a memory device (or circuit) 100 according to various embodiments. In short, the memory circuit 100 disclosed herein may include a WL auxiliary circuit that can be accurately activated based on a tracking signal, and after activation, the WL auxiliary circuit can raise the voltage level present on the nominal word line WL. The memory circuit 100 illustrated in Figure 1 has been simplified for illustrative purposes, and therefore it should be understood that the memory circuit 100 may include any of a variety of other elements while remaining within the scope of the embodiments disclosed herein.

[0013] As shown in the figure, the memory circuit 100 includes a memory controller 102, a WL auxiliary circuit 104, a WL driver 106, a precharge circuit 108, an optional BL auxiliary circuit 110, and a memory array 120. In various embodiments, the memory array 120 may include a plurality of storage circuits or memory cells 125 configured as one or more two-dimensional or three-dimensional arrays. Each memory cell 125 may be coupled to one or more corresponding word lines (WL) and one or more corresponding bit lines (BL). The memory cell 125 used to store data bits, the coupled word line WL, and the coupled bit line BL are sometimes referred to as a nominal memory cell, a nominal word line WL, and a nominal bit line BL, respectively. Based on the electrical signals present on the corresponding nominal word line WL and nominal bit line BL, the memory controller 102 may write data to or read data from the nominal memory array 125. In other embodiments, the memory circuit 100 includes more, fewer, or different elements compared to that shown in Figure 1.

[0014] The memory array 120 is a hardware element for storing data bits. The memory array 120 includes nominal word lines WL0…WLJ each extending in a first direction (e.g., the X direction) and nominal bit lines BL0…BLK each extending in a second direction (e.g., the Y direction). In some embodiments, the memory array 120 may be referred to as having a plurality of rows and a plurality of columns, wherein each of the rows corresponds to a separate nominal bit line BL, and each of the columns corresponds to a separate nominal word line WL. In the example of Figure 1, the memory array 120 may include K rows and J columns of nominal memory cells 125. In some embodiments, the nominal word lines WL and nominal bit lines BL may be conductive metal or conductive rails. Each nominal memory cell 125 is coupled to at least one corresponding nominal word line WL and at least one corresponding nominal bit line BL, and can operate according to the voltage or current passing through the corresponding nominal word line WL and the corresponding nominal bit line BL.

[0015] In some embodiments, each nominal bit line includes nominal bit lines BL and BLB coupled to one or more nominal memory cells 125 disposed along a second direction (e.g., the Y direction). The nominal bit lines BL and BLB may receive and / or provide differential signals. Each nominal memory cell 125 may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each nominal memory cell 125 is embodied as a static random access memory (SRAM) cell or other types of memory cell. In some embodiments, the memory array 120 includes additional wiring (e.g., select wiring, reference wiring, reference control wiring, power rails, etc.) while remaining within the scope of the embodiments disclosed herein.

[0016] For example, the nominal memory cell 125 may be implemented as a six-transistor (6T) static random access memory (SRAM) cell consisting of six transistors. An example of a 6T SRAM cell can be better understood from the circuit diagram in Figure 2. Generally, the nominal memory cell 125 may include a pair of access or pass transistors PG1 and PG2, which are biased (e.g., gated by the corresponding nominal word line WL) by the corresponding nominal word line WL. Access to the cross-coupled first inverter and second inverter is provided by the pass transistors PG1 and PG2, respectively. When the WL signal (voltage) fed to the gate terminals of the pass transistors PG1 and PG2 becomes true or the corresponding nominal word line WL is asserted, the pass transistors PG1 and PG2 can transmit bit line signals to the internal nodes of the cross-coupled first inverter and second inverter. In other words, when the nominal word line WL is asserted, the WL signal applied to the nominal word line WL can be turned on through gate transistors PG1 and PG2. The first inverter includes a pull-up (e.g., PMOS) transistor PU1 and a pull-down (e.g., NMOS) transistor PD1, and the second inverter includes a pull-up (e.g., PMOS) transistor PU2 and a pull-down (e.g., NMOS) transistor PD2. Gate transistors PG1 and PG2 are coupled to the first nominal bit line BL ("bit line") and the second nominal bit line BLB ("bit line bar"), respectively. This configuration is commonly referred to as a 6T (six-transistor) configuration.

[0017] During standby mode, the nominal word line WL has not been asserted, and therefore the nominal memory cell 125 is disconnected from the nominal bit lines, namely nominal BL and BLB, via transistors PG1 and PG2. Cross-coupled inverters are coupled between the power supply voltages (VDD and VSS) and are forced to maintain one of two possible logic states, wherein the stored data bit is at one of the internal nodes between the inverters (sometimes referred to as node Q or node BL_IN), and the complementary bit of that bit is at the other node between the inverters (sometimes referred to as node QB or node BLB_IN). During a read operation, nominal BL and BLB are precharged to a high logic state (e.g., logic 1), and nominal WL is asserted. The data bit stored at node Q is transferred to nominal BL, and the data bit at node QB is transferred to nominal BLB. During a write operation, when the nominal WL is asserted, the value to be written is provided at the nominal BL, and the complementary value of that value is provided at the nominal BLB. Although the 6T SRAM cell is described herein as an example implementation of memory cell 125, it should be understood that memory cell 125 may be implemented as other types of memory cells, including multiple types of memory other than SRAM and other types of SRAM configurations other than 6T (e.g., octet transistor (8T) or decaton transistor (10T) configurations), while remaining within the scope of the embodiments disclosed herein.

[0018] In addition to the nominal memory cells 125 used to store data bits, the memory circuitry 100 may include one or more tracking rows 130 disposed adjacent to or integrated into the memory array 120. For example, in Figure 1, the tracking row 130 may be disposed along one of the edges of the memory array 120, which extends parallel to the nominal bit lines BL0 to BLK. In various embodiments of the disclosed embodiments, each tracking row 130 may include a plurality of first tracking units 135, a plurality of second tracking units 140, and optionally a plurality of third tracking units 145. The first tracking units 135 may be used to simulate signal routing delay on the nominal bit line BL and present the simulated signal as a tracking signal, the second tracking units 140 may be used to provide control signals to activate the WL auxiliary circuit (e.g., 104) based on the transition of the tracking signal, and the third tracking units 145 may be used to simulate the loading of the nominal bit line BL, as will be discussed in further detail below. The first to third tracking units 135, 140, and 145 can be configured in any individual number, while remaining within the scope of the embodiments disclosed herein. In some embodiments, the total number of the first to third tracking units 135, 140, and 145 may be equal to the number of columns (J). As a non-limiting example, the number of the first tracking units 135 may be selected to simulate the worst-case conditions of write and / or read operations.

[0019] Tracking line 130 may further include at least one tracking word line (TRKWL) 150, at least one tracking bit line (TRKBL) 155, and at least one control line 160. In some embodiments, each of the first tracking units 135 may be coupled to the tracking word line TRKWL 150 and the tracking bit line TRKBL 155, each of the second tracking units 140 may be coupled to the tracking bit line TRKBL 155 and the control line 160, and each of the third tracking units 145 may be coupled to the tracking bit line TRKBL 155. The tracking word line TRKWL 150, the tracking bit line TRKBL 155, and the control line 160 are used to conduct respective tracking / control signals (e.g., TRKBL signal, TRKWL signal, ASTE signal, etc.), which will be discussed in more detail below.

[0020] For example, the trace word line TRKWL 150 may include a (e.g., horizontal) portion extending along a column (not explicitly shown) of the memory array 120, and a (e.g., vertical) portion extending along a row of the memory array 120, as shown in the first figure. The length of the vertical portion of the trace word line TRKWL 150 may be approximately equal to the height of the memory array (e.g., the distance from the memory controller 102 to the farthest trace unit of the trace row 130, depending on the orientation of the memory array in the first figure); and the length of the horizontal portion of the trace word line TRKWL 150 may be approximately equal to the width of the memory array 120 (e.g., the distance along any column from one edge of the array to the other, depending on the orientation of the memory array in the first figure). Therefore, the sum of the lengths of the first and second portions of the tracking character line TRKWL 150 can be configured such that the metal wiring delay for accessing the cell at the upper right corner of the memory array 120 is simulated, for example, the delay of signal input at the lower left portion that propagates horizontally and vertically over a path distance equal to the length of the path from one corner to the opposite corner.

[0021] Generally, the tracking units (135, 140, or 145) do not function, because the nominal memory units 125 function based on stored data and support read / write operations. Specifically, tracking units 135 to 145 may originally be a subset of the nominal memory units 125, but have been enumerated or reused for timing tracking. Therefore, in some embodiments, the tracking row 130 including tracking units 135 to 145 may be part of the memory array 120.

[0022] For example, the first tracking unit 135 is a bit cell with fixed logic values ​​configured and coupled to each other to respond predictably when addressed by a test or tracking signal. Some non-limiting implementations of the first tracking unit 135 will be discussed below. The second tracking unit 140 can essentially act as an inverter coupled between the tracking bit line TRKBL 155 and the control line 160. In response to detecting a transition edge (e.g., a falling edge) on the tracking bit line TRKBL 155, the second tracking unit 140 can cause a control signal (e.g., the ASTE signal mentioned above) present on the control line 160 to transition to activate the WL auxiliary circuit (e.g., 104). The third tracking unit 145 ensures that the capacitive and resistive environment is closely matched for an accurate modeling of the nominal memory cell environment. Typically, the tracked nominal bit line BL has two factors determining the propagation delay of the carried signal, namely the series resistance and the parallel capacitance. The third tracking unit 145 has a real capacitive load and mimics the capacitance coupled to the nominal bit line BL of the nominal memory cell. In some cases, if the third tracking unit 145 is not provided, the length of the tracking bit line will effectively appear to be shorter than the nominal bit line BL intended to be simulated. This will reduce resistance and capacitance and may cause the tracking circuit to determine that the read or write operation has been permanently terminated.

[0023] The memory controller 102 is a hardware component for controlling various operations of the memory array 120, such as reading data bits from the nominal memory cell 125, writing data bits into the nominal memory cell 125, and performing a tracing scheme for the individual timing of the read / write operations to activate the WL auxiliary circuit. In various embodiments of the disclosed embodiments, the WL auxiliary circuit (e.g., 104) can boost or otherwise increase the voltage level (sometimes referred to as the WL voltage) present on the asserted nominal word line WL after activation based on the tracing timing. Under this accurately boosted WL voltage, the performance (e.g., margin) of the various operations performed on the nominal memory cell 125 can be significantly improved. Although not explicitly illustrated, the memory controller 102 may include multiple circuits to perform such operations, each of which may be embodied as logic circuitry, analog circuitry, or a combination thereof.

[0024] Similarly, each of the WL auxiliary circuit 104, WL driver 106, precharge circuit 108, and BL auxiliary circuit 110 is a hardware component embodied as logic circuitry, analog circuitry, or a combination thereof to perform its respective operation. For example, the WL auxiliary circuit 104 may selectively boost the power supply voltage (e.g., VDD) based on a control signal (ASTE signal) provided by the second tracking unit 140. The WL driver 106 may apply a voltage (e.g., WL voltage) to one or more nominal word lines WL of the positively asserted memory array 120. The WL driver 106 may receive such WL voltages, which may be selectively boosted from the WL auxiliary circuit 104. The precharge circuit 108 may precharge the bit lines BL (including the nominal BL and the tracking BL) outside the normal (e.g., read or write) operation of the nominal memory cell 125. The precharge circuit 108 typically precharges the bit lines to the power supply voltage (VDD). An optional BL auxiliary circuit 110, operatively coupled to the precharge circuit 108, can reduce the voltage level present on those precharge bit lines BL to further improve the performance of the memory circuit 100 (e.g., increase the speed of write operations).

[0025] In some embodiments, the memory circuitry 100 may further include input / output (I / O) circuitry 170. The I / O circuitry 170 can sense voltage or current conducted through one or more nominal bit lines BL of the memory array 120. For example, the I / O circuitry 170 may include multiple sense amplifiers. Each of the sense amplifiers is operatively coupled to one or more of the nominal bit lines BL within the memory array 120. Once activated, each of the sense amplifiers amplifies a latched input value, which may be a voltage sensed from a corresponding nominal memory cell 125 via the coupled nominal bit lines BL / BLB.

[0026] Figure 2 illustrates an example circuit diagram of a portion of a memory circuit 100 according to some embodiments. For example, in Figure 2, the circuit implementations of the memory array 120, the tracking row 130, the WL auxiliary circuit 104, and the WL driver 106 are partially shown. The circuit diagram shown in Figure 2 has been simplified for illustrative purposes, and therefore it should be understood that the elements of the memory circuit 100 can be implemented in various other ways while remaining within the scope of the embodiments disclosed herein.

[0027] As described above, each of the nominal memory cells 125 of the memory array 120 may be implemented as a 6T SRAM cell, the 6T SRAM cell including gate transistors PG1 and PG2, pull-up transistors PU1 and PU2, and pull-down transistors PD1 and PD2, and coupled between a corresponding pair of nominal BL and BLB. In some embodiments of the disclosed embodiments, each of the tracking cells of the tracking row 130, such as the first tracking cell 135, the second tracking cell 140, and the third tracking cell 145, may be similar to the nominal memory cell 125 with individual modifications. Therefore, the following discussion regarding the tracking cells 135 to 145 will focus on the differences.

[0028] For example, the first tracking unit 135 includes six transistors 201, 202, 203, 204, 205, and 206, which are similarly configured as PU1, PU2, PD1, PD2, PG1, and PG2 of the nominal memory unit 125, respectively. Transistor 201 has its gate terminal connected to the gate terminal of transistor 203 (both of which are connected to VDD) while its source and drain terminals are both floating; and transistor 202 has its gate terminal connected to the gate terminal of transistor 204 while its source terminal is connected to VDD and its drain terminal is floating. Transistor 205 connects its gate to the tracking word line TRKWL 150, its drain to the tracking bit line TRKBL 155, and its source to ground voltage (VSS) via transistor 203; and transistor 206 connects its gate to the corresponding nominal word line WL (e.g., WL[0]), its drain to another tracking bit line TRKBLB 157, which is a complement to the tracking bit line TRKBL 155, and its source to ground voltage via transistor 204. With this configuration, after the tracking word line TRKWL 150 is asserted (e.g., the TRKWL signal is positively raised), transistor 205 can be turned on to discharge the tracking bit line TRKBL 155, which simulates the nominal bit line BL.

[0029] In another example, the second tracking unit 140 includes six transistors 211, 212, 213, 214, 215, and 216, which are similarly configured as PU1, PU2, PD1, PD2, PG1, and PG2 of the nominal memory unit 125, respectively. Transistor 211 has its gate connected to the gate of transistor 213, its source connected to a floating terminal, and its drain connected to the drain of transistor 213; and transistor 212 has its gate connected to the gate of transistor 214, its source connected to VDD, and its drain connected to the drain of transistor 214. The source of transistor 213 may also be floating. Transistor 215 connects its gate to ground voltage (VSS), its drain to tracking bit line TRKBL 155, and its source to the common node "X" between transistors 211 and 213; and transistor 216 connects its gate to the corresponding nominal word line WL (e.g., WL[J-1]), its drain to control wiring 160, and its source to the common node "Y" between transistors 212 and 214. Additionally, the second tracking unit 140 may include one or more conductive wires directly connecting tracking bit line TRKBL 155 to node X, and one or more second conductive wires directly connecting control wiring 160 to node Y.

[0030] In some embodiments, transistors 212 and 214 are operatively configured as inverters with inputs and outputs, wherein the input (e.g., node X) is coupled to the tracking bit line TRKBL 155. Therefore, when the TRKBL signal present on the tracking bit line TRKBL 155 changes (e.g., pulled low by the first tracking unit 135), the output (e.g., node Y) can thus change (e.g., be pulled up). Consequently, the ASTE signal present on the control wiring 160 directly coupled to node Y can change (e.g., to a logic high state). According to various embodiments of the present disclosure, when the ASTE signal is pulled up, the WL auxiliary circuit 104 can be activated to boost the power supply VDD, which will be described below.

[0031] In another example, the third tracking unit 145 includes six transistors 221, 222, 223, 224, 225, and 226, which are similarly configured as PU1, PU2, PD1, PD2, PG1, and PG2 of the nominal memory unit 125, respectively. Transistor 221 has its gate connected to the gate of transistor 223 (both of which are connected to VDD) while its source and drain terminals are both floating; and transistor 222 has its gate connected to the gate of transistor 224 while its source and drain terminals are both floating. Transistor 225 connects its gate to ground voltage (VSS), its drain to tracking bit line TRKBL 155, and its source to ground voltage via transistor 223; and transistor 226 connects its gate to the corresponding nominal word line WL (e.g., WL[J-2]), its drain to tracking bit line TRKBLB 157, and its source to ground voltage via transistor 224. In this configuration, the third tracking unit 145 can simulate the loading of the nominal bit line BL.

[0032] The WL auxiliary circuit 104 may include buffers 230 to 232, a transistor 234, and a capacitor 236. The transistor 234 may be implemented as a PMOS transistor coupled between the power supply voltage (VDD) and a first terminal of the capacitor 236. The first terminal of the capacitor 236 may be coupled to the WL driver 106. As illustrated in the example of Figure 2, the WL driver 106 may include a plurality of WL buffers or WL inverters 160[J-1], 160[J-2]…160[0] respectively coupled to the nominal word lines WL[J-1], WL[J-2]…WL[0]. In some embodiments, the first terminal of the capacitor 236 is used to provide an operating voltage (VDDHD) to power the WL inverters of the WL driver 106, such that each of the WL inverters, once asserted, can supply an operating voltage (VDDHD) to the corresponding one of the nominal word lines WL. VDDHD can sometimes be referred to as virtual power supply voltage.

[0033] In some embodiments, the WL assertion circuit 104 can operate in two stages. Based on the logic state of the ASTE signal (present on control wiring 160), one stage provides VDDHD as VDD, and the other stage provides VDDHD as VDD plus a boosted amount. For example, when the ASTE signal is in a logic low state or VSS (e.g., where the TRKBL signal remains in a logic high state), transistor 234 can be turned on, which couples VDD to the operating voltage (VDDHD). Since the second terminal of the capacitor 236 coupled to the ASTE signal is held at VSS, the voltage difference across the first and second terminals of capacitor 236 is ΔV = VDD - VSS. When the ASTE signal transitions from a logic low state to a logic high state or VDD, transistor 234 is turned off, which decouples VDD from the operating voltage (VDDHD). Therefore, capacitor 236 can raise the voltage level at its first terminal (i.e., the operating voltage VDDHD) to VDD+ΔV.

[0034] Figure 3 illustrates the waveforms of various signals over time when the memory circuit 100, implemented as shown in Figure 2, is operated according to some embodiments. For example, the waveforms of the TRKWL signal, TRKBL signal, ASTE signal, VDDHD, WL signal (voltage), and the voltage present on the nominal bit lines BL / BLB are respectively illustrated. In some embodiments, once VDDHD rises from VDD, the WL voltage may therefore rise or otherwise rise from VDD. The increased WL voltage can advantageously improve the performance of the nominal memory cell 125 during reading and / or writing.

[0035] As illustrated in Figure 3, when the TRKWL signal is pulled up (e.g., simultaneously with the WL voltage being pulled up), the first tracking unit 135 can be activated to pull the TRKBL signal low. In some embodiments, the TRKWL signal may be provided by a tracking WL driver, which may be part of WL driver 106 or memory controller 102. After the TRKBL signal is pulled down to a predefined voltage level, the ASTE signal may be pulled up, as indicated by symbol arrow 301. According to various embodiments of the present disclosure, the second tracking unit 140 may perform the ASTE signal transition after detecting that the TRKBL signal has been pulled down to a sufficiently low voltage level. Essentially, the second tracking unit 140 operatively acts as an inverter coupled between TRKBL 155 (presenting the TRKBL signal) and controller wiring 160 (presenting the ASTE signal). When the ASTE signal rises, the WL auxiliary circuit 104 can increase VDDHD by an amount of ΔV (e.g., approximately VDD-VSS). For example, VDDHD can be increased from VDD to VDD+ΔV. Therefore (as indicated by symbolic arrow 303), the WL voltage applied by the WL driver 106 to the asserted nominal word line WL can be increased from the first level 305 to the second level 307.

[0036] Figure 4 illustrates a circuit diagram of another embodiment of the trace line 130 according to some embodiments. The circuit implementation of the trace line 130 shown in Figure 4 is similar to the circuit implementation shown in Figure 2, except that the trace line 130 of Figure 4 further includes another type of trace unit.

[0037] As shown in Figure 4, in addition to tracking units 135 to 145, tracking row 130 includes tracking unit 410. Tracking unit 410 also includes six transistors 411, 412, 413, 414, 415, and 416, which are similarly configured as PU1, PU2, PD1, PD2, PG1, and PG2 of nominal memory unit 125, respectively. Transistor 411 has its gate terminal connected to the gate terminal of transistor 413, its source terminal floating, and its drain terminal connected to the drain terminal of transistor 413; and transistor 412 has its gate terminal connected to the gate terminal of transistor 414, its source terminal connected to VDD, and its drain terminal disconnected from the drain terminal of transistor 414. The source terminal of transistor 413 may also be floating. Transistor 415 connects its gate to ground voltage (VSS), its drain to tracking bit line TRKBL 155, and its source to the common node "X" between transistors 411 and 413; while transistor 416 connects its gate to the corresponding nominal word line WL, its drain to control wiring 160, and its source to the drain of transistor 414. Additionally, tracking unit 410 may include one or more conductive connections directly connecting tracking bit line TRKBL 155 to node X, and one or more second conductive connections directly connecting control wiring 160 to the drain of transistor 414. In this configuration, tracking unit 410 can reduce the threshold voltage of second tracking unit 140, which advantageously prevents the ASTE signal from rising prematurely.

[0038] Figure 5 illustrates a circuit diagram of another embodiment of trace line 130 according to some embodiments. The circuit implementation of trace line 130 shown in Figure 5 is similar to the circuit implementation shown in Figure 4, except that trace line 130 of Figure 5 is further coupled to one or more level generators.

[0039] As illustrated in Figure 5, the first tracking unit 135 is coupled to a level generator 510. The level generator 510 is used to reduce the voltage level present on the tracking word line TRKWL 150. By reducing the voltage level of TRKWL, the tracking unit 135 activated by TRKWL can mimic one or more of the nominal memory cells 125, which are relatively weak (e.g., having a relatively or unusually low threshold voltage on its pull-up transistor). In some embodiments, the level generator 510 may include an inverter 512 and a transistor 514. The inverter 512 may be powered by a supply voltage (VDD). The transistor 514 may be implemented as a PMOS transistor. In addition, the transistor 514 has its gate terminal connected to ground voltage (VSS), in which case the transistor 514 is always turned on; and its source and drain terminals are connected to the tracking word line TRKWL 150 and VSS, respectively. Therefore, after the tracking word line TRKWL 150 is asserted, the voltage level of TRKWL can be lowered. In some other embodiments, the first tracking unit 135 may be further coupled to another level generator 520 as needed, in which case an inverter 522 and a PMOS transistor 524 are also present. The level generator 520 may be coupled to the gate terminal of the pull-down transistor 203 of the first tracking unit 135.

[0040] Figure 6 illustrates an example circuit diagram of a portion of a memory circuit 100 according to some embodiments. For example, in Figure 6, the circuit implementations of the precharge circuit 108 and the BL auxiliary circuit 110 are partially shown. The circuit diagram shown in Figure 6 has been simplified for illustrative purposes, and therefore it should be understood that the elements of the memory circuit 100 can be implemented in various other ways while remaining within the scope of the embodiments disclosed herein.

[0041] As illustrated in Figure 6, the precharge circuit 108 includes a plurality of transistors 610 and 620, and the BL auxiliary circuit 110 includes a transistor 630, wherein the transistors 610 to 620 of the precharge circuit 108 are coupled to a corresponding pair of nominal bit lines BL / BLB (e.g., BL[0] and BLB[0]), and the transistor 630 of the BL auxiliary circuit 110 is coupled to a corresponding pair of nominal bit lines BL / BLB (e.g., BL[0] and BLB[0]). In some embodiments, each of the transistors 610 to 630 may be implemented as a PMOS transistor. Specifically, the gate terminals of transistors 610 and 620 in the pre-charge circuit 108 are connected to each other to receive the bit line pre-charge (BLPCHB) signal; the first source / drain terminals of transistors 610 and 620 in the pre-charge circuit 108 are connected to the nominal bit line BL and its supplementary bit line BLB; and the second source / drain terminals of transistors 610 and 620 in the pre-charge circuit 108 are connected to each other. The second source / drain terminals of transistors 610 and 620 are connected to the drain terminal of transistor 630 in the BL auxiliary circuit 110, which is further connected to the gate terminal of transistor 630 in the BL auxiliary circuit 110. The source terminal of transistor 630 in the BL auxiliary circuit 110 is connected to the power supply voltage (VDD).

[0042] In some embodiments, the precharge circuit 108 is used to precharge the nominal bit line BL / BLB and the tracking bit line TRKBL 155 to VDD, and the BL auxiliary circuit 110 is used to reduce the voltage level of the precharge voltage present on the nominal bit line BL / BLB and the tracking bit line TRKBL 155. For example, in Figure 7, outside of normal operation (read or write) where the WL voltage of the nominal memory cell 125 is kept in a logic low state, the BLPCHB signal is set to a logic low state. In this case, the precharge circuit 108 can be activated to precharge the nominal bit line BL / BLB and also precharge the tracking bit line TRKBL 155. In addition, while the bit lines are precharged to VDD, the BL auxiliary circuit 110 can be activated to pull down the voltage level present on the bit lines from VDD, as illustrated in Figure 7. By lowering the precharge voltage on the bit line from VDD, the bit performance of the memory circuit 100 can be further improved (e.g., increasing the speed of write operations).

[0043] Figure 8 illustrates another example circuit diagram of a portion of a memory circuit 100 according to some embodiments. The circuit diagram of Figure 8 is similar to the circuit diagram shown in Figure 2, except that the circuit diagram of Figure 8 further includes a WL suppression circuit 810. For example, in Figure 8, the circuit implementations of the memory array 120, the tracking row 130, the WL auxiliary circuit 104, and the WL driver 106 are partially shown together with the WL suppression circuit 810. The circuit diagram shown in Figure 8 has been simplified for illustrative purposes, and therefore it should be understood that the elements of the memory circuit 100 can be implemented in various other ways while remaining within the scope of the embodiments disclosed herein.

[0044] As illustrated in Figure 8, the WL suppression circuit 810 includes a plurality of transistors 820[J-1], 820[J-2], ..., 820[0] respectively coupled to the nominal word lines WL[J-1], WL[J-2]...WL[0]. In some embodiments, each of the transistors 820 may be implemented as a PMOS transistor. Specifically, the source terminals of the transistors 820 may be connected to the nominal word lines WL respectively; the gate terminals of the transistors 820 may be connected together to another control line 815 (presenting or receiving the ASTEB_RD signal); and the drain terminals of the transistors 820 may be connected to ground voltage (VSS).

[0045] In such embodiments, the memory circuit 100 may utilize the ASTEB_RD signal to suppress voltage levels present on the nominal word line WL and the tracking word line TRKWL 150. For example, before the ASTEB_RD signal transitions from a low logic state to a high logic state, the voltage levels present on the word lines (e.g., including WL[0] to WL[J-1] and TRKWL 150) may be lower than VDD, and when the ASTEB_RD signal transitions to a logic high state, the voltage levels present on the word lines may be boosted to VDD. Therefore, the memory circuit 100 may further include an ASTEB_RD driver 910 (Figure 9) for providing the ASTEB_RS signal and a tracking WL driver 950 (Figure 9) for providing the TRKWL signal based on the ASTEB_RD signal. Each of the ASTEB_RD driver 910 and the tracking WL driver 950 may be part of the WL driver 106 or the memory controller 102.

[0046] Referring to Figure 9, example circuit diagrams of the ASTEB_RD driver 910 and the tracking WL driver 950 are shown respectively. The tracking WL driver 950 may include inverters 952 and 954 and a PMOS transistor 956. Inverters 952 and 954 may both receive a control signal 901, which is used to enable or assert the tracking word line TRKWL 150. In addition, the inverter 952 of the tracking WL driver 950 may provide a TRKWL signal at its output based on the received control signal 901, wherein the output is coupled to ground voltage via the PMOS transistor 956. The PMOS transistor 956 of the tracking WL driver 950 may be gated by the ASTEB_RD signal. The inverter 954 of the tracking WL driver 950 may provide an intermediate signal to the ASTEB_RD driver 910 based on the received control signal 901. The ASTEB_RD driver 910 may include inverters 912 and 914 connected in series with each other. The ASTEB_RD driver 910 may provide the ASTEB_RD signal via inverters 912 and 914 based on the intermediate signal received from the inverter 954 of the self-tracking WL driver 950.

[0047] In this configuration, the TRKWL signal can be suppressed from VDD when the ASTEB_RD signal is in a logic low state. For example, when the ASTEB_RD signal is in a logic low state, the PMOS transistor 956 of the tracking WL driver 950 can be turned on. The PMOS transistor 956 typically has a relatively large resistance (when turned on), and therefore when the PMOS transistor 956 is turned on, the TRKWL signal can be pulled back from VDD by a voltage drop (ΔV). When the ASTEB_RD signal transitions from a logic low state to a logic high state, the PMOS transistor 956 is turned off, which disconnects the tracking word line TRKWL 150 from ground voltage. Therefore, the TRKWL signal can be boosted to VDD. The WL voltage present on the nominal word line WL can be controlled in a similar manner by the individual PMOS transistors 820, which are also gated by the ASTEB_RD signal.

[0048] Figure 10 illustrates the waveforms of various signals over time when operating the memory circuit 100 implemented as shown in Figure 8, according to some embodiments. For example, the waveforms of the TRKWL signal, TRKBL signal, ASTEB_RD signal, ASTE signal, VDDHD, WL signal (voltage), and the voltage present on the nominal bit lines BL / BLB are respectively illustrated. In some embodiments, once VDDHD rises from VDD, the WL voltage may therefore rise or otherwise rise from VDD. The increased WL voltage can advantageously improve the performance of the nominal memory cell 125 during reading and / or writing. In addition, the TRKWL signal and WL voltage may be suppressed below VDD based on the ASTEB_RD signal before reaching the VDD level to further prevent data corruption.

[0049] As illustrated in Figure 10, when the TRKWL signal is pulled up (e.g., simultaneously with the positive pull up of the WL voltage), the first tracking unit 135 can be activated to pull the TRKBL signal low. In some embodiments, when the TRKWL signal and the WL voltage are initially pulled up, the ASTEB_RD signal can remain in a logic low state. When the ASTEB_RD signal is in a logic low state, both the TRKWL signal and the WL voltage can be suppressed from VDD. After the ASTEB_RD signal positively transitions to a logic high state, the TRKWL signal and the WL voltage can be pulled up to VDD, as indicated by arrows 1001 and 1003, respectively. After the TRKBL signal is positively pulled down to a predefined voltage level, the ASTE signal can be pulled up, as indicated by arrow 1005. According to various embodiments of the present disclosure, the second tracking unit 140 can perform the transition of the ASTE signal after detecting that the TRKBL signal has been pulled down to a sufficiently low voltage level. When the ASTE signal rises, the WL auxiliary circuit 104 can increase VDDHD by an amount of ΔV (e.g., approximately VDD-VSS). For example, VDDHD can be increased from VDD to VDD+ΔV. Therefore (as indicated by symbolic arrow 1007), the WL voltage applied by the WL driver 106 to the asserted nominal word line WL can be increased to be higher than VDD.

[0050] Figure 11 illustrates a flowchart of an example method 1100 for operating a memory circuit including a WL auxiliary circuit based on tracking signal control, according to some embodiments. For example, the operation of method 1100 can be configured to operate the memory circuit 100 implemented according to the circuit diagram shown in Figure 2. Therefore, the following discussion of method 1100 may sometimes refer to the above diagram. It should be noted that method 1100 shown in Figure 11 is merely an example and is not intended to limit the embodiments disclosed herein. Therefore, it should be understood that the order of operations of method 1100 in Figure 11 may be changed, for example, additional operations may be provided before, during and after method 1100, and the following operations may only be briefly described herein.

[0051] Method 1100 begins with operation 1110 of initiating a first trace memory cell connected to a trace bit line via a non-suppressed trace word line signal, the trace bit line simulating a propagation delay present on a nominal bit line, thereby causing a first signal present on the trace bit line to transition from a first logic state to a second logic state. The first trace memory cell can be initiated by a trace word line signal that can be asserted to VDD simultaneously with the asserted nominal word line signal. For example, in Figure 2, the first trace memory cell 135 can be initiated after the TRKWL signal (present on trace word line TRKWL 150) rises from a logic low state to a logic high state, the low logic state corresponding to VSS and the logic high state corresponding to VDD. After initiation, the first trace memory cell 135 can begin to pull the TRKBL signal (present on trace bit line TRKBL 155) low, which has been pre-charged to VDD (or suppressed to VDD in other embodiments, such as Figure 6).

[0052] Method 1100 proceeds to the following operation 1120: In response to the first signal transitioning from a first logic state to a second logic state, a second signal present on the control line is transitioned from the second logic state to the first logic state via a second tracking memory unit connected to the tracking bit line. Continuing with the example of Figure 2, the second tracking memory unit 140 may detect or otherwise monitor the TRKBL signal. Once the TRKBL signal transitions from a logic high state (e.g., precharge VDD) to a logic low state, the second tracking memory unit 140 may pull up the ASTE signal (present on the control line 160).

[0053] In some embodiments, the second tracking memory unit 140 includes a first PMOS transistor (e.g., 211) and a first NMOS transistor (e.g., 213) connected in series to each other at a first node (e.g., node X), wherein the source terminal of the first PMOS transistor 211 is floating, and the source terminal of the first NMOS transistor 213 is floating. The second tracking memory unit 140 further includes a second PMOS transistor (e.g., 212) and a second NMOS transistor (e.g., 214) connected in series to each other at a second node (e.g., node Y), wherein the source terminal of the second PMOS transistor 212 is connected to the power supply voltage (VDD), and the source terminal of the second NMOS transistor 214 is connected to the ground voltage (VSS). The second tracking memory unit 140 further includes a first through-gate NMOS transistor (e.g., 215) whose source / drain terminals are respectively connected to the tracking bit line TRKBL 155 and node X. The second tracking memory cell 140 further includes a second NMOS transistor (e.g., 216) whose source / drain terminals are connected to the control wiring 160 and node Y, respectively. Additionally, the second tracking memory cell 140 further includes at least one conductive connection directly connecting the tracking bit line TRKBL 155 to node X, and another conductive connection directly connecting the control wiring 160 to node Y.

[0054] Method 1100 proceeds to the following operation 1130: in response to the second signal transitioning to the first logic state, the voltage level of the operating voltage applied to the nominal word line corresponding to one of the assertions in the plurality of nominal memory cells is increased. Continuing with the example of Figure 2, once the ASTE signal rises to the logic high state, the WL auxiliary circuit 104 is activated. After activation, the WL auxiliary circuit 104 can increase the operating voltage (VDDHD) from VDD to VDD+ΔV. In some embodiments, this operating voltage can be used to power the WL driver 106, in which case the WL voltage (existing on the nominal word line WL) is increased to VDD+ΔV.

[0055] Figure 12 illustrates a flowchart of an example method 1200 for operating a memory circuit including a WL auxiliary circuit based on tracking signal control, according to some embodiments. For example, the operation of method 1200 can be configured to operate a memory circuit 100 implemented according to the circuit diagram shown in Figure 8. Therefore, the following discussion of method 1200 may sometimes refer to the above diagram. It should be noted that method 1200 shown in Figure 12 is merely an example and is not intended to limit the embodiments disclosed herein. Therefore, it should be understood that the order of operations of method 1200 in Figure 12 may be changed, for example, additional operations may be provided before, during and after method 1200, and the following operations may only be briefly described herein.

[0056] Method 1200 begins with operation 1210 of initiating a first trace memory cell connected to a trace bit line via a suppressed trace word line signal, the trace bit line mimicking a propagation delay present on a nominal bit line, thereby causing a first signal present on the trace bit line to transition from a first logic state to a second logic state. The first trace memory cell can be initiated by a trace word line signal, which can assert to the suppressed VDD simultaneously with the assertion nominal word line signal. In some embodiments, the trace word line signal can remain at the suppressed VDD level while another control signal remains in the second logic state. For example, in Figure 8, the first trace memory cell 135 can be initiated after the TRKWL signal (present on trace word line TRKWL 150) rises from a logic low state to a logic high state, the low logic state corresponding to VSS and the logic high state corresponding to the suppressed VDD. The TRKWL signal and the WL voltage can remain at the suppressed VDD level as long as the ASTEB_RD signal remains in the logic low state. After startup, the first tracking memory unit 135 may begin to pull the TRKBL signal (present on the tracking bit line TRKBL 155) low, which has been pre-charged to VDD (or, in some alternative embodiments, VDD is suppressed, such as in Figure 6).

[0057] Method 1200 proceeds to operation 1220: the suppressed tracking word line signal is raised back to the power supply voltage level. Continuing the example in Figure 8, once the ASTEB_RD signal transitions from a logic low state to a logic high state, the TRKWL signal (present on the tracking word line TRKWL 150) can be raised back to VDD from suppressed VDD. Currently, the WL voltage (present on the nominal word line WL) can also be raised back to VDD from suppressed VDD. In some embodiments, the ASTEB_RD signal can be provided by the ASTEB_RD driver 910 based on control signal 901 (Figure 9).

[0058] Method 1200 proceeds to the following operation 1230: In response to the first signal transitioning from a first logic state to a second logic state, a second signal present on the control line is transitioned from the second logic state to the first logic state via a second tracking memory unit connected to the tracking bit line. Continuing with the example in Figure 8, the second tracking memory unit 140 may detect or otherwise monitor the TRKBL signal. Once the TRKBL signal transitions from a logic high state (e.g., precharge VDD) to a logic low state, the second tracking memory unit 140 may pull up the ASTE signal (present on the control line 160).

[0059] In some embodiments, the second tracking memory unit 140 includes a first PMOS transistor (e.g., 211) and a first NMOS transistor (e.g., 213) connected in series to each other at a first node (e.g., node X), wherein the source terminal of the first PMOS transistor 211 is floating, and the source terminal of the first NMOS transistor 213 is floating. The second tracking memory unit 140 further includes a second PMOS transistor (e.g., 212) and a second NMOS transistor (e.g., 214) connected in series to each other at a second node (e.g., node Y), wherein the source terminal of the second PMOS transistor 212 is connected to the power supply voltage (VDD), and the source terminal of the second NMOS transistor 214 is connected to the ground voltage (VSS). The second tracking memory unit 140 further includes a first through-gate NMOS transistor (e.g., 215) whose source / drain terminals are respectively connected to the tracking bit line TRKBL 155 and node X. The second tracking memory cell 140 further includes a second NMOS transistor (e.g., 216) whose source / drain terminals are connected to the control wiring 160 and node Y, respectively. Additionally, the second tracking memory cell 140 further includes at least one conductive connection directly connecting the tracking bit line TRKBL 155 to node X, and another conductive connection directly connecting the control wiring 160 to node Y.

[0060] Method 1200 proceeds to the following operation 1240: In response to the second signal transitioning to the first logic state, the voltage level of the operating voltage applied to the nominal word line corresponding to one of the assertions in the plurality of nominal memory cells is increased. Continuing with the example of Figure 8, once the ASTE signal rises to the logic high state, the WL auxiliary circuit 104 is activated. After activation, the WL auxiliary circuit 104 can increase the operating voltage (VDDHD) from VDD to VDD+ΔV. In some embodiments, this operating voltage can be used to power the WL driver 106, in which case the WL voltage (existing on the nominal word line WL) is increased from VDD to VDD+ΔV.

[0061] In some other embodiments of the disclosed embodiments, the transition directions of the various signals mentioned above can be inverted by adding an odd number of inverting logic gates (e.g., inverters) or by using transistors of opposite conductivity types. For example, when a signal is asserted, the signal of the gated PMOS transistor can transition to a logic low state. Similarly, when a signal is negated, the signal of the gated PMOS transistor can transition to a logic high state.

[0062] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes: a memory array comprising a plurality of first memory cells, each of the first memory cells being used to store a data bit; a trace row comprising at least one second memory cell and a third memory cell, wherein the second memory cell is coupled to a first trace bit line, a second trace bit line and a trace word line, and the third memory cell is coupled to the first trace bit line; and a word line auxiliary circuit operatively coupled to the memory array and the trace row. The word line auxiliary circuit is used to receive a control signal present on a control line coupled to the third memory cell; and to increase a voltage level applied to an operating voltage of a word line corresponding to an assertion among the first memory cells in response to a change of the control signal from a first logic state to a second logic state.

[0063] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a trace row disposed immediately adjacent to a memory array comprising a plurality of first memory cells, each of which stores a data bit. The trace row includes a plurality of second memory cells and a plurality of third memory cells. When activated via a trace word line, each of the second memory cells pulls down a first signal present on a first trace word line. Each of the third memory cells responds to the first signal being pulled down by pulling up a second signal present on a control line.

[0064] In another embodiment of this disclosure, a method for operating memory circuitry is disclosed. The method includes activating a first trace memory cell connected to a trace bit line, the trace bit line simulating a propagation delay present on a nominal bit line, thereby causing a first signal present on the trace bit line to transition from a first logic state to a second logic state. The method includes, in response to the first signal transitioning from the first logic state to the second logic state, causing a second signal present on a control wiring to transition from the second logic state to the first logic state via a second trace memory cell connected to the trace bit line. The method includes, in response to the second signal transitioning to the first logic state, increasing a voltage level of an operating voltage applied to a nominal word line corresponding to one of the nominal memory cells asserting a particular.

[0065] As used herein, the terms “about” and “approximately” generally indicate a given quantity value that may vary based on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the term “about” may indicate a given quantity value that varies within 10% to 30% of the value (e.g., within +10%, ±20%, or ±30% of the value).

[0066] The foregoing summarizes the features of several embodiments, enabling those skilled in the art to better understand the nature of the embodiments disclosed herein. Those skilled in the art should understand that the embodiments disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of the embodiments disclosed herein. [Simplified Explanation of the Diagram]

[0004] The embodiments disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, according to industry standard practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates a block diagram of a memory circuit according to some embodiments. Figure 2 illustrates a circuit diagram of one embodiment of the memory circuit of Figure 1 according to some embodiments. Figure 3 illustrates waveforms of various signals when operating the memory circuit implemented according to the circuit diagram of Figure 2 according to some embodiments. Figure 4 illustrates an example circuit diagram of a trace row of the memory circuit of Figure 1 according to some embodiments. Figure 5 illustrates another example circuit diagram of a trace row of the memory circuit of Figure 1 according to some embodiments. Figure 6 illustrates a circuit diagram of the circuit elements of the memory circuit of Figure 1 according to some embodiments. Figure 7 illustrates waveforms of various signals when operating the memory circuit implemented according to the circuit diagram of Figure 6 according to some embodiments. Figure 8 illustrates a circuit diagram of another embodiment of the memory circuit of Figure 1 according to some embodiments. Figure 9 illustrates a circuit diagram of circuit elements of a memory circuit implemented according to the circuit diagram of Figure 8 according to some embodiments. Figure 10 illustrates waveforms of various signals during operation of the memory circuit implemented according to the circuit diagram of Figure 8 according to some embodiments. Figure 11 illustrates a flowchart of an example method for operating a memory circuit according to some embodiments. Figure 12 illustrates a flowchart of another example method for operating a memory circuit according to some embodiments. [Biomaterial Storage]

[0068] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A memory circuit comprising: a memory array including a plurality of first memory cells, each of the first memory cells being configured to store a data bit; a trace row including at least one second memory cell and a third memory cell, wherein the second memory cell is coupled to a first trace bit line, a second trace bit line and a trace word line, and the third memory cell is coupled to the first trace bit line, wherein the second memory cell is configured to adjust the voltage of the first trace bit line according to a signal on the trace word line; and a word line auxiliary circuit operatively coupled to the memory array and the trace row, and configured to: receive a control signal present on a control line coupled to the third memory cell, wherein the control line is electrically disconnected from the second memory cell; and, in response to a transition of the control signal from a first logic state to a second logic state, increase a voltage level applied to an operating voltage of a word line corresponding to one of the first memory cells being asserted.

2. The memory circuit as claimed in claim 1, wherein the third memory cell comprises: a first inverter and a second inverter cross-coupled to each other to form a first node and a second node; a first through-gate transistor coupled between the first tracking bit line and the first node; and a second through-gate transistor coupled between the control wiring and the second node, wherein the first node and the first tracking bit line are directly coupled to each other, and the second node and the control wiring are directly coupled to each other.

3. The memory circuit as claimed in claim 1, wherein when activated via the trace word line, the second memory unit is configured to cause a first signal present on the first trace bit line to transition from the second logic state to the first logic state, wherein the third memory unit is configured to cause the control signal to transition from the first logic state to the second logic state in response to the first signal transitioning from the second logic state to the first logic state.

4. The memory circuit as claimed in claim 1, wherein the word line auxiliary circuit comprises: a transistor that connects a gate terminal to the control line, connects a first source / drain terminal to a power supply voltage, and provides a second source / drain terminal for supplying the operating voltage; and a capacitor that connects a first terminal and a second terminal to the control line and the second source / drain terminal, respectively, wherein when the control signal is in the first logic state, the power supply voltage is directly applied to the word line, and when the control signal changes from the first logic state to the second logic state, the power supply voltage applied to the word line increases by a voltage difference through the capacitor.

5. The memory circuit as claimed in claim 1, wherein the trace line further includes a fourth memory cell coupled to the control wiring and the first trace bit line, wherein the third memory cell includes: a first p-type transistor and a first n-type transistor connected in series at a first node, one source terminal of the first p-type transistor being floating and one source terminal of the first n-type transistor being floating; a second p-type transistor and a second n-type transistor connected in series at a second node, one source terminal of the second p-type transistor being connected to a power supply voltage and one source terminal of the second n-type transistor being connected to a ground voltage; a first through-gate transistor having its plurality of source / drain terminals respectively connected to the first trace bit line and the first node; and a second through-gate transistor having its plurality of source / drain terminals respectively connected to the control wiring and the second node; wherein the fourth memory cell includes: A third p-type transistor and a third n-type transistor are connected in series at a third node, with one source terminal of the third p-type transistor and one source terminal of the third n-type transistor floating; a fourth p-type transistor and a fourth n-type transistor, with one source terminal of the fourth p-type transistor connected to the power supply voltage and one source terminal of the fourth n-type transistor connected to a ground voltage; a third through-gate transistor, which connects its plurality of source / drain terminals to the first trace bit line and the third node respectively; and a fourth through-gate transistor, which connects its plurality of source / drain terminals to the control wiring and one drain terminal of the fourth n-type transistor respectively, wherein the trace line includes a plurality of the third memory cells and a plurality of the fourth memory cells.

6. The memory circuit as claimed in claim 1 further includes at least one level generator coupled to the trace word line and used to reduce a second signal present on the trace word line by a voltage difference.

7. A memory circuit comprising: a trace row immediately adjacent to a memory array comprising a plurality of first memory cells, each of the first memory cells being configured to store a data bit, the trace row comprising a plurality of second memory cells and a plurality of third memory cells; wherein each of the second memory cells comprises: a first p-type transistor and a first n-type transistor, wherein a gate of the first p-type transistor is coupled to a gate of the first n-type transistor; a second p-type transistor and a second n-type transistor, wherein a gate of the second p-type transistor is coupled to a gate of the second n-type transistor, wherein the first p-type transistor and the first n-type transistor are electrically isolated from the second p-type transistor and the second n-type transistor; and a first through-gate transistor coupled between a first trace bit line and the first n-type transistor; When activated via a trace word line, each of the second memory cells pulls a first signal present on the first trace bit line low; and each of the third memory cells responds to the first signal being pulled low by pulling up a second signal present on a control line.

8. The memory circuit as claimed in claim 7, wherein one source terminal of the first p-type transistor is floating and one drain terminal of the first p-type transistor is floating, wherein one source terminal of the second p-type transistor is connected to a power supply voltage and one drain terminal of the second p-type transistor is floating, wherein the second memory cell further comprises: a second through-gate transistor, wherein its plurality of source / drain terminals are respectively connected to a second trace bit line and a drain terminal of the second n-type transistor, wherein the third memory cell comprises: a third p-type transistor and a third n-type transistor connected in series at a first node, one source terminal of the third p-type transistor and one source terminal of the third n-type transistor being floating; a fourth p-type transistor and a fourth n-type transistor connected in series at a second node, one source terminal of the fourth p-type transistor being connected to the power supply voltage and one source terminal of the fourth n-type transistor being connected to a ground voltage; A third transistor with multiple source / drain terminals connected to the first tracking bit line and the first node respectively; and a fourth transistor with multiple source / drain terminals connected to the control wiring and the second node respectively, wherein the first node and the first tracking bit line are directly coupled to each other, and the second node and the control wiring are directly coupled to each other.

9. The memory circuit of claim 7, further comprising a word line auxiliary circuit for increasing a voltage level of an operating voltage applied to a word line in response to a second signal pull-up, the word line corresponding to one of the asserted first memory cells, wherein the word line auxiliary circuit comprises: a transistor that connects a gate terminal to the control line, a first source / drain terminal to a power supply voltage, and a second source / drain terminal to provide the operating voltage; and a capacitor that connects a first terminal and a second terminal to the control line and the second source / drain terminal, respectively, wherein when the second signal is in the first logic state, the power supply voltage is applied directly to the word line, and when the second signal transitions from the first logic state to the second logic state, the power supply voltage applied to the word line is increased by a voltage difference via the capacitor.

10. A method of operating a memory circuit, comprising the steps of: activating a first trace memory cell connected to a trace bit line, the trace bit line simulating a propagation delay present on a nominal bit line, thereby causing a first signal present on the trace bit line to transition from a first logic state to a second logic state; in response to the first signal transitioning from the first logic state to the second logic state, causing a second signal present on a control line to transition from the second logic state to the first logic state via a second trace memory cell connected to the trace bit line; and in response to the second signal transitioning to the first logic state, increasing a voltage level of an operating voltage applied to a nominal word line, the nominal word line corresponding to one of a plurality of nominal memory cells asserted, wherein the first trace memory cell comprises: a first p-type transistor and a first n-type transistor, wherein a gate of the first p-type transistor is coupled to a gate of the first n-type transistor; A second p-type transistor and a second n-type transistor, wherein a gate of the second p-type transistor is coupled to a gate of the second n-type transistor, wherein the first p-type transistor and the first n-type transistor are electrically separated from the second p-type transistor and the second n-type transistor; and a first pass gate transistor coupled between the tracking bit line and the first n-type transistor.

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