Mos transistor structur and method formanufacturing the same

Abstract

A method for manufacturing a metal-oxide-semiconductor transistor structure includes the following steps: defining a plurality of fin structures in a semiconductor substrate; forming sacrificial spacers around the sidewalls of each fin structure; forming a dielectric layer around the sacrificial spacers; and, after removing the sacrificial spacers, forming a gate structure above each fin structure to cover the sidewalls of each fin structure.

Description

Technical Field

[0001] This invention relates to integrated circuits (ICs) and their manufacturing methods, and more particularly to a metal-oxide-semiconductor (MOS) transistor structure and its manufacturing method. Prior Technology

[0002] In 2021, silicon-based single-chip integrated circuits achieved the formation of over 50 billion transistors on a single die. This marked the transition from the era of Very Large Scale Integration (VLSI, which involves forming millions of transistors on a single die) to the era of Gigabyte-Scale Integration (GSI, which involves forming billions of transistors on a single die). This achievement of higher transistor density on a single die significantly improved the performance of microsystems, substantially enhancing PPAC (higher performance, better power management capability, effective usage of area, and lower cost per bit). This led to the development of powerful chips such as CPUs, GPUs, FPGAs, SoCs, SRAM, and DRAM, enhancing system capabilities, continuously supporting Moore's Law, and laying the foundation for exponential economic growth.

[0003] The high productivity generated by new applications developed through GSI is stimulating rapid economic growth, leading to an increasingly strong demand for integrating more transistors onto a single die. Therefore, the semiconductor industry is expected to strive towards the era of trillion-scale integration (TSI), which involves forming more than a trillion transistors on a single die. This necessitates further inventions and engineering improvements to transistors, fundamentally changing transistor structure and achieving better power-to-acceptance (PPAC) to meet this TSI challenge. For example, if a chip does indeed form one trillion transistors on a single die, and the standby current (Ioff) of each transistor is set to approximately 0.5 pA (A is an abbreviation for ampere), then the Ioff of a die with a total of one trillion transistors will approach 0.5 amperes.

[0004] However, state-of-the-art transistors using process technologies with critical dimensions below 20 nanometers (nm) struggle to achieve an Ioff of 0.5 pA. Even with various transistor structures (such as FinFETs or Tri-Gate Designs), only a few transistor structures can achieve an Ioff of 5 to 10 pA. Reducing the Ioff (e.g., below 1 pA) while continuously shrinking device size has become one of the key challenges in this technological field.

[0005] The most advanced FinFETs currently available typically include a typical FET that uses a fin structure as the active region (as illustrated in Figure 1). The gate structure 5, formed by covering an insulator or dielectric layer (e.g., silicon oxide, silicon oxide / nitride, or a high-dielectric-number (k) dielectric material) with a conductive material (e.g., metal, polysilicon, or polysilicon silylate), is formed on a fin structure or a three-dimensional silicon surface, and its sidewalls are isolated from the sidewalls of other transistors using an insulating material (e.g., silicon oxide / nitride, oxygen, or other dielectric materials). For example, an NMOS transistor includes a source region 11 and a drain region 12 formed by implanting a high concentration of n-type dopant into a p-type substrate (or p-well) using an ion implantation heating annealing process, thereby creating two independent n+ / p junction regions. To reduce the impact of ion implantation and hot carrier injection during the formation of the aforementioned heavily doped n+ / p junction, an ion implantation heating annealing technique is typically used to form a lightly doped-drain (LDD) region 13 before forming the heavily doped n+ source region 11 / drain region 12. However, this ion implantation heating annealing process often causes the dopant in the lightly doped drain (LDD) region 13 to penetrate into the 3D active region located below the gate structure 5. Consequently, the effective channel between the lightly doped drain regions 13 is inevitably shortened.

[0006] On the other hand, as process technology continues to advance rapidly, the geometry of components is constantly shrinking in both the horizontal and vertical directions (for example, the minimum feature size, also known as Lambda(λ), has shrunk from 28 nanometers to 5 nanometers or 3 nanometers). With the application of new types of FinFETs or Trigate transistors and the shrinking of their geometries, many problems have arisen or worsened.

[0007] For example, as the gate length of components shrinks, traditional lithography and etching patterning techniques cannot effectively control the distance between two adjacent fin structures. Furthermore, traditional lithography and etching patterning techniques also struggle to control the spacing or distance between the gate electrodes of two adjacent MOS transistors.

[0008] Furthermore, as device dimensions continue to shrink to 7 nanometers, 5 nanometers, or 3 nanometers, the height of the fin structure (e.g., 50 nanometers to 100 nanometers) is much greater than the width of the fin structure (e.g., 3 nanometers to 10 nanometers). This will make the fin structure susceptible to damage or even collapse in subsequent processes (e.g., processes for forming source / drain electrodes, gate electrodes, etc.). Summary of the Invention

[0009] One object of the present invention is to provide a method for manufacturing a metal-oxide-semiconductor (MOS) transistor structure. This method includes the following steps: First, defining a first fin structure and a second fin structure adjacent to the first fin structure in a semiconductor substrate, wherein a shallow trench isolation (STI) region exists between the first and second fin structures. Next, a first sacrificial spacer is formed on the sidewall of the first fin structure; and a second sacrificial spacer is formed along the sidewall of the second fin structure, wherein a gap exists between the first and second sacrificial spacers. Then, an inserting dielectric layer is formed to fill the gap between the first and second sacrificial spacers. After removing the first and second sacrificial spacers, two gate structures are formed above the first and second fin structures, respectively. The two gate structures are separated from each other by the dielectric inserting layer.

[0010] In some embodiments of this specification, the first sacrificial spacer wall and the second sacrificial spacer wall comprise epitaxial semiconductor material selectively grown on the sidewalls of the first fin structure and the second fin structure as a substrate.

[0011] In some embodiments of this specification, prior to forming the first and second sacrificial spacer walls, the method further includes the following steps: First, forming a capping dielectric layer covering the first and second fin structures. Then, a gate opening is defined in the capping dielectric layer such that the sidewalls of the first and second fin structures are partially exposed from the gate opening.

[0012] In some embodiments of this specification, the method further includes the steps of: forming fin spacers to surround the sidewalls of the first fin structure and the second fin structure before forming the dielectric capping layer; and performing at least one etching process to remove the fin spacers located in the gate opening before forming the first sacrificial spacers and the second sacrificial spacers, so that the sidewalls of the first fin structure and the second fin structure are partially exposed.

[0013] In some embodiments of this specification, the material constituting the dielectric insertion layer is different from the material constituting the dielectric capping layer.

[0014] In some embodiments of this specification, the method further includes the step of deepening the gate opening after forming the epitaxial semiconductor material and before forming the dielectric intercalation layer to fill the gate opening, thereby exposing the semiconductor substrate.

[0015] In some embodiments of this specification, a portion of the semiconductor substrate is removed during the process of deepening the gate opening.

[0016] In some embodiments of this specification, while deepening the gate opening, a portion of the shallow trench isolation region is removed, leaving another portion of the shallow trench isolation region located beneath the epitaxial semiconductor material.

[0017] In some embodiments of this specification, the bottom of the dielectric insertion layer is lower than the bottom of another portion of the shallow trench isolation region.

[0018] In some embodiments of this specification, the dielectric constant of the dielectric intercalation layer is lower than that of silicon dioxide (SiO2).

[0019] In some embodiments of this specification, the first sacrificial spacer wall and the second sacrificial spacer wall comprise amorphous silicon covering the sidewalls of the first fin structure and the second fin structure.

[0020] In some embodiments of this specification, the method further includes the step of forming a fin gap wall to surround the sidewalls of the first fin structure and the second fin structure before forming the first sacrificial gap wall and the second sacrificial gap wall.

[0021] In some embodiments of this specification, the method further includes the steps of: forming a dielectric capping layer to cover the first fin structure, the second fin structure, the first sacrificial spacer wall, the second sacrificial spacer wall, and the dielectric insertion layer; and defining a gate opening in the dielectric capping layer so that the sidewalls of the first fin structure and the second fin structure are partially exposed from the gate opening.

[0022] In some embodiments of this specification, the method further includes the step of removing a portion of the shallow trench isolation region not covered by the first and second sacrificial spacers before removing the first and second sacrificial spacers, thereby exposing a portion of the semiconductor substrate.

[0023] In some embodiments of this specification, the bottom of the dielectric insertion layer is lower than the bottom of another portion of the shallow trench isolation region located below the first and second sacrificial spacer walls.

[0024] Another object of the present invention is to provide a metal-oxide-semiconductor transistor structure. The metal-oxide-semiconductor transistor structure includes a first active region, a second active region adjacent to the first active region, a dielectric intercalation layer, a first trench, a second trench, a first gate structure, and a second gate structure. The first and second active regions are formed in a semiconductor substrate, wherein a shallow trench isolation region is located between the first and second active regions. The dielectric intercalation layer is disposed between the first and second active regions. The first trench surrounds or is located above the first active region, wherein the first trench is adjacent to one side of the dielectric intercalation layer. The second trench surrounds or is located above the second active region, wherein the second trench is adjacent to the other side of the dielectric intercalation layer. The first gate structure is located above the first active region and within the first trench, wherein the first gate structure covers a first portion of the shallow trench isolation region. The second gate structure is located above the second active region and within the second trench. The second gate structure covers a second portion of the shallow trench isolation region; the distance between the first and second gate structures is determined by the dielectric intercalation layer.

[0025] In some embodiments of this specification, the metal-oxide-semiconductor transistor structure further includes: a first source region and a first drain region, electrically contacting a first channel located in the first active region; a second source region and a second drain region, electrically contacting a second channel located in the second active region. Furthermore, the width of the dielectric intercalation layer between the first and second active regions is not defined by a photolithographic process.

[0026] Another object of the present invention is to provide a metal-oxide-semiconductor transistor structure. The metal-oxide-semiconductor transistor structure includes a first fin structure, a second fin structure adjacent to the first fin structure, a dielectric insertion layer, a first trench, a second trench, a first gate structure, and a second gate structure. The first fin structure and the second fin structure are formed in a semiconductor substrate, wherein a shallow trench isolation region is located between the first fin structure and the second fin structure. The dielectric insertion layer is disposed between the first fin structure and the second fin structure. The first trench surrounds the first fin structure or is located above the first fin structure, wherein the first trench is adjacent to one side of the dielectric insertion layer. The second trench surrounds the second fin structure or is located above the second fin structure, wherein the second trench is adjacent to the other side of the dielectric insertion layer. The first gate structure is located above the first fin structure and within the first trench, wherein the first gate structure covers a first portion of the shallow trench isolation region. The second gate structure is located above the second fin structure and within the second trench. The second gate structure covers the second part of the shallow trench isolation region; the bottom of the dielectric insertion layer is lower than the bottom of the first or second part of the shallow trench isolation region.

[0027] In some embodiments of this specification, the metal-oxide-semiconductor transistor structure further includes: a first source region and a first drain region, which are electrically contacted with a first channel located in a first fin structure; a second source region and a second drain region, which are electrically contacted with a second channel located in a second fin structure. Simple Explanation of the Diagram

[0028] The technical advantages and spirit of this invention can be understood through the following description and in conjunction with the accompanying drawings. After reading the various drawings and the detailed description of the preferred embodiments shown in the drawings, those skilled in the art will gain a better understanding of the above and other aspects of this specification. Figure 1 illustrates a schematic diagram of a conventional FinFET (Fin Field-Effect Transistor); Figure 2A(1) shows a top view of the fabrication structure after the fin structure has been defined in the semiconductor substrate; Figure 2A(2) is a cross-sectional view of the structure drawn along the tangent C2A1 shown in Figure 2A(1); Figure 2A(3) is a structural cross-section drawn along the tangent C2A2 shown in Figure 2A(2); Figure 2B(1) shows a top view of the fabrication structure after the dielectric capping layer is formed to cover the fin structure; Figure 2B(2) is a structural cross-section drawn along the tangent C2B1 shown in Figure 2B(1); Figure 2B(3) is a cross-sectional view of the structure drawn along the tangent C2B2 shown in Figure 2B(1); Figure 2C(1) shows a top view of the process structure after the fin structure is partially exposed from the gate opening; Figure 2C(2) is a cross-sectional view of the structure drawn along the tangent C2C1 shown in Figure 2C(1); Figure 2C(3) is a cross-sectional view of the structure drawn along the tangent C2C2 shown in Figure 2C(1); Figure 2D(1) shows a top view of the fabrication structure after the formation of the epitaxial semiconductor material; Figure 2D(2) is a cross-sectional view of the structure drawn along the tangent C2D1 shown in Figure 2D(1); Figure 2E(1) shows a top view of the fabrication structure after the dielectric insertion layer is formed to fill the gate opening; Figure 2E(2) is a cross-sectional view of the structure drawn along the tangent C2E1 shown in Figure 2E(1); Figure 2F(1) shows a top view of the process structure after the gate structure is formed; Figure 2F(2) is a structural cross-section drawn along the tangent C2F1 shown in Figure 2F(1); Figure 2F(3) is a cross-sectional view of the structure drawn along the tangent C2F2 shown in Figure 2F(1); Figure 2G shows a perspective view of a semiconductor element with two adjacent metal-oxide-semiconductor transistors formed using the methods shown in Figures 2A(1) to 2F(3); Figure 3A(1) shows a top view of the fabrication structure after the fin structure has been defined in the semiconductor substrate; Figure 3A(2) is a cross-sectional view of the structure drawn along the tangent C3A1 shown in Figure 3A(1); Figure 3A(3) is a cross-sectional view of the structure drawn along the tangent C3A2 shown in Figure 3A(1); Figure 3B(1) shows a top view of the fabrication structure after the dielectric insertion layer and dielectric capping layer have been formed; Figure 3B(2) is a cross-sectional view of the structure drawn along the tangent C3B1 shown in Figure 3B(1); Figure 3B(3) is a cross-sectional view of the structure drawn along the tangent C3B2 shown in Figure 3B(1); Figure 3C(1) shows a top view of the process structure after the fin structure is partially exposed from the gate opening; Figure 3C(2) is a cross-sectional view of the structure drawn along the tangent C3C1 shown in Figure 3C(1); Figure 3C(3) is a cross-sectional view of the structure drawn along the tangent C3C2 shown in Figure 3C(1); Figure 3D(1) shows a top view of the process structure after the gate structure is formed; Figure 3D(2) is a cross-sectional view of the structure drawn along the tangent C3D1 shown in Figure 3D(1); Figure 3D(3) is a structural cross-section drawn along the tangent C3D2 shown in Figure 3D(1); Figure 4A(1) shows a top view of the fabrication structure after the fin structure has been defined in the semiconductor substrate; Figure 4A(2) is a structural cross-section drawn along the tangent C4A1 shown in Figure 4A(1); Figure 4A(3) is a cross-sectional view of the structure drawn along the tangent C4A2 shown in Figure 4A(1); Figure 4B(1) shows a top view of the fabrication structure after the dielectric capping layer is formed on the fin structure; Figure 4B(2) is a structural cross-section drawn along the tangent C4B1 shown in Figure 4B(1); Figure 4B(3) is a cross-sectional view of the structure drawn along the tangent C4B2 shown in Figure 4B(1); Figure 4C(1) shows a top view of the process structure after the fin structure is partially exposed from the gate opening; Figure 4C(2) is a cross-sectional view of the structure drawn along the tangent C4C1 shown in Figure 4C(1); Figure 4C(3) is a cross-sectional view of the structure drawn along the tangent C4C2 shown in Figure 4C(1); Figure 4D(1) shows a top view of the fabrication structure after the formation of the epitaxial semiconductor material; Figure 4D(2) is a structural cross-section drawn along the tangent C4D1 shown in Figure 4D(1); Figure 4E(1) shows a top view of the process structure after the gate opening is deepened to expose the semiconductor substrate; Figure 4E(2) is a structural cross-section drawn along the tangent C4E1 shown in Figure 4E(1); Figure 4F(1) shows a top view of the fabrication structure after the dielectric insertion layer is formed to fill the gate opening; Figure 4F(2) is a structural cross-section drawn along the tangent C4F1 shown in Figure 4F(1); Figure 4G(1) shows a top view of the process structure after the gate structure is formed; Figure 4G(2) is a structural cross-section drawn along the tangent C4G1 shown in Figure 4G(1); Figure 4G(3) is a cross-sectional view of the structure drawn along the tangent C4G2 shown in Figure 4G(1); Figure 5A(1) shows a top view of the fabrication structure after the fin structure has been defined in the semiconductor substrate; Figure 5A(2) is a cross-sectional view of the structure drawn along the tangent C5A1 shown in Figure 5A(1); Figure 5A(3) is a structural cross-section drawn along the tangent C5A2 shown in Figure 5A(1); Figure 5B(1) shows a top view of the process structure after a portion of the shallow groove isolation area not covered by the fin spacer walls has been removed; Figure 5B(2) is a structural cross-section drawn along the tangent C5B1 shown in Figure 5B(1); Figure 5B(3) is a cross-sectional view of the structure drawn along the tangent C5B2 shown in Figure 5B(1); Figure 5C(1) shows a top view of the fabrication structure after the dielectric insertion layer and dielectric capping layer have been formed; Figure 5C(2) is a cross-sectional view of the structure drawn along the tangent C5C1 shown in Figure 5C(1); Figure 5C(3) is a cross-sectional view of the structure drawn along the tangent C5C2 shown in Figure 5C(1); Figure 5D(1) shows a top view of the process structure after the fin structure is partially exposed from the gate opening; Figure 5D(2) is a structural cross-section drawn along the tangent C5D1 shown in Figure 5D(1); Figure 5D(3) is a structural cross-section drawn along the tangent C5D2 shown in Figure 5D(1); Figure 5E(1) shows a top view of the process structure after the gate structure has been formed; Figure 5E(2) is a structural cross-section drawn along the tangent C5E1 shown in Figure 5E(1); and Figure 5E(3) is a cross-sectional view of the structure drawn along the tangent C5E2 shown in Figure 5E(1). Implementation

[0029] This invention provides a method for manufacturing a semiconductor device having multiple MOS transistors, for miniaturizing MOS transistors and effectively controlling the spacing between two adjacent gate structures of two adjacent MOS transistors. The claims will be described in more detail below with reference to the structures and arrangements described in the specification using specific embodiments.

[0030] It should be noted that the preferred embodiments presented in this specification are merely for illustrating and describing the invention, and are not intended to disclose or limit the invention in a precise and exhaustive manner. Furthermore, it should be pointed out that the embodiments disclosed herein can still be implemented using other features, elements, steps, and parameters not specifically described in the following specification. Therefore, the description and drawings in this specification are merely illustrative and not intended to limit the invention. Those skilled in the art can provide various modifications and similar configurations without departing from the spirit of this specification. Additionally, the drawings are not necessarily drawn to scale, and the same elements in different embodiments may be represented by the same element reference numerals.

[0031] [Example] [1]

[0032] This embodiment discloses a semiconductor device 20 having two MOS transistors T21 and T22, wherein the MOS transistors T21 and T22 are formed on two adjacent fin structures 201F1 and 201F2 as substrates, respectively. The method steps for manufacturing the semiconductor device 20 are detailed below: Step S21: Define a plurality of fin structures 201F1 and 201F2 in the semiconductor substrate 201. Each fin structure 201F1 and 201F2 is surrounded by a fin spacer wall 207. Step S21 includes sub-steps S211 to S215: Sub-step S211: A portion of the semiconductor substrate 201 is removed using a patterned pad dielectric layer 210 (including a patterned pad silicon oxide layer 210A and a patterned pad silicon nitride layer 210B) as an etching mask, thereby defining fin structures 201F1 and 201F2; Sub-step S212: Forming shallow trench isolation (STI) regions 208 around fin structures 201F1 and 201F2; Sub-step S213: Perform a back etching process to remove a portion of the shallow trench isolation (STI) region 208, thereby exposing the sidewalls of the fin structures 201F1 and 201F2; Sub-step S214: Perform a thermal oxidation process to form silicon oxide interstitial walls 207A on the sidewalls of fin structures 201F1 and 201F2; and Sub-step S215: Perform a silicon nitride deposition process to form a silicon nitride interstitial wall 207B on the silicon oxide interstitial wall 207A; Step S22: Define a gate opening 202 in the dielectric capping layer 209 covering the fin structures 201F1 and 201F2 and the shallow trench isolation (STI) region 208. A portion of the sidewalls of the fin structures 201F1 and 201F2 are exposed from the corresponding gate opening 202. Step S22 includes sub-steps S221 to S223: Sub-step S221: Perform a silicon oxide deposition process to form a dielectric capping layer 209 on the fin structures 201F1 and 201F2; Sub-step S222: Perform a patterning process, removing a portion of the dielectric capping layer 209 to define the gate opening 202, exposing the silicon nitride spacer wall 207B from the gate opening 202; and Sub-step S223: Remove the silicon nitride spacer wall 207B and silicon oxide spacer wall 207A located within the gate opening 202, so that the fin structures 201F1 and 201F2 are partially exposed from the gate opening 202; Step S23: Using the exposed portions of fin structures 201F1 and 201F2 as a substrate, form an epitaxial semiconductor material 203 (as a sacrificial spacer); Step S24: Form a dielectric insertion layer 211 to fill the gate opening 202, thereby surrounding the epitaxial semiconductor material 203; Step S25: Remove the epitaxial semiconductor material 203, thereby re-exposing the exposed portions 201E1 and 201E2 of the fin structures 201F1 and 201F2; and Step S26: Gate structures 204 and 205 are formed on fin structures 201F1 and 201F2, respectively. Step S26 includes sub-steps S261 to S262: Sub-step S261: Remove silicon nitride spacer wall 207B and silicon oxide spacer wall 207A to expose fin structures 201F1 and 201F2; Sub-step S262: Form gate dielectric layers 204O and 205O, respectively covering the top and sidewalls of fin structures 201F1 and 201F2; and Sub-step S263: Form gate electrodes 204S and 205S, respectively covering the gate dielectric layers 204O and 205O.

[0033] Please refer to step S21: Define multiple fin structures 201F1 and 201F2 in the semiconductor substrate 201. Each fin structure 201F1 and 201F2 is surrounded by a fin spacer wall 207. Figure 2A(1) shows a top view of the fabrication structure after the fin structures 201F1 and 201F2 are defined in the semiconductor substrate 201; Figure 2A(2) is a cross-sectional view of the structure drawn along the tangent C2A1 shown in Figure 2A(1); and Figure 2A(3) is a cross-sectional view of the structure drawn along the tangent C2A2 shown in Figure 2A(2). The definition of fin structures 201F1 and 201F2 includes the following sub-steps S211 to S215:

[0034] Please refer to sub-step S211: An etching process is performed using a patterned pad dielectric layer 210 (including a patterned pad silicon oxide layer 210A and a patterned pad silicon nitride layer 210B) as an etching mask to remove a portion of the silicon material in the semiconductor substrate 201 to construct multiple trenches 201T, thereby defining fin structures 201F1 and 201F2 in the semiconductor substrate 201. In some embodiments, the distance between two adjacent fin structures 201F1 and 201F2 can be between approximately 30 nanometers and 50 nanometers. The thicknesses of the two fin structures 201F1 and 201F2 can be between 3 nanometers and 10 nanometers, for example, 5 nanometers.

[0035] Please refer to substep S212: Form shallow trench isolation (STI) regions 208 to surround fin structures 201F1 and 201F2. In some embodiments of this specification, silicon oxide material is deposited to completely fill trench 201T, and then an etch-back process is performed so that the remaining silicon oxide material in trench 201T is used as shallow trench isolation (STI) regions 208 surrounding multiple fin structures 201F1 and 201F2. Please refer to substep S213: Perform another etch-back process to remove a portion of the shallow trench isolation (STI) regions 208, exposing the sidewalls of fin structures 201F1 and 201F2.

[0036] Then, please refer to sub-step S214: perform a thermal oxidation process to form silicon oxide spacer walls 207A on the sidewalls of fin structures 201F1 and 201F2. Please refer to sub-step S215: perform a silicon nitride deposition process to form silicon nitride spacer walls 207B on silicon oxide spacer walls 207A (as shown in Figures 2A(2) and 2A(3)).

[0037] Please refer to step S22: Define a gate opening 202 in the dielectric capping layer 209 covering the fin structures 201F1 and 201F2 and the shallow trench isolation (STI) region 208. A portion of the sidewalls of the fin structures 201F1 and 201F2 are exposed from the corresponding gate opening 202. Step S22 includes sub-steps S221 to S223:

[0038] Please refer to sub-step S221: Perform a silicon oxide deposition process to form a dielectric capping layer 209 on fin structures 201F1 and 201F2. Figure 2B(1) is a top view of the process structure after the dielectric capping layer 209 is formed to cover fin structures 201F1 and 201F2; Figure 2B(2) is a cross-sectional view of the structure drawn along tangent C2B1 shown in Figure 2B(1); Figure 2B(3) is a cross-sectional view of the structure drawn along tangent C2B2 shown in Figure 2B(1). In this embodiment, after the silicon oxide deposition process to form the dielectric capping layer 209, a planarization process is then performed. The dielectric capping layer 209 is covered with silicon dioxide (SiO2).

[0039] Please refer to sub-step S222: Perform a patterning process to remove a portion of the dielectric capping layer 209, thereby defining the gate opening 202 and exposing the silicon nitride spacer 207B from the gate opening 202. Please refer to sub-step S223: Perform another etching process to remove the silicon nitride spacer 207B and silicon oxide spacer 207A located within the gate opening 202, so that the fin structures 201F1 and 201F2 are partially exposed from the gate opening 202. Figure 2C(1) is a top view of the process structure after the fin structures 201F1 and 201F2 are partially exposed from the gate opening 202; Figure 2C(2) is a cross-sectional view of the structure drawn along the tangent C2C1 shown in Figure 2C(1); Figure 2C(3) is a cross-sectional view of the structure drawn along the tangent C2C2 shown in Figure 2C(1).

[0040] Please refer to step S23: using the exposed portions of fin structures 201F1 and 201F2 as a substrate, an epitaxial semiconductor material 203 (as a sacrificial spacer) is formed. Figure 2D(1) is a top view of the process structure after the formation of the epitaxial semiconductor material 203; Figure 2D(2) is a cross-sectional view of the structure drawn along the tangent C2D1 shown in Figure 2D(1). In some embodiments of the present invention, a selective epitaxial growth (SEG) method is used to form the epitaxial semiconductor material 203 (e.g., silicon (Si), silicon-germanium (SiGe), germanium (Ge), etc.) using the exposed portions of fin structures 201F1 and 201F2 as a substrate. In some other embodiments of this specification, other semiconductor epitaxial materials (e.g., silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.) can be grown on the exposed portions of fin structures 201F1 and 201F2 as a substrate, depending on the materials of the fin structures 201F1 and 201F2. The thickness of the epitaxial semiconductor material 203 is between about 5 nanometers and 12 nanometers, for example, between 7 nanometers and 8 nanometers.

[0041] Please refer to step S24: Forming a dielectric insertion layer 211 to fill the gate opening 202, thereby surrounding the epitaxial semiconductor material 203. Figure 2E(1) is a top view of the process structure after the dielectric insertion layer 211 is formed to fill the gate opening 202; Figure 2E(2) is a cross-sectional view of the structure drawn along the tangent C2E1 shown in Figure 2E(1). In some embodiments of this specification, the material constituting the dielectric insertion layer 211 may be different from the material constituting the dielectric capping layer 209. In this embodiment, the dielectric insertion layer 211 is formed using a low dielectric constant (k) dielectric material (e.g., hydrogenated silicon carbide (SiCOH)) deposition process. The dielectric insertion layer 211 can then be etched back, thereby exposing the patterned pad silicon nitride layer 210B (or even the pad silicon oxide layer 210A) from the gate opening 202, which is only partially filled. Furthermore, as illustrated in Figure 2E(2), the distance D2 between the epitaxial semiconductor materials 203 or the sacrificial spacer walls on both sides is between 15 nanometers and 30 nanometers, for example, about 20 nanometers. And the distance D2 can be equal to or substantially equal to a "gate cut" spacing or "poly cut" spacing between the two gate structures 204 and 205 of the adjacent transistor.

[0042] Please refer to step S25: Remove the epitaxial semiconductor material 203 to expose the exposed portions 201E1 and 201E2 of the fin structures 201F1 and 201F2 to the outside again. Please refer to step S26: Form gate structures 204 and 205 on the fin structures 201F1 and 201F2 respectively. Figure 2F(1) is a top view of the process structure after the formation of gate structures 204 and 205; Figure 2F(2) is a cross-sectional view of the structure drawn along the tangent C2F1 shown in Figure 2F(1); Figure 2F(3) is a cross-sectional view of the structure drawn along the tangent C2F2 shown in Figure 2F(1).

[0043] Step S26, which forms gate structures 204 and 205, includes sub-steps S261 to S262: Referring to sub-step S261: Remove silicon nitride spacer walls 207B and silicon oxide spacer walls 207A, exposing fin structures 201F1 and 201F2. In this embodiment, different etching processes can be used to remove silicon nitride spacer walls 207B and silicon oxide spacer walls 207A respectively.

[0044] Please refer to sub-step S262: Form gate dielectric layers 204O and 205O, respectively covering the top and sidewalls of fin structures 201F1 and 201F2. In some embodiments of the present invention, gate dielectric layers 204O and 205O are formed using a silicon oxide deposition process. Next, please refer to sub-step S263: Form gate electrodes 204S and 205S, respectively covering gate dielectric layers 204O and 205O. In some embodiments of this specification, gate electrodes 204S and 205S are formed of polycrystalline silicon or metal. The space formed after removing the epitaxial semiconductor material 203 is just filled by gate dielectric layers 204O and 205O and gate electrodes 204S and 205S.

[0045] After forming gate structures 204 and 205, source regions 212 and drain regions 213 of the transistor can be formed. For example, a portion of the fin structure outside the gate region is removed first, and then (optionally) local isolation regions 215 and 225 are formed in the semiconductor substrate 201. Then, a source region 212 comprising a lightly doped drain region (e.g., N-semiconductor region) 212A, an N+ semiconductor region 212B, and a bonding pad 212C, and a drain region 213 comprising a lightly doped drain region (e.g., N-semiconductor region) 213A, an N+ semiconductor region 213B, and a bonding pad 213C are formed on the local isolation region 215, so that the source regions 212 / drain regions 213 are in electrical contact with the fin structure 201F1. The bonding pad 212C (or 213C) can contact the outermost lateral sidewall of the N+ semiconductor region 212B (or 213B). Similarly, a source region 222 comprising a lightly doped drain region (e.g., an N-semiconductor region) 222A, an N+semiconductor region 222B, and a bonding pad 222C, and a drain region 223 comprising a lightly doped drain region (e.g., an N-semiconductor region) 223A, an N+semiconductor region 223B, and a bonding pad 223C, are formed on the local isolation region 225, so that the source region 222 / drain region 223 are in electrical contact with the fin structure 201F2. Thus, a semiconductor element 20 having two adjacent MOS transistors T21 and T22 is formed (see Figure 2G), and they are separated from each other by a gate electrode spacing P2 (or "gate notch" distance or "polysilicon notch" distance), wherein the gate electrode spacing P2 may be equal to a specific distance D2 defined by the portion of dielectric material (dielectric insertion layer 211) located between the two adjacent fin structures 201F1 and 201F2.

[0046] After a series of subsequent back-end process steps, a semiconductor device 20 (e.g., an SRAM cell) using MOS transistors T21 and T22 can be formed. Since the specific distance D2 mentioned above can be well controlled by the dielectric material (dielectric insertion layer 211) deposited in the gate opening 202, and is much smaller than the conventional lithography rule used to define the gate electrode spacing between two adjacent MOS transistors, the gate electrode spacing P2 between the two adjacent MOS transistors T21 and T22 can be significantly reduced.

[0047] In addition, since the fin structures 201F1 and 201F2 are protected by the fin spacer wall 207 before the gate and source / drain regions are formed, and are well supported by the dielectric material (dielectric capping layer 209), the fragile fin structures 201F1 and 201F2 can be prevented from collapsing during the formation of the gate structures 204 and 205, the source regions 212 / 222 and the drain regions 213 / 223.

[0048] [Example] [2]

[0049] This embodiment discloses another semiconductor device 30 having two MOS transistors T31 and T32, wherein the MOS transistors T31 and T32 are formed on two adjacent fin structures 301F1 and 301F2 as substrates, respectively. The method steps for manufacturing the semiconductor device 30 are detailed below: Step S31: Define a plurality of fin structures 301F1 and 301F2 in the semiconductor substrate 301. Each fin structure 301F1 and 301F2 is surrounded by a fin spacer wall 307. Step S31 includes sub-steps S311 to S316: Sub-step S311: Using a patterned pad dielectric layer 310 (including a patterned pad silicon oxide layer 310A and a patterned pad silicon nitride layer 310B) as an etching mask, a portion of the semiconductor substrate 301 is removed, thereby defining fin structures 301F1 and 301F2; Sub-step S312: Forming shallow trench isolation (STI) regions 308 around fin structures 301F1 and 301F2; Sub-step S313: Perform a back etching process to remove a portion of the shallow trench isolation (STI) region 308, thereby exposing the sidewalls of the fin structures 301F1 and 301F2; Sub-step S314: Perform a thermal oxidation process to form silicon oxide interstitial walls 307A on the sidewalls of fin structures 301F1 and 301F2; Sub-step S315: Perform a silicon nitride deposition process to form a silicon nitride interstitial wall 307B on the silicon oxide interstitial wall 307A; and Sub-step S316: Form an amorphous silicon interstitial wall 307C (as a sacrificial interstitial wall) on the silicon nitride interstitial wall 307B; Step S32: Define a gate opening 302 in the dielectric capping layer 309 covering the fin structures 301F1 and 301F2 and the shallow trench isolation (STI) region 308. A portion of the sidewalls of the fin structures 301F1 and 301F2 are exposed from the corresponding gate opening 302. Step S32 includes sub-steps S321 to S324: Sub-step S321: Form a dielectric insertion layer 311 to surround the sidewalls of fin structures 301F1 and 301F2; Sub-step S322: Perform silicon oxide deposition process to form a dielectric capping layer 309 on the fin structures 301F1 and 301F2 and the dielectric insertion layer 311; Sub-step S323: Perform a patterning process, removing a portion of the dielectric capping layer 309 to define the gate opening 302; and Sub-step S324: Remove the amorphous silicon spacer wall 307C, silicon nitride spacer wall 307B, and silicon oxide spacer wall 307A, so that a portion of the fin structures 301F1 and 301F2 are exposed from the gate opening 302; Step S33: Gate structures 304 and 305 are formed on fin structures 301F1 and 301F2, respectively. Step S33 includes sub-steps S331 to S332: Sub-step S331: Form gate dielectric layers 304O and 305O, respectively covering the top and sidewalls of fin structures 301F1 and 301F2; and Sub-step S332: Form gate electrodes 304S and 305S, respectively covering the gate dielectric layers 304O and 305O.

[0050] Please refer to step S31: Define multiple fin structures 301F1 and 301F2 in the semiconductor substrate 301. Each fin structure 301F1 and 301F2 is surrounded by a fin spacer wall 307. Figure 3A(1) is a top view of the process structure after the fin structures 301F1 and 301F2 are defined in the semiconductor substrate 301; Figure 3A(2) is a cross-sectional view of the structure drawn along the tangent C3A1 shown in Figure 3A(1); Figure 3A(3) is a cross-sectional view of the structure drawn along the tangent C3A2 shown in Figure 3A(1). The definition of fin structures 301F1 and 301F2 includes the following sub-steps S311 to S316:

[0051] Please refer to sub-step S311: An etching process is performed using a patterned pad dielectric layer 310 (including a patterned pad silicon oxide layer 310A and a patterned pad silicon nitride layer 310B) as an etching mask to remove a portion of the silicon material in the semiconductor substrate 301 to construct multiple trenches 301T, thereby defining fin structures 301F1 and 301F2 in the semiconductor substrate 301. In some embodiments, the distance between two adjacent fin structures 301F1 and 301F2 can be between approximately 30 nanometers and 50 nanometers. The thicknesses of the two fin structures 301F1 and 301F2 can be between 3 nanometers and 10 nanometers, for example, 5 nanometers.

[0052] Please refer to substep S312: Form shallow trench isolation (STI) regions 308 to surround fin structures 301F1 and 301F2. In some embodiments of this specification, silicon oxide material is deposited to completely fill trench 301T, and then an etching process is performed to allow the remaining silicon oxide material in trench 301T to serve as shallow trench isolation (STI) regions 208 surrounding the multiple fin structures 301F1 and 301F2. Please refer to substep S313: Perform another etching process to remove a portion of the shallow trench isolation (STI) regions 308, exposing the sidewalls of fin structures 201F1 and 301F2.

[0053] Then, referring to sub-step S314: a thermal oxidation process is performed to form silicon oxide spacer walls 307A on the sidewalls of fin structures 301F1 and 301F2. Referring to sub-step S315: a silicon nitride deposition process is performed to form silicon nitride spacer walls 307B on silicon oxide spacer walls 307A. Referring to sub-step S316: an amorphous silicon spacer wall 307C (as a sacrificial spacer wall) is formed on silicon nitride spacer walls 307B. In some embodiments of this specification, forming the amorphous silicon spacer 307C includes the following steps: first, depositing amorphous silicon to cover the fin spacer walls 307, the shallow trench isolation (STI) region 308, and the fin structures 301F1 and 301F2; then performing an isotropic etching process to remove a portion of the amorphous silicon, leaving another portion of the amorphous silicon located on the sidewalls of the silicon nitride spacer wall 307B. The thickness of each amorphous silicon interstitial wall 307C is between approximately 5 nanometers and 10 nanometers.

[0054] Please refer to step S32: Define a gate opening 302 in the dielectric capping layer 309 covering the fin structures 301F1 and 301F2 and the shallow trench isolation (STI) region 308. A portion of the sidewalls of the fin structures 301F1 and 301F2 are exposed from the corresponding gate opening 302. Step S32 includes sub-steps S321 to S324:

[0055] Please refer to sub-step S321: Form a dielectric insertion layer 311 to surround the sidewalls of fin structures 301F1 and 301F2; then refer to sub-step S322: Perform a silicon oxide deposition process to form a dielectric capping layer 309 on fin structures 301F1 and 301F2 and dielectric insertion layer 311. Figure 3B(1) is a top view of the process structure after the formation of dielectric insertion layer 311 and dielectric capping layer 309; Figure 3B(2) is a cross-sectional view of the structure drawn along tangent C3B1 shown in Figure 3B(1); Figure 3B(3) is a cross-sectional view of the structure drawn along tangent C3B2 shown in Figure 3B(1).

[0056] In some embodiments of the present invention, the material constituting the dielectric insertion layer 311 may be different from the material constituting the dielectric capping layer 309. In this embodiment, the dielectric insertion layer 311 is formed by a low dielectric constant (k) dielectric material (e.g., hydrogenated silicon carbide (SiCOH)) deposition process and fills the trench 301T. The deposited low dielectric constant (k) dielectric material can be planarized by chemical mechanical polishing (CMP) technology. Then, the pad silicon nitride layer 310B, silicon nitride spacer 307B, and amorphous silicon spacer 307C are used as etch stop layers for etching back. Thus, the pad silicon nitride layer 310B, silicon nitride spacer 307B, and amorphous silicon spacer 307C can be exposed from the partially filled trench 301T. The silicon oxide deposition process for forming the dielectric capping layer 309 described in sub-step S322 includes depositing silicon dioxide to cover the pad silicon nitride layer 310B, silicon nitride interstitial wall 307B and amorphous silicon interstitial wall 307C, followed by a planarization process (e.g., CMP).

[0057] Please refer to sub-step S323: Perform a patterning process to remove a portion of the dielectric capping layer 309, thereby defining the gate opening 302. In some embodiments, a patterned photoresist layer (not shown) is first formed on the dielectric capping layer 309 to expose a portion of the dielectric capping layer 309 covering the fin structures 301F1 and 301F2. Then, an etching process is performed to remove the exposed portion of the dielectric capping layer 309, thereby defining the gate opening 302 in the dielectric capping layer 309.

[0058] Please refer to sub-step S324: Remove the amorphous silicon spacer wall 307C, silicon nitride spacer wall 307B, and silicon oxide spacer wall 307A, so that a portion of the fin structures 301F1 and 301F2 are exposed from the gate opening 302. Figure 3C(1) is a top view of the process structure after the fin structures 301F1 and 301F2 are partially exposed from the gate opening 302; Figure 3C(2) is a cross-sectional view of the structure drawn along the tangent C3C1 shown in Figure 3C(1); Figure 3C(3) is a cross-sectional view of the structure drawn along the tangent C3C2 shown in Figure 3C(1).

[0059] In this embodiment, after defining the gate opening 302 in the dielectric capping layer 309, another etching process is performed to remove the amorphous silicon spacer wall 307C. This includes performing another etching process after stripping the patterned photoresist layer to remove the silicon nitride spacer wall 307B and a portion of the patterned silicon nitride layer 310B exposed from the gate opening 302. Next, another etching process removes the silicon oxide spacer wall 307A and a portion of the patterned pad silicon oxide layer 310A exposed from the gate opening 302, thereby exposing the top and sidewalls of the fin structures 301F1 and 301F2.

[0060] Please refer to step S33: form gate structures 304 and 305 on fin structures 301F1 and 301F2 respectively. Figure 3D(1) is a top view of the process structure after forming gate structures 304 and 305; Figure 3D(2) is a cross-sectional view of the structure drawn along the tangent C3D1 shown in Figure 3D(1); Figure 3D(3) is a cross-sectional view of the structure drawn along the tangent C3D2 shown in Figure 3D(1).

[0061] Step S33, forming gate structures 304 and 305, includes the following sub-steps S331 to S332: Referring to sub-step S331: Gate dielectric layers 304O and 305O are formed, respectively covering the top and sidewalls of fin structures 301F1 and 301F2. In some embodiments of the present invention, gate dielectric layers 304O and 305O are formed using a silicon oxide deposition process. Next, referring to sub-step S332: Gate electrodes 304S and 305S are formed, respectively covering gate dielectric layers 304O and 305O. In some embodiments of this specification, gate electrodes 304S and 305S are formed of polycrystalline silicon or metal.

[0062] After forming the gate structures 304 and 305, the dielectric capping layer 309 is removed, and then the source / drain regions are formed as described above. Similarly, the distance between the gate electrodes of two adjacent MOS transistors T31 and T32 can be well controlled by the second dielectric material of the dielectric insertion layer 311 deposited in the gate opening 302. Furthermore, this distance is much smaller than the gate electrode spacing defined by conventional lithography processes, thus significantly reducing the spacing between the gate electrodes of two adjacent MOS transistors T31 and T32.

[0063] In addition, since the fin structures 301F1 and 301F2 are protected by the fin spacer wall 307 before the gate and source / drain regions are formed, and are well supported by the first dielectric material of the dielectric capping layer 309 and the second dielectric material of the dielectric insertion layer 311, the fragile fin structures 301F1 and 301F2 can be prevented from collapsing during the formation of the gate structures 304 and 305, the source regions 312 / 322 and the drain regions 313 / 323.

[0064] [Example] [3]

[0065] This embodiment discloses another semiconductor device 40 having two MOS transistors T41 and T42, wherein the MOS transistors T41 and T42 are formed on two adjacent fin structures 401F1 and 401F2 as substrates, respectively. The method steps for manufacturing the semiconductor device 40 are detailed below: Step S41: Define a plurality of fin structures 401F1 and 401F2 in the semiconductor substrate 401. Each fin structure 401F1 and 401F2 is surrounded by a fin spacer wall 407. Step S41 includes sub-steps S411 to S415: Sub-step S411: Using a patterned pad dielectric layer 410 (including a patterned pad silicon oxide layer 410A and a patterned pad silicon nitride layer 410B) as an etching mask, a portion of the semiconductor substrate 401 is removed, thereby defining fin structures 401F1 and 401F2; Sub-step S412: Forming shallow trench isolation (STI) regions 408 around fin structures 401F1 and 401F2; Sub-step S413: Perform a back etching process to remove a portion of the shallow trench isolation (STI) region 408, thereby exposing the sidewalls of the fin structures 401F1 and 401F2; Sub-step S414: Perform a thermal oxidation process to form silicon oxide interstitial walls 407A on the sidewalls of fin structures 401F1 and 401F2; and Sub-step S415: Perform a silicon nitride deposition process to form a silicon nitride interstitial wall 407B on the silicon oxide interstitial wall 407A; Step S42: Define a gate opening 402 in the dielectric capping layer 409 covering the fin structures 401F1 and 401F2 and the shallow trench isolation (STI) region 408. A portion of the sidewalls of the fin structures 401F1 and 401F2 are exposed from the corresponding gate opening 402. Step S42 includes sub-steps S421 to S423: Sub-step S421: Perform a silicon oxide deposition process to form a dielectric capping layer 409 on the fin structures 401F1 and 401F2; Sub-step S422: Perform a patterning process, removing a portion of the dielectric capping layer 409 to define the gate opening 402, exposing the silicon nitride spacer wall 407B from the gate opening 402; and Sub-step S423: Remove the silicon nitride spacer wall 407B and silicon oxide spacer wall 407A within the gate opening 402, so that the fin structures 401F1 and 401F2 are partially exposed from the gate opening 402; Step S43: Form an epitaxial semiconductor material 403 (as a sacrificial spacer) using the exposed portions of fin structures 401F1 and 401F2 as a substrate; Step S44: The gate opening 402 is deepened by etching the shallow trench isolation (STI) region 408, thereby exposing the semiconductor substrate 401. Step S45: A dielectric insertion layer 411 is formed to fill the gate opening 402 and surround the epitaxial semiconductor material 403; Step S46: Remove the epitaxial semiconductor material 403, thereby re-exposing the previously exposed portions 401E1 and 401E2 of the fin structures 401F1 and 401F2; and Step S47: Gate structures 404 and 405 are formed on fin structures 401F1 and 401F2, respectively.

[0066] Please refer to step S41: Define multiple fin structures 401F1 and 401F2 in the semiconductor substrate 401. Each fin structure 401F1 and 401F2 is surrounded by a fin spacer wall 407. Figure 4A(1) is a top view of the process structure after the fin structures 401F1 and 401F2 are defined in the semiconductor substrate 401; Figure 4A(2) is a cross-sectional view of the structure drawn along the tangent C4A1 shown in Figure 4A(1); Figure 4A(3) is a cross-sectional view of the structure drawn along the tangent C4A2 shown in Figure 4A(1). Step S41, which defines multiple fin structures 401F1 and 401F2, includes sub-steps S411 to S415:

[0067] Please refer to sub-step S411: A portion of the semiconductor substrate 401 is removed using a patterned pad dielectric layer 410 (including a patterned pad silicon oxide layer 410A and a patterned pad silicon nitride layer 410B) as an etching mask, thereby defining fin structures 401F1 and 401F2 in the semiconductor substrate 401. In some embodiments, the distance between two adjacent fin structures 401F1 and 401F2 can be approximately between 30 nanometers and 50 nanometers. The thickness of each fin structure 401F1 and 401F2 is approximately between 3 nanometers and 10 nanometers, for example, 5 nanometers.

[0068] Please refer to substep S412: Forming shallow trench isolation (STI) regions 408 around fin structures 401F1 and 401F2. In some embodiments of this specification, this includes depositing silicon oxide material to completely fill the trench 401T, followed by etching back, so that the remaining silicon oxide material in the trench 401T can be used as shallow trench isolation (STI) regions 408, surrounding fin structures 401F1 and 401F2. Please refer to substep S413: Performing an etching back process to remove a portion of the shallow trench isolation (STI) regions 408, thereby exposing the sidewalls of fin structures 401F1 and 401F2.

[0069] Then, refer to sub-step S414: perform a thermal oxidation process to form silicon oxide spacer walls 407A on the sidewalls of fin structures 401F1 and 401F2. Next, refer to sub-step S414: perform a silicon nitride deposition process to form silicon nitride spacer walls 407B on silicon oxide spacer walls 407A (as shown in Figures 4A(2) and 4A(3)).

[0070] Please refer to step S42: Define a gate opening 402 in the dielectric capping layer 409 covering the fin structures 401F1 and 401F2 and the shallow trench isolation (STI) region 408. A portion of the sidewalls of the fin structures 401F1 and 401F2 are exposed from the corresponding gate opening 402. Step S42 includes sub-steps S421 to S423:

[0071] Please refer to sub-step S421: Perform a silicon oxide deposition process to form a dielectric capping layer 409 on fin structures 401F1 and 401F2. Figure 4B(1) is a top view of the process structure after the dielectric capping layer 409 is formed on fin structures 401F1 and 401F2; Figure 4B(2) is a cross-sectional view of the structure drawn along tangent C4B1 shown in Figure 4B(1); Figure 4B(3) is a cross-sectional view of the structure drawn along tangent C4B2 shown in Figure 4B(1). In this embodiment, a planarization process is included after the step of forming the dielectric capping layer 409 in the silicon oxide deposition process. The dielectric capping layer 409 comprises silicon dioxide.

[0072] Please refer to sub-step S422: Perform a patterning process, remove a portion of the dielectric capping layer 409 to define the gate opening 402, and expose the silicon nitride spacer wall 407B from the gate opening 402. Please refer to sub-step S423: Remove the silicon nitride spacer wall 407B and silicon oxide spacer wall 407A within the gate opening 402, so that the fin structures 401F1 and 401F2 are partially exposed from the gate opening 402. Figure 4C(1) is a top view of the process structure after the fin structures 401F1 and 401F2 are partially exposed from the gate opening 402; Figure 4C(2) is a cross-sectional view of the structure drawn along the tangent C4C1 shown in Figure 4C(1); Figure 4C(3) is a cross-sectional view of the structure drawn along the tangent C4C2 shown in Figure 4C(1).

[0073] Please refer to step S43: An epitaxial semiconductor material 403 (as a sacrificial spacer) is formed using the exposed portions of fin structures 401F1 and 401F2 as a substrate. Figure 4D(1) is a top view of the process structure after the formation of the epitaxial semiconductor material 403; Figure 4D(2) is a cross-sectional view of the structure drawn along the tangent C4D1 shown in Figure 4D(1). In some embodiments of this specification, the epitaxial semiconductor material 403 (e.g., silicon, silicon-germanium, germanium, etc.) is formed using selective epitaxial growth (SEG) on the exposed portions of fin structures 401F1 and 401F2 as a substrate. In some other embodiments of this specification, other semiconductor epitaxial materials (e.g., silicon carbide, gallium arsenide, gallium nitride, etc.) can be grown using selective epitaxial growth (SEG) on the exposed portions of fin structures 401F1 and 401F2 as a substrate. The thickness of epitaxial semiconductor material 403 is between about 5 nanometers and 12 nanometers, for example, between 7 nanometers and 8 nanometers.

[0074] Please refer to step S44: the gate opening 402 is deepened by etching the shallow trench isolation (STI) region 408 to expose the semiconductor substrate 401. Figure 4E(1) is a top view of the process structure after the gate opening 402 has been deepened to expose the semiconductor substrate 401; Figure 4E(2) is a cross-sectional view of the structure drawn along the tangent C4E1 shown in Figure 4E(1). In some embodiments of the present invention, this step includes performing an etching process to remove a portion of the shallow trench isolation (STI) region 408 exposed from the gate opening 402 and to remove a portion of the semiconductor substrate 401 located below the removed portion of the shallow trench isolation (STI) region 408.

[0075] Please refer to step S45: A dielectric insertion layer 411 is formed to fill the gate opening 402 and surround the epitaxial semiconductor material 403 and the remaining shallow trench isolation (STI) region 408. Figure 4F(1) is a top view of the process structure after the dielectric insertion layer 411 is formed to fill the gate opening 402; Figure 4F(2) is a cross-sectional view of the structure drawn along the tangent C4F1 shown in Figure 4F(1). In some embodiments of the present invention, the material constituting the dielectric insertion layer 411 may be different from the material constituting the dielectric capping layer 409. In this embodiment, the dielectric insertion layer 411 is formed using a low dielectric constant (k) dielectric material (e.g., hydrogenated silicon carbide (SiCOH)) deposition process. The height of the bottom of the dielectric insertion layer 411 (SiCOH) is lower than the height of the bottom of the shallow trench isolation (STI) region 408. Since the dielectric constant of the dielectric intercalation layer 411 (SiCOH) is lower than that of the shallow trench isolation (STI) region 408, the coupling effect between the two gate structures 404 and 406 (formed later, see Figures 4G(1) to 4G(3)) can be improved. The dielectric intercalation layer 411 can then be etched back. This exposes the patterned pad silicon nitride layer 410B from the partially filled gate opening 402. Furthermore, as illustrated in Figure 4F(2), the distance D4 between the two epitaxial semiconductor materials 403 or sacrificial spacers is approximately between 15 nm and 30 nm, for example, approximately 20 nm, and the distance D4 can be equal to or substantially equal to the "gate cut" distance or "polysilicon cut" distance between the two gate structures of adjacent transistors. The distance D4 can be equal to the width of the dielectric intercalation layer 411 located between the fin structures 401F1 and 401F2.

[0076] Please refer to step S46: Remove the epitaxial semiconductor material 403 to form a space and thereby expose the sidewalls of the fin structures 401F1 and 401F2 again. Then, please refer to step S47: Form gate structures 404 and 405 on the fin structures 401F1 and 401F2 respectively. Figure 4G(1) is a top view of the process structure after the formation of gate structures 404 and 405; Figure 4G(2) is a cross-sectional view of the structure drawn along the tangent C4G1 shown in Figure 4G(1); Figure 4G(3) is a cross-sectional view of the structure drawn along the tangent C4G2 shown in Figure 4G(1).

[0077] Step S47, which forms gate structures 404 and 405, includes the following sub-steps S471 to S473: Referring to sub-step S471: Remove silicon nitride spacer walls 407B and silicon oxide spacer walls 407A to expose fin structures 401F1 and 401F2. In this embodiment, silicon nitride spacer walls 407B and silicon oxide spacer walls 407A can be removed using different etching processes.

[0078] Next, referring to sub-step S471: gate dielectric layers 404O and 405O are formed, respectively covering the top and sidewalls of fin structures 401F1 and 401F2. In some embodiments of the present invention, gate dielectric layers 404O and 405O are formed using a silicon oxide deposition process. Next, referring to sub-step S473: gate electrodes 404S and 405S are formed, respectively covering gate dielectric layers 404O and 405O. In some embodiments of this specification, gate electrodes 404S and 405S are formed from polycrystalline silicon or metal. Therefore, the space formed after removing the epitaxial semiconductor material 403 can be just filled by gate dielectric layers 404O and 405O and gate electrodes 404S and 405S.

[0079] After forming gate structures 404 and 405, the source / drain regions of the transistor can be formed as described above.

[0080] Compared to Example 1, in this example, the bottom height of the dielectric insertion layer 411 (SiCOH) between the two gate structures 404 and 405 is lower than the bottom height of the shallow trench isolation (STI) region 408. Since the dielectric constant of the dielectric insertion layer 411 (SiCOH) is lower than the dielectric constant of the trench isolation (STI) region 408, the coupling effect between the two gate structures 404 and 405 can be improved.

[0081] [Example] [4]

[0082] This embodiment discloses another semiconductor device 50 having two MOS transistors T51 and T52, wherein the MOS transistors T51 and T52 are formed on two adjacent fin structures 501F1 and 501F2 as substrates, respectively. The method steps for manufacturing the semiconductor device 50 are detailed below: Step S51: Define a plurality of fin structures 501F1 and 501F2 in the semiconductor substrate 501. Each fin structure 501F1 and 501F2 is surrounded by a fin spacer wall 507. Step S51 includes sub-steps S511 to S516: Sub-step S511: Using a patterned pad dielectric layer 510 (including a patterned pad silicon oxide layer 510A and a patterned pad silicon nitride layer 510B) as an etching mask, a portion of the semiconductor substrate 501 is removed, thereby defining fin structures 501F1 and 501F2; Sub-step S512: Forming shallow trench isolation (STI) regions 508 around fin structures 501F1 and 501F2; Sub-step S513: Perform a back etching process to remove a portion of the shallow trench isolation (STI) region 508, thereby exposing the sidewalls of the fin structures 501F1 and 501F2; Sub-step S514: Perform a thermal oxidation process to form silicon oxide interstitial walls 507A on the sidewalls of fin structures 501F1 and 501F2; and Sub-step S515: Perform a silicon nitride deposition process to form a silicon nitride interstitial wall 507B on the silicon oxide interstitial wall 507A; Sub-step S516: Forming an amorphous silicon interstitial wall 507C (as a sacrificial interstitial wall) on the silicon nitride interstitial wall 507B; Step S52: Remove a portion of the shallow trench isolation (STI) region 508 not covered by the fin spacers 507 (including silicon oxide spacers 507A, silicon nitride spacers 507B, and amorphous silicon spacers 507C), thereby exposing a portion of the semiconductor substrate 501 located beneath the removed portion of the shallow trench isolation (STI) region 508. Step S53: Define a gate opening 502 in the dielectric capping layer 509 covering the fin structures 501F1 and 501F2 and the shallow trench isolation (STI) region 508. A portion of the sidewalls of the fin structures 501F1 and 501F2 are exposed from the corresponding gate opening 502. Step S52 includes sub-steps S531 to S534: Sub-step S531: Form a dielectric insertion layer 511 to surround the sidewalls of fin structures 501F1 and 501F2; Sub-step S532: Perform silicon oxide deposition process to form a dielectric capping layer 509 on the fin structures 501F1 and 501F2 and the dielectric insertion layer 511; Sub-step S533: Perform a patterning process, removing a portion of the dielectric capping layer 509 to define the gate opening 502; and Sub-step S534: Remove the amorphous silicon spacer wall 507C, silicon nitride spacer wall 507B, and silicon oxide spacer wall 507A, so that a portion of the fin structures 501F1 and 501F2 are exposed from the gate opening 502; Step S54: Gate structures 504 and 505 are formed on fin structures 501F1 and 501F2, respectively. Step S54 includes sub-steps S541 to S542: Sub-step S541: Form gate dielectric layers 504O and 505O, respectively covering the top and sidewalls of fin structures 501F1 and 501F2; and Sub-step S542: Form gate electrodes 504S and 505S, respectively covering the gate dielectric layers 504O and 505O.

[0083] Please refer to step S51: Define multiple fin structures 501F1 and 501F2 in the semiconductor substrate 501. Each fin structure 501F1 and 501F2 is surrounded by a fin spacer wall 507. Figure 5A(1) shows a top view of the process structure after the fin structures 501F1 and 501F2 are defined in the semiconductor substrate 501; Figure 5A(2) is a cross-sectional view of the structure drawn along the tangent C5A1 shown in Figure 5A(1); Figure 5A(3) is a cross-sectional view of the structure drawn along the tangent C5A2 shown in Figure 5A(1). Step S51, which defines multiple fin structures 501F1 and 501F2, includes sub-steps S511 to S516:

[0084] Please refer to sub-step S511: A portion of the semiconductor substrate 501 is removed using a patterned pad dielectric layer 510 (including a patterned pad silicon oxide layer 510A and a patterned pad silicon nitride layer 510B) as an etching mask, thereby defining fin structures 501F1 and 501F2 in the semiconductor substrate 501. In some embodiments, the distance between two adjacent fin structures 501F1 and 501F2 can be between about 30 nanometers and 50 nanometers. The thickness of each fin structure 501F1 and 501F2 is between about 3 nanometers and 10 nanometers, for example, 5 nanometers.

[0085] Please refer to substep S512: Forming shallow trench isolation (STI) regions 508 around fin structures 501F1 and 501F2. In some embodiments of this specification, this includes depositing silicon oxide material to completely fill the trench 501T, followed by etching back, so that the remaining silicon oxide material in the trench 501T can be used as shallow trench isolation (STI) regions 508, surrounding fin structures 501F1 and 501F2. Please refer to substep S513: Performing an etching back process to remove a portion of the shallow trench isolation (STI) regions 508, thereby exposing the sidewalls of fin structures 501F1 and 501F2.

[0086] Then, referring to sub-step S514: a thermal oxidation process is performed to form silicon oxide spacer walls 507A on the sidewalls of fin structures 501F1 and 501F2. Referring to sub-step S515: a silicon nitride deposition process is performed to form silicon nitride spacer walls 507B on silicon oxide spacer walls 507A. Referring to sub-step S516: an amorphous silicon spacer wall 507C (as a sacrificial spacer wall) is formed on silicon nitride spacer walls 507B. In some embodiments of this specification, forming the amorphous silicon spacer 507C includes the following steps: first, depositing amorphous silicon to cover the fin spacer walls 507, the shallow trench isolation (STI) region 508, and the fin structures 501F1 and 501F2; then performing an isotropic etching process to remove a portion of the amorphous silicon, leaving another portion of the amorphous silicon located on the sidewalls of the silicon nitride spacer wall 507B. The thickness of each amorphous silicon interstitial wall 307C is between approximately 5 nanometers and 10 nanometers.

[0087] Please refer to step S52: Remove a portion of the shallow trench isolation (STI) region 508 not covered by the fin spacer walls 507 (including silicon oxide spacer walls 507A, silicon nitride spacer walls 507B, and amorphous silicon spacer walls 507C), thereby exposing a portion of the semiconductor substrate 501 located below the removed portion of the shallow trench isolation (STI) region 508. Figure 5B(1) is a top view of the process structure after removing a portion of the shallow trench isolation region 508 not covered by the fin spacer walls 507; Figure 5B(2) is a cross-sectional view of the structure drawn along the tangent C5B1 shown in Figure 5B(1); Figure 5B(3) is a cross-sectional view of the structure drawn along the tangent C5B2 shown in Figure 5B(1).

[0088] In this embodiment, a portion of the semiconductor substrate 501 located below the shallow trench isolation (STI) region 508 of the removed portion may also be removed, such that the top surface of the remaining portion of the semiconductor substrate 501 is lower than the bottom of the remaining portion of the shallow trench isolation (STI) region 508.

[0089] Please refer to step S53: Define a gate opening 502 in the dielectric capping layer 509 covering the fin structures 501F1 and 501F2 and the shallow trench isolation (STI) region 508. A portion of the sidewalls of the fin structures 501F1 and 501F2 are exposed from the corresponding gate opening 502. Step S52 includes sub-steps S531 to S534:

[0090] Please refer to sub-step S531: forming a dielectric insertion layer 511 to surround the sidewalls of fin structures 501F1 and 501F2; then refer to sub-step S532: performing a silicon oxide deposition process to form a dielectric capping layer 509 on fin structures 501F1 and 501F2 and dielectric insertion layer 511. Figure 5C(1) is a top view of the process structure after the formation of dielectric insertion layer 511 and dielectric capping layer 509; Figure 5C(2) is a cross-sectional view of the structure drawn along tangent C5C1 shown in Figure 5C(1); Figure 5C(3) is a cross-sectional view of the structure drawn along tangent C5C2 shown in Figure 5C(1).

[0091] In some embodiments of the present invention, the material constituting the dielectric insertion layer 511 may be different from the material constituting the dielectric capping layer 509. In this embodiment, the dielectric insertion layer 511 is formed by a low dielectric constant (k) dielectric material (e.g., hydrogenated silicon carbide (SiCOH)) deposition process and fills the trench 501T. The deposited low dielectric constant (k) dielectric material can be planarized by chemical mechanical polishing (CMP) technology. Then, the pad silicon nitride layer 510B, silicon nitride spacer 507B, and amorphous silicon spacer 507C are used as etch stop layers for etching back. Thus, the pad silicon nitride layer 510B, silicon nitride spacer 507B, and amorphous silicon spacer 507C can be exposed from the partially filled trench 501T.

[0092] Please refer to sub-step S532: Perform a silicon oxide deposition process to form a dielectric capping layer 509 comprising silicon dioxide to fill the trench 501T. Then, perform a planarization process (e.g., CMP) to make the bottom height of the dielectric insertion layer 511 (SiCOH) lower than the bottom height of the remaining portion of the shallow trench isolation (STI) region 508. Since the dielectric constant of the dielectric insertion layer 511 (SiCOH) is lower than the dielectric constant of the shallow trench isolation (STI) region 508, the coupling effect between the two gate structures 504 and 506 can be improved (as shown in the figure below).

[0093] Please refer to sub-step S533: Perform a patterning process to remove a portion of the dielectric capping layer 509, thereby defining the gate opening 502. In some embodiments, a patterned photoresist layer (not shown) is first formed on the dielectric capping layer 509 to expose a portion of the dielectric capping layer 509 covering the fin structures 501F1 and 501F2. Then, an etching process is performed to remove the exposed portion of the dielectric capping layer 509, thereby defining the gate opening 502 in the dielectric capping layer 509.

[0094] Please refer to sub-step S534: Remove the amorphous silicon spacer 507C, silicon nitride spacer 507B, and silicon oxide spacer 507A, so that a portion of the fin structures 501F1 and 501F2 are exposed from the gate opening 502. In this embodiment, after defining the gate opening 502 in the dielectric capping layer 509, another etching process is performed to remove the amorphous silicon spacer 507C that is not covered by the patterned photoresist layer from the gate opening 502.

[0095] Next, another etching process is performed to remove the silicon nitride spacer wall 507B and a portion of the patterned pad silicon nitride layer 510B exposed from the gate opening 502. After stripping the patterned photoresist layer, the silicon oxide spacer wall 507A and a portion of the patterned pad silicon oxide layer 510A exposed from the gate opening 502 are removed by another etching process to expose the top and sidewalls of the fin structures 501F1 and 501F2. Figure 5D(1) is a top view of the process structure after the fin structures 501F1 and 501F2 are partially exposed from the gate opening 502; Figure 5D(2) is a cross-sectional view of the structure drawn along the tangent C5D1 shown in Figure 5D(1); Figure 5D(3) is a cross-sectional view of the structure drawn along the tangent C5D2 shown in Figure 5D(1).

[0096] Please refer to step S54: form gate structures 504 and 505 on fin structures 501F1 and 501F2 respectively. Figure 5E(1) is a top view of the process structure after forming gate structures 504 and 505; Figure 5E(2) is a cross-sectional view of the structure drawn along the tangent C5E1 shown in Figure 5E(1); and Figure 5E(3) is a cross-sectional view of the structure drawn along the tangent C5E2 shown in Figure 5E(1).

[0097] Step S54, forming gate structures 504 and 505, includes sub-steps S541 to S542: Referring to sub-step S541, gate dielectric layers 504O and 505O are formed, respectively covering the top and sidewalls of fin structures 501F1 and 501F2. In some embodiments of the invention, gate dielectric layers 504O and 505O are formed using a silicon oxide deposition process. Next, referring to sub-step S542, gate electrodes 504S and 505S are formed, respectively covering gate dielectric layers 504O and 505O. In some embodiments of this specification, gate electrodes 504S and 505S are formed from polycrystalline silicon or metal. After forming gate structures 504 and 505, the dielectric capping layer 509 is removed, and then the source / drain regions are formed as described above.

[0098] Compared to Example 2, in this example, the bottom height of the dielectric insertion layer 511 (SiCOH) between the two gate structures 504 and 505 is lower than the bottom height of the shallow trench isolation (STI) region 508. Since the dielectric constant of the dielectric insertion layer 511 (SiCOH) is lower than the dielectric constant of the shallow trench isolation (STI) region 508, the coupling effect between the two gate structures 504 and 505 can be improved.

[0099] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0100] 5: Crystal gate structure 11: Source Region 12: Dublin Zone 13: Lightly doped drain region 20: Semiconductor components 30: Semiconductor components 40: Semiconductor components 50: Semiconductor components 201: Semiconductor substrate 201F1: Fin Structure 201F2: Fin Structure 201T: Trench 202: Gate Opening 203: Epitaxial Semiconductor Materials 204: Gate structure 204O: Gate dielectric layer 204S: Gate electrode 205: Gate structure 205O: Gate dielectric layer 205S: Gate electrode 207: Fin spacer wall 207A: Silicon oxide interstitial wall 207B: Silicon nitride interstitial wall 208: Shallow Ditch Isolation Zone 209: Dielectric capping layer 210: Pad dielectric layer 210A: Silicon oxide pad 210B: Silicon nitride pad 211: Dielectric Insertion Layer 212: Source Region 212A: Lightly doped drain region 212B: N+ Semiconductor Region 212C: Landing solder pad 213: Duji Zone 213A: Lightly doped drain region 213B: N+ Semiconductor Region 213C: Falling solder pad 215: Localized Isolation Zone 222: Source Region 222A: Lightly doped drain region 222B: N+ Semiconductor Region 222C: Landing solder pad 223: Drainage Zone 223A: Lightly doped drain region 223B: N+ Semiconductor Region 223C: Landing solder pad 225: Localized Isolation Zone 301: Semiconductor substrate 301T: Groove 302: Gate Opening 304: Gate structure 304O: Gate dielectric layer 304S: Gate electrode 305: Gate structure 305O: Gate dielectric layer 305S: Gate electrode 301F1: Fin Structure 301F2: Fin structure 307: Fin spacer wall 307A: Silicon oxide interstitial wall 307B: Silicon nitride interstitial wall 308: Shallow Ditch Isolation Zone 309: Dielectric capping layer 310: Pad dielectric layer 310A: Silicon oxide layer 310B: Silicon nitride pad 311: Dielectric Insertion Layer 312: Source Region 322: Source Region 313: Duji Zone 323: Drainage Zone 401: Semiconductor substrate 401T: Groove 402: Gate Opening 403: Epitaxial Semiconductor Material 404: Gate structure 404O: Gate dielectric layer 404S: Gate electrode 405: Gate structure 405O: Gate dielectric layer 405S: Gate electrode 401F1: Fin Structure 401F2: Fin structure 407: Fin spacer wall 407A: Silicon oxide interstitial wall 407B: Silicon nitride interstitial wall 408: Shallow Ditch Isolation Zone 409: Dielectric capping layer 410: Pad dielectric layer 410A: Silicon oxide pad 410B: Silicon nitride pad 411: Dielectric Insertion Layer 501: Semiconductor substrate 501T: Groove 502: Gate Opening 504: Gate structure 504O: Gate dielectric layer 504S: Gate electrode 505: Gate structure 505O: Gate dielectric layer 505S: Gate electrode 501F1: Fin Structure 501F2: Fin Structure 507: Fin spacer wall 507A: Silicon oxide interstitial wall 507B: Silicon nitride interstitial wall 508: Shallow Ditch Isolation Zone 509: Dielectric capping layer 510: Pad dielectric layer 510A: Silicon oxide layer 510B: Silicon nitride pad 511: Dielectric Insertion Layer T21: MOS transistor T22: MOS transistor T31: MOS transistor T32: MOS transistor T41: MOS transistor T42: MOS transistor T51: MOS transistor T52: MOS transistor D2: Distance D4: Distance C2A1: Tangent C2A2: Tangent C2B1: Tangent C2B2: Tangent C2C1: Tangent C2C2: Tangent C2D1: Tangent C2E1: Tangent C2F1: Tangent C2F2: Tangent C3A1: Tangent C3A2: Tangent C3B1: Tangent C3B2: Tangent C3C1: Tangent C3C2: Tangent C3D1: Tangent C3D2: Tangent C4A1: Tangent C4A2: Tangent C4B1: Tangent C4B2: Tangent C4C1: Tangent C4C2: Tangent C4D1: Tangent C4E1: Tangent C4F1: Tangent C4F2: Tangent C4G1: Tangent C4G2: Tangent C5A1: Tangent C5A2: Tangent C5B1: Tangent C5B2: Tangent C5C1: Tangent C5C2: Tangent C5D1: Tangent C5D2: Tangent C5E1: Tangent C5E2: Tangent P2: Spacing

[0101] none.

Claims

1. A method for manufacturing a metal-oxide-semiconductor (MOS) transistor structure, comprising: defining a first fin structure and a second fin structure adjacent to the first fin structure in a semiconductor substrate, wherein a shallow trench isolation (STI) region is provided between the first fin structure and the second fin structure; a first sacrificial spacer is disposed on a sidewall of the first fin structure, and the first sacrificial spacer does not cover a top of the first fin structure; a second sacrificial spacer is formed along a sidewall of the second fin structure, and the second sacrificial spacer does not cover a top of the second fin structure, wherein a gap exists between the first sacrificial spacer and the second sacrificial spacer; and an inserting dielectric layer is formed to fill the gap between the first sacrificial spacer and the second sacrificial spacer. Remove the first sacrificial spacer wall and the second sacrificial spacer wall; and form two gate structures above the first fin structure and the second fin structure respectively, so that the two gate structures are separated from each other by the dielectric insertion layer.

2. The method for manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 1, wherein the first sacrificial spacer and the second sacrificial spacer comprise an epitaxial semiconductor material selectively grown on the sidewalls of the first fin structure and the second fin structure as a substrate.

3. The method of manufacturing a metal-oxide-semiconductor transistor structure as described in claim 2 further includes: forming a capping dielectric layer covering the first fin structure and the second fin structure; and defining a gate opening in the capping dielectric layer such that the sidewalls of the first fin structure and the second fin structure are partially exposed from the gate opening.

4. The method of manufacturing a metal-oxide-semiconductor transistor structure as described in claim 3 further includes: forming a fin spacer around the sidewalls of the first fin structure and the second fin structure before forming the dielectric capping layer; and performing at least one etching process to remove the fin spacer located in the gate opening before forming the first sacrificial spacer and the second sacrificial spacer, so that the sidewalls of the first fin structure and the second fin structure are partially exposed.

5. A method for manufacturing a metal-oxide-semiconductor transistor structure as described in claim 3, wherein the material constituting the dielectric intercalation layer is different from the material constituting the dielectric capping layer.

6. The method for manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 3, further comprising, after forming the epitaxial semiconductor material and before forming the dielectric intercalation layer to fill the gate opening, deepening the gate opening to expose the semiconductor substrate.

7. A method for manufacturing a metal-oxide-semiconductor transistor structure as described in claim 6, wherein a portion of the semiconductor substrate is removed during the process of deepening the gate opening.

8. The method for manufacturing a metal-oxide-semiconductor transistor structure as described in claim 6, wherein while deepening the gate opening, a portion of the shallow trench isolation region is removed, and another portion of the shallow trench isolation region located below the epitaxial semiconductor material remains.

9. A method for manufacturing a metal-oxide-semiconductor transistor structure as described in claim 8, wherein a bottom of the dielectric intercalation layer is lower than a bottom of the other portion of the shallow trench isolation region.

10. A method for manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 1, wherein a dielectric constant of the dielectric intercalation layer is lower than a dielectric constant of silicon dioxide (SiO2).

11. A method for manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 1, wherein the first sacrificial spacer wall and the second sacrificial spacer wall comprise amorphous silicon covering the sidewalls of the first fin structure and the second fin structure.

12. A method of manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 11, further comprising, prior to forming the first sacrificial spacer wall and the second sacrificial spacer wall: forming a fin spacer wall to surround the sidewalls of the first fin structure and the second fin structure.

13. The method of manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 11, further comprising: forming a dielectric capping layer to cover the first fin structure, the second fin structure, the first sacrificial spacer wall, the second sacrificial spacer wall, and the dielectric insertion layer; and defining a gate opening in the dielectric capping layer such that the sidewalls of the first fin structure and the second fin structure are partially exposed from the gate opening.

14. The method of manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 11, further comprising, before removing the first sacrificial spacer wall and the second sacrificial spacer wall: removing a portion of the shallow trench isolation region not covered by the first sacrificial spacer wall and the second sacrificial spacer wall, thereby exposing a portion of the semiconductor substrate.

15. A method of manufacturing a metal-oxide-semiconductor transistor structure as claimed in claim 14, wherein a bottom of the dielectric intercalation layer is lower than a bottom of another portion of the shallow trench isolation region located below the first sacrificial spacer wall and the second sacrificial spacer wall.

16. A metal-oxide-semiconductor transistor structure, comprising: a first active region and a second active region adjacent to the first active region, formed in a semiconductor substrate, wherein a shallow trench isolation region is located between the first active region and the second active region; a spacer wall surrounding and contacting a plurality of sidewalls of the first active region and the second active region; a dielectric intercalation layer disposed between the first active region and the second active region; a first trench surrounding the first active region or located above the first active region, wherein the first trench is adjacent to one side of the dielectric intercalation layer; and a second trench surrounding the second active region or located above the second active region, wherein the second trench is adjacent to the other side of the dielectric intercalation layer. A first gate structure is located above the first active region and within the first trench, wherein the first gate structure covers a first portion of the shallow trench isolation region; and a second gate structure is located above the second active region and within the second trench, wherein the second gate structure covers a second portion of the shallow trench isolation region; and a distance between the first gate structure and the second gate structure is determined by the dielectric insertion layer.

17. The metal-oxide-semiconductor transistor structure as described in claim 16, wherein a width between the first active region and the second active region at the dielectric insertion layer is not defined by a photolithographic process.

18. A metal-oxide-semiconductor transistor structure, comprising: a first fin structure and a second fin structure adjacent to the first fin structure, wherein a shallow trench isolation region is located between the first fin structure and the second fin structure; a dielectric intercalation layer disposed between the first fin structure and the second fin structure; a first trench surrounding the first fin structure or located above the first fin structure, wherein the first trench is adjacent to one side of the dielectric intercalation layer; and a second trench surrounding the second fin structure or located above the second fin structure, wherein the second trench is adjacent to the other side of the dielectric intercalation layer. A first gate structure is located above the first fin structure and within the first trench, wherein the first gate structure covers a first portion of the shallow trench isolation region; and a second gate structure is located above the second fin structure and within the second trench, wherein the second gate structure covers a second portion of the shallow trench isolation region; a bottom of the dielectric insertion layer is lower than a bottom of a first portion of the shallow trench isolation region or a bottom of a second portion of the shallow trench isolation region.

19. The metal-oxide-semiconductor transistor structure of claim 18 further includes: a first source region and a first drain region, respectively electrically contacted with a first channel located in the first fin structure; and a second source region and a second drain region, respectively electrically contacted with a second channel located in the second fin structure.

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