Hammerhead bottom electrode in memory devices

Abstract

Forming planar resistive memory devices on metal vias and flush with the surrounding insulating material can transfer dish-shaped or other surface defects from the via surface into the layers of the memory cells, reducing device performance. A bottom electrode with a "hammerhead" shape can be formed by leaving the top portion of the metal layer on the insulating layer, rather than polishing it to the insulating layer. The top portion of the electrode may be oxidized to form the switching layer of the memory cell itself. This hammerhead electrode may have a substantially flat surface to allow for the formation of planar memory cell layers, resulting in better memory performance and heat dissipation. When oxidized, the hammerhead electrode also eliminates the metal / metal oxide interface between the bottom electrode and the switching material.

Description

Technical Field

[0001] This application claims the benefit and priority of U.S. nonprovisional application No. 18 / 606,414, filed on March 15, 2024, entitled "Hammer-shaped bottom electrode in a memory device," the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] This technology relates to semiconductor systems, processes, and devices. More specifically, this technology relates to processes and systems for forming bottom electrodes in memory devices. Prior Technology

[0003] The realization of integrated circuits relies on the processing of material layers with fine patterns on the surface of a substrate. Creating patterned material on a substrate requires controlling the methods of material formation and removal. As device sizes continue to shrink, features within integrated circuits may become smaller, aspect ratios of structures may increase, and maintaining the dimensions of these structures during processing operations may become challenging. For example, resistive random access memory (RRAM), also known as resistive RAM or ReRAM, is a non-volatile memory technology that stores data by changing the resistance of a material. ReRAM stores data by storing various resistance values ​​in a stack of materials, typically composed of metal oxide layers. The resistance values ​​represent binary states, one corresponding to high resistance and the other to low resistance. By applying a voltage to the material, this binary state can be switched, changing it from a high-resistance state to a low-resistance state or vice versa. This ability to change the resistance state allows RRAM to store data reliably and efficiently. Summary of the Invention

[0004] In some embodiments, the memory device may include a metal plug having a through-hole surrounded by an insulating material and a top portion located above the insulating material and extending laterally beyond the width of the through-hole. The memory device may also include memory cells formed above the metal plug.

[0005] In some embodiments, the memory device may include a metal plug comprising a through-hole surrounded by an insulating material, and a top portion extending over the insulating material and laterally beyond the width of the through-hole. The top portion of the metal plug may be oxidized to form a metal-oxide switching region of the memory device. The memory device may also include a top electrode formed on the top portion of the metal plug.

[0006] In some embodiments, a method of forming a memory device may include forming a metal layer that fills features in an insulating layer to form a via, and the metal layer may extend beyond the top surface of the insulating layer. The method may also include partially removing a portion of the metal layer, wherein the remaining metal layer continues to cover the insulating layer. The method may further include forming one or more layers on or within the remaining metal layer to form a memory cell. The method further includes performing etching to form a memory device over the via, wherein the etching may extend below the top surface of the insulating layer.

[0007] In any embodiment, any and all of the following features may be implemented in any combination and are not limited thereto. The height of the via may be between about 50 nm and about 150 nm, and the width of the via may be between about 50 nm and about 150 nm. The top portion may extend laterally beyond the via width by about 50 nm to about 150 nm. The bottom surface of the via may be electrically connected to the underlying metal layer in the back end of line (BEOL) portion of the integrated circuit. The memory cell may include a resistive random access memory (ReRAM) cell, including a switching layer located between a bottom electrode and a top electrode. The bottom electrode of the memory cell may extend along the entire upper surface of the top portion of the metal plug. The via may have a first inclined sidewall oriented in a first direction, and the top portion of the metal plug may have a second inclined sidewall oriented in a second direction. The metal plug may not have an interface between the via and the top portion of the metal plug, and the metal-oxide switching region may form a continuous oxide material gradient on the top portion of the metal plug. The via may contain copper, tantalum, or titanium, while the top portion of the metal plug may contain copper oxide, tantalum oxide, or titanium oxide. The height of the top portion of the metal plug may be between approximately 5 nm and approximately 50 nm. The memory device may not have a bottom electrode between the metal-oxide switching region and the via. The etching process for forming the memory device may include a first etching process configured to stop at the remaining portion of the metal layer. The etching process for forming the memory device may include a second etching process configured to etch through the remaining metal layer and into the insulating material. The remaining metal layer may form a substantially flat surface, and there is no dish-shaped recess above the via after a chemical mechanical polishing (CMP) process. Forming one or more layers to constitute a memory cell may include oxidizing the top portion of the metal layer on or within the metal layer to form the metal-oxide switching region of the memory device, wherein the memory device may not contain a bottom electrode between the metal-oxide switching region and the via; and forming a top electrode on the top portion of the metal layer. Forming one or more layers on or within a metal layer to form a memory cell may include forming a bottom electrode layer on the remaining metal layer; forming a metal-oxide switching layer on the bottom electrode layer; and forming a top electrode layer on the metal-oxide switching layer. Performing etching to form a memory device over a via may include forming a metal plug including the via and its top portion, the top portion extending over an insulating material and laterally beyond the width of the via. Performing etching to form a memory device over a via may include forming a metal plug with a hammerhead shape. Simple Explanation of the Diagram

[0008] A further understanding of the nature and advantages of the various embodiments can be obtained by referring to the remainder of the specification and illustrations, wherein the same element symbols are used repeatedly in multiple illustrations to refer to similar elements. In some cases, a sublabel is associated with an element symbol to indicate one of a plurality of similar elements. When an element symbol is referred to without a sublabel, it is intended to refer to all of these plurality of similar elements.

[0009] Figure 1 shows a top plan view of one embodiment of a processing system that includes deposition, etching, baking, and curing chambers, which may be included or configured according to certain embodiments of the present technology.

[0010] Figures 2A-2E illustrate the process of forming a memory device according to certain embodiments.

[0011] Figure 3 illustrates a flowchart of a method for forming a memory device according to certain embodiments.

[0012] Figures 4A-4D illustrate the process of forming a memory device with hammerhead electrodes according to certain embodiments.

[0013] Figures 5A-5D illustrate the process of forming a memory device with an oxide hammerhead electrode according to certain embodiments.

[0014] Figure 6 illustrates a photograph of a hammerhead electrode sample according to certain embodiments. Implementation

[0015] Forming planar resistive memory devices on metal vias, when parallel to the surrounding insulating material, can transfer dish-like defects or other surface irregularities from the via surface to the layers of the memory cell, reducing device performance. A "hammerhead" shaped bottom electrode can be formed by leaving the top portion of a metal layer on the insulating layer, rather than grinding it down. This top portion of the electrode can be oxidized to form the switching layer of the memory cell itself. This hammerhead electrode can have a substantially flat surface, facilitating the formation of planar memory cell layers, thereby improving memory performance and heat dissipation. Oxidation also eliminates the metal / metal oxide interface between the bottom electrode and the switching material.

[0016] Emerging non-volatile memories, such as resistive random access memory (ReRAM), are becoming increasingly attractive platforms for embedded applications. For example, several high-performance memories embedded in copper-based back-end process (BEOL) layers have been demonstrated for various applications, including artificial intelligence, image processing, and pattern recognition. Typically, this type of memory structure uses planar cells. However, the performance of planar cells utilizing ultrathin films is extremely sensitive to the flatness of the top and bottom electrodes, which can significantly impact the performance, variability, and yield loss of the memory device.

[0017] Specifically, memory arrays can be fabricated by forming resistive random access memory (ReRAM) cells with planar memory elements. For example, a ReRAM cell can be formed as a capacitor located between two metal layers. In other words, the memory cell comprises a planar element located between two metal plugs. These metal plugs can be made of any conductive material, such as copper, tungsten, cobalt, etc. The memory cell can be placed on a bottom metal plug formed as an oxide layer to connect the bottom electrode of the memory cell to the underlying interconnect layer (e.g., M3, M4, etc.). The plug can be formed by etching features or vias in the oxide layer. These features can then be filled with metal and planarized using a chemical mechanical polishing (CMP) process. Unfortunately, this process inevitably leaves some dish-shaped or recessed traces in the metal vias due to the CMP process. These surface irregularities in the vias can adversely affect the planarity of the memory cell and the bottom electrode formed thereon. Therefore, this can lead to non-uniform electric fields within the cell dielectric and other variations in performance.

[0018] The embodiments described in this specification address these and other technical problems by using specially configured hammer-bottom electrodes to reduce inhomogeneities within resistive random access memory (ReRAM). For example, the hammer-bottom electrode may include a metal plug (e.g., tungsten, nickel, cobalt, copper, etc.) with its upper portion protruding from the surface of the oxide layer to form a flat bottom electrode for ReRAM bit cells. In addition to improving the flatness of the bottom electrode in the memory array, this process eliminates the need to polish three different materials, a requirement of previous solutions. For example, prior art requires polishing bulk metal material, tantalum nitride / titanium nitride substrate, and the surrounding oxide layer. In contrast, these embodiments only require the removal of the bulk metal material. These techniques are also insensitive to feature pattern size and pattern density. In some embodiments, the hammer-bottom electrode can be used to form a seamless metal / metal-oxide interface (e.g., tungsten / tungsten oxide) by partially oxidizing the metal layer using O2 / O3 plasma. Metal oxides such as titanium oxide have optimized properties as resistive switching materials. This seamless metal / metal-oxide junction, with the metal as the bottom electrode and the metal oxide as the active memory layer, is immune to unwanted defects and traps at the metal / oxide interface, representing a significant advantage over the deposited bilayer stacks used in previous designs.

[0019] While subsequent disclosures will periodically identify specific etching and deposition processes utilizing the disclosed techniques, it will be readily understood that these systems and methods are equally applicable to a variety of other processes that may occur in the described chambers. Therefore, this technique should not be considered limited to use with the described etching or deposition processes. This disclosure will discuss one possible system that can be used with the present technology, and then describe a sample sequence of processes of systems and methods or operations according to certain embodiments of the present technology. It should be understood that this technique is not limited to the described apparatus, and the processes discussed can be performed in any number of processing chambers and systems.

[0020] Figure 1 shows a top view of one embodiment of a processing system 100 having deposition, etching, polishing, baking, and curing chambers. In the figure, a pair of front-opening wafer cassettes 102 supply substrates of various sizes, which are received by robotic arms 104 and placed into a low-pressure holding region 106 before being placed into substrate processing chambers 108a-f in series sections 109a-c. A second robotic arm 110 can be used to transport substrate wafers from the holding region 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform a variety of substrate processing operations, including the dry etching process described herein, as well as cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processes.

[0021] The substrate processing chambers 108a-f may include one or more system elements for depositing, annealing, curing, and / or etching material films on a substrate or wafer. In one configuration, two pairs of processing chambers, such as 108c-d and 108e-f, may be used for depositing material on the substrate, while a third pair of processing chambers, such as 108a-b, may be used for curing, annealing, or processing the deposited film. In another configuration, all three pairs of chambers, such as 108a-f, may be configured to simultaneously deposit and cure films on the substrate. Any one or more of the described processes may be performed in other chambers separate from the illustrated manufacturing system. System 100 takes into account other configurations of chambers for material film deposition, etching, annealing, and curing. Furthermore, other numbers of processing systems may be used with this technology, which may contain chambers for performing any specific operation. In some embodiments, the chamber system may provide access to multiple processing chambers, such as the aforementioned holding and transfer areas, while maintaining a vacuum environment, so that operations can be performed in multiple chambers while maintaining a specific vacuum environment between individual procedures.

[0022] System 100, or more specifically, the chamber incorporated in system 100 or other processing systems, can be used to produce structures according to certain embodiments of the present technology. For example, system 100 can be used to perform deposition processes, chemical mechanical polishing (CMP) processes, etching processes, etc., to form memory devices or a series of memory devices, including resistive random access memory (ReRAM) devices. Although a ReRAM memory cell is used as an example in this disclosure, the hammer-bottom electrode described below can also be incorporated into any other memory technology to improve performance and reduce device variability. For example, such a hammer-bottom electrode can also be used in FRAM devices, MRAM devices, etc.

[0023] Figures 2A-2E illustrate a process for forming a memory device according to certain embodiments. As shown below, this method uses a chemical mechanical polishing (CMP) process to remove metal layers down to oxide or insulating layers. This can cause surface defects to propagate into other layers of the memory cell. This can, in turn, lead to early switching and other inhomogeneities during memory device operation.

[0024] Figure 2A illustrates the formation of two metal plugs 208 in an insulating layer 202 for interface with individual memory cells. The insulating layer 202 may be formed over a metal layer 201. For example, in a BEOL process, the metal layer 201 may represent a BEOL metal layer, such as M3, M4, etc. The insulating layer 202 may be formed of an oxide (e.g., silicon oxide) or any other electrical insulator. Features or vias may be formed in the insulating layer 202 to expose the underlying metal layer 201. These features may fill the metal layer 206 to form the metal plugs 208, which may serve as vias or electrical interfaces between the metal layer 201 and the bottom electrode of the memory cell.

[0025] Before forming the metal plug 208, a liner 204 may be integrally formed on the insulating layer 202. In some embodiments, the liner 204 may comprise a double-layer liner. The first layer of the liner may comprise a material such as tantalum nitride to isolate the metal layer 201 from the metal plug 208. For example, when the metal layer 201 and the metal plug 208 use different metals (e.g., tungsten and copper), the tantalum nitride layer can prevent migration between the two metals. Furthermore, the second layer of the liner 204 may comprise a titanium nitride layer. These layers of the liner 204 may be formed using a chemical vapor deposition (CVD) process or any other suitable process. In some embodiments, the liner 204 may extend integrally along the sidewalls and bottom of features or holes in the insulating layer 202. The liner 204 may also integrally cover the top surface between the features in the insulating layer 202, as shown in FIG2A.

[0026] After the substrate 204 is formed, a metal layer 206 can be formed on the insulating layer 202. For example, a conductive metal (e.g., tantalum, titanium, tungsten, copper, etc.) can be deposited on the insulating layer 202. The metal layer 206 can fill each feature to form a metal plug 208. Furthermore, the metal layer 206 can cover the top surface of the insulating layer 202. For example, the metal layer 206 can extend more than 100 nm beyond the top surface of the insulating layer 202.

[0027] Figure 2B illustrates a process for large-volume removal of a portion of metal layer 206 according to certain embodiments. For example, a chemical mechanical polishing (CMP) process may be used to remove most of metal layer 206, leaving the remainder of metal layer 210. The CMP process may be configured to rapidly remove the vast majority of metal layer 206 and may stop before the top surfaces of liner 204 and / or insulating layer 202 are exposed. The thickness of the remaining portion of metal layer 210 may be less than 100 nm, less than 50 nm, less than 25 nm, and / or other thicknesses depending on the embodiment. This process may remove more than 50%, more than 60%, more than 70%, more than 80%, more than 90%, and / or more than 90% of metal layer 206.

[0028] Figure 2C illustrates the removal of the remaining portion of metal layer 210 according to some embodiments. For example, a chemical mechanical polishing (CMP) process may be used to remove the remaining portion of metal layer 210. In some embodiments, this removal process may also remove a portion of the liner 204 covering the top surface of insulating layer 202. The CMP process may be slower or more tightly controlled than a large-volume CMP process used to remove the aforementioned metal layer 206. At this stage, the remaining portion of metal layer 210 (and liner 204) above insulating layer 202 is typically completely removed to separate the metal plug 208.

[0029] In some embodiments, this CMP process may use endpoint detection technology to determine when the remainder of metal layer 210 is removed. The CMP process may detect when the top surface of insulating layer 202 has been exposed. As shown in FIG2C, the CMP process removing the remainder of metal layer 210 may leave surface irregularities in metal plug 208. For example, the CMP process may leave "dents" or "disc-shaped" anomalies 214 in metal plug 208. These surface irregularities are primarily caused by the simultaneous polishing of multiple materials after the CMP process removes the remainder of metal layer 210. For example, dents may occur when the CMP process simultaneously polishes the top of metal plug 208 and the top surface of insulating layer 202. These anomalies 214 can be a significant problem, especially in areas with high feature density.

[0030] Figure 2D illustrates, according to some embodiments, the formation of a memory cell 216 above a metal plug 208. The memory cell 216 may be a relatively flat device formed of multiple layers 218. For example, the memory cell 216 may include a metal layer as part of a bottom electrode, a switching material for realizing the memory function, and another metal layer as part of a top electrode of the memory cell. The switching material may include different materials depending on the type of memory. For example, a ReRAM device may include a metal-oxide material as the switching material. These layers 218 may be formed on top of the metal plug, and these layers 218 may cover the metal plug 208 and the insulating layer 202.

[0031] Figure 2E illustrates the formation of individual memory cells 220 according to certain embodiments. An etching process can be used to isolate the individual memory cells 220 from each other and to position these individual memory cells 220 on corresponding metal plugs 208. For example, a mask pattern can be formed on layer 218 of the memory cells, and an etching process can be performed to remove layer 218 between the metal plugs 208. In some embodiments, the etching process may completely etch through layer 218 of the memory cells (e.g., by means of top and bottom electrode materials and switching materials). The etching process may also etch into insulating layer 202. This process forms and isolates the individual memory cells 220 from each other. Note that the bottom electrode of the memory cell 220 is electrically connected to the metal plug 208, which in turn is electrically connected to metal layer 201. Although not shown, the individual memory cells 220 may be part of a larger memory array formed on substrate 200. Furthermore, metal layer 201 may include metal lines for circuitry and routing, which provide individual connections for each metal plug 208.

[0032] Note that the surface irregularities (e.g., dish-shaped recesses) in the metal plug 208 are transferred to the layers of these individual memory cells 220 when the memory cells 220 are formed on the metal plug 280. These irregularities affect the performance of the individual memory cells 220 and may affect the overall yield of the substrate 200. Furthermore, the top surface of the metal plug 208 interfaces only with a portion of the bottom electrode of the individual memory cells 220. For example, the sides of the individual memory cells 220 extend beyond the outer diameter of the metal plug 208. This tends to cause current flow and heat to concentrate in the central portion of the individual memory cells 220, rather than being distributed across the bottom electrode.

[0033] The embodiments described herein address the issues of surface irregularities on the metal plug 208 and current / heat concentration at the center of the bottom electrode. Specifically, these embodiments form a metal plug with a "hammerhead" shape, providing a flat surface for the memory cell layers and interfaceing with the entire surface area of ​​the bottom electrode.

[0034] Figure 3 illustrates a flowchart of method 300 according to some embodiments for forming a memory device. The memory device may include a metal plug containing a through-hole or post, through a surrounding insulating material, and a top portion extending over the insulating material and laterally beyond the width of the through-hole. Figures 4A-D and 5A-D illustrate example structures that can be formed by this method 300. However, the structures shown in these figures are provided by way of example only and are not intended to be limiting.

[0035] Method 300 may include forming a metal layer (302). Figure 4A illustrates a structure 400, in which a metal layer 406 is filled in an insulating layer 402. The filled areas of these features may form vias 407. The metal layer 406 may extend beyond the top surface of the insulating layer 402. Structure 400 may also include a liner 404, such as the double-layer liner mentioned above. The vias 407 may extend into the underlying metal layer 401. Note that Figure 4A is similar to Figure 2A described above. Therefore, any features associated with Figure 2A may also apply to Figure 4A.

[0036] The method 300 may also include partially removing a portion (304) of the metal layer 406. As described above and in Figure 2B, a CMP process can be used to partially remove a portion of the metal layer 406. Figure 4B shows the case where a portion of the metal layer 406 has been removed. The remaining metal layer 410 may continue to cover the insulating layer 402. Compared to the process described in Figure 2C, some embodiments may leave the remaining portion of the metal layer 410 on the insulating layer 402. The CMP process may leave a substantially flat surface and no dish-shaped recesses will appear on the via 407 because the CMP process only polishes the metal layer 406. For example, since the CMP process is performed on a uniform layer of metal material and does not require exposing the insulating layer 402 and / or the liner 404, the CMP process does not require polishing two materials with different surface hardnesses simultaneously.

[0037] This method may include forming one or more layers on or within the remaining portion of metal layer 410 to form a memory cell (306). Figure 4C illustrates the formation of layer 418 of the memory cell. For example, forming layer 418 may include forming a bottom electrode layer on the remaining portion of metal layer 410, forming a metal-oxide switching layer on the bottom electrode layer, and forming a top electrode layer on the metal-oxide switching layer. In some embodiments, the formation of a separate bottom electrode layer may be omitted, and the top of the metal plug may serve entirely as the bottom electrode. An alternative method for forming the memory cell layers, as described in Figure 5C, is to oxidize the remaining portion of metal layer 410 to form a metal-oxide switching layer. Note that layer 418 of the memory cell is formed on a substantially flat surface of the remaining portion of metal layer 410. Therefore, this substantially flat topology is transferred to all layers 418 of the memory cell, thereby making these layers 418 substantially flat as well. This effectively prevents irregularities previously present on the metal plug 408 from causing corresponding irregularities in the memory cell.

[0038] The method may further include performing etching to form a memory device (308) over the via. Figure 4D illustrates how, according to some embodiments, the etching process forms a metal plug with a hammerhead shape. This etching process may include multiple etching steps. For example, a first etching step may be configured to etch through layer 418 of the memory cell and stop at the remainder of metal layer 410. A second etching step may be configured to etch through the remainder of metal layer 410 and into insulating layer 402. This etching step isolates the metal plug 408 and forms the individual memory cells 420.

[0039] For example, the height of the via portion of the metal plug 408 may be between about 50 nm and about 75 nm, about 75 nm and about 100 nm, about 100 nm and about 125 nm, about 125 nm and about 150 nm, about 150 nm and about 175 nm, about 175 nm and about 200 nm, etc. The height of the via may include any combination of the ranges described above (e.g., between about 50 nm and about 150 nm). The height of the via may also include any single value contained in any combination of the ranges described above (e.g., about 100 nm).

[0040] For example, the width of a via may be between about 50 nm and about 75 nm, about 75 nm and about 100 nm, about 100 nm and about 125 nm, about 125 nm and about 150 nm, about 150 nm and about 175 nm, about 175 nm and about 200 nm, etc. The width of a via can include any combination of the ranges described above (e.g., between about 50 nm and about 150 nm). The width of a via can also include any single value contained in any combination of the ranges described above (e.g., about 100 nm).

[0041] The hammerhead shape of the metal plug 408 may include a through-hole portion running vertically through the insulating layer 402, and a top portion of the metal plug 408 located above the insulating material and extending laterally beyond the width of the through-hole portion. For example, the overhang, i.e., the amount by which the top portion of the metal plug extends laterally across the width of the through-hole, may be between about 10 nm and about 20 nm, about 20 nm and about 30 nm, about 30 nm and about 40 nm, about 40 nm and about 50 nm, about 50 nm and about 60 nm, about 60 nm and about 70 nm, about 70 nm and about 80 nm, about 80 nm and about 90 nm, about 90 nm and about 100 nm, and so on. The overhang of the top portion of the metal plug may include any combination of the above ranges (e.g., between about 25 nm and about 50 nm). The width of the through-hole may also include any single value within any of the ranges previously described (e.g., about 75 nm).

[0042] The length of the overhang can also be measured relative to the width or critical dimension (CD) of the through-hole. For example, the overhang may be between approximately 10% and approximately 20%, approximately 20% and 30%, approximately 30% and 40%, approximately 40% and 50%, approximately 50% and 60%, approximately 60% and 70%, etc., of the through-hole CD. The overhang of the top portion of the metal plug may include any combination of the above ranges (e.g., between approximately 30% and approximately 50%). The width of the through-hole may also include any single value within any of the ranges described above (e.g., approximately 45%).

[0043] In some embodiments, the length of the overhang may be determined by the height of the remaining metal layer 410 after the main portion of metal layer 406 has been removed by a chemical mechanical polishing (CMP) process. For example, the etching process may leave sloping sidewalls as shown in FIG4D. The size of the top electrode of memory cell 420 may be determined by the size of the corresponding opening in the masking layer during the etching process. Therefore, the width of the bottom electrode, the overall width of the top portion of the metal plug, and the length of the overhang may be determined by the overall height of the device. In other words, as the device height increases, the etching angle will leave a wider memory device substrate area. The sidewall angle of the overhang may be between about 3° and about 5°, about 5° and about 8°, about 8° and about 10°, about 10° and about 12°, about 12° and about 15°, about 15° and about 20°, about 20° and about 25°, about 25° and about 35°, etc. In some embodiments, the overall height of the memory cell may be limited by the process height between metal layers in the BEOL process. For example, the height of the top portion of the metal plug 408 and the layer 418 of the memory device may be limited to a standard height, such as 200 nm. This may therefore limit the width of the top portion of the metal plug 408.

[0044] As shown in Figure 4D, the sidewalls of the through-hole portion of the metal plug 408 may also have inclined sidewalls. The angle of the sidewalls of the through-hole portion may be oriented in a first direction, which is approximately opposite to the angle of the top portion of the metal plug 408. For example, when measured from a 90° line perpendicular to the substrate or the underlying metal layer 401, the angle of the through-hole sidewalls may be between about 5° and about 30°, while the angle of the sidewalls of the top portion of the metal plug 408 may be between about -5° and about -30°.

[0045] As shown in Figure 4D, the top portion of the metal plug 408 may now be in full contact with the memory cell. For example, the top portion of the metal plug 408 may be electrically connected to the entire bottom surface of the bottom electrode (if present) in the memory cell layer 418. This may allow for a more uniform current distribution on the bottom electrode and enable more efficient heat dissipation than previous designs.

[0046] Returning to Figure 3, the formation of one or more layers of memory cells can be performed on the metal layer as described above. Alternatively, in some embodiments, one or more layers (306) of memory cells may be formed within the metal layer itself. For example, Figure 5A shows structure 500, in which the metal layer 506 fills features in the insulating layer 502. Figure 5A is similar to Figures 2A and 4A described above. Therefore, any descriptions related to Figures 2A and 4A may also apply to Figure 5A. As described above, a portion of the metal layer 506 may be partially removed using a chemical mechanical polishing (CMP) process. Figure 5B shows a case where a portion of the metal layer 506 has been removed. The remaining portion of the metal layer 510 may continue to cover the insulating layer 502 to form a substantially flat surface.

[0047] Figure 5C illustrates the process of forming a switching layer for memory cells in the remaining portion of metal layer 510. For example, an oxidation process may be performed on structure 500 using O2 / O3 plasma. This may cause the top portion of the metallic material in the metal layer to transform into a metal-oxide material. For example, when titanium is used as the remaining portion of metal layer 510, the oxidation process may form titanium oxide, which serves as the switching material in the memory cells.

[0048] In this configuration, the oxidized portion 511 of the metal layer 510 can serve as the switching region or layer of the memory cell, while the unoxidized portion of the metal layer 510 can serve as the bottom electrode of the memory cell. In some embodiments, the oxidation process may result in an oxidation gradient on the top portion of the remaining metal layer 510. This gradient may manifest as a continuous decrease in the concentration of the metal-oxide material until the metal material is no longer oxidized at a certain depth. Therefore, the memory cell may lack a separate interface between the metal-oxide and the metal material, which typically exists between the switching material and the bottom electrode. This seamless metal / metal-oxide interface, where the metal acts as the bottom electrode and the metal oxide acts as the active memory layer, avoids the undesirable defects and pitfalls that typically occur at metal / oxide interfaces. This is a significant advantage compared to the deposited bilayer stacks used in other designs.

[0049] Figure 5D illustrates the formation of the top electrode 522 and the result of the etching process performed to form individual memory elements 520. The top electrode 522 can be formed using a similar process to that described in Figures 4A-D above. This etching process may form individual memory elements 520 as described in Figure 4D above.

[0050] Figure 6 shows an example photograph of a hammer electrode according to some embodiments. This example shows a hammer electrode 608 with a vertical through-hole, the top portion of which extends over the insulating material 603 and laterally, or hangs over the width of the through-hole. The hanging portion 602 shows sloping sidewalls and its height relative to the rest of the memory device. Figure 6 also shows a double-layer liner 601 that may be present in some embodiments.

[0051] Layer 606 of the memory device is also shown. In this embodiment, the bottom electrode, switching material, and top electrode are separate layers within layer 606 of the memory device. As described above, some embodiments may omit the bottom electrode layer and / or form the switching material in the overhang portion 602 of the hammer assembly. The second through-hole 604 shows electrical contact with the top electrode of the memory device, thereby connecting the memory device to subsequent metal layers and interconnects.

[0052] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without these details or with the addition of other details.

[0053] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative structures, and equivalent solutions can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the technology, many well-known processes and elements have not been described. Therefore, the above description should not be considered as limiting the scope of the technology.

[0054] When a numerical range is provided, it should be understood that between the upper and lower limits of the range, in the smallest fraction of the lower limit unit, each intermediate value is explicitly disclosed unless the context explicitly indicates otherwise. Any narrower range between any stated or unstated interventional value and any other stated or interventional value within the range is also included. The upper and lower limits of these smaller ranges may be independently included or excluded from the range, and ranges not included in the smaller range, whether one, both, or neither, are also included in the technique, subject to any specific exclusions imposed by the range. When the range includes one or both limits, ranges excluding either or both inclusion limits are also included.

[0055] In this document and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly indicates otherwise. Thus, for example, to a person skilled in the art, a reference to “a pillar” includes multiple such pillars, a reference to “the layer” includes references to one or more layers and their equivalents, etc.

[0056] Furthermore, the terms "comprising," "containing," "having," and "including" as used in this specification and subsequent requests are intended to indicate the presence of the stated feature, integer, element, or operation, but do not preclude the presence or addition of one or more other features, integers, elements, operations, behaviors, or groups. The terms "about," "approximately," and / or "substantially" may refer to a deviation of no more than 10% of the nominal size or measurement of the stated value.

[0057] The above description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the description of the various embodiments above will provide a feasible disclosure for performing at least one embodiment. It should be understood that the function and arrangement of elements can be varied without departing from the spirit and scope of some of the embodiments described in the following claims.

[0058] The foregoing description provides specific details to provide a thorough understanding of the embodiments. However, it should be understood that embodiments may be implemented without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown in block diagram form to avoid obscuring the embodiments with unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may not be shown in excessive detail to avoid obscuring the embodiments.

[0059] Furthermore, it is worth noting that individual embodiments may be described as processes shown in the form of flowcharts, diagrams, data flow charts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. Moreover, the order of operations may be rearranged. When an operation of a process is completed, it terminates, but may include additional steps not shown in the diagram. A process may correspond to a method, function, program, subroutine, subroutines, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0060] The term "computer-readable media" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or transmitting instructions and / or data. A piece of code or executable machine instructions can represent a program, function, subroutine, routine, module, software package, class, or any combination of instructions, data structures, or program statements. A piece of code can be connected to another piece of code or hardware circuitry by passing and / or receiving information, data, parameters, or memory contents. Information, parameters, data, etc., can be passed, forwarded, or transmitted by any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0061] Furthermore, embodiments can be implemented using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments that perform the necessary tasks can be stored in a computer-readable medium. The processor can then perform the necessary tasks.

[0062] Furthermore, for illustrative purposes, these methods are described in a specific order. It should be understood that in other embodiments, the execution order of these methods may differ from that described. It should also be noted that the methods described above can be executed by hardware components or can be embodied in a sequence of executable machine instructions that can be used to drive a machine (e.g., a general-purpose or special-purpose processor or logic circuits programmed with instructions) to perform these methods. These executable machine instructions can be stored on one or more computer-readable media, such as CD-ROMs or other types of optical discs, floppy disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or other computer-readable media suitable for storing electronic instructions. Alternatively, these methods can be executed by a combination of hardware and software.

[0063] 100: Processing System 102: Front-opening wafer cassette 104: Robotic Arm 106: Low-pressure maintenance area 108a: Substrate processing chamber 108b: Substrate processing chamber 108c: Substrate processing chamber 108d: Substrate processing chamber 108e: Substrate processing chamber 108f: Substrate processing chamber 109a: Series section 109b: Series section 109c: Series section 110: Robotic Arm 200:Substrate 201: Metal layer 202: Insulation layer 204: Lining 206: Metal layer 208: Metal plug 210: Metal layer 214: Anomaly 216: Memory Unit 218: Floor 220: Memory Unit 300: Method 302: Steps 304: Steps 306: Steps 308: Steps 400: Structure 401: Metallic layer 402: Insulation layer 404: Lining 406: Metallic layer 407: Through hole 408: Metal plug 410: Metal layer 418: Layers of memory units 420: Memory Unit 500: Structure 502: Insulation layer 506: Metallic layer 510: Metal layer 511: Oxidized portion 520: Individual memory elements 522: Top electrode 601: Double-layer lining 602: Overhanging section 603: Insulating materials 604: Second through hole 606: Layer of memory device

[0064] Domestic storage information (please note in order of storage institution, date, and number) none

[0065] Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A memory device, comprising: A metal plug includes a through hole surrounded by an insulating material, and a top portion extending above the insulating material and laterally beyond the width of the through hole; And a memory cell is formed above the metal plug, wherein the top portion of the metal plug has a substantially flat surface without a disc-shaped recess.

2. The memory device as claimed in claim 1, wherein a height of the via is between about 50 nm and about 150 nm, and a width of the via is between about 50 nm and about 150 nm.

3. The memory device as claimed in claim 1, wherein the top portion extends laterally beyond the width of the via by about 50 nm to about 150 nm.

4. The memory device as claimed in claim 1, wherein a bottom surface of the via is electrically connected to a bottom metal layer in a back-end process (BEOL) portion of an integrated circuit.

5. The memory device as claimed in claim 1, wherein the memory cell includes a resistive random access memory (ReRAM) cell, the ReRAM cell including a switching layer located between a bottom electrode and a top electrode.

6. The memory device as claimed in claim 5, wherein the bottom electrode of the memory cell extends along an entire upper surface of the top portion of the metal plug.

7. The memory device as claimed in claim 1, wherein the through-hole includes a first inclined sidewall that is inclined in a first direction, and the top portion of the metal plug includes a second inclined sidewall that is inclined in a second direction.

8. A memory device, comprising: A metal plug comprising a through-hole surrounded by an insulating material, and a top portion extending over the insulating material and laterally extending beyond the width of the through-hole, wherein the top portion of the metal plug is oxidized to form a metal-oxide switching region of the memory device and wherein the top portion of the metal plug has a substantially flat surface without a disc-shaped recess. And a top electrode formed on the top portion of the metal plug.

9. The memory device of claim 8, wherein the metal plug does not include an interface between the through-hole and the top portion of the metal plug, and the metal-oxide switching region forms a continuous oxide material gradient in the top portion of the metal plug.

10. The memory device as claimed in claim 8, wherein the through-hole comprises copper, tantalum, or titanium, and the top portion of the metal plug comprises copper oxide, tantalum oxide, or titanium oxide.

11. The memory device as claimed in claim 8, wherein the top portion of the metal plug has a height between about 5 nm and about 50 nm.

12. The memory device as claimed in claim 8, wherein the memory device does not include a bottom electrode between the metal-oxide switching region and the via.

13. A method of forming a memory device, the method comprising the steps of: forming a metal layer, wherein the metal layer fills a feature in an insulating layer to form a via, and the metal layer extends above a top surface of the insulating layer; partially removing a portion of the metal layer, wherein a remaining portion of the metal layer continues to cover the insulating layer; forming one or more layers for a memory cell on or within the remaining portion of the metal layer; and performing an etching to form the memory device above the via, wherein the etching extends below the top surface of the insulating layer, wherein the remaining portion of the metal layer is formed using a chemical mechanical polishing (CMP) process to form a substantially flat surface without a dish-shaped recess above the via.

14. The method of claim 13, wherein the etching forming the memory device includes a first etching process configured to stop at the remaining portion of the metal layer.

15. The method of claim 14, wherein the etching forming the memory device includes a second etching process configured to etch through the remaining portion of the metal layer and into the insulating layer.

16. The method of claim 13, wherein the step of forming one or more layers for a memory cell on or within the metal layer includes the steps of: oxidizing a top portion of the metal layer to form a metal-oxide switching region of the memory device, wherein the memory device does not include a bottom electrode between the metal-oxide switching region and the via; and forming a top electrode on the top portion of the metal layer.

17. The method of claim 13, wherein the step of forming one or more layers for a memory cell on or within the metal layer includes the steps of: forming a bottom electrode layer on the remaining portion of the metal layer; forming a metal-oxide switching layer on the bottom electrode layer; and forming a top electrode layer on the metal-oxide switching layer.

18. The method of claim 13, wherein the step of performing the etching to form the memory device over the via includes the steps of: forming a metal plug including the via and a top portion of the metal plug extending over the insulating layer and laterally extending beyond the width of the via.

19. The method of claim 13, wherein the step of performing the etching to form the memory device over the via comprises the step of forming a metal plug having a hammerhead shape.

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