Semiconductor structure and method of fabricating the same

Abstract

A semiconductor structure includes a first die and a second die. The first die includes a first substrate, a first interconnect layer, a first inductor pattern, and a first bonding layer. The first interconnect layer is disposed on the first substrate. The first inductor pattern is disposed on the first interconnect layer. The first bonding layer includes a first bonding pad. The second die is bonded to the first die and includes a second substrate, a second interconnect layer, a second inductor pattern, and a second bonding layer. The second interconnect layer is disposed on the second substrate. The second inductor pattern is disposed on the second interconnect layer. The second bonding layer includes a second bonding pad, wherein the second bonding pad is bonded to the first bonding pad, and wherein the first inductor pattern is electrically connected to the second inductor pattern through the first and second bonding layers.

Description

Prior Technology

[0001] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronics continues to grow, there is a need for smaller and more innovative semiconductor die packaging technologies. Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity. Figures 1A to 4 are schematic cross-sectional and top views of various stages in a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. Figure 5 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. Figures 6A to 6D are schematic top views of various inductor pattern designs according to some embodiments of the present disclosure. Figure 7A is a schematic cross-sectional view of a semiconductor package according to some other embodiments of the present disclosure. Figure 7B is an exploded top view of the stacked inductor pattern of the semiconductor package shown in Figure 7A. Figure 7C is a three-dimensional view of the stacked inductor pattern of the semiconductor package shown in Figure 7A. Figure 8 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure. Figure 9A is a schematic cross-sectional view of a semiconductor package according to some other embodiments of the present disclosure. Figure 9B is an exploded top view of the stacked inductor pattern of the semiconductor package shown in Figure 9A. Figure 9C is a three-dimensional view of the stacked inductor pattern of the semiconductor package shown in Figure 9A. Figure 10 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure. Figure 11 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure. Figure 12 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure. Implementation

[0003] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0004] Additionally, for ease of description, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. Besides the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0005] Semiconductor chips typically include inductor patterns at the same level as conductive pads, where the inductor patterns may further lie on an interconnect layer. However, the presence of conductive / metal layers in the interconnect layer below the inductor pattern can degrade inductance performance due to magnetic fields / magnetic flux, thereby reducing inductance and quality factor. On the other hand, removing conductive / metal layers above and below the inductor pattern can improve inductance performance, but it can cause a decrease in local pattern density, resulting in poor plating uniformity and morphology. According to some embodiments of this disclosure, a stacked inductor pattern design is provided to reduce the blank areas above and below each inductor pattern to obtain inductance and alleviate uniformity / morphology problems.

[0006] Figures 1A to 4 are schematic cross-sectional and top views of various stages of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure. Referring to Figures 1A and 1B, in some embodiments, a first die D100 (or top die) is formed having a first substrate 102, a first interconnect layer 104, a first inductor pattern IP1, a first conductive pad 106A, a dielectric layer 106B, and a first bonding layer 108.

[0007] In some embodiments, the first substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or the like. The first substrate 102 may be doped (e.g., using p-type or n-type dopants) or undoped. The first substrate 102 may be a wafer, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the first substrate 102 includes elemental semiconductors such as silicon or germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, alloy semiconductors such as SiGe, GaAsP, AllnAs, AlGaAs, GaInAs, GaInP, and GaInAsP, or combinations thereof.

[0008] In some embodiments, the first substrate 102 further includes active elements (e.g., transistors or the like) and optional passive elements (e.g., resistors, capacitors, inductors, or the like) formed in the first substrate 102. In some other embodiments, the first substrate 102 includes various devices disposed thereon. These devices include integrated circuit devices. These devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuses, or other similar devices. Other devices, such as capacitors, resistors, diodes, photodiodes, fuses, etc., may also be formed on the first substrate 102. The functions of these devices may include memory, processors, sensors, amplifiers, power distribution, input / output circuitry, or similar functions.

[0009] As shown in FIG1A, a first interconnect layer 104 is formed on a first substrate 102. In some embodiments, forming the first interconnect layer 104 includes forming a plurality of conductive layers 104-MX and a plurality of dielectric layers 104A, which are stacked alternately along a stacking direction. In one embodiment, the plurality of conductive layers 104-MX comprises seventeen conductive layers. The first conductive layer 104-M1 is closest to the first substrate 102, and the second conductive layer, the third conductive layer (not shown), up to the seventeenth conductive layer 104-M17 are sequentially formed on the first conductive layer 104-M1. In some embodiments, the first conductive layer 104-M1 may be electrically connected to a component (e.g., a transistor) located on the first substrate 102. Furthermore, the plurality of conductive layers 104-MX may be electrically connected to each other through a plurality of conductive vias (not shown). In some embodiments, the dielectric layer 104A surrounds and covers the conductive layers 104-MX.

[0010] In some embodiments, the material of dielectric layer 104A may be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or combinations thereof. The material of dielectric layer 104A may be patterned using lithography and / or etching processes. In some embodiments, dielectric layer 104A is formed using suitable fabrication techniques (e.g., spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.). This disclosure is not limited thereto.

[0011] In some embodiments, the material of the conductive layer 104-MX (and the conductive vias) may include conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof, which may be patterned using lithography and etching processes. In some embodiments, the conductive layer 104-MX (and the conductive vias) may be a patterned copper layer or other suitable patterned metal layer. Throughout this disclosure, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing trace amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0012] In some embodiments, the first interconnect layer 104 is formed with a first keep-out zone KO1, which does not contain the plurality of conductive layers 104-MX. For example, in an exemplary embodiment, the height of the first keep-out zone KO1 is equal to or greater than the total height of the four conductive layers (e.g., the fourteenth conductive layer 104-M14, the fifteenth conductive layer 104-M15, the sixteenth conductive layer 104-M16, and the seventeenth conductive layer 104-M17). In some embodiments, the first keep-out zone KO1 is a region located below the first inductor pattern IP1, wherein at least four of the plurality of conductive layers 104-MX are absent (or not formed). The height of the first keep-out zone KO1 can be measured from the bottom surface of the first inductor pattern IP1 to the top surface of the nearest conductive layer (e.g., the thirteenth conductive layer 104-M13) located vertically below it. For example, the height of the first keep-out zone KO1 may be at least 6µm or greater than 6µm. Although seventeen conductive layers 104-MX are shown here, it should be noted that the number of conductive layers 104-MX is not limited to this and can be adjusted according to design requirements. In some other embodiments, the number of conductive layers 104-MX can be appropriately adjusted as long as the first forbidden zone KO1 is maintained in the first interconnect layer 104.

[0013] As further shown in FIG1A, a plurality of conductive pads 106A and a first inductor pattern IP1 are formed on the first interconnect layer 104. For example, the conductive pads 106A and the first inductor pattern IP1 are formed in the same steps by forming a conductive layer (not shown) and patterning or etching the conductive layer. In some embodiments, the conductive pads 106A and the first inductor pattern IP1 are electrically connected to the first interconnect layer 104 through a plurality of conductive vias (not shown). Furthermore, the first inductor pattern IP1 is formed on the first interconnect layer 104 such that the first inductor pattern IP1 is disposed above the first forbidden zone KO1.

[0014] As shown in Figure 1B, which is a top view of the first inductor pattern IP1, in some embodiments, the first inductor pattern IP1 is a helical inductor pattern with a rectangular shape. For example, in one embodiment, the first inductor pattern IP1 has three coil turns, including a first coil turn IP1-T1, a second coil turn IP1-T2 coupled to the first coil turn IP1-T1, and a third coil turn IP1-T3 coupled to the second coil turn IP1-T2. Although three coil turns are shown here, it should be noted that the number of coil turns in the first inductor pattern IP1 is not particularly limited, and can be appropriately adjusted as long as the number of coil turns is more than one. In some embodiments, one terminal of the first coil turn IP1-T1 (inner coil turn) is connected to a conductive via CV1, while one terminal of the third coil turn IP1-T3 (outer coil turn) is connected to a conductive via CV2. For example, conductive via CV1 is electrically connected to a first bonding pad 108A of the first bonding layer 108, while conductive via CV2 is electrically connected to the seventeenth conductive layer 104-M17 in the first interconnect layer 104. After forming the conductive pad 106A and the first inductance pattern IP1, a dielectric layer 106B is formed to laterally surround the conductive pad 106A and the first inductance pattern IP1.

[0015] In a subsequent step, a first bonding layer 108 is formed on the dielectric layer 106B. Forming the first bonding layer 108 includes forming a plurality of first bonding pads 108A and a first bonding film 108B surrounding the first bonding pads 108A. For example, the first bonding pads 108A are formed using suitable techniques, such as damascene, dual-damascene, electroplating, deposition, similar techniques, or combinations thereof. In some embodiments, the first bonding pads 108A are formed of a conductive material such as copper or a similar material. Furthermore, a conductive via CV1 directly connects one of the first bonding pads 108A to the first inductance pattern IP1. In some embodiments, the material of the first bonding film 108B is similar to the material of the dielectric layer 104A; therefore, a detailed description of the first bonding film 108B will be omitted here.

[0016] Referring to Figures 2A and 2B, in some embodiments, the second grain D200 (or intermediate grain) is formed with a second substrate 202, a substrate via 202TX, a second interconnect layer 204, a second inductor pattern IP2, and a second bonding layer 208.

[0017] In some embodiments, the second substrate 202 may be, for example, a bulk substrate (such as a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or the like. The second substrate 202 may be doped (e.g., doped with p-type or n-type dopants) or undoped. The second substrate 202 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer is, for example, a buried oxide (BOX) layer, a silicon dioxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the second substrate 202 includes elemental semiconductors such as silicon or germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, or combinations thereof.

[0018] In some embodiments, the second substrate 202 further includes active elements (e.g., transistors or the like) and optional passive elements (e.g., resistors, capacitors, inductors, or the like) formed in the second substrate 20. In some other embodiments, the second substrate 202 includes various devices disposed thereon. These devices include integrated circuit devices. These devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. Other devices, such as capacitors, resistors, diodes, photodiodes, fuses, etc., may also be formed above the second substrate 202. The functions of these devices may include memory, processors, sensors, amplifiers, power distribution, input / output circuitry, or similar functions. Furthermore, in some embodiments, the second substrate 202 includes a first surface 202S1 and a second surface 202S2 opposite to the first surface 202S1. In some embodiments, a substrate via 202TX is embedded in the second substrate 202, and the top surface of the substrate via 202TX is exposed at the second surface 202S2.

[0019] As further shown in FIG2A, a second interconnect layer 204 is formed on a second surface 202S2 of a second substrate 202. In some embodiments, forming the second interconnect layer 204 includes forming a plurality of conductive layers 204-MX and a plurality of dielectric layers 204A, which are stacked alternately along a stacking direction. In an exemplary embodiment, the plurality of conductive layers 204-MX includes three conductive layers, such as a first conductive layer 204-M1, a second conductive layer 204-M2, and a third conductive layer 204-M3. In some embodiments, the first conductive layer 204-M1 is electrically connected to a substrate via 202TX in the second substrate 202, or may be electrically connected to an element (e.g., a transistor) located on the second substrate 202. Furthermore, the plurality of conductive layers 204-MX can be electrically connected to each other through a plurality of conductive vias (not shown). In some embodiments, the dielectric layer 204A surrounds and covers the conductive layers 204-MX.

[0020] In some embodiments, the dielectric layer 204A may be made of polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, or the like. These materials may be patterned using lithography and / or etching processes. In some embodiments, the dielectric layer 204A is formed using suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or similar processes. This disclosure is not limited thereto.

[0021] In some embodiments, the material of the conductive layer 204-MX (and the conductive vias) may include conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof, which may be patterned using lithography and etching processes. In some embodiments, the conductive layer 204-MX (and the conductive vias) may be a patterned copper layer or other suitable patterned metal layer. Throughout this disclosure, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing trace amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0022] In some embodiments, the second interconnect layer 204 is formed with a second forbidden zone KO2, which does not contain the plurality of conductive layers 204-MX. For example, in an exemplary embodiment, the height of the second forbidden zone KO2 is equal to or greater than the total height of two conductive layers (e.g., the first conductive layer 204-M1 and the second conductive layer 204-M2) of the plurality of second conductive layers 204-MX. In some alternative embodiments, the height of the second forbidden zone KO2 is equal to or greater than the height of one of the conductive layers 204-MX. In some embodiments, the second forbidden zone KO2 is a region located below the second inductor pattern IP2, wherein at least one of the plurality of conductive layers 204-MX is absent (or not formed). The height of the second forbidden zone KO2 can be measured from the bottom surface of the second inductor pattern IP2 to the top surface (if present) of the nearest conductive layer located vertically below it, or measured to the bottom surface of the second interconnect layer 204. Although three conductive layers 204-MX are shown here, it should be noted that the number of conductive layers 204-MX is not limited to this and can be adjusted according to design requirements. In some other embodiments, the number of conductive layers 204-MX can be appropriately adjusted as long as the second forbidden zone KO2 is maintained in the second interconnect layer 204.

[0023] As further shown in Figure 2A, in some embodiments, the second inductor pattern IP2 is formed on the second interconnect layer 204 and surrounded by the dielectric layer 204A. In some embodiments, the second inductor pattern IP2 is formed parallel to the third conductive layer 204-M3 and located above the second forbidden zone KO2 of the second interconnect layer 204. As shown in the top view of the second inductor pattern IP2 in Figure 2B, in some embodiments, the second inductor pattern IP2 is a helical inductor pattern with a rectangular shape. For example, in one embodiment, the second inductor pattern IP2 has three coil turns, including a first coil turn IP2-T1, a second coil turn IP2-T2 coupled to the first coil turn IP2-T1, and a third coil turn IP2-T3 coupled to the second coil turn IP2-T2. Although three coil turns are shown here, it should be noted that the number of coil turns in the second inductor pattern IP2 is not particularly limited, and can be appropriately adjusted as long as the number of coil turns is more than one. In some embodiments, one terminal of the first coil turn IP2-T1 (inner coil turn) is connected to a conductive via CV3, and one terminal of the third coil turn IP2-T3 (outer coil turn) is connected to a conductive via CV4. For example, the conductive via CV3 is electrically connected to a second bonding pad 208A of the second bonding layer 208, and the conductive via CV4 is electrically connected to a second conductive layer 204-M2 in the second interconnect layer 204. In some embodiments, the material of the second inductor pattern IP2 is different from the material of the first inductor pattern IP1. For example, in one embodiment, the material of the second inductor pattern IP2 is copper, while the material of the first inductor pattern IP1 is aluminum. In some alternative embodiments, the material of the second inductor pattern IP2 is the same as the material of the first inductor pattern IP1, for example, both are made of copper.

[0024] After forming the second interconnect layer 204 and the second inductor pattern IP2, a second bonding layer 208 is formed on the second interconnect layer 204. In some embodiments, forming the second bonding layer 208 includes forming a plurality of second bonding pads 208A and a second bonding film 208B surrounding the second bonding pads 208A. For example, the second bonding pads 208A are formed using suitable techniques such as damascene, dual-damascene, electroplating, deposition, similar techniques, or combinations thereof. In some embodiments, the second bonding pads 208A are formed of a conductive material such as copper or a similar material. Furthermore, the conductive via CV3 directly connects one second bonding pad 208A to the second inductor pattern IP2. In some embodiments, the material of the second bonding film 208B is similar to the material of the dielectric layer 104A; therefore, details of the second bonding film 208B will be omitted here.

[0025] Referring to FIG3A, after the formation of the first die D100 and the second die D200, dielectric-to-dielectric bonding and direct metal-to-metal bonding are used to bond the first die D100 to the second die D200. In some embodiments, the first die D100 is diced before being bonded to the second die D200. In some embodiments, the first bonding layer 108 is directly connected to the second bonding layer 208, wherein the first bonding pad 108A is bonded to the second bonding pad 208A, and the first bonding film 108B is bonded to the second bonding film 208B. In this exemplary embodiment, the first inductor pattern IP1 is electrically connected to the second inductor pattern IP2 through the conductive via CV1, the first bonding pad 108A, the second bonding pad 208A, and the conductive via CV3. Thus, a stacked inductor pattern can be formed.

[0026] Figure 3B is an exploded top view of the stacked inductor pattern according to the package structure shown in Figure 3A. Figure 3C is a three-dimensional view of the stacked inductor pattern according to the package structure shown in Figure 3A. As shown in Figures 3A to 3C, a first inductor pattern IP1 is stacked on a second inductor pattern IP2 to form a stacked inductor pattern IPX_TV1. For example, the first inductor pattern IP1 and the second inductor pattern IP2 partially overlap each other to include an overlapping region OX1 and a non-overlapping region NOX1. The area where the first inductor pattern IP1 and the second inductor pattern IP2 overlap each other in the stacking direction is defined as the overlapping region OX1, while the area where the first inductor pattern IP1 and the second inductor pattern IP2 do not overlap in the stacking direction is defined as the non-overlapping region NOX1. In some embodiments, the first inductor pattern IP1 and the second inductor pattern IP2 are both helical inductor patterns with a rectangular shape, wherein the sidewalls of the first inductor pattern IP1 are aligned with the sidewalls of the second inductor pattern IP2. However, the start and end points of the terminals of the first inductor pattern IP1 are different from the start and end points of the terminals of the second inductor pattern IP2. In other words, the first inductor pattern IP1 and the second inductor pattern IP2 may have the same number of coil turns, but the terminal arrangement of the first inductor pattern IP1 is offset relative to the terminal arrangement of the second inductor pattern IP2. In some embodiments, the thickness of the first inductor pattern IP1 is different from the thickness of the second inductor pattern IP2. For example, the thickness of the first inductor pattern IP1 is greater than the thickness of the second inductor pattern IP2. However, this disclosure is not limited to this; in some other embodiments, the thickness of the first inductor pattern IP1 may be the same as or less than the thickness of the second inductor pattern IP2. In some embodiments, the thicknesses of the first inductor pattern IP1 and the second inductor pattern IP2 may be adjusted according to product requirements.

[0027] Referring to Figure 4, in subsequent steps, a thinning process is performed on the second substrate 202 of the second die D200 until the substrate via 202TX is exposed on the first surface 202S1. In some embodiments, the thinning process may include a back-side grinding process, a polishing process, or an etching process. After the substrate via 202TX is exposed on the second substrate 202, conductive pillars 302A and conductive terminals 302B are then formed on the first surface 202S1 of the second substrate 202. In some embodiments, the conductive pillars 302A and conductive terminals 302B are disposed on and electrically connected to the substrate via 202TX. In some embodiments, the conductive pillars 302A and conductive terminals 302B are also electrically connected to elements embedded in the second substrate 202 of the second die D200. In some embodiments, the conductive pillar 302A comprises a conductive material, such as copper or a similar material. Furthermore, the conductive terminals 302B are formed on and electrically connected to the conductive pillar 302A. In some embodiments, the conductive terminal 302B is a microbump, such as a microbump having copper pillars. In some alternative embodiments, the conductive terminal 302B is a solder ball, a lead-free solder ball, or a microbump, such as a controlled collapse chip connection (C4) bump or a microbump containing copper pillars. After the conductive pillars 302A and the conductive terminal 302B are formed on the second substrate 202, the stacked structure can be diced to form a single semiconductor package. For example, the dicing process can be a laser dicing process, a mechanical sawing process, or other suitable processes. Accordingly, a semiconductor package PK1 according to some embodiments of this disclosure can be completed.

[0028] Figure 5 is a schematic cross-sectional view of a semiconductor structure according to some exemplary embodiments of the present disclosure. Referring to Figure 5, in some embodiments, the semiconductor package PK1 obtained in Figure 4 is mounted or attached to a circuit board 400 via conductive terminals 302B. In some embodiments, the circuit board 400 includes contact pads 410, contact pads 420, a metallization layer 430, and vias (not shown). In some embodiments, contact pads 410 and 420 are distributed on two opposite sides of the circuit board 400 and exposed for electrical connection to subsequently formed components / features. In some embodiments, the metallization layer 430 and the vias are embedded in the circuit board 400 and together provide wiring functionality for the circuit board 400, wherein the metallization layer 430 and the vias are electrically connected to the contact pads 410 and 420. In other words, at least some of the contact pads 410 are electrically connected to some of the contact pads 420 via the metallization layer 430 and the vias. In some embodiments, the contact pads 410 and 420 may comprise metal pads or metal alloy pads. In some embodiments, the materials of the metallization layer 430 and the via may be substantially the same as or similar to the materials of the contact pads 410 and 420.

[0029] Furthermore, in some embodiments, the semiconductor package PK1 is bonded to the circuit board 400 by physically connecting the conductive terminals 302B and contact pads 410 to form a stacked structure. In some embodiments, the semiconductor package PK1 is electrically connected to the circuit board 400. In some embodiments, the circuit board 400 is, for example, an organic flexible substrate or a printed circuit board. In these embodiments, the conductive terminals 302B are, for example, chip connectors. In some embodiments, a plurality of conductive balls 440 are formed on the circuit board 400. As shown in FIG5, for example, the conductive balls 440 are connected to the contact pads 420 of the circuit board 400. In other words, the conductive balls 440 are electrically connected to the circuit board 400 through the contact pads 420. Through the contact pads 410 and 420, some of the conductive balls 440 are electrically connected to the first die D100 and / or the second die D200 of the semiconductor package PK1. In some embodiments, the conductive balls 440 are, for example, solder balls or ball grid array (BGA) balls.

[0030] Furthermore, as shown in FIG5, a passive component PDX (integrated passive component or surface mount device) may be mounted on the circuit board 400. For example, the passive component PDX may be mounted on the contact pad 410 of the circuit board 400 via a soldering process. This disclosure is not limited thereto. In some embodiments, the passive component PDX may be mounted on the circuit board 400 to surround the semiconductor package PK1. As further shown in FIG5, in some embodiments, an underfill structure UX1 is formed to fill the space between the circuit board 400 and the semiconductor package PK1. In some embodiments, the underfill structure UX1 fills the space between adjacent conductive pillars 302A and conductive terminals 302B, and covers the conductive pillars 302A and conductive terminals 302B. In some embodiments, the passive component PDX is exposed by the underfill structure UX1 and is kept at a certain distance from the underfill structure UX1. In other words, the underfill structure UX1 does not cover the passive component PDX. After the semiconductor package PK1 is bonded to the circuit board 400 and the underfill structure UX1 is formed, the semiconductor structure SM10 according to some embodiments of this disclosure is completed.

[0031] In the semiconductor package PK1 and semiconductor structure SM10 disclosed herein, since the second inductor pattern IP2 is electrically connected to the first inductor pattern IP1, and the first and second inductor patterns IP1 and IP2 are stacked together to form a stacked inductor pattern, the inductance can be increased without excessively sacrificing area by removing the conductive / metal layers above and below the inductor pattern. In other words, the presence of the second inductor pattern IP2 can occupy the originally empty area to obtain inductance, which can also alleviate uniformity / topography problems.

[0032] Figures 6A to 6D are schematic top views of various inductor pattern designs according to some exemplary embodiments of the present disclosure. In previous embodiments, the first inductor pattern IP1 and the second inductor pattern IP2 are helical inductor patterns with a rectangular shape. However, the present disclosure is not limited thereto. In various embodiments, the first inductor pattern IP1 and the second inductor pattern IP2 are helical inductor patterns with a rectangular or square shape as shown in Figure 6A, helical inductor patterns with an octagonal shape as shown in Figure 6B, helical inductor patterns with a circular shape as shown in Figure 6C, or helical inductor patterns with a hexagonal shape as shown in Figure 6D. In other words, the first inductor pattern IP1 and the second inductor pattern IP2 may have the same shape pattern, but the shapes of the first and second inductor patterns IP1, IP2 are not particularly limited and can be adjusted according to design requirements. Furthermore, the various inductor pattern designs shown in Figures 6A to 6D can be applied to any inductor pattern described in the present disclosure.

[0033] Figure 7A is a schematic cross-sectional view of a semiconductor package according to some other exemplary embodiments of the present disclosure. Figure 7B is an exploded top view of the stacked inductor pattern of the semiconductor package shown in Figure 7A. Figure 7C is a three-dimensional view of the stacked inductor pattern of the semiconductor package shown in Figure 7A. The semiconductor package PK2 and the stacked inductor pattern IPX_TV2 shown in Figures 7A to 7C are similar to the semiconductor package PK1 and the stacked inductor pattern IPX_TV1 shown in Figures 4 and 3B to 3C. Therefore, the same element symbols will be used to denote the same or similar parts, and their detailed description will be omitted here. The difference between the embodiments is the arrangement of the inductor patterns (IP1, IP2) and the presence of the auxiliary inductor pattern AP1.

[0034] As shown in Figures 7A to 7C, in some embodiments, the first bonding layer 108 in the first die D100 further includes an auxiliary inductor pattern AP1 connected to the first inductor pattern IP1. For example, the auxiliary inductor pattern AP1 is parallel to the first bonding pad 108A in the first bonding layer 108 and is made of the same material as the first bonding pad 108A. In an exemplary embodiment, a conductive via CV1 electrically connects the first inductor pattern IP1 to the auxiliary inductor pattern AP1. Furthermore, a conductive via CV2 electrically connects the first inductor pattern IP1 to the seventeenth conductive layer 104-M17 in the first interconnect layer 104.

[0035] In some embodiments, the second inductor pattern IP2 is a second bonding layer 208 embedded in the second die D200. For example, the second inductor pattern IP2 is located next to and parallel to the second bonding pad 208A, and is made of the same material as the second bonding pad 208A. In an exemplary embodiment, the first die D100 is bonded to the second die D200 such that the auxiliary inductor pattern AP1 is directly bonded to the second inductor pattern IP2 by direct metal-to-metal bonding. Furthermore, the conductive via CV4 electrically connects the second inductor pattern IP2 to the third conductive layer 204-M3 in the second interconnect layer 204. In some embodiments, the auxiliary inductor pattern AP1 and the second inductor pattern IP2 have the same inductor pattern design. In some embodiments, the auxiliary inductor pattern AP1 completely overlaps the second inductor pattern IP2 in the stacking direction. For example, the coil turns and terminals of the auxiliary inductor pattern AP1 and the second inductor pattern IP2 are matched and aligned with each other.

[0036] As further shown in Figure 7B, the first inductor pattern IP1 partially overlaps with the auxiliary inductor pattern AP1 and the second inductor pattern IP2, comprising an overlapping region OX1 and a non-overlapping region NOX1. The area of ​​the first inductor pattern IP1 that overlaps with the auxiliary inductor pattern AP1 and the second inductor pattern IP2 in the stacking direction is defined as the overlapping region OX1, while the area of ​​the first inductor pattern IP1 that does not overlap with the auxiliary inductor pattern AP1 and the second inductor pattern IP2 is defined as the non-overlapping region NOX1. In some embodiments, the first inductor pattern IP1, the auxiliary inductor pattern AP1, and the second inductor pattern IP2 are all helical inductor patterns with a rectangular shape, wherein the sidewalls of the first inductor pattern IP1, the auxiliary inductor pattern AP1, and the second inductor pattern IP2 are aligned with each other. However, the start and end points of the terminals of the first inductor pattern IP1 are different from the start and end points of the terminals of the auxiliary inductor pattern AP1 and the second inductor pattern IP2. Therefore, the first inductor pattern IP1, the auxiliary inductor pattern AP1, and the second inductor pattern IP2 are stacked on top of each other in the stacking direction to form a stacked inductor pattern IPX_TV2.

[0037] Figure 8 is a schematic cross-sectional view of a semiconductor structure according to some other exemplary embodiments of the present disclosure. The semiconductor structure SM20 shown in Figure 8 is similar to the semiconductor structure SM10 shown in Figure 5. Therefore, the same element symbols are used to denote the same or similar parts, and their detailed descriptions will be omitted here.

[0038] Referring to FIG8, in some embodiments, the semiconductor package PK2 obtained in FIG7A is mounted or attached to the circuit board 400 via conductive terminals 302B. Next, a passive component PDX (integrated passive component or surface mount device) can be mounted on the circuit board 400, and the underfill structure UX1 can be formed in the same manner as described in FIG5, surrounding the conductive pillars 302A and conductive terminals 302B. After bonding the semiconductor package PK2 to the circuit board 400 and forming the underfill structure UX1, the semiconductor structure SM20 according to some embodiments of this disclosure can be completed.

[0039] In the semiconductor package PK2 shown in Figure 7A and the semiconductor structure SM20 shown in Figure 8, since the second inductor pattern IP2 and the auxiliary inductor pattern AP1 are electrically connected to the first inductor pattern IP1, and the inductor patterns (IP1, AP1, IP2) are stacked together to form a stacked inductor pattern, the inductance can be increased without excessively sacrificing area by removing the conductive / metal layers above and below the inductor patterns. In other words, the presence of the auxiliary inductor pattern AP1 and the second inductor pattern IP2 can occupy the originally empty area to obtain inductance, which can also alleviate uniformity / topography problems.

[0040] Figure 9A is a schematic cross-sectional view of a semiconductor package according to some other exemplary embodiments of the present disclosure. Figure 9B is an exploded top view of the stacked inductor pattern of the semiconductor package shown in Figure 9A. Figure 9C is a three-dimensional view of the stacked inductor pattern of the semiconductor package shown in Figure 9A. The semiconductor package PK3 and the stacked inductor pattern IPX_TV3 shown in Figures 9A and 9B are similar to the semiconductor package PK1 and the stacked inductor pattern IPX_TV1 shown in Figures 4 and 3B. Therefore, the same element symbols will be used to represent the same or similar parts, and their detailed descriptions will be omitted here. The difference between the embodiments is the arrangement of the inductor patterns (IP1, IP2) and the presence of the auxiliary inductor pattern AP1 and the second auxiliary inductor pattern AP2.

[0041] As shown in Figures 9A to 9C, in some embodiments, the first bonding layer 108 in the first die D100 further includes an auxiliary inductor pattern AP1 connected to the first inductor pattern IP1. For example, the auxiliary inductor pattern AP1 is parallel to the first bonding pad 108A in the first bonding layer 108 and is made of the same material as the first bonding pad 108A. In an exemplary embodiment, via CV1 electrically connects the first inductor pattern IP1 to the auxiliary inductor pattern AP1. Furthermore, via CV2 electrically connects the first inductor pattern IP1 to the seventeenth conductive layer 104-M17 in the first interconnect layer 104.

[0042] Furthermore, the second bonding layer 208 in the second die D200 also includes a second auxiliary inductor pattern AP2 connected to the second inductor pattern IP2. For example, the second auxiliary inductor pattern AP2 is located on one side of and parallel to the second bonding pad 208A, and is made of the same material as the second bonding pad 208A. In an exemplary embodiment, the first die D100 is bonded to the second die D200 such that the auxiliary inductor pattern AP1 is directly bonded to the second auxiliary inductor pattern AP2 by direct metal-to-metal bonding. Furthermore, via CV3 electrically connects the second auxiliary inductor pattern AP2 to the second inductor pattern IP2, while via CV4 electrically connects the second inductor pattern IP2 to the second conductive layer 204-M2 in the second interconnect layer 204. In some embodiments, the auxiliary inductor pattern AP1 and the second auxiliary inductor pattern AP2 have the same inductor pattern design. In some embodiments, the auxiliary inductor pattern AP1 completely overlaps the second auxiliary inductor pattern AP2 in the stacking direction. For example, the coil turns and terminals of the auxiliary inductor pattern AP1 and the second auxiliary inductor pattern AP2 are matched and aligned with each other.

[0043] As further shown in Figure 9B, the first inductor pattern IP1 partially overlaps with the auxiliary inductor pattern AP1 and the second auxiliary inductor pattern AP2, including an overlapping region OX1 and a non-overlapping region NOX1. In the stacking direction, the area where the first inductor pattern IP1 overlaps with the auxiliary inductor pattern AP1 and the second auxiliary inductor pattern AP2 is defined as the overlapping region OX1, while the area where the first inductor pattern IP1 does not overlap with the auxiliary inductor patterns AP1 and AP2 is defined as the non-overlapping region NOX1. Similarly, the first inductor pattern IP1 partially overlaps with the second inductor pattern IP2, including an overlapping region OX2 and a non-overlapping region NOX2. In the stacking direction, the area where the first inductor pattern IP1 overlaps with the second inductor pattern IP2 is defined as the overlapping region OX2, while the area where the first inductor pattern IP1 does not overlap with the second inductor pattern IP2 is defined as the non-overlapping region NOX2.

[0044] In some embodiments, the first inductor pattern IP1, the auxiliary inductor pattern AP1, the second auxiliary inductor pattern AP2, and the second inductor pattern IP2 are all helical inductor patterns with a rectangular shape, wherein the sidewalls of the first inductor pattern IP1, the auxiliary inductor pattern AP1, the second auxiliary inductor pattern AP2, and the second inductor pattern IP2 are aligned with each other. However, the start and end points of the terminals of the first inductor pattern IP1 are different from the start and end points of the terminals of the auxiliary inductor patterns AP1 and AP2. Similarly, the start and end points of the terminals of the second inductor pattern IP2 are different from the start and end points of the terminals of the auxiliary inductor patterns AP1 and AP2. Accordingly, the first inductor pattern IP1, the auxiliary inductor pattern AP1, the second auxiliary inductor pattern AP2, and the second inductor pattern IP2 are stacked on top of each other along the stacking direction to form a stacked inductor pattern IPX_TV3.

[0045] Figure 10 is a schematic cross-sectional view of a semiconductor structure according to some other exemplary embodiments of the present disclosure. The semiconductor structure SM30 shown in Figure 10 is similar to the semiconductor structure SM10 shown in Figure 5. Therefore, the same element symbols will be used to denote the same or similar parts, and their detailed descriptions will be omitted here.

[0046] Referring to FIG10, in some embodiments, the semiconductor package PK3 obtained in FIG9A is mounted or attached to the circuit board 400 via conductive terminals 302B. Next, passive components PDX (integrated passive components or surface-mount components) can be mounted on the circuit board 400, and an underfill structure UX1 can be formed around the conductive pillars 302A and conductive terminals 302B in the same manner as described in FIG5. After bonding the semiconductor package PK3 to the circuit board 400 and forming the underfill structure UX1, the semiconductor structure SM30 according to some embodiments of this disclosure is completed.

[0047] In the semiconductor package PK3 shown in Figure 9A and the semiconductor structure SM30 shown in Figure 10, since the second inductor pattern IP2, the auxiliary inductor pattern AP1, and the second auxiliary inductor pattern AP2 are electrically connected to the first inductor pattern IP1, and the inductor patterns (IP1, AP1, AP2, IP2) are stacked together to form a stacked inductor pattern, the inductance can be increased without excessively sacrificing area by removing the conductive / metal layers above and below the inductor patterns. In other words, the presence of the auxiliary inductor pattern AP1, the second auxiliary inductor pattern AP2, and the second inductor pattern IP2 can occupy the originally empty area to obtain inductance, which can also alleviate uniformity / topography problems.

[0048] Figure 11 is a schematic cross-sectional view of a semiconductor structure according to some other exemplary embodiments of the present disclosure. The semiconductor structure SM40 shown in Figure 11 is similar to the semiconductor structure SM30 shown in Figure 10. Therefore, the same element symbols will be used to denote the same or similar parts, and their detailed descriptions will be omitted here.

[0049] In previous embodiments, a first die D100 was stacked on a second die D200 to form a semiconductor package, with the sidewalls of the first die D100 aligned with the sidewalls of the second die D200. However, this disclosure is not limited thereto. In the embodiment shown in FIG11, in the semiconductor package PK4, the lateral dimension of the first die D100 is smaller than the lateral dimension of the second die D200. Therefore, after the first die D100 is bonded to the second die D200 to form the semiconductor package PK4, the sidewalls of the first die D100 and the sidewalls of the second die D200 are not aligned.

[0050] In some embodiments, forming the semiconductor package PK4 further includes forming an interstitial filling layer or encapsulation 180 surrounding the first die D100. For example, the encapsulation 180 may be made of a polymer (such as epoxy, phenolic resin, silicone-containing resin, or other suitable resin), a dielectric material having a low dielectric constant (Dk) and low loss tangent (Df), or other suitable materials. In another embodiment, the encapsulation 180 may include an acceptable insulating encapsulation material. In some embodiments, the encapsulation 180 may also include the addition of inorganic fillers or inorganic compounds (e.g., silica, clay, etc.) to optimize the coefficient of thermal expansion (CTE) of the encapsulation 180. This disclosure is not limited thereto. After forming the encapsulation 180 around the first die D100, the sidewalls of the encapsulation 180 are aligned with the sidewalls of the second die D200.

[0051] As further shown in Figure 11, after forming the semiconductor package PK4 and placing the semiconductor package PK4 on the circuit board 400, the passive component PDX (integrated passive device or surface mount device) can be mounted on the circuit board 400, and a bottom filling structure UX1 can be formed to surround the conductive pillar 302A and the conductive terminal 302B, as described in Figure 5. Thus, the semiconductor structure SM40 according to some embodiments of this disclosure is completed.

[0052] In the semiconductor structure SM40 shown in Figure 11, since the second inductor pattern IP2, the auxiliary inductor pattern AP1, and the second auxiliary inductor pattern AP2 are electrically connected to the first inductor pattern IP1, and the inductor patterns (IP1, AP1, AP2, IP2) are stacked together to form a stacked inductor pattern, the inductance can be increased without excessively sacrificing area by removing the conductive / metal layers above and below the inductor patterns. In other words, the presence of the auxiliary inductor pattern AP1, the second auxiliary inductor pattern AP2, and the second inductor pattern IP2 can occupy the originally empty area to obtain inductance, which can also alleviate uniformity / topography problems.

[0053] Figure 12 is a schematic cross-sectional view of a semiconductor structure according to some other exemplary embodiments of the present disclosure. The semiconductor structure SM50 shown in Figure 12 is similar to the semiconductor structure SM40 shown in Figure 11. Therefore, the same component symbols are used to denote the same or similar parts, and their detailed descriptions are omitted here. The difference between the embodiments is that the semiconductor structure SM50 shown in Figure 12 also includes a third auxiliary inductor pattern AP3 in the semiconductor package PK5.

[0054] As shown in Figure 12, in an exemplary embodiment, the second inductor pattern IP2 is further connected to the third auxiliary inductor pattern AP3 via a conductive via CV5. For example, the third auxiliary inductor pattern AP3 is formed parallel to the second conductive layer 204-M2 and is made of the same material as the second conductive layer 204-M2. In this embodiment, the height of the second forbidden zone KO2 is approximately equal to the height of one of the plurality of second conductive layers 204-MX (e.g., the first conductive layer 204-M1). Furthermore, in an exemplary embodiment, the auxiliary inductor pattern AP1 and the second auxiliary inductor pattern AP2 have mutually matched and aligned inductor patterns, while the first inductor pattern IP1, the second inductor pattern IP2, and the third auxiliary inductor pattern AP3 have mutually mismatched and misaligned inductor patterns.

[0055] In the semiconductor structure SM50 shown in Figure 12, since the second inductor pattern IP2, the auxiliary inductor pattern AP1, the second auxiliary inductor pattern AP2, and the third auxiliary inductor pattern AP3 are electrically connected to the first inductor pattern IP1, and the inductor patterns (IP1, AP1, AP2, AP3, IP2) are stacked together to form a stacked inductor pattern, the inductance can be further increased without excessively sacrificing area by removing the conductive / metal layers above and below the inductor patterns. In other words, the presence of the auxiliary inductor pattern AP1, the second auxiliary inductor pattern AP2, the third auxiliary inductor pattern AP3, and the second inductor pattern IP2 can occupy the originally empty area to obtain inductance, which can also alleviate uniformity / topography problems.

[0056] In the above embodiments, the semiconductor structure includes at least a second inductor pattern electrically connected to the first inductor pattern, wherein the second inductor pattern directly overlaps with the first inductor pattern. Therefore, the presence of the additional inductor pattern replaces the conductive layer / metal layer of the interconnect layer originally located below and above the single inductor pattern. Accordingly, the reduction in inductance performance caused by the magnetic field / magnetic flux induced by the conductive layer / metal layer can be reduced. Furthermore, removing the conductive layer / metal layer on one side of the inductor pattern and solidly connecting the other side of the inductor pattern to another inductor pattern will further improve inductance performance. In other words, by using a stacked inductor pattern design, inductance can be further increased without excessively sacrificing area by removing the conductive layer / metal layer above and below the inductor pattern, and uniformity / morphology issues are also resolved.

[0057] According to some embodiments disclosed herein, a semiconductor structure includes a first die and a second die. The first die includes a first substrate, a first interconnect layer, a first inductor pattern, and a first bonding layer. The first interconnect layer is disposed on the first substrate. The first inductor pattern is disposed on the first interconnect layer and electrically connected to the first interconnect layer. The first bonding layer includes a first bonding pad. The second die is bonded to the first die and includes a second substrate, a second interconnect layer, a second inductor pattern, and a second bonding layer. The second interconnect layer is disposed on the second substrate. The second inductor pattern is disposed on the second interconnect layer and electrically connected to the second interconnect layer. The second bonding layer includes a second bonding pad, wherein the second bonding pad is bonded to the first bonding pad, and wherein the first inductor pattern is electrically connected to the second inductor pattern through the first bonding layer and the second bonding layer.

[0058] According to some other embodiments disclosed herein, a semiconductor structure includes a circuit substrate, a top die, and an intermediate die. The top die is disposed on and electrically connected to the circuit substrate, wherein the top die includes a first interconnect layer and a first inductor pattern. The first interconnect layer includes a plurality of alternately stacked conductive layers and a plurality of dielectric layers, wherein the first interconnect layer includes a first stop-gate region that does not contain the plurality of conductive layers. The first inductor pattern is disposed on the first interconnect layer and above the first stop-gate region. The intermediate die electrically connects the top die to the circuit substrate, wherein the intermediate die includes a second interconnect layer and a second inductor pattern. The second interconnect layer includes a plurality of alternately stacked second conductive layers and a plurality of second dielectric layers, wherein the second interconnect layer includes a second stop-gate region that does not contain the plurality of second conductive layers. The second inductor pattern is disposed on the second interconnect layer and above the second stop-gate region, wherein the second inductor pattern is electrically connected to the first inductor pattern of the top die.

[0059] According to another embodiment of this disclosure, a method for manufacturing a semiconductor structure is described. The method includes the following steps: forming a first die, wherein forming the first die includes forming a first interconnect layer on a first substrate; forming a first inductor pattern disposed on and electrically connected to the first interconnect layer; and forming a first bonding layer on the first inductor pattern, wherein the first bonding layer includes a plurality of first bonding pads. Forming a second die, wherein forming the second die includes forming a second interconnect layer on a second substrate; and forming a second inductor pattern electrically connected to the second interconnect layer, and forming a second bonding layer on the second interconnect layer, wherein the second bonding layer includes a plurality of second bonding pads. The method further includes bonding the first die to the second die by connecting the plurality of first bonding pads to the plurality of second bonding pads, wherein the first inductor pattern is electrically connected to the second inductor pattern through the first bonding layer and the second bonding layer.

[0060] Other features and processes may also be included. For example, a test structure may be included to illustrate verification testing of a three-dimensional (3D) package or three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, to enable testing of the 3D package or 3DIC using probes and / or probe cards. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0061] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

[0062] 102: First basement 104: First Inner Wiring Layer 104A, 106B, 204A: Dielectric layer 104-MX, 204-MX: Conductive layer 104-M1, 204-M1: First conductive layer 104-M13: Thirteenth conductive layer 104-M14: Fourteenth conductive layer 104-M15: Fifteenth conductive layer 104-M16: Sixteenth conductive layer 104-M17: Seventeenth conductive layer 106A: Conductive pad 108: First bonding layer 108A: First bonding pad 108B: First bonding film 180: Encapsulation 202: Second basement 202S1: First Surface 202S2: Second Surface 202TX: Substrate perforation 204: Second Inner Connection Layer 204-M2: Second conductive layer 204-M3: Third conductive layer 208: Second bonding layer 208A: Second bonding pad 208B: Second bonding film 302A: Conductive post 302B: Conductive terminal 400: Circuit board 410, 420: Contact pads 430: Metallization layer 440: Conductive sphere AP1: Auxiliary inductor pattern AP2: Second auxiliary inductor pattern AP3: Third Auxiliary Inductor Pattern CV1, CV2, CV3, CV4, CV5: Conductive vias D100: First grain D200: Second grain IP1: First Inductor Pattern IP1-T1, IP2-T1: First coil turns IP1-T2, IP2-T2: Second coil turns IP1-T3, IP2-T3: Third coil turns IP2: Second Inductor Pattern IPX_TV1: Stacked inductor pattern KO1: First Forbidden Zone KO2: The Second Forbidden Zone NOX1, NOX2: Non-overlapping regions OX1, OX2: Overlapping areas PDX: Passive Component PK1, PK2, PK3, PK4, PK5: Semiconductor Packaging SM10, SM20, SM30, SM40, SM50: Semiconductor Structure UX1: Bottom padding structure

Claims

1. A semiconductor structure, comprising: A first die includes: a first substrate; a first interconnect layer disposed on the first substrate; a first inductor pattern disposed on and electrically connected to the first interconnect layer; and a first bonding layer including a plurality of first bonding pads; a second die bonded to the first die and including: a second interconnect layer; a second inductor pattern disposed on and electrically connected to the second interconnect layer; and a second bonding layer including a plurality of second bonding pads, wherein the plurality of second bonding pads are bonded to the plurality of first bonding pads, and wherein the first inductor pattern is electrically connected to the second inductor pattern through the first bonding layer and the second bonding layer, and the first inductor pattern and the second inductor pattern partially overlap each other in a stacking direction to include overlapping regions and non-overlapping regions, wherein the area of ​​the overlapping region is larger than the area of ​​the non-overlapping region.

2. The semiconductor structure of claim 1, wherein the second inductor pattern is embedded in the second bonding layer and located on one side of the plurality of second bonding pads, and the first bonding layer further includes an auxiliary inductor pattern bonded to the second inductor pattern.

3. The semiconductor structure of claim 1, wherein the first bonding layer further includes an auxiliary inductor pattern connected to the first inductor pattern, and the second bonding layer further includes a second auxiliary inductor pattern connected to the second inductor pattern, and the auxiliary inductor pattern is bonded to the second auxiliary inductor pattern.

4. A semiconductor structure, comprising: Circuit board; A top die, disposed on and electrically connected to the circuit substrate, wherein the top die comprises: a first interconnect layer comprising alternatingly stacked plurality of conductive layers and plurality of dielectric layers, wherein the first interconnect layer comprises a first stop region, the first stop region not containing the plurality of conductive layers; and a first inductor pattern disposed on the first interconnect layer and located above the first stop region; an intermediate die electrically connected to the top die to the circuit substrate, wherein the intermediate die comprises: a second interconnect layer comprising alternatingly stacked plurality of second conductive layers and plurality of second dielectric layers, wherein the second interconnect layer comprises a second stop region, the second stop region not containing the plurality of second conductive layers; and a second inductor pattern disposed on the second interconnect layer and located above the second stop region, wherein the second inductor pattern is electrically connected to the first inductor pattern of the top die.

5. The semiconductor structure of claim 4, wherein the top die further includes a first bonding layer including a plurality of first bonding pads, and the intermediate die further includes a second bonding layer including a plurality of second bonding pads, wherein the plurality of second bonding pads are bonded to the plurality of first bonding pads, and the first inductor pattern is electrically connected to the second inductor pattern through the first bonding layer.

6. The semiconductor structure of claim 5, wherein the first bonding layer further includes an auxiliary inductor pattern connected to the first inductor pattern, and the second bonding layer further includes a second auxiliary inductor pattern connected to the second inductor pattern, wherein the auxiliary inductor pattern is bonded to the second auxiliary inductor pattern.

7. The semiconductor structure of claim 4, wherein the height of the first barrier region is equal to or greater than the total height of four of the plurality of conductive layers, and the height of the second barrier region is equal to or greater than the height of one of the plurality of second conductive layers.

8. A method for manufacturing a semiconductor structure, comprising: Forming a first die includes: forming a first interconnect layer on a first substrate, wherein the first interconnect layer includes a first stop-gate region without a conductive layer and a plurality of first conductive layers surrounding the first stop-gate region; forming a first inductor pattern on the first stop-gate region of the first interconnect layer, wherein the first inductor pattern is electrically connected to the first interconnect layer; and forming a first bonding layer on the first inductor pattern, wherein the first bonding layer includes a plurality of first bonding pads, the plurality of first bonding pads overlapping the plurality of first conductive layers in a stacking direction; forming a second die includes: forming a second interconnect layer; and forming a second inductor pattern electrically connected to the second interconnect layer, and forming a second bonding layer on the second interconnect layer, wherein the second bonding layer includes a plurality of second bonding pads; bonding the first die to the second die by connecting the plurality of first bonding pads to the plurality of second bonding pads, wherein the first inductor pattern is electrically connected to the second inductor pattern through the first bonding layer and the second bonding layer, and the second inductor pattern overlapping the first inductor pattern and the first stop-gate region in the stacking direction.

9. The method of claim 8, wherein after the first die is bonded to the second die, the first inductor pattern partially overlaps with the second inductor pattern to include overlapping and non-overlapping regions.

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