Semiconductor device package and methods of formation

Abstract

Some embodiments of this disclosure provide a semiconductor device package including a first integrated circuit die and a second integrated circuit die, wherein the second integrated circuit die is bonded to the first integrated circuit die and is arranged perpendicularly to the first integrated circuit die. The first integrated circuit die includes a bonding via coupled to and perpendicularly adjacent to a metal pad structure, a barrier liner located on a plurality of sidewalls of the bonding via, a bonding pad coupled to and perpendicularly adjacent to the bonding via, and a dielectric layer located on a plurality of sidewalls of the bonding pad, wherein the bonding via is perpendicularly located between the bonding pad and the metal pad structure, and the barrier liner and the dielectric layer comprise different materials.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor die packages may include a plurality of integrated circuit (IC) dies providing various functionalities. Examples of integrated circuit dies include system-on-chip (SoC) IC dies, dynamic random access memory (DRAM) IC dies, logic IC dies, and / or high bandwidth memory (HBM) IC dies, or other examples. Some semiconductor die packages include an interposer layer that allows the IC dies to be arranged laterally thereon. In some semiconductor die packages, the IC dies are arranged vertically using, for example, three-dimensional (3D) packaging techniques with direct bonding. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A through 1C illustrate examples of semiconductor die packaging described herein. Figures 2A through 2D illustrate example top-view shapes of the jointing pads described herein. Figures 3A through 3H illustrate example embodiments of forming the integrated circuit die described herein. Figures 4A through 4K illustrate example embodiments of the integrated circuit die described herein. Figures 5A through 5H illustrate example embodiments of the semiconductor die package described herein. Figures 6 through 9 illustrate example embodiments of bonding configurations in semiconductor die packages described herein, in which bonding pads of an integrated circuit die are bonded to another integrated circuit die. Figure 10 illustrates a flowchart of an example fabrication process for forming the semiconductor device described herein. Figure 11 illustrates a flowchart of an example process for forming the semiconductor device described herein. Implementation

[0005] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, this document may use spatial relative terms such as "below," "under," "lower," "above," "upper," etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0007] When a first integrated circuit (IC) die and a second integrated circuit die are stacked together within a device package, the substrate layer of the first IC die may include one or more through-substrate interconnect structures to facilitate signal and / or power transmission between the two IC dies. The through-substrate interconnect structures (sometimes referred to as through-silicon vias or through-substrate vias, TSVs) may extend between conductive structures on the front side and conductive structures on the rear side of the substrate layer, and may be electrically coupled to these conductive structures. The conductive structures located on the rear side of the substrate layer and coupled to the through-substrate interconnect structures may be bonded to bonding structures (e.g., bonding vias, bonding pads) of the second IC die.

[0008] The bonding structure of the second integrated circuit die can be formed of a metallic material such as copper (Cu). The metallic material of the bonding structure may readily migrate into the surrounding dielectric layer. Therefore, a barrier liner may be included between the bonding structure and the surrounding dielectric layer to avoid, minimize, and / or reduce the possibility of material migration into the surrounding dielectric layer, which could otherwise cause leakage current in the bonding structure.

[0009] Barrier liners that impede material migration are typically formed of hard materials highly resistant to material removal processes such as chemical mechanical planarization (CMP) and polishing, such as tantalum nitride (TaN) and / or titanium nitride (TiN). In contrast, the bonding structure is made of a softer metallic material, and therefore, for CMP / polishing, the metallic material of the bonding structure may have a faster material removal rate than the material of the barrier liner included on the sidewalls of the bonding structure. This difference in material removal rates can result in uneven material removal between the bonding structure and the barrier liner, potentially removing too much material from the bonding structure and creating voids between them. These voids can lead to weak electrical connections (or breaks) between the bonding structure and the through-substrate interconnects (degrading the electrical performance of the device package), and / or can reduce the bonding mechanical strength between the bonding structure and the through-substrate interconnects, increasing the likelihood of delamination between the first integrated circuit die and the second integrated circuit die.

[0010] In some embodiments described herein, a first integrated circuit die and a second integrated circuit die are bonded together in a stacked configuration within a device package. The second integrated circuit die includes at least one bonding structure bonded to the first integrated circuit die. The bonding structure is formed in such a manner that a barrier layer is omitted from the top sidewall of the bonding structure. After the bonding structure is formed, the barrier layer is removed and replaced by a dielectric liner formed on the sidewall.

[0011] The material removal rate of the dielectric liner (used in processes such as chemical mechanical planarization, polishing, and / or chemical surface cleaning) is closer to that of the bonding structure than that of the barrier liner. Removing too much material from the bonding structure can create voids, while the aforementioned structure can reduce the likelihood of these voids forming between the first integrated circuit die and the second integrated circuit die.

[0012] In this manner, removing the barrier liner around the top of the bonding structure can create a strong electrical connection between the bonding structure and the first integrated circuit die, thereby reducing the electrical resistance and / or power consumption of the device package and improving its electrical performance. Additionally and / or alternatively, removing the barrier liner around the top of the bonding structure can increase the bonding mechanical strength between the bonding structure and the first integrated circuit die, thus reducing the likelihood of delamination between the first and second integrated circuit dies.

[0013] Figures 1A through 1C illustrate an example 100 of the semiconductor die package 102 described herein. The semiconductor die package 102 includes a packaged semiconductor device, wherein the semiconductor device includes a plurality of active integrated circuit dies or wafers. The plurality of active integrated circuit dies can be vertically aligned and / or stacked in the semiconductor die package 102 using, for example, direct-attachment three-dimensional packaging techniques.

[0014] Figure 1A illustrates a top view of semiconductor die package 102. As shown in Figure 1A, semiconductor die package 102 includes integrated circuit die 104. Integrated circuit die 104 is an integrated circuit die that includes active integrated circuitry of semiconductor die package 102 and is configured to perform multiple processing functions of semiconductor die package 102. Examples of integrated circuit chips 104 include logic integrated circuit chips, memory integrated circuit chips, high-bandwidth memory (HBM) integrated circuit chips, input / output (I / O) chips, system-on-chip (SoC) integrated circuit chips, dynamic random access memory (DRAM) integrated circuit chips, complementary metal-oxide-semiconductor (CMOS) image sensor integrated circuit chips, silicon photonics integrated circuit chips, central processing unit (CPU) integrated circuit chips, graphics processing unit (GPU) integrated circuit chips, digital signal processing (DSP) integrated circuit chips, application-specific integrated circuit (ASIC) integrated circuit chips, and / or other types of active integrated circuit chips.

[0015] As further shown in Figure 1A, the semiconductor die package 102 further includes an integrated circuit die 106. The integrated circuit die 104 includes the integrated circuit die 106 such that the integrated circuit die 104 and the integrated circuit die 106 are stacked and vertically arranged along the z-direction in the semiconductor die package 102. In some embodiments, the integrated circuit die 104 and the integrated circuit die 106 are the same type of active integrated circuit die. For example, the integrated circuit die 104 and the integrated circuit die 106 may each be a separate central processing unit die. In some embodiments, the integrated circuit die 104 and the integrated circuit die 106 are different types of active integrated circuit dies. For example, the integrated circuit die 104 may be a central processing unit die, and the integrated circuit die 106 may be an input / output die or a high-bandwidth memory die.

[0016] As further shown in Figure 1A, the top view area of ​​integrated circuit die 106 may differ from the top view area of ​​integrated circuit die 104. For example, the top view dimension of integrated circuit die 104 (e.g., the xy area occupied by integrated circuit die 104) may be larger than the top view dimension of integrated circuit die 106 (e.g., the xy area occupied by integrated circuit die 106). Alternatively, the top view areas of integrated circuit die 104 and integrated circuit die 106 may be approximately the same.

[0017] In some embodiments where integrated circuit die 104 and integrated circuit die 106 have different top view areas, one or more passive dies 108a and / or passive dies 108b may be included above and / or on integrated circuit die 104, located in a region where integrated circuit die 104 extends laterally beyond integrated circuit die 106. Passive dies 108a and / or passive dies 108b may each be a die including passive components and / or a die that does not perform electronic and / or processing functions of semiconductor die package 102. Examples of passive dies 108a and / or passive dies 108b include dummy dies, integrated passive device (IPD) dies, dielectric structures (e.g., thick films), and / or other types of passive dies. Passive dies may also be referred to as insertion dies, fill dies, and / or other die types that do not perform electronic and / or processing functions of semiconductor die package 102. Integrated passive device chips may include capacitors or capacitor chips, resistors or resistor chips, inductors or inductor chips, or combinations thereof.

[0018] The passive die 108a and the integrated circuit die 106 may be in physical contact (e.g., physically in contact with each other) or may be separated by a gap 110. The passive die 108b and the integrated circuit die 106 may be in physical contact (e.g., physically in contact with each other) or may be separated by a gap 110. In some embodiments, the passive die 108a and the passive die 108b may be in physical contact (e.g., physically in contact with each other) or may be separated by a gap 110.

[0019] Figure 1B illustrates a cross-sectional view of the semiconductor die package 102 along line AA in Figure 1A. Therefore, the cross-sectional view shown in Figure 1B includes the integrated circuit die 104, the integrated circuit die 106 located above and / or on the integrated circuit die 104, and the passive die 108a located above and / or on the integrated circuit die 104 and laterally adjacent to the integrated circuit die 106. Alternatively, the passive die 108a may be omitted.

[0020] As shown in Figure 1B, integrated circuit die 104 and integrated circuit die 106 are bonded together in a bonding dielectric layer 112 (or bonding film). The bonding dielectric layer 112 comprises one or more types of materials, such as silicon oxide (SiOx) exemplified by silicon dioxide (SiO2) and / or other types of dielectric bonding materials. Integrated circuit die 104 and integrated circuit die 106 can be directly bonded (e.g., without an intermediary layer or other intervening structure between them), such that integrated circuit die 104 and integrated circuit die 106 are stacked and vertically aligned along the z-direction in the semiconductor die package 102.

[0021] As further shown in Figure 1B, dielectric filling layer 114a fills the region surrounding the sides of integrated circuit die 104, such that dielectric filling layer 114a surrounds integrated circuit die 104, and dielectric filling layer 114b fills the region surrounding the sides of integrated circuit die 106 and non-active die 108a (including gap 110), such that dielectric filling layer 114b surrounds integrated circuit die 106. Dielectric filling layer 114b may further surround non-active die 108a and non-active die 108b. Dielectric filling layer 114a and dielectric filling layer 114b may each include one or more dielectric materials, such as silicon oxide (SiOx), silicon oxynitride (SiON), and / or other types of dielectric materials, exemplified by silicon dioxide (SiO2). The dielectric filling layers 114a and 114b can increase the stability and electrical isolation of the integrated circuit die 104 and the integrated circuit die 106.

[0022] The semiconductor die package 102 includes a plurality of passivation layers, wherein the passivation layers include passivation layers 116 and 118 on and / or above the bottom side of the semiconductor die package 102, and passivation layers 120, 122, and 124 on and / or above the top side of the semiconductor die package 102, or other examples besides the above. In some embodiments, passivation layers 116, 118, 120, 122, and 124 may each include various types of electrically insulating materials, such as silicon nitride (SixNy), undoped silicate glass (USG), silicon oxide (SiOx) such as silicon dioxide (SiO2), and / or other types of passivation materials.

[0023] Integrated circuit die 104 and integrated circuit die 106 may each include a substrate (e.g., substrate 126a in integrated circuit die 104 and substrate 126b in integrated circuit die 106). Substrate 126a and substrate 126b may each include a silicon (Si) substrate, a substrate formed of a silicon-containing material, such as a gallium arsenide (GaAs) III-V compound semiconductor material substrate, a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates.

[0024] Integrated circuit die 104 and integrated circuit die 106 may each include a plurality of stacked layers, including interlayer dielectric (ILD) layers (e.g., interlayer dielectric layer 128a on substrate 126a and interlayer dielectric layer 128b on substrate 126b). Interlayer dielectric layer 128a and interlayer dielectric layer 128b may each include silicon nitride (SixNy), oxide (e.g., silicon oxide (SiOx) and / or other oxide materials) and / or other types of dielectric materials.

[0025] Integrated circuit die 104 and integrated circuit die 106 may each include an integrated circuit device (e.g., integrated circuit device 130a in substrate 126a and / or interlayer dielectric layer 128a, integrated circuit device 130b in substrate 126b and / or interlayer dielectric layer 128b). Integrated circuit device 130a and integrated circuit device 130b may include front-end transistor structures (e.g., front-end planar transistor structure, front-end fin field-effect transistor (finFET) structure, front-end gate all-around (GAA) transistor structure), pixel sensors, capacitors, resistors, inductors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices.

[0026] Integrated circuit die 104 and integrated circuit die 106 may each include contacts (e.g., contact 132a, contact 132b) electrically coupled to the integrated circuit device. Contact 132a may extend through interlayer dielectric layer 128a and may be electrically coupled to integrated circuit device 130a, while contact 132b may extend through interlayer dielectric layer 128b and may be electrically coupled to integrated circuit device 130b. Contacts 132a and 132b may include vias, plugs, and / or other types of extended conductive structures. Contacts 132a and 132b may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au), or other electrically conductive materials other than those described above.

[0027] Integrated circuit die 104 and integrated circuit die 106 may each include a plurality of dielectric layers, wherein these dielectric layers are alternately arranged along the z-direction in the semiconductor die package 102. For example, integrated circuit die 104 may include a plurality of alternating interlayer dielectric layers 134a and etch stop layers (ESL) 136a. Integrated circuit die 104 may include a plurality of conductive structures 138a in the interlayer dielectric layers 134a and etch stop layers 136a. Substrate 126a, interlayer dielectric layers 128a, integrated circuit devices 130a and contacts 132a may correspond to the device layer or front end of line (FEOL) region of integrated circuit die 104, while interlayer dielectric layers 134a, etch stop layers 136a and conductive structures 138a may correspond to the interconnect layer or back end of line (BEOL) region of integrated circuit die 104.

[0028] Similarly, the integrated circuit die 106 may include a plurality of alternating interlayer dielectric layers 134b and etch stop layers 136b. The integrated circuit die 106 may include a plurality of conductive structures 138b in the interlayer dielectric layers 134b and etch stop layers 136b. The substrate 126b, interlayer dielectric layers 128b, integrated circuit devices 130b, and contacts 132b may correspond to the device layer or FEOL region of the integrated circuit die 106, while the interlayer dielectric layers 134b, etch stop layers 136b, and conductive structures 138b may correspond to the interconnect layer or BEOL region of the integrated circuit die 106.

[0029] Interlayer dielectric layers 134a and 134b may each comprise an oxide (e.g., silicon oxide (SiOx) and / or other oxide materials), undoped silicate glass, boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, interlayer dielectric layer 134a or interlayer dielectric layer 134b comprises an extremely low dielectric constant (ELK) dielectric material having a dielectric constant below approximately 2.5. Examples of dielectric materials with extremely low dielectric constants include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiOx), or other examples not listed above. Etch stop layers 136a and 136b may each comprise silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials.

[0030] Conductive structures 138a and 138b provide electronic paths that can provide signals and / or power to, and / or from, integrated circuit devices 130a and / or 130b. Conductive structures 138a and 138b may include trenches, metallization layers, wires, vias, interconnects, and / or combinations of other types of conductive structures. Conductive structures 138a and 138b may each include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, or other examples of electrically conductive materials.

[0031] The integrated circuit die 104 may further include a sealing ring structure 140a surrounding the conductive structure 138a to protect the integrated circuit die 104 from physical and / or electronic damage during the dicing operation separating the integrated circuit die 104 from the wafer. The sealing ring structure 140a may further provide protection against moisture intrusion and other contamination. Similarly, the integrated circuit die 106 may include a sealing ring structure 140b surrounding the conductive structure 138b to protect the integrated circuit die 106 from physical and / or electronic damage during the dicing operation separating the integrated circuit die 106 from the wafer. The sealing ring structure 140b may further provide protection against moisture intrusion and other contamination.

[0032] The integrated circuit die 104 may include passivation layers 142a and 144a above and / or on alternating plurality of dielectric layers (e.g., interlayer dielectric layer 134a and etch stop layer 136a) to passivate the interconnect layers of the integrated circuit die 104. Similarly, the integrated circuit die 106 may include passivation layers 142b and 144b above and / or on alternating plurality of dielectric layers (e.g., interlayer dielectric layer 134b and etch stop layer 136b) to passivate the interconnect layers of the integrated circuit die 106.

[0033] A metal gasket structure 146a may be included on and / or on the conductive structure 138a, and a metal gasket structure 148a may be included on and / or on the sealing ring structure 140a. A metal gasket structure 146b may be included on and / or on the conductive structure 138b, and a metal gasket structure 148b may be included on and / or on the sealing ring structure 140b. The metal gasket structures 146a and 148a may be included in and / or extend through the passivation layers 142a and / or 144a. The metal gasket structures 146b and 148b may be included in and / or extend through the passivation layers 142b and / or 144b.

[0034] Metal pad structures 146a, 148a, 146b, and 148b may each comprise aluminum (Al), aluminum-copper (AlCu), copper (Cu), and / or other conductive materials. Metal pad structures 146a and 148a may correspond to the redistribution layer (RDL) of integrated circuit die 104, while metal pad structures 146b and 148b may correspond to the redistribution layer of integrated circuit die 106.

[0035] A dielectric layer 150a may be included above the passivation layer 144a, and a dielectric layer 150b may be included above the passivation layer 144b. Dielectric layers 150a and 150b may be capping layers and may include one or more dielectric layers, such as silicon oxide (SiOx, e.g., SiO2), silicon nitride (SixNy, e.g., Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and / or silicon carbonitride (SiCN), or other examples not described above. A bonding dielectric layer 112 for the integrated circuit die 106 may be included above the dielectric layer 150b.

[0036] Sealing ring structure 140a and sealing ring structure 140b may further include bonding gasket 152a and bonding gasket 152b, respectively. Alternatively, bonding gasket 152a and / or bonding gasket 152b may be omitted. Bonding gasket 152a and bonding gasket 152b may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, or other electrically conductive materials not mentioned above.

[0037] The integrated circuit die 104 further includes a bonding layer 154, wherein the bonding layer 154 is used to bond the integrated circuit die 104 to a carrier substrate during the fabrication of the semiconductor die package 102. The bonding layer 154 includes one or more types of materials, such as silicon oxide (SiOx) exemplified by silicon dioxide (SiO2) and / or other types of dielectric bonding materials.

[0038] The integrated circuit die 106 may further include one or more bonding vias 156 and / or one or more bonding pads 158, thereby allowing the integrated circuit die 106 to be bonded to the integrated circuit die 104. The bonding vias 156 and / or bonding pads 158 may extend through the bonding dielectric layer 112, the dielectric layer 150b, and / or the passivation layer 144b, and may be electrically coupled and / or physically coupled to one or more metal pad structures 146b. The bonding vias 156 and bonding pads 158 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, or other electrically conductive materials not mentioned above.

[0039] In some embodiments, the bonding vias 156 and / or bonding pads 158 of the integrated circuit die 106 can be electrically coupled to a through-substrate interconnect structure 160, which extends through the substrate 126a of the integrated circuit die 104. The through-substrate interconnect structure 160 may include die-to-die wires, substrate vias, or other types of die-to-die interconnects. The through-substrate interconnect structure 160 also electrically connects the integrated circuit die 104 and the integrated circuit die 106. In this manner, electronic signals and / or power can be provided between the integrated circuit die 104 and the integrated circuit die 106 through the through-substrate interconnect structure 160.

[0040] The through-substrate interconnect structure 160 includes a conductive material, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, or other examples of conductive materials not listed above. The through-substrate interconnect structure 160 may include vias, pillars, columns, and / or other types of extended conductive structures, such that the extended conductive structures extend between the front side (the side of substrate 126a including conductive structure 138a) of the substrate 126a of the integrated circuit die 104 and the rear side of the substrate 126a of the integrated circuit die 104, wherein the rear side is perpendicular to the front side. The rear side of the integrated circuit die 104 may be bonded to the integrated circuit die 106, and bonding pads 162 on the rear side of the integrated circuit die 104 may be bonded to bonding pads 158 of the integrated circuit die 106.

[0041] As further shown in Figure 1B, the top layer (e.g., top metal layer) of the conductive structure 138a of the integrated circuit die 104 can be coupled to a connection structure 164 located on top of the semiconductor die package 102 (facing downwards in Figure 1B). The connection structure 164 may include solder balls, solder bumps, contact pads (e.g., pads of a land grid array (LGA), contact pins (e.g., pins of a pin grid array (PGA), under bump metallization (UBM) connectors, microbumps, balls of a ball grid array (BGA), controlled collapse chip connection (C4) bumps, and / or other types of connection structures that allow the semiconductor die package 102 to be connected to a substrate or socket, or other examples besides those described above.

[0042] Figure 1C illustrates an enlarged view of portion 166 of the integrated circuit die 106 in Figure 1B. As shown in Figure 1C, the metal pad structure 146b may include one or more via portions 168 extending through the passivation layer 142b, and the passivation layer 144b includes trench portions 170. A barrier liner 172 may be included between the via portions 168 and the passivation layer 142b. The barrier liner 172 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and / or other layers that prevent material from migrating from the via portions 168 into the passivation layer 142b. In some embodiments, the barrier liner 172 is included between the via portion 168 and the topmost conductive structure 138b. In some embodiments, the barrier liner 172 is omitted at the interface between the via portion 168 and the topmost conductive structure 138b, and the via portion 168 substantially contacts the topmost conductive structure 138b.

[0043] A dielectric liner 174 may be included on the top surface and sidewalls of the trench portion 170 of the metal liner structure 146b. A dielectric liner 174 may be included between the trench portion 170 and the passivation layer 144b. The dielectric liner 174 may include silicon oxide (SiOx, e.g., SiO2), silicon nitride (SixNy, e.g., Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and / or silicon carbonitride (SiCN), or other examples besides those described above.

[0044] As further shown in Figure 1C, the bonding via 156 may be perpendicularly adjacent (e.g., along the z-direction) to the metal pad structure 146b and may be coupled to the trench portion 170 of the metal pad structure 146b. The bonding via 156 may extend through the dielectric layer 150b and into the passivation layer 144b to the metal pad structure 146b. A barrier liner 176 may be included on the sidewall of the bonding via 156 between the bonding via 156 and the dielectric layer 150b. In some embodiments, a barrier liner 176 is also included between the bottom of the bonding via 156 and the trench portion 170 of the metal pad structure 146b. In some embodiments, the barrier liner 176 is omitted from the bottom of the bonding via 156, such that the bonding via 156 contacts the trench portion 170 of the metal pad structure 146b.

[0045] As further shown in Figure 1C, the bonding pad 158 may be perpendicularly adjacent (e.g., along the z-direction) to the bonding via 156 and may be electrically coupled and / or physically coupled to the bonding via 156. The bonding dielectric layer 112 may include the bonding pad 158, and / or the bonding pad 158 may extend through the bonding dielectric layer 112.

[0046] The sidewalls of the bonding pad 158 may include a dielectric liner 178 replacing the barrier liner 176. During the formation of the integrated circuit die 106, the bonding pad 158 may be formed on the bonding via 156 such that the barrier liner 176 contacts the sidewalls of the bonding pad 158. Subsequently, the barrier liner 176 is removed from the sidewalls of the bonding pad 158 and replaced by the dielectric liner 178. The dielectric liner 178 may be formed before the formation of the bonding dielectric layer 112, and the dielectric liner 178 may thus extend between the dielectric layer 150b and the bonding dielectric layer 112.

[0047] The barrier liner 176 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and / or other layers that prevent material migration from the bonding via 156 into the dielectric layer 150b. The dielectric liner 178 is formed after the bonding pad 158 is formed. Because a high-temperature process (e.g., copper reflow annealing) for forming the bonding pad 158 has been performed prior to the formation of the dielectric liner 178, the dielectric liner 178 is less susceptible to material migration from the bonding pad 158 during the high-temperature process.

[0048] The dielectric liner 178 may include silicon oxide (SiOx, e.g., SiO2), silicon nitride (SixNy, e.g., Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and / or silicon carbonitride (SiCN), or other examples besides those listed above. The material of the dielectric liner 178 may have a lower material hardness than the barrier liner 176, and the material hardness of the dielectric liner 178 may be closer to the material hardness of the bonding pad 158 than the material of the barrier liner 176. In some embodiments, the dielectric liner 178 comprises a low-k dielectric material having a dielectric constant lower than that of the material of the dielectric liner 178 (e.g., lower than that of TaN, lower than that of TiN). Low-dielectric-constant dielectric materials tend to have lower material hardness than high-dielectric-constant dielectric materials. Therefore, the material removal rate of low-dielectric-constant dielectric materials (used in processes such as chemical mechanical planarization, polishing, and / or chemical surface cleaning) is closer to the material removal rate of the bonding pad 158 than that of the barrier liner 176. This reduces the possibility of dishing and / or crowding on the surface of the bonding pad 158, and thus reduces the possibility of voids forming between the bonding pad 158 and the integrated circuit die 104.

[0049] In some embodiments, the bonding via 156 and the bonding pad 158 form a single structure, referred to as bonding structure 180. The bonding via 156 may correspond to the via portion (or bottom) of bonding structure 180, and the bonding pad 158 may correspond to the pad portion (or top) of bonding structure 180. Bonding structure 180 may be called a "bonding structure" because it is used to bond integrated circuit die 106 to integrated circuit die 104. Examples and descriptions of different bonding types can be found in Figures 6 through 9.

[0050] As further shown in Figure 1C, the engagement via 156 may have a top width corresponding to dimension D1 (e.g., located at the top of the engagement via 156), and the engagement gasket 158 ​​may have a width corresponding to dimension D2. In some embodiments, dimensions D1 and D2 are approximately equal. In some embodiments, dimension D2 is greater than dimension D1, such that the engagement gasket 158 ​​extends laterally beyond the sidewall of the engagement via 156.

[0051] In some embodiments, the connecting via 156 may have a bottom width corresponding to dimension D3 (e.g., located at the bottom of the connecting via 156). In some embodiments, dimensions D1 and D3 are approximately equal. In some embodiments, dimension D1 is greater than dimension D3. In some embodiments, the maximum value of dimension D1 is approximately 100,000 times the minimum value of dimension D1. However, other values ​​and ranges of dimension D1 are also within the scope of embodiments of this disclosure.

[0052] As described above, Figures 1A through 1C are provided as an example. Other examples may differ from those shown in Figures 1A through 1C.

[0053] Figures 2A through 2D illustrate example top view shapes of the bonding pad 158 described herein. Figures 2A through 2D provide multiple examples, but other example top view shapes of the bonding pad 158 are also within the scope of embodiments of this disclosure. Additionally, the integrated circuit die 106 may include a plurality of bonding pads 158 having combinations of the example top view shapes.

[0054] As shown in Figure 2A, the example top view shape 200 includes an approximately circular top view shape. The dimension D2 of the joining pad 158 may correspond to the diameter of the approximately circular top view shape of the joining pad 158.

[0055] As shown in Figure 2B, the example top view shape 202 includes an approximately hexagonal top view shape. The dimension D2 of the joining pad 158 may correspond to the maximum diameter of the approximately hexagonal top view shape of the joining pad 158.

[0056] As shown in Figure 2C, the example top view shape 204 includes an approximately rectangular top view shape. The dimension D2 of the joining pad 158 may correspond to the width of the joining pad 158 along the short side of the approximately rectangular top view shape, and the dimension D3 of the joining pad 158 may correspond to the width of the joining pad 158 along the long side of the approximately rectangular top view shape.

[0057] As shown in Figure 2D, the example top view shape 206 includes an approximately L-shape having a first top view segment 208a and a second top view segment 208b, wherein the ends of the first top view segment 208a and the second top view segment 208b are joined together. The dimension D2 of the joining pad 158 may correspond to the width of the first top view segment 208a along its short side, and the dimension D4 of the joining pad 158 may correspond to the width of the first top view segment 208a along its long side. The dimension D5 of the joining pad 158 may correspond to the width of the second top view segment 208b along its short side, and the dimension D6 of the joining pad 158 may correspond to the width of the second top view segment 208b along its long side.

[0058] In some embodiments, dimensions D2 and D5 are approximately equal. In some embodiments, dimensions D2 and D5 are different values. In some embodiments, dimensions D4 and D6 are approximately equal. In some embodiments, dimensions D4 and D6 are different values.

[0059] As described above, Figures 2A through 2D are provided as an example. Other examples may differ from those shown in Figures 2A through 2D.

[0060] Figures 3A through 3H illustrate an example embodiment 300 for forming the integrated circuit die described herein. While the process steps of example embodiment 300 are illustrated and described in relation to forming the integrated circuit die 104 described herein, the process steps of example embodiment 300 can be used to form other integrated circuit dies described herein, such as integrated circuit die 106. In some embodiments, one or more semiconductor process tools may be used to perform the one or more semiconductor process steps described with respect to Figures 3A through 3H, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0061] Referring to Figure 3A, a substrate 126a is provided for an integrated circuit die 104. The substrate 126a may be in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor components.

[0062] As shown in Figure 3B, an integrated circuit device 130a may be formed in and / or on a substrate 126a of an integrated circuit die 104. One or more semiconductor process tools may be used to form one or more portions of the integrated circuit device 130a. For example, a deposition tool may be used to perform multiple deposition operations to deposit layers and / or structures of the integrated circuit device 130a, and / or deposit a photoresist layer for etching the substrate 126a and / or portions of the deposited layers. As another example, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a developing tool may be used to develop the pattern in the photoresist layer. As another example, an etching tool may be used to etch the substrate 126a and / or portions of the deposited layers to form the integrated circuit device 130a. As another example, a planarization tool may be used to planarize portions of the integrated circuit device 130a. As another example, an electroplating tool may be used to deposit metal structures and / or layers of the integrated circuit device 130a.

[0063] As further shown in Figure 3B, a deposition tool is used to deposit an interlayer dielectric layer 128a over and / or on the substrate 126a and the integrated circuit device 130a. The deposition tool may use physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques to deposit the interlayer dielectric layer 128a. In some embodiments, a planarization tool may be used to perform a planarization operation, such as chemical mechanical planarization, to planarize the interlayer dielectric layer 128a after deposition.

[0064] As shown in Figure 3C, contacts 132a of an integrated circuit device 130a can be formed through the interlayer dielectric layer 128a. Contacts 132a can be formed within grooves in the interlayer dielectric layer 128a. In some embodiments, a pattern in the photoresist layer is used to etch the interlayer dielectric layer 128a to form grooves. In these embodiments, a deposition tool can be used to form a photoresist layer on the interlayer dielectric layer 128a. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer based on the pattern to form grooves. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique to form grooves based on patterned etching of the interlayer dielectric layer 128a.

[0065] The deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit material for contact 132a in the groove. Material for contact 132a can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the material for contact 132a is deposited on the seed layer. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize contact 132a after deposition, such that the top of contact 132a is approximately coplanar with the top of interlayer dielectric layer 128a.

[0066] As shown in Figure 3C, a first portion of the interconnect layer of the integrated circuit die 104 is formed over the interlayer dielectric layer 128a. One or more deposition tools are used to deposit alternating layers of interlayer dielectric layer 134a and etch stop layer 136a in the first portion of the interconnect layer of the integrated circuit die 104. In this manner, the interlayer dielectric layer 134a and etch stop layer 136a can be aligned along the z-direction of the integrated circuit die 104. One or more deposition tools can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the respective interlayer dielectric layer 134a and etch stop layer 136a. In some embodiments, a planarization tool can be used to planarize the interlayer dielectric layer 134a and / or etch stop layer 136a after deposition.

[0067] As further shown in Figure 3C, deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools can be used to perform multiple operations to form a first portion of the sealing ring structure 140a in the first portion of the interconnect layer of the conductive structure 138a and the integrated circuit die 104. The first portion of the conductive structure 138a and the sealing ring structure 140a can be included in the interlayer dielectric layer 134a and / or the etch stop layer 136a.

[0068] The first portion of the conductive structure 138a and the sealing ring structure 140a may be formed within a groove in one or more interlayer dielectric layers 134a and / or one or more etch stop layers 136a. In some embodiments, a pattern in the photoresist layer is used to etch the interlayer dielectric layer 134a and the etch stop layer 136a to form the groove. In these embodiments, a deposition tool may be used to form the photoresist layer on the topmost interlayer dielectric layer 134a. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the interlayer dielectric layer 134a and the etch stop layer 136a based on the pattern to form the groove. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique for forming grooves based on patterned etched interlayer dielectric layer 134a and etch stop layer 136a.

[0069] The deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit material of the first portion of the conductive structure 138a and the sealing ring structure 140a in the groove. The material of the first portion of the conductive structure 138a and the sealing ring structure 140a can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the material of the first portion of the conductive structure 138a and the sealing ring structure 140a is deposited on the seed layer. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the first portion of the conductive structure 138a and the sealing ring structure 140a.

[0070] As shown in Figure 3D, a through-substrate interconnect structure 160 is formed through the first portion of the interconnect layer and extends into the substrate 126a. To form the through-substrate interconnect structure 160, a groove is formed through the first portion of the interconnect layer and extends into the substrate 126a.

[0071] In some embodiments, the pattern in the photoresist layer is used to etch the interlayer dielectric layer 134a and etch stop layer 136a, interlayer dielectric layer 128a, and substrate 126a of a first portion of the interconnect layer to form a groove. In these embodiments, a deposition tool can be used to form the photoresist layer on the topmost interlayer dielectric layer 134a. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the interlayer dielectric layer 134a and etch stop layer 136a, interlayer dielectric layer 128a, and substrate 126a of the first portion of the interconnect layer based on the pattern to form a groove. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique to pattern-based groove formation.

[0072] Deposition tools can be used to deposit the through-substrate interconnect structure 160 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. The through-substrate interconnect structure 160 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the through-substrate interconnect structure 160 is deposited on the seed layer. In some embodiments, one or more liners (e.g., barrier liners, adhesive liners) can be deposited first in a trench, and the through-substrate interconnect structure 160 can be deposited on one or more liners in the trench. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the through-substrate interconnect structure 160 after deposition.

[0073] As shown in Figure 3E, a second portion of the interconnect layer of the integrated circuit die 104 may be formed. Forming the second portion of the interconnect layer may include forming additional interlayer dielectric layers 134a, additional etch stop layers 136a, additional conductive structures 138a, and / or additional sealing ring structures 140a in a manner similar to that shown in Figure 3C. As further shown in Figure 3E, a passivation layer 142a may be deposited, metal pad structures 146a may be formed on one or more conductive structures 138a, and one or more metal pad structures 148a may be formed on the sealing ring structure 140a. The passivation layer 144a may be deposited on the passivation layer 142a.

[0074] As shown in Figure 3F, a bonding pad 152a may be formed on the metal pad structure 148a. In some embodiments, the bonding pad may also be formed on one or more conductive structures 138a. Additionally, a dielectric layer 150a may be formed over the passivation layer 144a, and a bonding layer 154 may be formed over the dielectric layer 150a. Another bonding layer 302 may be formed on the bonding layer 154. In some embodiments, an etch stop layer is deposited on the bonding layer 154, and the bonding layer 302 is deposited on the etch stop layer.

[0075] The deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit the bonding pad 152a. The bonding pad 152a can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the bonding pad 152a is deposited on the seed layer. In some embodiments, one or more liners (e.g., barrier liners, adhesive liners) can be deposited first in the groove, and the bonding pad 152a can be deposited on one or more liners in the groove. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the bonding pad 152a after deposition.

[0076] The deposition tools can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit dielectric layer 150a, bonding layer 154, and bonding layer 302. Dielectric layer 150a, bonding layer 154, and bonding layer 302 can be deposited in one or more deposition operations. In some embodiments, planarization tools are used to perform planarization operations (e.g., chemical mechanical planarization) to planarize dielectric layer 150a, bonding layer 154, and bonding layer 302 after deposition.

[0077] As shown in Figure 3G, the integrated circuit die 104 is bonded to the carrier substrate 304 using bonding layers 302 and 306. Therefore, the integrated circuit die 104 can be flipped or rotated 180 degrees to bond it to the carrier substrate 304. Additionally, the bonding layer 306 (e.g., a fused bonding layer or other type of bonding layer) included on the carrier substrate 304 is used to bond the integrated circuit die 104 and the carrier substrate 304. Bonding tools can be used to bond the integrated circuit die 104 to the carrier substrate 304 using fused bonding technology and / or other bonding techniques.

[0078] As shown in Figure 3H, the dielectric filling layer 114a fills the region surrounding the integrated circuit die 104. The dielectric filling layer 114a can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The dielectric filling layer 114a can be deposited in one or more deposition operations.

[0079] As further shown in Figure 3H, a planarization tool or wafer polishing tool can be used to perform a planarization operation (e.g., chemical mechanical planarization, wafer polishing) to planarize the dielectric filler layer 114a and remove material from the back side of the substrate 126a, thereby exposing the back side of the substrate 126a to the through-substrate interconnect structure 160.

[0080] As further shown in Figure 3H, the bonding dielectric layer 308 is formed above and / or on the rear side of the substrate 126a of the integrated circuit die 104. The bonding dielectric layer 112 can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the bonding dielectric layer 112.

[0081] As further shown in Figure 3H, the deposition tool can use chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques to deposit bonding pads 162 on the back side of substrate 126a. Bonding pads 162 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and bonding pads 162 are deposited on the seed layer. In some embodiments, one or more liners (e.g., barrier liners, adhesive liners) can be deposited first in a recess, and bonding pads 162 can be deposited on one or more liners in the recess. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize bonding pads 162 after deposition.

[0082] As described above, Figures 3A through 3H are provided as an example. Other examples may differ from those described in Figures 3A through 3H.

[0083] Figures 4A through 4K illustrate an example embodiment 400 for forming the integrated circuit die described herein. While the process steps of example embodiment 400 are illustrated and described in relation to forming the integrated circuit die 106 described herein, the process steps of example embodiment 400 can be used to form other integrated circuit dies described herein, such as integrated circuit die 104. In some embodiments, one or more semiconductor process tools may be used to perform the one or more semiconductor process steps described with respect to Figures 4A through 4K, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0084] As shown in Figure 4A, similar process steps as described with respect to Figures 3A to 3E can be performed to form integrated circuit devices 130b, interlayer dielectric layer 128b, contacts 132b, interlayer dielectric layer 134b, etch stop layer 136b, vertically aligned layers of conductive structures 138b, sealing ring structure 140b, passivation layer 142b, passivation layer 144b, metal pad structure 146b, and / or metal pad structure 148b in and / or on the substrate 126b of the integrated circuit die 106.

[0085] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4B, a dielectric layer 150b may be formed above and / or on the passivation layer 144b, such that the dielectric layer 150b is located above the metal pad structure 146b of the integrated circuit die 106. As further shown in Figure 4B, a photoresist layer 402 may be formed above and / or on the dielectric layer 150b. The photoresist layer 402 may be formed of one or more photoresist materials, such as organic and / or inorganic photoresist materials. The photoresist material of the photoresist layer 402 may be photosensitive, and therefore the photoresist layer 402 can be patterned using photolithography.

[0086] The deposition tool can use physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques to deposit the dielectric layer 150b. The dielectric layer 150b can be deposited in one or more deposition operations. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the dielectric layer 150b after deposition. The deposition tool can use spin coating techniques and / or other suitable deposition techniques to deposit the photoresist layer 402.

[0087] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4C, a groove 404 can be formed through the photoresist layer 402. The groove 404 can be formed above a portion of the metal pad structure 146b. The portion of the groove 404 that extends through the photoresist layer 402 can correspond to the trench portion 406 (or top) of the groove 404.

[0088] An exposure tool can be used to expose the photoresist layer 402 to a radiation source to pattern the photoresist layer 402, thereby forming the trench portion 406 of the recess 404. A development tool can be used to develop and remove portions of the photoresist layer 402 to expose the pattern corresponding to the trench portion 406 of the recess 404. The trench portion 406 of the recess 404 may have substantially vertical sidewalls.

[0089] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4D, the dielectric layer 150b exposed in the trench portion 406 of the recess 404 can be etched to extend the recess 404 through the dielectric layer 150b and to the underlying metal pad structure 146b. Therefore, the recess 404 can extend through the photoresist layer 402, the dielectric layer 150b, and to the underlying metal pad structure 146b. In some embodiments, the recess 404 may also extend through a portion of the passivation layer 144b above the metal pad structure 146b.

[0090] The portion of the groove 404 extending through the dielectric layer 150b may correspond to the via portion 408 of the groove 404. The via portion 408 of the groove 404 may have tapered sidewalls such that the width of the groove 404 at the top of the via portion 408 is greater than the width of the groove 404 at the bottom of the via portion 408. Alternatively, the via portion 408 may have substantially vertical sidewalls.

[0091] An etching tool can be used to etch the dielectric layer 150b based on a pattern in the photoresist layer 402 (e.g., a trench portion 406 corresponding to a recess 404) to form a via portion 408 of a recess in the dielectric layer 150b. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0092] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4E, the barrier liner 176 can be deposited on the sidewalls of the recess 404 and the bottom surface of the recess 404. For example, the barrier liner 176 can be deposited on the sidewalls of the trench portion 406 of the recess 404, the sidewalls of the via portion 408 of the recess 404, and / or the bottom surface of the via portion 408 of the recess 404. The barrier liner 176 can also extend along the top surface of the photoresist layer 402.

[0093] The barrier liner 176 can be conformally deposited in the groove. The deposition tool can be used to deposit the barrier liner 176 using conformal deposition techniques, such as atomic layer deposition and / or chemical vapor deposition, or other examples besides those described above.

[0094] As shown in the enlarged view of portion 166 of integrated circuit die 106 in Figure 4F, a bonding structure 180 may be formed in a groove 404 such that the bonding structure 180 sits on a metal pad structure 146b. Specifically, a bonding via 156 (or via portion or bottom of bonding structure 180) may be formed in a via portion 408 of the groove 404 on the metal pad structure 146b, and a bonding pad 158 (or pad portion or top of bonding structure 180) may be formed in a trench portion 406 of the groove 404 on the bonding via 156. The bonding via 156 may be formed on a barrier liner 176 such that the barrier liner 176 is located between the bonding via 156 and the metal pad structure 146b and between the bonding via 156 and the dielectric layer 150b. A bonding pad 158 may be formed such that the barrier liner 176 is located between the bonding pad 158 and the photoresist layer 402.

[0095] The deposition tool can be used to deposit the bonding structure 180 (or the bonding via 156 and bonding pad 158) using deposition techniques such as atomic layer deposition, chemical vapor deposition, physical vapor deposition and / or electroplating, or other examples besides those described above. As shown in Figure 4F, excess material of the bonding structure 180 can be deposited on the top surface of the photoresist layer 402.

[0096] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4G, a planarization operation can be performed to remove excess material of the bonding structure 180 from the top of the photoresist layer 402. Alternatively, the portion of the barrier liner 176 located on the top surface of the photoresist layer 402 can be removed to expose the photoresist layer 402, allowing the photoresist layer 402 to be removed.

[0097] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4H, the photoresist layer 402 can be removed from the bonding pad 158. In some embodiments, the photoresist removal tool uses a chemical stripping technique to remove the photoresist layer 402, wherein the chemical stripping technique uses a chemical agent to strip or dissolve the photoresist layer 402. In some embodiments, the photoresist removal tool uses a plasma ashing technique to remove the photoresist layer 402, wherein the plasma ashing technique uses plasma decompose to remove the photoresist layer 402. In some embodiments, the photoresist removal tool uses other photoresist removal techniques to remove the photoresist layer 402.

[0098] As further shown in Figure 4H, the portion of the barrier liner 176 located on the sidewall of the bonding pad 158 is also removed. This exposes the sidewall of the bonding pad 158. In some embodiments, the portion of the barrier liner 176 located on the sidewall of the bonding pad 158 is removed during the process of removing the photoresist layer 402. In some embodiments, the process of removing the portion of the barrier liner 176 located on the sidewall of the bonding pad 158 is performed after the photoresist layer 402 is removed.

[0099] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4I, a dielectric liner 178 is conformally deposited on the dielectric layer 150b and the sidewalls and top surface of the bonding pad 158. The deposition tool can be used to deposit the dielectric liner 178 using conformal deposition techniques, such as atomic layer deposition and / or chemical vapor deposition, or other examples besides those described above.

[0100] As further shown in Figure 4I, a bonding dielectric layer 112 is deposited around the bonding pad 158. The bonding dielectric layer 112 is deposited on the dielectric liner 178, and in some embodiments, the bonding dielectric layer 112 is deposited over the bonding pad 158 such that the bonding dielectric layer 112 covers the bonding pad 158. The bonding dielectric layer 112 can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques.

[0101] As shown in the enlarged view of portion 166 of the integrated circuit die 106 in Figure 4J, a planarization operation is performed to remove excess material from the bonding dielectric layer 112, thereby exposing the top surface of the bonding pad 158 through the bonding dielectric layer 112. A planarization tool may be used to perform the planarization operation, and the planarization operation may include chemical mechanical planarization, polishing, and / or other types of planarization operations. Additionally and / or alternatively, an etching operation may be performed to remove excess material from the bonding dielectric layer 112.

[0102] As shown in Figure 4J, the planarization operation results in the top surface of the bonding dielectric layer 112 being approximately coplanar with the top surface of the bonding pad 158. Removing the barrier liner 176 from around the bonding pad 158 can create a substantially uniform surface with minimal or no voids at locations spanning the bonding pad 158 and the bonding dielectric layer 112.

[0103] As shown in Figure 4K, in some embodiments, a mating gasket 152b is also formed on the sealing ring structure 140b. In some embodiments, the mating gasket 152b may be formed in a manner similar to that of the mating gasket 158 ​​illustrated in Figures 4B to 4J.

[0104] As described above, Figures 4A through 4K are provided as an example. Other examples may differ from those described in Figures 4A through 4K.

[0105] Figures 5A through 5H illustrate an example embodiment 500 forming the semiconductor die package 102 described herein. In some embodiments, one or more semiconductor process tools may be used to perform one or more semiconductor process steps described in Figures 5A through 5H, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0106] As shown in Figures 5A and 5B, integrated circuit die 106 is bonded to integrated circuit die 104 such that integrated circuit die 104 and integrated circuit die 106 are stacked and vertically aligned within semiconductor die package 102. In some embodiments, a bonding tool is used to form a dielectric-to-dielectric bond between a bonding dielectric layer 112 on integrated circuit die 106 and a bonding dielectric layer 308 on integrated circuit die 104 to bond integrated circuit die 104 and integrated circuit die 106. In some embodiments, a bonding tool is used to form a metal-to-metal bond between a bonding pad 162 on the rear side of integrated circuit die 104 and a bonding pad 158 on integrated circuit die 106 to bond integrated circuit die 104 and integrated circuit die 106. In some embodiments, the bonding tool is used to form a combination of dielectric-to-dielectric and metal-to-metal bonding to bond integrated circuit die 104 and integrated circuit die 106. In some embodiments, the bonding tool is used to form a dielectric-to-metal bonding between the bonding pad 158 of integrated circuit die 106 and the bonding dielectric layer 308 of integrated circuit die 104 to bond integrated circuit die 104 and integrated circuit die 106.

[0107] As shown in Figures 5C and 5D, inactive dies 108a and 108b may be provided above and / or on the integrated circuit die 104, such that the inactive dies 108a and 108b are laterally adjacent to one or more sides of the integrated circuit die 106. Specifically, inactive dies 108a and 108b may be provided above and / or on the same side of the integrated circuit die 104 that is bonded to the integrated circuit die 106. In some embodiments, inactive dies 108a and / or 108b comprise semiconductor dies (e.g., silicon dies), and are bonded to a bonding dielectric layer 308. In some embodiments, inactive dies 108a and / or 108b comprise a dielectric layer (e.g., a dielectric thick film) deposited on the integrated circuit die 104 using a deposition tool. In these embodiments, chemical vapor deposition, physical vapor deposition, atomic layer deposition, oxidation and / or other suitable deposition techniques can be used to deposit inactive grains 108a and / or inactive grains 108b.

[0108] As shown in Figure 5E, the dielectric filling layer 114b fills the regions surrounding the integrated circuit die 106, the inactive die 108a, and the inactive die 108b. If the integrated circuit die 106, the inactive die 108a, and / or the inactive die 108b are separated by gaps 110, the material of the dielectric filling layer 114b can fill the gaps 110. The dielectric filling layer 114b can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The dielectric filling layer 114b can be deposited in one or more deposition operations. A planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the dielectric filling layer 114b, the substrate 126b of the integrated circuit die 106, the inactive die 108a, and the inactive die 108b, such that the dielectric filling layer 114b, the substrate 126b of the integrated circuit die 106, the inactive die 108a, and the inactive die 108b are approximately coplanar.

[0109] As shown in Figure 5F, passivation layers 120 to 124 are formed or provided over the integrated circuit die 106. Deposition tools can be used to deposit passivation layers 120 to 124 using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. Passivation layers 120 to 124 can be deposited in one or more deposition operations.

[0110] In some embodiments, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization) to planarize the passivation layers 120 to 124 after deposition. Additionally and / or alternatively, one or more of the passivation layers 120 to 124 may be disposed on the integrated circuit die 104. Additionally and / or alternatively, the semiconductor die package 102 may be disposed over and / or on one or more of the passivation layers 120 to 124 on a carrier substrate.

[0111] As shown in Figure 5G, the semiconductor die package 102 is flipped, and one or more operations are performed to remove the carrier substrate 304, bonding layer 302, and bonding layer 306 from the semiconductor die package 102. In some embodiments, the carrier substrate 304 is separated from the semiconductor die package 102 by changing the adhesive properties of the bonding layer 302 and / or bonding layer 306 through a heating operation. For example, an energy source such as ultraviolet (UV) laser, carbon dioxide (CO2) laser, infrared (IR) radiation, or other examples besides those described above is used to irradiate and heat the bonding layer 302 and / or bonding layer 306 until the adhesive properties of the bonding layer 302 and / or bonding layer 306 are reduced. Then, the carrier substrate 304, bonding layer 302, and bonding layer 306 are physically separated and removed from the semiconductor die package 102. Additionally and / or alternatively, the carrier substrate 304, bonding layer 302, and / or bonding layer 306 can be removed by etching and / or planarization.

[0112] As shown in Figure 5H, passivation layers 116 and 118 are formed on the integrated circuit die 104. Deposition tools can be used to deposit passivation layers 116 and 118 using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. Passivation layers 116 and 118 can be deposited in one or more deposition operations. In some embodiments, planarization tools are used to perform planarization operations (e.g., chemical mechanical planarization) to planarize passivation layers 116 and 118 after deposition. Additionally and / or alternatively, passivation layers 116 and / or 118 can be distributed onto the integrated circuit die 104. Connection structure 164 can also be attached to the semiconductor die package 102.

[0113] As described above, Figures 5A through 5H are provided as an example. Other examples may differ from those described in Figures 5A through 5H.

[0114] Figures 6 through 9 illustrate example embodiments of a bonding configuration in which bonding pads 158 of an integrated circuit die 106 are bonded to an integrated circuit die 104 in the semiconductor die package 102 described herein. While Figures 6 through 9 provide several example embodiments of the bonding configuration, other example embodiments of the bonding configuration are also within the scope of embodiments of this disclosure. Additionally, the semiconductor die package 102 may include a plurality of bonding configurations.

[0115] As shown in Figure 6, an example embodiment 600 of the bonding configuration includes bonding pads 158 (or pad portions of bonding structure 180) of integrated circuit die 106 bonded to bonding pads 162 of integrated circuit die 104 in a metal-to-metal bonding manner. The metal-to-metal bonding between bonding pads 158 and bonding pads 162 provides electrical connection between integrated circuit die 104 and integrated circuit die 106.

[0116] The bonding dielectric layer 308 includes a bonding pad 162. The bonding dielectric layer 308 of the integrated circuit die 104 and the bonding dielectric layer 112 of the integrated circuit die 106 are bonded together in a dielectric-to-dielectric bonding manner.

[0117] As shown in Figure 7, an example embodiment 700 of the bonding configuration includes bonding pads 158 (or pad portions of bonding structures 180) of integrated circuit die 106 bonded to the bonding dielectric layer 308 of integrated circuit die 104 in a metal-to-dielectric bonding manner. In example embodiment 700, bonding pads 158 serve as dummy structures (e.g., not for providing electrical connections between integrated circuit die 104 and integrated circuit die 106), and the integrated circuit die 106 includes bonding pads 158 to achieve a specific pattern density in the integrated circuit die 106.

[0118] As shown in Figure 8, an example embodiment 800 of the bonding configuration includes bonding pads 158 (or pad portions of bonding structure 180) of integrated circuit die 106 bonded to bonding pads 162 of integrated circuit die 104 in a metal-to-metal bonding manner. The metal-to-metal bonding between bonding pads 158 and bonding pads 162 provides electrical connection between integrated circuit die 104 and integrated circuit die 106.

[0119] As further shown in Figure 8, the bonding via 156 of the integrated circuit die 106 (or the via portion of the bonding structure 180) is coupled to the metal pad structure 146b of the integrated circuit die 106. The metal pad structure 146b in Example Embodiment 800 is formed of aluminum (Al), unlike the metal pad structure 146b in Example Embodiments 600 and 700 (which can be formed of other metals such as copper (Cu). Therefore, in Example Embodiment 800, the dielectric liner 174 around the trench portion 170 of the metal pad structure 146b can be omitted.

[0120] As shown in Figure 9, an example embodiment 900 of the bonding configuration includes a plurality of bonding pads 158 (or pad portions of bonding structures 180) of the integrated circuit die 104 bonded to the integrated circuit die 104. In example embodiment 900, a plurality of bonding vias 156 (or via portions of bonding structures 180) are coupled to the same metal pad structure 146b. The plurality of bonding pads 158 (or pad portions of bonding structures 180) may be bonded to the bonding dielectric layer 308 of the integrated circuit die 104 in a metal-to-dielectric bonding manner, and / or the plurality of bonding pads 158 may be bonded to the bonding pads 162 of the integrated circuit die 104 in a metal-to-metal bonding manner.

[0121] As mentioned above, Figures 6 through 9 are provided as an example. Other examples may differ from those shown in Figures 6 through 9.

[0122] Figure 10 illustrates a flowchart of an example process 1000 relating to the formation of the semiconductor device described herein. In some embodiments, one or more process blocks of Figure 10 may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0123] As shown in Figure 10, process 1000 may include forming one or more integrated circuit devices (block 1010) in a substrate of an integrated circuit die. For example, one or more semiconductor process tools may be used to form one or more integrated circuit devices (e.g., integrated circuit device 130b) in a substrate (e.g., substrate 126b) of an integrated circuit die (e.g., integrated circuit die 106), as described herein.

[0124] As further shown in Figure 10, process 1000 may include forming a plurality of vertically aligned metallization layers (block 1020) over one or more integrated circuit devices. For example, one or more semiconductor process tools may be used to form a plurality of vertically aligned metallization layers (e.g., vertically aligned conductive structure 138b) over one or more integrated circuit devices, as described herein.

[0125] As further shown in Figure 10, process 1000 may include forming a metal pad structure (block 1030) on the topmost metallization layer of the vertically aligned metallization layers. For example, one or more semiconductor process tools may be used to form a metal pad structure (e.g., metal pad structure 146b) on the topmost metallization layer of the vertically aligned metallization layers, as described herein.

[0126] As further shown in Figure 10, process 1000 may include forming a groove (block 1040) through a first and second layer above the metal liner structure. For example, one or more semiconductor process tools may be used to form a groove (e.g., groove 404) through a first layer (e.g., dielectric layer 150b) and a second layer (e.g., photoresist layer 402) above the metal liner structure, as described herein.

[0127] As further shown in Figure 10, process 1000 may include forming a bonding structure in a recess such that the bonding structure sits on a metal pad structure (block 1050). For example, one or more semiconductor process tools may be used to form the bonding structure (e.g., bonding structure 180, bonding via 156, and bonding pad 158) in the recess such that the bonding structure sits on a metal pad structure, as described herein.

[0128] As further shown in Figure 10, process 1000 may include removing a second layer around the bonding structure (block 1060). For example, one or more semiconductor process tools may be used to remove the second layer around the bonding structure, as described herein.

[0129] As further shown in Figure 10, process 1000 may include forming a bonding dielectric layer (block 1070) around the bonding structure above the first layer. For example, one or more semiconductor process tools may be used to form a bonding dielectric layer (e.g., bonding dielectric layer 112) around the bonding structure above the first layer, as described herein.

[0130] Process 1000 may include additional implementations, such as any single or combined implementations described below, and / or one or more other processes described in combination with other parts of this document.

[0131] In the first embodiment, the first layer includes a dielectric layer and the second layer includes a photoresist layer.

[0132] In the second embodiment, either alone or in combination with the first embodiment, forming a joining structure includes a through-hole portion (e.g., joining through-hole 156) forming the joining structure in a first portion (e.g., through-hole portion 408) through which the groove passes through the first layer, and a pad portion (e.g., joining pad 158) forming the joining structure in a second portion (e.g., groove portion 406) through which the groove passes through the second layer.

[0133] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the second layer is located above the first layer, and the padding portion is located above the through-hole portion.

[0134] In the fourth embodiment, forming a joining structure, either alone or in combination with one or more of the first to third embodiments, includes forming a barrier liner (e.g., barrier liner 176) on the sidewall of the first portion of the groove and the sidewall of the second portion of the groove, forming a through-hole portion of the joining structure such that the barrier liner is located between the sidewall of the through-hole portion and the sidewall of the first portion of the groove, and forming a pad portion of the joining structure such that the barrier liner is located between the sidewall of the pad portion and the sidewall of the second portion of the groove.

[0135] In the fifth embodiment, process 1000 includes removing the barrier liner from the sidewall of the liner portion of the bonding structure, either alone or in combination with one or more of the first to fourth embodiments.

[0136] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 1000 includes forming a dielectric liner (e.g., dielectric liner 178) directly on the sidewall of the bonding structure after removing the second layer from around the bonding structure, wherein the dielectric liner has a dielectric constant lower than that of tantalum nitride (TaN).

[0137] Although Figure 10 shows an example block of process 1000, in some implementations, process 1000 includes more blocks, fewer blocks, different blocks, or different arrangements of blocks compared to that shown in Figure 10. Alternatively, two or more blocks of process 1000 may be executed in parallel.

[0138] Figure 11 illustrates a flowchart of an example process 1100 relating to the formation of the semiconductor device described herein. In some embodiments, one or more process blocks of Figure 11 may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0139] As shown in Figure 11, process 1100 may include forming one or more integrated circuit devices (block 1110) in a substrate of an integrated circuit die. For example, one or more semiconductor process tools may be used to form one or more integrated circuit devices (e.g., integrated circuit device 130b) in a substrate (e.g., substrate 126b) of an integrated circuit die (e.g., integrated circuit die 106), as described herein.

[0140] As further shown in Figure 11, process 1100 may include forming a plurality of vertically aligned metallization layers (block 1120) over one or more integrated circuit devices. For example, one or more semiconductor process tools may be used to form a plurality of vertically aligned metallization layers (e.g., vertically aligned conductive structure 138b) over one or more integrated circuit devices, as described herein.

[0141] As further shown in Figure 11, process 1100 may include forming a metal pad structure (block 1130) on the topmost metallization layer of the vertically aligned metallization layers. For example, one or more semiconductor process tools may be used to form a metal pad structure (e.g., metal pad structure 146b) on the topmost metallization layer of the vertically aligned metallization layers, as described herein.

[0142] As further shown in Figure 11, process 1100 may include forming a first portion (block 1140) of a groove through a first layer located above the metal liner structure. For example, one or more semiconductor process tools may be used to form a first portion (e.g., groove 404) (e.g., trench portion 406) of a groove through a first layer (e.g., photoresist layer 402) located above the metal liner structure, as described herein.

[0143] As further shown in Figure 11, process 1100 may include forming a second portion (block 1150) of a groove through a second layer located above the metal liner structure and below the first layer. For example, one or more semiconductor process tools may be used to form a second portion (e.g., via portion 408) of a groove through a second layer (e.g., dielectric layer 150b) located above the metal liner structure and below the first layer, as described herein.

[0144] As further shown in Figure 11, process 1100 may include forming a bonding via in a second portion of the recess, such that the bonding via is situated on a metal pad structure (block 1160). For example, one or more semiconductor process tools may be used to form a bonding via (e.g., bonding via 156) in the second portion of the recess, such that the bonding via is situated on a metal pad structure, as described herein.

[0145] As further shown in Figure 11, process 1100 may include forming a bonding pad in a first portion of the recess such that the bonding pad sits on a bonding via (block 1170). For example, one or more semiconductor process tools may be used to form a bonding pad (e.g., bonding pad 158) in the first portion of the recess such that the bonding pad sits on a bonding via, as described herein.

[0146] As further shown in Figure 11, process 1100 may include removing a first layer around the bonding pad (block 1180). For example, one or more semiconductor process tools may be used to remove the first layer around the bonding pad, as described herein.

[0147] As further shown in Figure 11, process 1100 may include forming a bonding dielectric layer (block 1190) around the bonding pad over the second layer. For example, one or more semiconductor process tools may be used to form a bonding dielectric layer (e.g., bonding dielectric layer 112) around the bonding pad over the second layer, as described herein.

[0148] Process 1100 may include additional implementations, such as any single or combined implementations described below, and / or one or more other processes described in combination with other parts of this document.

[0149] In a first embodiment, process 1100 includes forming a tantalum-based barrier liner (e.g., barrier liner 176) on the sidewall of the groove, wherein forming a bonding via includes forming a bonding via on the tantalum-based barrier liner, and wherein forming a bonding pad includes forming a bonding pad such that the tantalum-based barrier liner is located between the sidewall of the bonding pad and the first layer.

[0150] In the second embodiment, alone or in combination with the first embodiment, process 1100 includes removing a tantalum-based barrier liner from the sidewall of the bonding pad and forming a silicon-based dielectric liner (e.g., dielectric liner 178) on the sidewall of the bonding pad.

[0151] In the third embodiment, forming a bonding dielectric layer, either alone or in combination with one or more of the first and second embodiments, includes forming a bonding dielectric layer such that a silicon-based dielectric liner is located between the sidewall of the bonding pad and the bonding dielectric layer.

[0152] In the fourth embodiment, removing the first layer from around the bonding pad, either alone or in combination with one or more of the first to third embodiments, includes performing a chemical stripping operation to remove the first layer, or performing a plasma ashing operation to remove the first layer.

[0153] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the first portion of forming the groove includes forming the first portion of the groove by photolithographic patterning, and the second portion of forming the groove includes forming the second portion of the groove by etching.

[0154] Although Figure 11 shows an example block of process 1100, in some embodiments, process 1100 includes more blocks, fewer blocks, different blocks, or different arrangements of blocks compared to that shown in Figure 11. Alternatively, two or more blocks of process 1100 may be performed in parallel.

[0155] In this manner, a first integrated circuit die and a second integrated circuit die are bonded together in a stacked configuration within the device package. The second integrated circuit die includes at least one bonding structure bonded to the first integrated circuit die. The bonding structure is formed such that a barrier layer is omitted from the top sidewall of the bonding structure. After the bonding structure is formed, the barrier layer is removed and replaced by a dielectric liner on the sidewall. The material removal rate of the dielectric liner (used in processes such as chemical mechanical planarization, polishing, and / or chemical surface cleaning) is closer to the material removal rate of the bonding structure than that of the barrier liner. Removing too much material from the bonding structure may create voids, and the above structure reduces the likelihood of these voids forming between the first and second integrated circuit dies. In this manner, removing the barrier liner around the top of the bonding structure creates a strong electrical connection between the bonding structure and the first integrated circuit die, thereby reducing the electrical resistance and / or power consumption of the device package and improving the electrical performance of the device package. Additionally and / or alternatively, removing the barrier liner around the top of the bonding structure can increase the bonding mechanical strength between the bonding structure and the first integrated circuit die, thereby reducing the possibility of delamination between the first integrated circuit die and the second integrated circuit die.

[0156] As described in more detail above, some embodiments described herein provide a method. The method includes forming one or more integrated circuit devices in a substrate of an integrated circuit die. The method includes forming a plurality of vertically aligned metallization layers over the one or more integrated circuit devices. The method includes forming a metal pad structure on the topmost metallization layer of the vertically aligned metallization layers. The method includes forming a groove through a first and second layer above the metal pad structure. The method includes forming a bonding structure in the groove such that the bonding structure sits on the metal pad structure. The method includes removing a second layer around the bonding structure. The method includes forming a bonding dielectric layer around the bonding structure over the first layer.

[0157] As described in more detail above, some embodiments described herein provide a method. The method includes forming one or more integrated circuit devices in a substrate of an integrated circuit die. The method includes forming a plurality of vertically aligned metallization layers over the one or more integrated circuit devices. The method includes forming a metal pad structure on the topmost metallization layer of the vertically aligned metallization layers. The method includes forming a first portion of a recess through a first layer located above the metal pad structure. The method includes forming a second portion of the recess through a second layer located above the metal pad structure and below the first layer. The method includes forming a bonding via in the second portion of the recess such that the bonding via is situated on the metal pad structure. The method includes forming a bonding pad in the first portion of the recess such that the bonding pad is situated on the bonding via. The method includes removing the first layer around the bonding pad. The method includes forming a bonding dielectric layer around the bonding pad over the second layer.

[0158] As described in more detail above, some embodiments described herein provide a device package. The device package includes a first integrated circuit die. The device package includes a second integrated circuit die bonded to and perpendicularly aligned with the first integrated circuit die. The first integrated circuit die includes a bonding via coupled to a metal pad structure, wherein the metal pad structure is perpendicularly adjacent to the bonding via. The first integrated circuit die includes a barrier liner located on the sidewall of the bonding via. The first integrated circuit die includes a bonding pad coupled to the bonding via. The bonding pad is perpendicularly adjacent to the bonding via. The bonding via is perpendicularly located between the bonding pad and the metal pad structure. The first integrated circuit die includes a dielectric layer located on the sidewall of the bonding pad. The barrier liner and the dielectric layer comprise different materials.

[0159] The terms "approximately" and "substantially" can refer to a value that varies within 5% of a given value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are illustrative only and are not intended to be limiting. It should be understood that the terms "approximately" and "substantially" can represent a percentage of a given value in an embodiment of this disclosure.

[0160] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0161] 100: Example 102: Semiconductor die packaging 104, 106: Integrated circuit chips 108a, 108b: Non-active grains 110: Gap 112: Bonding Dielectric Layer 114a, 114b: Dielectric filling layer 116, 118, 120, 122, 124: Passivation layer 126a,126b:Substrate 128a, 128b: Interlayer dielectric layers 130a, 130b: Integrated circuit devices 132a, 132b: Contact elements 134a, 134b: Interlayer dielectric layers 136a, 136b: Etching stop layers 138a, 138b: Conductive structure 140a, 140b: Sealing ring structure 142a, 142b, 144a, 144b: Passivation layers 146a, 146b, 148a, 148b: Metal gasket structure 150a, 150b: Dielectric layers 152a, 152b: Joint gaskets 154: Bonding layer 156: Connecting through hole 158: Joint gasket 160: Through-substrate interconnect structure 162: Joint gasket 164: Connection Structure 166: Part 168: Through-hole section 170: Groove section 172: Barrier Lining 174: Dielectric liner 176: Barrier Lining 178: Dielectric liner 180: Joint structure 200, 202, 204, 206: Example top view shapes 208a: First top view section 208b: Second top view section 300: Example Implementation 302: Bonding layer 304: Substrate 306: Bonding layer 308: Bonding Dielectric Layer 400: Example Implementation 402: Photoresist layer 404: Groove 406: Groove section 408: Through-hole portion 500, 600, 700, 800, 900: Example Implementation 1000: Process 1010, 1020, 1030, 1040, 1050, 1060, 1070: Square 1100: Process 1110, 1120, 1130, 1140, 1150, 1160, 1170, 1180, 1190: Square AA: Line D1, D2, D3, D4, D5, D6: Dimensions x, y, z: Direction

[0162] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor device package, comprising: One or more integrated circuit devices are formed in a substrate of an integrated circuit die; a plurality of vertically aligned metallization layers are formed above the one or more integrated circuit devices; a metal pad structure is formed on the topmost metallization layer of the vertically aligned metallization layers; a groove and an additional groove are formed through a dielectric layer and a photoresist layer above the metal pad structure; a bonding structure is formed in the groove, and an additional bonding structure is formed in the additional groove, such that the bonding structure and the additional bonding structure are respectively located on the metal pad structure; the photoresist layer is removed from the area around the bonding structure and the additional bonding structure; and a bonding dielectric layer is formed above the dielectric layer around the bonding structure.

2. The method as described in claim 1, wherein forming the joint structure comprises: A through-hole portion of the bonding structure is formed in a first portion of the groove that passes through the dielectric layer; And a pad portion forming the bonding structure in a second portion of the groove passing through the photoresist layer.

3. The method as described in claim 2, wherein forming the joint structure comprises: A barrier liner is formed on multiple sidewalls of the first portion of the groove and multiple sidewalls of the second portion of the groove; The through-hole portion forming the joint structure is such that the barrier liner is located between the plurality of sidewalls of the through-hole portion and the sidewalls of the first portion of the groove; and the pad portion forming the joint structure is such that the barrier liner is located between the plurality of sidewalls of the pad portion and the sidewalls of the second portion of the groove.

4. The method as described in claim 1, further comprising: After the photoresist layer is removed from the bonding structure, a dielectric liner is formed directly on a plurality of sidewalls of the bonding structure, wherein the dielectric constant of the dielectric liner is lower than that of tantalum nitride.

5. A method for forming a semiconductor device package, comprising: One or more integrated circuit devices are formed in a substrate of an integrated circuit die; a plurality of vertically aligned metallization layers are formed above the one or more integrated circuit devices; a metal pad structure is formed on a topmost metallization layer of the vertically aligned metallization layers; a first portion of a groove and an additional first portion of an additional groove are formed through a dielectric layer located above the metal pad structure; a second portion of the groove and an additional second portion of the additional groove are formed through a photoresist layer located above the metal pad structure and below the dielectric layer; a bonding via and an additional bonding via are formed in the second portion of the groove and the additional second portion of the additional groove, respectively, such that the bonding via and the additional bonding via are respectively located on the metal pad structure; a bonding pad and an additional bonding pad are formed in the first portion of the groove and the additional first portion of the additional groove, respectively, such that the bonding pad is located on the bonding via and the additional bonding pad is located on the additional bonding via. Remove the dielectric layer around the bonding pad and the additional bonding pad; and form a bonding dielectric layer around the bonding pad and the additional bonding pad above the photoresist layer.

6. The method as described in claim 5, further comprising: A tantalum-based barrier liner is formed on a plurality of sidewalls of the groove, wherein forming the bonding via includes forming the bonding via on the tantalum-based barrier liner, and wherein forming the bonding pad includes forming the bonding pad such that the tantalum-based barrier liner is located between the sidewalls of the bonding pad and the dielectric layer.

7. A semiconductor device package, comprising: A first integrated circuit die; A second integrated circuit die is attached to the first integrated circuit die and arranged perpendicularly to it. The first integrated circuit die includes: a bonding via and an additional bonding via, each coupled to a metal pad structure, wherein the metal pad structure is perpendicularly adjacent to the bonding via and the additional bonding via; a barrier liner and an additional barrier liner, the barrier liner being located on a plurality of sidewalls of the bonding via, and the additional barrier liner being located on a plurality of additional sidewalls of the additional bonding via; a bonding pad and an additional bonding pad, the bonding pad being coupled to the bonding via, and the additional bonding pad being coupled to the additional bonding via. The bonding pad is perpendicularly adjacent to the bonding via, and the additional bonding pad is perpendicularly adjacent to the additional bonding via, wherein the bonding via is perpendicularly located between the bonding pad and the metal pad structure, and the additional bonding via is perpendicularly located between the additional bonding pad and the metal pad structure; and a dielectric layer is located on a plurality of sidewalls of the bonding pad and the additional bonding pad, wherein the barrier liner and the dielectric layer comprise different materials.

8. The semiconductor device package as claimed in claim 7, wherein the bonding pad is bonded to a through-substrate interconnect structure, the through-substrate interconnect structure being included in the second integrated circuit die.

9. The semiconductor device package as claimed in claim 7, wherein the bonding pad is bonded to a bonding dielectric layer, the bonding dielectric layer being included in the second integrated circuit die.

10. The semiconductor device package as claimed in claim 7, wherein the metal pad structure includes a first metal material; wherein the bonding via and the bonding pad include a second metal material; and wherein the first metal material and the second metal material are different metal materials.

Images